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https://opencores.org/ocsvn/riscv_vhdl/riscv_vhdl/trunk
Subversion Repositories riscv_vhdl
[/] [riscv_vhdl/] [trunk/] [rtl/] [patches/] [run.srcipt] - Rev 5
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git clone https://github.com/ucb-bar/rocket-chip.gitcd rocket-chipgit submodule update --initcd riscv-tools/git submodule update --init --recursive riscv-testscd rocket-chip/rocket-chip/fsim/make CONFIG=GnssConfig verilog