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[/] [riscv_vhdl/] [trunk/] [rtl/] [prj/] [ml605/] [riscv_soc.xise] - Rev 5
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<?xml version="1.0" encoding="UTF-8" standalone="no" ?><project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema"><header><!-- ISE source project file created by Project Navigator. --><!-- --><!-- This file contains project source information including a list of --><!-- project source files, project and process properties. This file, --><!-- along with the project source files, is sufficient to open and --><!-- implement in ISE Project Navigator. --><!-- --><!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. --></header><version xil_pn:ise_version="14.7" xil_pn:schema_version="2"/><files><file xil_pn:name="../../commonlib/types_common.vhd" xil_pn:type="FILE_VHDL"><association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/><association xil_pn:name="Implementation" xil_pn:seqID="1"/><library xil_pn:name="commonlib"/></file><file xil_pn:name="../../commonlib/types_util.vhd" xil_pn:type="FILE_VHDL"><association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/><association xil_pn:name="Implementation" xil_pn:seqID="0"/><library xil_pn:name="commonlib"/></file><file xil_pn:name="../../techmap/bufg/bufgmux_fpga.vhd" xil_pn:type="FILE_VHDL"><association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/><association xil_pn:name="Implementation" xil_pn:seqID="0"/><library xil_pn:name="techmap"/></file><file xil_pn:name="../../techmap/bufg/bufgmux_tech.vhd" xil_pn:type="FILE_VHDL"><association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/><association xil_pn:name="Implementation" xil_pn:seqID="0"/><library xil_pn:name="techmap"/></file><file xil_pn:name="../../techmap/gencomp/gencomp.vhd" xil_pn:type="FILE_VHDL"><association xil_pn:name="BehavioralSimulation" xil_pn:seqID="5"/><association xil_pn:name="Implementation" xil_pn:seqID="10"/><library xil_pn:name="techmap"/></file><file xil_pn:name="../../techmap/pll/SysPLL_tech.vhd" xil_pn:type="FILE_VHDL"><association xil_pn:name="BehavioralSimulation" xil_pn:seqID="6"/><association xil_pn:name="Implementation" xil_pn:seqID="51"/><library xil_pn:name="techmap"/></file><file xil_pn:name="../../techmap/pll/SysPLL_v6.vhd" xil_pn:type="FILE_VHDL"><association xil_pn:name="BehavioralSimulation" xil_pn:seqID="7"/><association xil_pn:name="Implementation" xil_pn:seqID="33"/><library xil_pn:name="techmap"/></file><file xil_pn:name="../../rocketlib/types_rocket.vhd" xil_pn:type="FILE_VHDL"><association xil_pn:name="BehavioralSimulation" xil_pn:seqID="8"/><association xil_pn:name="Implementation" xil_pn:seqID="27"/><library xil_pn:name="rocketlib"/></file><file xil_pn:name="../../work/config_common.vhd" xil_pn:type="FILE_VHDL"><association xil_pn:name="BehavioralSimulation" xil_pn:seqID="10"/><association xil_pn:name="Implementation" xil_pn:seqID="49"/></file><file xil_pn:name="config_v6.vhd" xil_pn:type="FILE_VHDL"><association xil_pn:name="BehavioralSimulation" xil_pn:seqID="11"/><association xil_pn:name="Implementation" xil_pn:seqID="45"/></file><file xil_pn:name="../../techmap/mem/bootrom_inferred.vhd" xil_pn:type="FILE_VHDL"><association xil_pn:name="BehavioralSimulation" xil_pn:seqID="16"/><association xil_pn:name="Implementation" xil_pn:seqID="26"/><library xil_pn:name="techmap"/></file><file xil_pn:name="../../techmap/mem/bootrom_tech.vhd" xil_pn:type="FILE_VHDL"><association xil_pn:name="BehavioralSimulation" xil_pn:seqID="17"/><association xil_pn:name="Implementation" xil_pn:seqID="37"/><library xil_pn:name="techmap"/></file><file xil_pn:name="../../techmap/mem/sram8_inferred.vhd" xil_pn:type="FILE_VHDL"><association xil_pn:name="BehavioralSimulation" xil_pn:seqID="18"/><association xil_pn:name="Implementation" xil_pn:seqID="24"/><library xil_pn:name="techmap"/></file><file xil_pn:name="../../techmap/mem/srambytes_tech.vhd" xil_pn:type="FILE_VHDL"><association xil_pn:name="BehavioralSimulation" xil_pn:seqID="19"/><association xil_pn:name="Implementation" xil_pn:seqID="35"/><library xil_pn:name="techmap"/></file><file xil_pn:name="../../techmap/mem/romimage_inferred.vhd" xil_pn:type="FILE_VHDL"><association xil_pn:name="BehavioralSimulation" xil_pn:seqID="23"/><association xil_pn:name="Implementation" xil_pn:seqID="25"/><library xil_pn:name="techmap"/></file><file xil_pn:name="../../techmap/mem/romimage_tech.vhd" xil_pn:type="FILE_VHDL"><association xil_pn:name="BehavioralSimulation" xil_pn:seqID="24"/><association xil_pn:name="Implementation" xil_pn:seqID="36"/><library xil_pn:name="techmap"/></file><file xil_pn:name="../../rocketlib/tilelink/axibridge.vhd" xil_pn:type="FILE_VHDL"><association xil_pn:name="BehavioralSimulation" xil_pn:seqID="25"/><association xil_pn:name="Implementation" xil_pn:seqID="0"/><library xil_pn:name="rocketlib"/></file><file xil_pn:name="../../techmap/pll/types_pll.vhd" xil_pn:type="FILE_VHDL"><association xil_pn:name="BehavioralSimulation" xil_pn:seqID="28"/><association xil_pn:name="Implementation" xil_pn:seqID="50"/><library xil_pn:name="techmap"/></file><file xil_pn:name="../../techmap/mem/types_mem.vhd" xil_pn:type="FILE_VHDL"><association xil_pn:name="BehavioralSimulation" xil_pn:seqID="29"/><association xil_pn:name="Implementation" xil_pn:seqID="8"/><library xil_pn:name="techmap"/></file><file xil_pn:name="../../techmap/bufg/types_buf.vhd" xil_pn:type="FILE_VHDL"><association xil_pn:name="BehavioralSimulation" xil_pn:seqID="30"/><association xil_pn:name="Implementation" xil_pn:seqID="53"/><library xil_pn:name="techmap"/></file><file xil_pn:name="../../techmap/mem/ram32_inferred.vhd" xil_pn:type="FILE_VHDL"><association xil_pn:name="BehavioralSimulation" xil_pn:seqID="33"/><association xil_pn:name="Implementation" xil_pn:seqID="0"/><library xil_pn:name="techmap"/></file><file xil_pn:name="../../techmap/mem/ram32_tech.vhd" xil_pn:type="FILE_VHDL"><association xil_pn:name="BehavioralSimulation" xil_pn:seqID="34"/><association xil_pn:name="Implementation" xil_pn:seqID="0"/><library xil_pn:name="techmap"/></file><file xil_pn:name="../../techmap/mem/romprn_inferred.vhd" xil_pn:type="FILE_VHDL"><association xil_pn:name="BehavioralSimulation" xil_pn:seqID="35"/><association xil_pn:name="Implementation" xil_pn:seqID="0"/><library xil_pn:name="techmap"/></file><file xil_pn:name="../../techmap/mem/romprn_tech.vhd" xil_pn:type="FILE_VHDL"><association xil_pn:name="BehavioralSimulation" xil_pn:seqID="36"/><association xil_pn:name="Implementation" xil_pn:seqID="0"/><library xil_pn:name="techmap"/></file><file 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xil_pn:name="../../techmap/bufg/obuf_inferred.vhd" xil_pn:type="FILE_VHDL"><association xil_pn:name="BehavioralSimulation" xil_pn:seqID="64"/><association xil_pn:name="Implementation" xil_pn:seqID="0"/><library xil_pn:name="techmap"/></file><file xil_pn:name="../../techmap/bufg/obuf_tech.vhd" xil_pn:type="FILE_VHDL"><association xil_pn:name="BehavioralSimulation" xil_pn:seqID="65"/><association xil_pn:name="Implementation" xil_pn:seqID="0"/><library xil_pn:name="techmap"/></file><file xil_pn:name="../../rocketlib/rocket_l1only.vhd" xil_pn:type="FILE_VHDL"><association xil_pn:name="BehavioralSimulation" xil_pn:seqID="67"/><association xil_pn:name="Implementation" xil_pn:seqID="58"/></file><file xil_pn:name="../../ambalib/axictrl.vhd" xil_pn:type="FILE_VHDL"><association xil_pn:name="BehavioralSimulation" xil_pn:seqID="72"/><association xil_pn:name="Implementation" xil_pn:seqID="72"/><library xil_pn:name="ambalib"/></file><file xil_pn:name="../../ambalib/types_amba4.vhd" xil_pn:type="FILE_VHDL"><association xil_pn:name="BehavioralSimulation" xil_pn:seqID="73"/><association xil_pn:name="Implementation" xil_pn:seqID="7"/><library xil_pn:name="ambalib"/></file><file xil_pn:name="../../techmap/mem/syncram_2p_inferred.vhd" xil_pn:type="FILE_VHDL"><association xil_pn:name="BehavioralSimulation" xil_pn:seqID="131"/><association xil_pn:name="Implementation" xil_pn:seqID="9"/><library xil_pn:name="techmap"/></file><file xil_pn:name="../../techmap/mem/syncram_2p_tech.vhd" xil_pn:type="FILE_VHDL"><association xil_pn:name="BehavioralSimulation" xil_pn:seqID="132"/><association xil_pn:name="Implementation" xil_pn:seqID="23"/><library xil_pn:name="techmap"/></file><file xil_pn:name="../../riverlib/dsu/axi_dsu.vhd" xil_pn:type="FILE_VHDL"><association xil_pn:name="BehavioralSimulation" xil_pn:seqID="136"/><association xil_pn:name="Implementation" xil_pn:seqID="60"/><library xil_pn:name="riverlib"/></file><file xil_pn:name="../../techmap/bufg/igdsbuf_tech.vhd" xil_pn:type="FILE_VHDL"><association xil_pn:name="BehavioralSimulation" xil_pn:seqID="142"/><association xil_pn:name="Implementation" xil_pn:seqID="55"/><library xil_pn:name="techmap"/></file><file xil_pn:name="../../techmap/bufg/igdsbuf_v6.vhd" xil_pn:type="FILE_VHDL"><association xil_pn:name="BehavioralSimulation" xil_pn:seqID="143"/><association xil_pn:name="Implementation" xil_pn:seqID="39"/><library xil_pn:name="techmap"/></file><file xil_pn:name="../../techmap/pll/clkp90_tech.vhd" xil_pn:type="FILE_VHDL"><association xil_pn:name="BehavioralSimulation" xil_pn:seqID="144"/><association xil_pn:name="Implementation" xil_pn:seqID="52"/><library xil_pn:name="techmap"/></file><file xil_pn:name="../../techmap/pll/clkp90_v6.vhd" xil_pn:type="FILE_VHDL"><association xil_pn:name="BehavioralSimulation" xil_pn:seqID="145"/><association xil_pn:name="Implementation" xil_pn:seqID="34"/><library xil_pn:name="techmap"/></file><file xil_pn:name="../../techmap/bufg/idsbuf_tech.vhd" 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xil_pn:name="BehavioralSimulation" xil_pn:seqID="115"/><association xil_pn:name="Implementation" xil_pn:seqID="2"/><library xil_pn:name="riverlib"/></file><file xil_pn:name="../../riverlib/river_top.vhd" xil_pn:type="FILE_VHDL"><association xil_pn:name="BehavioralSimulation" xil_pn:seqID="116"/><association xil_pn:name="Implementation" xil_pn:seqID="44"/><library xil_pn:name="riverlib"/></file><file xil_pn:name="../../riverlib/types_river.vhd" xil_pn:type="FILE_VHDL"><association xil_pn:name="BehavioralSimulation" xil_pn:seqID="117"/><association xil_pn:name="Implementation" xil_pn:seqID="43"/><library xil_pn:name="riverlib"/></file><file xil_pn:name="../../riverlib/core/bp_predic.vhd" xil_pn:type="FILE_VHDL"><association xil_pn:name="BehavioralSimulation" xil_pn:seqID="118"/><association xil_pn:name="Implementation" xil_pn:seqID="18"/><library xil_pn:name="riverlib"/></file><file xil_pn:name="../../riverlib/core/csr.vhd" xil_pn:type="FILE_VHDL"><association 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xil_pn:name="misclib"/></file><file xil_pn:name="../../misclib/nasti_pnp.vhd" xil_pn:type="FILE_VHDL"><association xil_pn:name="BehavioralSimulation" xil_pn:seqID="97"/><association xil_pn:name="Implementation" xil_pn:seqID="66"/><library xil_pn:name="misclib"/></file><file xil_pn:name="../../misclib/nasti_romimage.vhd" xil_pn:type="FILE_VHDL"><association xil_pn:name="BehavioralSimulation" xil_pn:seqID="98"/><association xil_pn:name="Implementation" xil_pn:seqID="65"/><library xil_pn:name="misclib"/></file><file xil_pn:name="../../misclib/nasti_sram.vhd" xil_pn:type="FILE_VHDL"><association xil_pn:name="BehavioralSimulation" xil_pn:seqID="99"/><association xil_pn:name="Implementation" xil_pn:seqID="64"/><library xil_pn:name="misclib"/></file><file xil_pn:name="../../misclib/nasti_uart.vhd" xil_pn:type="FILE_VHDL"><association xil_pn:name="BehavioralSimulation" xil_pn:seqID="100"/><association xil_pn:name="Implementation" xil_pn:seqID="63"/><library xil_pn:name="misclib"/></file><file xil_pn:name="../../misclib/reset_glb.vhd" xil_pn:type="FILE_VHDL"><association xil_pn:name="BehavioralSimulation" xil_pn:seqID="101"/><association xil_pn:name="Implementation" xil_pn:seqID="62"/><library xil_pn:name="misclib"/></file><file xil_pn:name="../../misclib/tap_uart.vhd" xil_pn:type="FILE_VHDL"><association xil_pn:name="BehavioralSimulation" xil_pn:seqID="102"/><association xil_pn:name="Implementation" xil_pn:seqID="61"/><library xil_pn:name="misclib"/></file><file xil_pn:name="../../misclib/types_misc.vhd" xil_pn:type="FILE_VHDL"><association xil_pn:name="BehavioralSimulation" xil_pn:seqID="103"/><association xil_pn:name="Implementation" xil_pn:seqID="30"/><library xil_pn:name="misclib"/></file><file xil_pn:name="../../misclib/dcom_uart.vhd" xil_pn:type="FILE_VHDL"><association xil_pn:name="BehavioralSimulation" xil_pn:seqID="136"/><association xil_pn:name="Implementation" xil_pn:seqID="46"/><library xil_pn:name="misclib"/></file><file xil_pn:name="../../misclib/dcom_jtag.vhd" xil_pn:type="FILE_VHDL"><association xil_pn:name="BehavioralSimulation" xil_pn:seqID="135"/><association xil_pn:name="Implementation" xil_pn:seqID="135"/><library xil_pn:name="misclib"/></file><file xil_pn:name="../../misclib/tap_jtag.vhd" xil_pn:type="FILE_VHDL"><association xil_pn:name="BehavioralSimulation" xil_pn:seqID="136"/><association xil_pn:name="Implementation" xil_pn:seqID="136"/><library xil_pn:name="misclib"/></file></files><properties><property xil_pn:name="AES Initial Vector virtex5" xil_pn:value="" xil_pn:valueState="default"/><property xil_pn:name="AES Initial Vector virtex6" xil_pn:value="" xil_pn:valueState="default"/><property xil_pn:name="AES Key (Hex String)" xil_pn:value="" xil_pn:valueState="default"/><property xil_pn:name="AES Key (Hex String) virtex6" xil_pn:value="" xil_pn:valueState="default"/><property xil_pn:name="Add I/O Buffers" xil_pn:value="true" xil_pn:valueState="default"/><property xil_pn:name="Allow Logic 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