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[/] [robust_axi_fabric/] [trunk/] [src/] [base/] [def_ic.txt] - Rev 11

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<##//////////////////////////////////////////////////////////////////
////                                                             ////
////  Author: Eyal Hochberg                                      ////
////          eyal@provartec.com                                 ////
////                                                             ////
////  Downloaded from: http://www.opencores.org                  ////
/////////////////////////////////////////////////////////////////////
////                                                             ////
//// Copyright (C) 2010 Provartec LTD                            ////
//// www.provartec.com                                           ////
//// info@provartec.com                                          ////
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//// This source file may be used and distributed without        ////
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//// the original copyright notice and the associated disclaimer.////
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//// This source file is free software; you can redistribute it  ////
//// and/or modify it under the terms of the GNU Lesser General  ////
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//// This source is distributed in the hope that it will be      ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied  ////
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//// PURPOSE.  See the GNU Lesser General Public License for more////
//// details. http://www.gnu.org/licenses/lgpl.html              ////
////                                                             ////
//////////////////////////////////////////////////////////////////##>

INCLUDE def_ic_static.txt

SWAP #FFD       #1                              ##flip-flop delay

SWAP PREFIX     fabric_MASTER_NUM_SLAVE_NUM     ##prefix for all module and file names

SWAP MASTER_NUM 3                               ##number of masters
SWAP SLAVE_NUM  6                               ##number of slaves

DEFINE DEF_DECERR_SLV                           ##use interanl decode slave error

SWAP ID_BITS    3                               ##AXI ID bits
LOOP M0_IDX     2                               ##number of IDs for master 0
SWAP ID_M0_ID0  ID_BITS'b000                    ##master 0 ID0
SWAP ID_M0_ID1  ID_BITS'b001                    ##master 0 ID1
LOOP M1_IDX     1                               ##number of IDs for master 1
SWAP ID_M1_ID0  ID_BITS'b011                    ##master 1 ID0
LOOP M2_IDX     1                               ##number of IDs for master 2
SWAP ID_M2_ID0  ID_BITS'b101                    ##master 2 ID0
 
SWAP CMD_DEPTH  8                               ##AXI command depth for read and write

SWAP DATA_BITS 64                               ##AXI data bits
SWAP ADDR_BITS 32                               ##AXI address bits

SWAP USER_BITS  4                               ##AXI user bits

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