URL
https://opencores.org/ocsvn/robust_axi_fabric/robust_axi_fabric/trunk
Subversion Repositories robust_axi_fabric
[/] [robust_axi_fabric/] [trunk/] [src/] [base/] [def_ic_static.txt] - Rev 23
Compare with Previous | Blame | View Log
<##//////////////////////////////////////////////////////////////////
//// ////
//// Author: Eyal Hochberg ////
//// eyal@provartec.com ////
//// ////
//// Downloaded from: http://www.opencores.org ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2010 Provartec LTD ////
//// www.provartec.com ////
//// info@provartec.com ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation.////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more////
//// details. http://www.gnu.org/licenses/lgpl.html ////
//// ////
//////////////////////////////////////////////////////////////////##>
VERIFY (DATA_BITS in 32, 64) ##stub supports 32 or 64 bits data bus
VERIFY (SIZE_BITS in 2, 3) ##stub supports 32 or 64 bits data bus
VERIFY (MASTER_NUM in 1..8)
VERIFY (SLAVE_NUM in 1..16)
SWAP.GLOBAL MODEL_NAME AXI interconnect fabric
SWAP MSTRS MASTER_NUM
SWAP SLVS EXPR(SLAVE_NUM+DVAL(DEF_DECERR_SLV))
LOOP MX MSTRS
LOOP SX SLVS
SWAP MSTR_BITS LOG2(MSTRS)
SWAP SLV_BITS LOG2(SLVS)
SWAP SERR EXPR(SLVS-1)
IFDEF UNIQUE_ID
SWAP ID_BITS MSTR_ID_BITS
SWAP ADD_ID NULL
ELSE UNIQUE_ID
SWAP ID_BITS EXPR(MSTR_ID_BITS+EXTRA_BITS)
SWAP ADD_ID BIN(MX MSTR_BITS NOPRE)_
ENDIF UNIQUE_ID
GROUP IC_AXI_A is {
ID ID_BITS input SON(CHANGE 1)
ADDR ADDR_BITS input
LEN 4 input
SIZE SIZE_BITS input
BURST 2 input
CACHE 4 input
PROT 3 input
LOCK 2 input
USER USER_BITS input
VALID 1 input
READY 1 output
}
GROUP IC_AXI_W is {
ID ID_BITS input SON(CHANGE 1)
DATA DATA_BITS input
STRB DATA_BITS/8 input
LAST 1 input
USER USER_BITS input
VALID 1 input
READY 1 output
}
GROUP IC_AXI_B is {
ID ID_BITS output SON(CHANGE 1)
RESP 2 output
USER USER_BITS output
VALID 1 output
READY 1 input
}
GROUP IC_AXI_R is {
ID ID_BITS output SON(CHANGE 1)
DATA DATA_BITS output
RESP 2 output
LAST 1 output
USER USER_BITS output
VALID 1 output
READY 1 input
}
GROUP IC_AXI joins {
GROUP IC_AXI_A prefix_AW
GROUP IC_AXI_W prefix_W
GROUP IC_AXI_B prefix_B
GROUP IC_AXI_A prefix_AR
GROUP IC_AXI_R prefix_R
}
GROUP IC_AXI_CMD is {
SLV SLV_BITS input
ID ID_BITS input SON(CHANGE 1)
VALID 1 input
READY 1 input
}