Subversion Repositories rs232_syscon

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<b><font size=+2 face="Helvetica, Arial"color=#bf0000>Project: rs232_syscon</font></b><p><table  align=center border=1 cellPadding=2 cellSpacing=0 width="100%" valign="top"><tbody><tr bgcolor=#bbccff>    <td align=center valign=center>
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<p><center><font  color="#bf0000" size=+3> <b>Download</b></font></center></p>
<p><font color="#2080bf" size=+1> <b>Allright, here are "the goods!"</b></font></p>
<p>Unfortunately, there is no testbench for this core.  It was developed through many design iterations in an actual Xilinx XC2V200 SpartanII FPGA, with the aid of a HP16500 series logic analyzer.  This proved to be much faster than simulating, (or at least that is how we felt) since the serial-ports need thousands and thousands of clock cycles between output transitions...  Or maybe we were just too "lazy" to make a testbench!  But, this core does work.  It is just over 1000 lines of Verilog code, with lots of comments, and it took many hours to debug it.</p>
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<p>Downloads:</p>
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<p><a href="./rs232_syscon_1_01_xsoc.zip">rs232_syscon_1_01_xsoc.zip</a>.  This file contains the updated rs232_syscon, which supports muxing of the stb_o and we_o lines (in addition to the adr_o lines, which were already muxed between rs232_syscon and the normal bus master.)  This file shows how the rs232_syscon can be connected to a host microcontroller.  In this case the microcontroller is a 16-bit RISC design, modified from the original XSOC project.  This entire design takes up only about 900 Xilinx Virtex slices.  The rs232_syscon uses more than half of this logic....  The RISC microcontroller runs at about 32 MHz on the XC2S200 SpartanII chip, without any floorplanning and without any aggressive timing constraints.
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<a href="./rs232_syscon_soc1.zip">rs232_syscon_soc1.zip</a>.
This file contains the rs232_syscon connected to a set of 8 registers, 1 of which is read only (uses "reg_8_pack.v" for the registers).  It is a good example of how the tri-state data bus connects to the registers.  It also has an lcd-panel test block connected to the outputs of the registers, but you can easily delete that part.
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<a href="./rs232_syscon_soc2.zip">rs232_syscon_soc2.zip</a>.
This file contains an additional register block (uses "reg_4_pack.v") and it also shows how the output from the registers is connected to an lcd flat-panel test module, which has a "bouncing pong-ball" on the screen, with grid lines, and an aimable "crosshairs" sight.  The lcd flat-panel which was tested was from an IBM 700C laptop computer, and it required a pixel clock of around 25 MHz (this design used 49.152 MHz divided by two.)  (New surplus lcd panels are available in USA from Brigar Electronics for only $12.95US!  If you get one, email us and we will send you a connection diagram.)
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<a href="./rs232_syscon_soc3.zip">rs232_syscon_soc3.zip</a>.
This file contains rs232_syscon, connected to some instantiations of Xilinx dual-ported block-RAM.  Using the registers, the user can write to the 16-bit side of the memory block, and read from the 32-bit side!  The memory block is arranged to be "little endian."
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<a href="./rs232_syscon_1_00_source.zip">rs232_syscon_1_00_source.zip</a>.This file contains only "rs232_syscon.v" and "serial.v".  The serial port function is in "serial.v"  This is the bare minimum design.
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