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[/] [rv01_riscv_core/] [trunk/] [Release_Notes.txt] - Rev 5

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---------------------------------------------------------------
December 2017
---------------------------------------------------------------

This is first release of RV01 RISC-V core version 1.0.

Release directory structure:

RV01_RISCV_V1_0
|
+--> DOCS (core datasheet and reference RISC-V specifications)
|
+--> SIM
|    |
|    +--> MODELSIM (self-test simulation script)
|    +--> ISIM (self-test simulation notes)
|
+--> SYN
|    |
|    +--> XILINX (self-test module synthesis script)
|
+--> VHDL (core source files)
|    |
|    +--> SELF_TEST (self-test module source files)
|
+--> Release_Notes.txt (this file)

Additional info about files included in the current release can 
be found in README.txt files located in the sub-directories.

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