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https://opencores.org/ocsvn/rv01_riscv_core/rv01_riscv_core/trunk
Subversion Repositories rv01_riscv_core
[/] [rv01_riscv_core/] [trunk/] [SYN/] [XILINX/] [RV01_artix.xdc] - Rev 5
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create_clock -period 10.000 -name CLK_100M_i -waveform {0.000 5.000} [get_ports CLK_100M_i]set_property IOSTANDARD LVCMOS33 [get_ports DONE_o]set_property IOSTANDARD LVCMOS33 [get_ports CLK_100M_i]set_property IOSTANDARD LVCMOS33 [get_ports PASS_o]set_property IOSTANDARD LVCMOS33 [get_ports RSTN_i]set_property IOSTANDARD LVCMOS33 [get_ports TIE_HIGH_o]set_property IOSTANDARD LVCMOS33 [get_ports TIE_LOW_o]set_property PACKAGE_PIN E3 [get_ports CLK_100M_i]set_property PACKAGE_PIN T6 [get_ports TIE_HIGH_o]set_property PACKAGE_PIN C12 [get_ports RSTN_i]set_property PACKAGE_PIN T8 [get_ports DONE_o]set_property PACKAGE_PIN V9 [get_ports PASS_o]set_property PACKAGE_PIN R8 [get_ports TIE_LOW_o]set_false_path -from [get_ports RSTN_i]set_false_path -to [get_ports {TIE_HIGH_o TIE_LOW_o}]