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S1 Core - Functional Specification
==================================

Preface
-------
The S1 is a CPU core that makes use of a single SPARC Core
extracted from the OpenSPARC T1, with the addition of a
Wishbone Bridge, a Reset Controller and an Interrupt
Controller.
           ___________________________________
          |             S1 Core               |
          | _______  _____ ________  ________ |
          ||       ||     ||       ||        ||
          || Reset || Int || SPARC ||Wishbone||
          || Ctrl. ||Ctrl.|| Core  || Bridge ||
          ||       ||     ||       ||        ||
          | -------  -----  -------  -------- |
           -----------------------------------

Instruction Set Architecture
----------------------------
The CPU inside the S1 Core is the SPARC Core of the
OpenSPARC T1 microprocessor, so you can read OpenSPARC
documents for the specification of this CPU.
Basically it follows the SPARC v9 64-bit ISA, specified
in the documents freely available on the opensparc.net
website; for the full documentation you also have to read
the datasheet and other specs included in the download
file of the T1 design.

Software Support
----------------
The SPARC v9 ISA is obviously supported by the GCC compiler;
also GNU/Linux is supported and the latest versions of the
kernel are ready for the T1.
There's also a complete GNU/Linux distribution, Ubuntu,
that comes ready for the SPARC Core of the T1 and could be
used in a seamless way also for S1 based micros.

S1 Memory Map
-------------
The S1 Core has 64-bit wide Data Bus and Address Bus.
Each bit of the Address Bus has a different meaning:
- bits [63:59] specify the one-hot encoding for the T1 target region number;
- bits [58:40] are 19 bits always hardwired to zero;
- bits [39:0] are the 40-bit Physical Address as it comes from the SPARC Core.

For most applications the lowest 40-bit address coming from the SPARC Core
should be enough, so it should be safe to ignore the other bits (unless
you suspect that for instance Physical Address zero in region 0 is
different from address zero in region 1 and so forth).

S1 Physical Address [63:56]
---------------------------
the first byte specifies the T1 target region number (one-hot encoded
on the most significant 5 bits, the 3 least significant bits are
hardwired to zero):
- 0x08           RAM Bank 0 (bit 59 set)
- 0x10           RAM Bank 1 (bit 60 set)
- 0x20           RAM Bank 2 (bit 61 set)
- 0x40           RAM Bank 3 (bit 62 set)
- 0x80           I/O Bridge (bit 63 set)

As you can see one of the five most significant bits of the
address must be always set depending on the target region.

S1 Physical Address [39:32]
---------------------------
In the T1 bit 39 is zero for all memory addresses and 1 for I/O
addresses. Then the T1, from which the S1 is derived, uses the
following memory map for bits [39:32] (please note that this
mapping is NOT used by the S1):
- 0x00-0x7F      RAM
- 0x80           JBus
- 0x81-0x95      <Reserved>
- 0x96           Clock Unit
- 0x97           RAM Controller
- 0x98           I/O Bridge Management Block
- 0x99           TAP Unit
- 0x9A-0x9D      <Reserved>
- 0x9E           TAP2ASI
- 0x9F           I/O Bridge Interrupt Table
- 0xA0-0xBF      L2 Control Registers
- 0xC0-0xFE      JBus
- 0xFF           Boot ROM

For the S1 Core the memory map is different and the following
table applies:
- 0x00-0x7F     RAM
- 0x80-0x95     <Reserved>
- 0x96          Real Time Clock
- 0x97          RAM Controller
- 0x98          Wishbone Interconnect Arbiter
- 0x99          DMA Controller
- 0x9A-0x9D     <Reserved>
- 0x9E          General Purpose I/O
- 0x9F          Interrupt Controller
- 0xA0-0xFE     <Reserved>
- 0xFF          Boot ROM

If you intend to use in your system not only the least significant
40 bits generated by the SPARC Core, take into account that for
accesses not directed to RAM but to configuration registers it
should be an access to the I/O region (bit 63 set), so for instance
the full 64-bit base address for the Interrupt Controller should
be 0x8000_009F_0000_0000.

S1 Physical Address [2:0]
-------------------------
The S1 Core implements a Wishbone Master interface with a data bus
of 64 bits and a granularity of 1 byte.
Then the address generated by the S1 is always aligned on 64-bit
boundaries, i.e. bits [2:0] are always zero; the information
about the bytes that have to be accessed during a Wishbone
bus cycle is obviously encoded on the SEL signals described
in the Wishbone spec.

Reset Controller
----------------
The boot sequence of the T1 is quite complex; we have then written
a reset controller for the S1 that just takes one reset signal
and generates all the signals required by the SPARC Core to boot
up properly.

Interrupt Controller
--------------------
Early versions of the S1 Core feature a very basic Interrupt
Controller that latches interrupt requests arriving to the core
that are then signaled to the SPARC Core with the proper CPX
packet.
Currently this block is untested and it will be enhanced in
the future.

Wishbone Bridge
---------------
The eight SPARC Cores inside the OpenSPARC T1 microprocessor
make use of a proprietary protocol to communicate with the
rest of the chip; this protocol is often referred to as
PCX/CPX protocol, where PCX stands for "Processor-to-Cache
Xbar" and is used for the requests outgoing the SPARC Cores
and CPX stands for "Cache-to-Processor Xbar" and is used for
incoming packets.
The main block designed specifically for the S1 Core is the
"SPARC Core to Wishbone Master interface bridge" that translates
the requests and return packets of the SPARC Core into the
Wishbone protocol.
You can find the full specification of the Wishbone protocol
on the OpenCores site at http://www.opencores.org

Interface Details
-----------------
These are the features of the bus interface of the S1 Core
(they can also be referred to as "Wishbone Datasheet"):
- Wishbone Master interface that follows revision B.3;
- standard signals names identified by leading "wbm_" chars;
- no ERR/RTY support;
- 64-bit Address Bus (with some bits unused, see above);
- 64-bit Data Bus supporting 8, 16, 32 and 64 bit accesses;
- data transfer ordering is Big Endian;
- supports Single Read/Write Cycles.