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[/] [s1_core/] [trunk/] [docs/] [SYNTHESIS.txt] - Rev 114

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S1 Core - Synthesis Environment

The scripts to run synthesis are similar to the ones
used for simulations, you can still use the free Icarus
Verilog software (that will target an FPGA application)
or a commercial Design Compiler tool from Synopsys (that
will be used for ASIC). In addition there is also a good
synthesis tool for FPGAs from Xilinx named XST (could be
"Xilinx Synthesis Tool").

To synthesize using XST:

  s1_synth xst

With Icarus you will use the "fpga" target, to do so
just run:

  s1_synth fpga

If you want to use Synopsys Design Compiler instead you
have to use:

  s1_synth dc

Please note that the commercial tools are NOT supported, and
they will probably not work unless you fix all the required
parameters properly (we are focusing on free software since
we want to build up a community of developers around the S1).

The results for these scripts are in the directories:


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