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[/] [s6soc/] [trunk/] [rtl/] [altbusmaster.v] - Rev 5

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// Filename: 	altbusmaster.v
// Project:	CMod S6 System on a Chip, ZipCPU demonstration project
// Purpose:	
// Creator:	Dan Gisselquist, Ph.D.
//		Gisselquist Technology, LLC
// Copyright (C) 2015-2016, Gisselquist Technology, LLC
// This program is free software (firmware): you can redistribute it and/or
// modify it under the terms of  the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or (at
// your option) any later version.
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
// for more details.
// You should have received a copy of the GNU General Public License along
// with this program.  (It's in the $(ROOT)/doc directory, run make with no
// target there if the PDF file isn't present.)  If not, see
// <> for a copy.
// License:	GPL, v3, as defined and found on,
`include "builddate.v"
`define	CFG_SCOPE
`define	INCLUDE_RTC	// 2017 slice LUTs w/o, 2108 with (!!!)
module	altbusmaster(i_clk, i_rst,
		i_rx_stb, i_rx_data, o_tx_stb, o_tx_data, i_tx_busy,
		// The SPI Flash lines
		o_qspi_cs_n, o_qspi_sck, o_qspi_dat, i_qspi_dat, o_qspi_mod,
		// The board I/O
		i_btn, o_led, o_pwm, o_pwm_aux,
		// Keypad connections
		i_kp_row, o_kp_col,
		// UART control
		// GPIO lines
		i_gpio, o_gpio);
			BUS_ADDRESS_WIDTH=23, BAW=23; // 24bits->2,258,23b->2181
	input			i_clk, i_rst;
	// The bus commander, via an external JTAG port
	input			i_rx_stb;
	input		[7:0]	i_rx_data;
	output	wire		o_tx_stb;
	output	wire	[7:0]	o_tx_data;
	input			i_tx_busy;
	output	wire		o_uart_rts;
	// SPI flash control
	output	wire		o_qspi_cs_n, o_qspi_sck;
	output	wire	[3:0]	o_qspi_dat;
	input		[3:0]	i_qspi_dat;
	output	wire	[1:0]	o_qspi_mod;
	// Board I/O
	input		[1:0]	i_btn;
	output	wire	[3:0]	o_led;
	output	wire		o_pwm;
	output	wire	[1:0]	o_pwm_aux;
	// Keypad
	input		[3:0]	i_kp_row;
	output	wire	[3:0]	o_kp_col;
	// UART control
	output	wire	[29:0]	o_uart_setup;
	// GPIO liines
	input		[15:0]	i_gpio;
	output	wire	[15:0]	o_gpio;
	// Master wishbone wires
	wire		wb_cyc, wb_stb, wb_we, wb_stall, wb_ack, wb_err;
	wire	[31:0]	wb_data, wb_idata;
	wire	[(BAW-1):0]	wb_addr;
	wire	[5:0]		io_addr;
	assign	io_addr = {
			wb_addr[22],	// Flash
			wb_addr[13],	// RAM
			wb_addr[11],	// RTC
			wb_addr[10],	// CFG
			wb_addr[ 9],	// SCOPE
			wb_addr[ 8] };	// I/O
	// Wires going to devices
	// And then headed back home
	wire	w_interrupt;
	// Oh, and the debug control for the ZIP CPU
	wire		zip_dbg_ack, zip_dbg_stall;
	wire	[31:0]	zip_dbg_data;
	// The BUS master (source): The WB to UART conversion bus
	wire		zip_cyc, zip_stb, zip_we, zip_cpu_int;
	wire	[(ZA-1):0]	w_zip_addr;
	wire	[(BAW-1):0]	zip_addr;
	wire	[31:0]		zip_data;
	// and then coming from devices
	wire		zip_ack, zip_stall, zip_err;
	wire	dwb_we, dwb_stb, dwb_cyc, dwb_ack, dwb_stall, dwb_err;
	wire	[(BAW-1):0]	dwb_addr;
	wire	[31:0]		dwb_odata;
	// wire	[31:0]	zip_debug;
	wbubus busbdriver(i_clk, i_rx_stb, i_rx_data,
			// The wishbone interface
			wb_cyc, wb_stb, wb_we, w_wbu_addr, wb_data,
				wb_ack, wb_stall, wb_err, wb_idata,
			// Provide feedback to the UART
			o_tx_stb, o_tx_data, i_tx_busy);
	assign	o_uart_rts = (~rx_rdy);
	if (ZA < BAW)
		assign	wb_addr = { {(BAW-ZA){1'b0}}, w_wbu_addr };
		assign	wb_addr = w_zip_addr;
	wire	io_sel, flash_sel, flctl_sel, scop_sel, cfg_sel, mem_sel,
			rtc_sel, none_sel, many_sel;
	wire	flash_ack, scop_ack, cfg_ack, mem_ack;
	wire	rtc_ack, rtc_stall;
	assign	rtc_stall = 1'b0;
	wire	io_stall, flash_stall, scop_stall, cfg_stall, mem_stall;
	reg	io_ack, uart_ack;
	wire	[31:0]	flash_data, scop_data, cfg_data, mem_data, pwm_data,
			spio_data, gpio_data, uart_data;
	reg	[31:0]	io_data;
	reg	[(BAW-1):0]	bus_err_addr;
	assign	wb_ack = (wb_cyc)&&((io_ack)||(scop_ack)||(cfg_ack)
	assign	wb_stall = ((io_sel)&&(io_stall))
			// (none_sel)&&(1'b0)
	assign	wb_idata = (io_ack)?io_data
			: ((scop_ack)?scop_data
			: ((cfg_ack)?cfg_data
			: ((mem_ack)?mem_data
			: ((flash_ack)?flash_data
			: 32'h00))));
	assign	wb_idata =  (io_ack|scop_ack)?((io_ack )? io_data  : scop_data)
			: ((cfg_ack|uart_ack) ? ((cfg_ack)?cfg_data: uart_data)
			: ((mem_ack|rtc_ack)?((mem_ack)?mem_data:rtc_data)
			: flash_data)); // if (flash_ack)
	assign	wb_err = ((wb_cyc)&&(wb_stb)&&(none_sel || many_sel)) || many_ack;
	// Addresses ...
	//	0000 xxxx	configuration/control registers
	//	1 xxxx xxxx xxxx xxxx xxxx	Up-sampler taps
	assign	io_sel   =((wb_cyc)&&(io_addr[5:0]==6'h1));
	assign	flctl_sel= 1'b0; // ((wb_cyc)&&(io_addr[5:1]==5'h1));
	assign	scop_sel =((wb_cyc)&&(io_addr[5:1]==5'h1));
	assign	cfg_sel  =((wb_cyc)&&(io_addr[5:2]==4'h1));
	// zip_sel is not on the bus at this point
	assign	rtc_sel  =((wb_cyc)&&(io_addr[5:3]==3'h1));
	assign	mem_sel  =((wb_cyc)&&(io_addr[5:4]==2'h1));
	assign	flash_sel=((wb_cyc)&&(io_addr[5]));
	assign	none_sel =((wb_cyc)&&(wb_stb)&&(io_addr==6'h0));
	assign	many_sel =((wb_cyc)&&(wb_stb)&&(
			 {3'h0, io_sel}
			+{3'h0, flctl_sel}
			// +{3'h0, scop_sel}
			+{3'h0, cfg_sel}
			+{3'h0, mem_sel}
			+{3'h0, flash_sel} > 1));
	assign	many_sel = 1'b0;
	wire	many_ack;
	assign	many_ack =((wb_cyc)&&(
			 {3'h0, io_ack}
			+{3'h0, scop_ack}
			+{3'h0, cfg_ack}
			+{3'h0, rtc_ack}
			+{3'h0, mem_ack}
			+{3'h0, flash_ack} > 1));
	wire		flash_interrupt, scop_interrupt, tmra_int, tmrb_int,
			rtc_interrupt, gpio_int, pwm_int, keypad_int,button_int;
	reg		rx_rdy;
	wire	[10:0]	int_vector;
	assign	int_vector = { gpio_int, pwm_int, keypad_int,
				1'b0, rx_rdy, tmrb_int, tmra_int,
				rtc_interrupt, scop_interrupt,
				wb_err, button_int };
	wire	[31:0]	pic_data;
	icontrol #(11)	pic(i_clk, 1'b0,
			wb_data, pic_data, int_vector, w_interrupt);
	initial	bus_err_addr = `DATESTAMP;
	always @(posedge i_clk)
		if (wb_err)
			bus_err_addr <= wb_addr;
	wire		zta_ack, zta_stall, ztb_ack, ztb_stall;
	wire	[31:0]	timer_a, timer_b;
	ziptimer	zipt_a(i_clk, 1'b0, 1'b1, wb_cyc,
				wb_we, wb_data, zta_ack, zta_stall, timer_a,
	ziptimer	zipt_b(i_clk, 1'b0, 1'b1, wb_cyc,
				wb_we, wb_data, ztb_ack, ztb_stall, timer_b,
	wire	[31:0]	rtc_data;
	wire	rtcd_ack, rtcd_stall, ppd;
	// rtcdate	thedate(i_clk, ppd, wb_cyc, (wb_stb)&&(io_sel), wb_we,
			// wb_data, rtcd_ack, rtcd_stall, date_data);
	reg	r_rtc_ack;
	initial	r_rtc_ack = 1'b0;
	always @(posedge i_clk)
		r_rtc_ack <= ((wb_stb)&&(rtc_sel));
	assign	rtc_ack = r_rtc_ack;
		#(32'h35afe5)		// 80 MHz clock
		thetime(i_clk, wb_cyc,
			((wb_stb)&&(rtc_sel)), wb_we,
			{ 1'b0, wb_addr[1:0] }, wb_data, rtc_data,
			rtc_interrupt, ppd);
	assign	rtc_interrupt = 1'b0;
	assign	rtc_data = 32'h00;
	assign	rtc_ack  = 1'b0;
	always @(posedge i_clk)
			4'h0: io_data <= pic_data;
			4'h1: io_data <= { {(32-BAW){1'b0}}, bus_err_addr };
			4'h2: io_data <= timer_a;
			4'h3: io_data <= timer_b;
			4'h4: io_data <= pwm_data;
			4'h5: io_data <= spio_data;
			4'h6: io_data <= gpio_data;
			4'h7: io_data <= uart_data;
			default: io_data <= `DATESTAMP;
			// 4'h8: io_data <= `DATESTAMP;
	always @(posedge i_clk)
		io_ack <= (wb_cyc)&&(wb_stb)&&(io_sel);
	assign	io_stall = 1'b0;
	wire	pwm_ack, pwm_stall;
	wbpwmaudio	theaudio(i_clk, wb_cyc,
				((wb_stb)&&(io_sel)&&(wb_addr[3:0]==4'h4)), wb_we,
				1'b0, wb_data,
				pwm_ack, pwm_stall, pwm_data, o_pwm, o_pwm_aux,
	// Special Purpose I/O: Keypad, button, LED status and control
	spio	thespio(i_clk, wb_cyc,(wb_stb)&&(io_sel)&&(wb_addr[3:0]==4'h5),wb_we,
			wb_data, spio_data, o_kp_col, i_kp_row, i_btn, o_led,
			keypad_int, button_int);
	// General purpose (sort of) I/O:  (Bottom two bits robbed in each
	// direction for an I2C link at the toplevel.v design)
	wbgpio	#(16,16,16'hffff) thegpio(i_clk, wb_cyc,
			(wb_stb)&&(io_sel)&&(wb_addr[3:0]==4'h6), wb_we,
			wb_data, gpio_data, i_gpio, o_gpio, gpio_int);
	//	Rudimentary serial port control
	reg	[7:0]	r_rx_data;
	// Baud rate is set by clock rate / baud rate.
	// Thus, 80MHz / 115200MBau
	//	= 694.4, or about 0x2b6. 
	// although the CPU might struggle to keep up at this speed without a
	// hardware buffer.
	// We'll add the flag for two stop bits.
	assign	o_uart_setup = 30'h080002b6; // 115200 MBaud @ an 80MHz clock
	wire	flash_cs_n, flash_sck, flash_mosi;
	wbqspiflashp #(24)	flashmem(i_clk,
			wb_addr[21:0], wb_data,
		flash_ack, flash_stall, flash_data,
		o_qspi_sck, o_qspi_cs_n, o_qspi_mod, o_qspi_dat, i_qspi_dat,
	wire	[31:0]	cfg_scope;
	wbicape6	fpga_cfg(i_clk, wb_cyc,(cfg_sel)&&(wb_stb), wb_we,
				wb_addr[5:0], wb_data,
				cfg_ack, cfg_stall, cfg_data,
	reg	r_cfg_ack;
	always @(posedge i_clk)
		r_cfg_ack <= (wb_cyc)&&(cfg_sel)&&(wb_stb);
	assign	cfg_ack   = r_cfg_ack;
	assign	cfg_stall = 1'b0;
	assign	cfg_data  = 32'h00;
	assign	cfg_scope = 32'h00;
	memdev	#(12) ram(i_clk, wb_cyc, (wb_stb)&&(mem_sel), wb_we,
			wb_addr[11:0], wb_data, mem_ack, mem_stall, mem_data);
	wire	[31:0]	scop_cfg_data;
	wire		scop_cfg_ack, scop_cfg_stall, scop_cfg_interrupt;
`ifdef	CFG_SCOPE
	wire		scop_cfg_trigger;
	assign	scop_cfg_trigger = (wb_cyc)&&(wb_stb)&&(cfg_sel);
	wbscope	#(5'ha) wbcfgscope(i_clk, 1'b1, scop_cfg_trigger, cfg_scope,
		// Wishbone interface
		i_clk, wb_cyc, ((wb_stb)&&(scop_sel)&&(wb_addr[2:1]==2'b01)),
				wb_we, wb_addr[0], wb_data,
			scop_cfg_ack, scop_cfg_stall, scop_cfg_data,
	assign	scop_interrupt = scop_cfg_interrupt;
	assign	scop_ack   = scop_cfg_ack;
	assign	scop_stall = scop_cfg_stall;
	assign	scop_data  = scop_cfg_data;
// 0x8684 interrupts ...???

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