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https://opencores.org/ocsvn/sata_controller_core/sata_controller_core/trunk
Subversion Repositories sata_controller_core
[/] [sata_controller_core/] [trunk/] [sata2_bus_v1_00_a/] [base_system/] [__xps/] [DDR3_SDRAM_ctrl_path_table.txt] - Rev 11
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// This file has been automatically generated. Do not modify.// Command Line Options: -family virtex6 -enable_ecc 0 -tRAS 37500 -part_data_width 16 -cas_latency 6 -cas_wr_latency 5 -memory_burst_length 8 -tRC 50625 -tRCD 13130 -nDQSS 1 -tWR 15000 -tRP 13130 -tRRD 7500 -tRFC 110000 -nAL 0 -nCCD 4 -tWTR 7500 -tRTP 7500 -nZQCS 64 -c 5000 -reg 0 -m DDR3 -d 32 -f_txt /raid/home/aamendon/open_source/svn/sata_controller_core/sata_controller_core/trunk/sata2_bus_v1_00_a/base_system/__xps/DDR3_SDRAM_ctrl_path_table.txt -f_err /raid/home/aamendon/open_source/svn/sata_controller_core/sata_controller_core/trunk/sata2_bus_v1_00_a/base_system/__xps/DDR3_SDRAM_ctrl_path_generation_errors.txt -f_ver /raid/home/aamendon/open_source/svn/sata_controller_core/sata_controller_core/trunk/sata2_bus_v1_00_a/base_system/__xps/DDR3_SDRAM_ctrl_path_params.v -static_phy 0 -wr_mem_pipeline 1//// Timing Parameters:// Memory Clock Period (ps): 2500// CAS Latency : 6// CAS Write Latency : 5// +------------------------------+--------+-----+-------+-------+---------+// | | | Clocks | Nanoseconds |// |Parameter | Symbol | MIN | MAX | MIN | MAX |// +------------------------------+--------+-----+-------+-------+---------+// |ACTIVATE to internal READ or | tRCD | 7 | - | 13.1 | - |// |WRITE delay time* | | | | | |// +------------------------------+--------+-----+-------+-------+---------+// |PRECHARGE command period | tRP | 6 | - | 13.1 | - |// +------------------------------+--------+-----+-------+-------+---------+// |ACTIVATE-to-ACTIVATE or | tRC | 21 | - | 50.6 | - |// |REFRESH command period | | | | | |// +------------------------------+--------+-----+-------+-------+---------+// |ACTIVATE-to-PRECHARGE | tRAS | 15 | - | 37.5 | - |// |command period | | | | | |// +------------------------------+--------+-----+-------+-------+---------+// |ACTIVATE-to-ACTIVATE minimum | tRRD | 4 | - | 7.5 | - |// |command period | | | | | |// +------------------------------+--------+-----+-------+-------+---------+// |Write recovery time | tWR | 6 | - | 15.0 | - |// +------------------------------+--------+-----+-------+-------+---------+// |Delay from start of internal | tWTR | | - | 7.5 | - |// |WRITE transaction to internal | | | | | |// |READ command | | | | | |// +------------------------------+--------+-----+-------+-------+---------+// |READ-to-PRECHARGE time | tRTP | 4 | - | 7.5 | - |// +------------------------------+--------+-----+-------+-------+---------+// |CAS#-to-CAS# command delay | tCCD | 4 | - | | - |// +------------------------------+--------+-----+-------+-------+---------+// |ZQCS command: short calib time| nZQCS | 64 | - | | - |// +------------------------------+--------+-----+-------+-------+---------+// * tRCD must be an odd number of clock cycles when using Virtex-6 DDR3 (DFI)//--------------------------------------------------------------------------//// FSM PATTERN 0: WORD WRITE//// Control Signals 0 00 0// (32 Signals) 0123456789abcdef// --------------- -------------------------------- ------------------------------/* 0 CTRL_COMPLETE */ 0000000000100000 // Delayed by 1/* 1 CTRL_IS_WRITE */ 1111111111111111 // Delayed by 1/* 2 CTRL_DFI_RAS_N_0 */ 1011111111110111 // Delayed by 2/* 3 CTRL_DFI_CAS_N_0 */ 1111111111111111 // Delayed by 2/* 4 CTRL_DFI_WE_N_0 */ 1111111111110111 // Delayed by 2/* 5 UNUSED */ 0000000000000000 // Delayed by 0/* 6 UNUSED */ 0000000000000000 // Delayed by 0/* 7 UNUSED */ 0000000000000000 // Delayed by 0/* 8 CTRL_DP_WRFIFO_POP */ 0010000000000000 // Delayed by 1/* 9 UNUSED */ 0000000000000000 // Delayed by 0/* 10 UNUSED */ 0000000000000000 // Delayed by 0/* 11 UNUSED */ 0000000000000000 // Delayed by 0/* 12 CTRL_AP_COL_CNT_LOAD */ 0001000000000000 // Delayed by 1/* 13 CTRL_AP_COL_CNT_ENABLE */ 0000100000000000 // Delayed by 1/* 14 CTRL_AP_PRECHARGE_ADDR10 */ 0000000000001000 // Delayed by 1/* 15 CTRL_AP_ROW_COL_SEL */ 0100000000000000 // Delayed by 1/* 16 UNUSED */ 0000000000000000 // Delayed by 0/* 17 CTRL_REPEAT4 */ 0000000000000000 // Delayed by 1/* 18 CTRL_DFI_WRDATA_EN */ 0000100000000000 // Delayed by 2/* 19 CTRL_DFI_RDDATA_EN */ 0000000000000000 // Delayed by 2/* 20 CTRL_DFI_RAS_N_1 */ 1111111111111111 // Delayed by 2/* 21 CTRL_DFI_CAS_N_1 */ 1111011111111111 // Delayed by 2/* 22 CTRL_DFI_WE_N_1 */ 1111011111111111 // Delayed by 2/* 23 CTRL_AP_OTF_ADDR12 */ 0000000000000000 // Delayed by 1/* 24 UNUSED */ 0000000000000000 // Delayed by 0/* 25 UNUSED */ 0000000000000000 // Delayed by 0/* 26 UNUSED */ 0000000000000000 // Delayed by 0/* 27 UNUSED */ 0000000000000000 // Delayed by 0/* 28 UNUSED */ 0000000000000000 // Delayed by 0/* 29 UNUSED */ 0000000000000000 // Delayed by 0/* 30 UNUSED */ 0000000000000000 // Delayed by 0/* 31 UNUSED */ 0000000000000000 // Delayed by 0/* 32 UNUSED */ 0000000000000000 // Delayed by 0/* 33 UNUSED */ 0000000000000000 // Delayed by 0/* 34 UNUSED */ 0000000000000000 // Delayed by 0/* 35 UNUSED */ 0000000000000000 // Delayed by 0//--------------------------------------------------------------------------//// FSM PATTERN 1: WORD READ//// Control Signals 0 01 1// (32 Signals) 0123456789ab// --------------- -------------------------------- ------------------------------/* 0 CTRL_COMPLETE */ 000000100000 // Delayed by 1/* 1 CTRL_IS_WRITE */ 000000000000 // Delayed by 1/* 2 CTRL_DFI_RAS_N_0 */ 101111111111 // Delayed by 2/* 3 CTRL_DFI_CAS_N_0 */ 111111111111 // Delayed by 2/* 4 CTRL_DFI_WE_N_0 */ 111111111111 // Delayed by 2/* 5 UNUSED */ 000000000000 // Delayed by 0/* 6 UNUSED */ 000000000000 // Delayed by 0/* 7 UNUSED */ 000000000000 // Delayed by 0/* 8 CTRL_DP_WRFIFO_POP */ 000000000000 // Delayed by 1/* 9 UNUSED */ 000000000000 // Delayed by 0/* 10 UNUSED */ 000000000000 // Delayed by 0/* 11 UNUSED */ 000000000000 // Delayed by 0/* 12 CTRL_AP_COL_CNT_LOAD */ 000100000000 // Delayed by 1/* 13 CTRL_AP_COL_CNT_ENABLE */ 000010000000 // Delayed by 1/* 14 CTRL_AP_PRECHARGE_ADDR10 */ 000000001000 // Delayed by 1/* 15 CTRL_AP_ROW_COL_SEL */ 010000000000 // Delayed by 1/* 16 UNUSED */ 000000000000 // Delayed by 0/* 17 CTRL_REPEAT4 */ 000000000000 // Delayed by 1/* 18 CTRL_DFI_WRDATA_EN */ 000000000000 // Delayed by 2/* 19 CTRL_DFI_RDDATA_EN */ 000010000000 // Delayed by 2/* 20 CTRL_DFI_RAS_N_1 */ 111111110111 // Delayed by 2/* 21 CTRL_DFI_CAS_N_1 */ 111101111111 // Delayed by 2/* 22 CTRL_DFI_WE_N_1 */ 111111110111 // Delayed by 2/* 23 CTRL_AP_OTF_ADDR12 */ 000000000000 // Delayed by 1/* 24 UNUSED */ 000000000000 // Delayed by 0/* 25 UNUSED */ 000000000000 // Delayed by 0/* 26 UNUSED */ 000000000000 // Delayed by 0/* 27 UNUSED */ 000000000000 // Delayed by 0/* 28 UNUSED */ 000000000000 // Delayed by 0/* 29 UNUSED */ 000000000000 // Delayed by 0/* 30 UNUSED */ 000000000000 // Delayed by 0/* 31 UNUSED */ 000000000000 // Delayed by 0/* 32 UNUSED */ 000000000000 // Delayed by 0/* 33 UNUSED */ 000000000000 // Delayed by 0/* 34 UNUSED */ 000000000000 // Delayed by 0/* 35 UNUSED */ 000000000000 // Delayed by 0//--------------------------------------------------------------------------//// FSM PATTERN 2: DOUBLE WORD WRITE//// Control Signals 0 01 2 2// (32 Signals) cdef0123456789ab// --------------- -------------------------------- ------------------------------/* 0 CTRL_COMPLETE */ 0000000000100000 // Delayed by 1/* 1 CTRL_IS_WRITE */ 1111111111111111 // Delayed by 1/* 2 CTRL_DFI_RAS_N_0 */ 1011111111110111 // Delayed by 2/* 3 CTRL_DFI_CAS_N_0 */ 1111111111111111 // Delayed by 2/* 4 CTRL_DFI_WE_N_0 */ 1111111111110111 // Delayed by 2/* 5 UNUSED */ 0000000000000000 // Delayed by 0/* 6 UNUSED */ 0000000000000000 // Delayed by 0/* 7 UNUSED */ 0000000000000000 // Delayed by 0/* 8 CTRL_DP_WRFIFO_POP */ 0010000000000000 // Delayed by 1/* 9 UNUSED */ 0000000000000000 // Delayed by 0/* 10 UNUSED */ 0000000000000000 // Delayed by 0/* 11 UNUSED */ 0000000000000000 // Delayed by 0/* 12 CTRL_AP_COL_CNT_LOAD */ 0001000000000000 // Delayed by 1/* 13 CTRL_AP_COL_CNT_ENABLE */ 0000100000000000 // Delayed by 1/* 14 CTRL_AP_PRECHARGE_ADDR10 */ 0000000000001000 // Delayed by 1/* 15 CTRL_AP_ROW_COL_SEL */ 0100000000000000 // Delayed by 1/* 16 UNUSED */ 0000000000000000 // Delayed by 0/* 17 CTRL_REPEAT4 */ 0000000000000000 // Delayed by 1/* 18 CTRL_DFI_WRDATA_EN */ 0000100000000000 // Delayed by 2/* 19 CTRL_DFI_RDDATA_EN */ 0000000000000000 // Delayed by 2/* 20 CTRL_DFI_RAS_N_1 */ 1111111111111111 // Delayed by 2/* 21 CTRL_DFI_CAS_N_1 */ 1111011111111111 // Delayed by 2/* 22 CTRL_DFI_WE_N_1 */ 1111011111111111 // Delayed by 2/* 23 CTRL_AP_OTF_ADDR12 */ 0000000000000000 // Delayed by 1/* 24 UNUSED */ 0000000000000000 // Delayed by 0/* 25 UNUSED */ 0000000000000000 // Delayed by 0/* 26 UNUSED */ 0000000000000000 // Delayed by 0/* 27 UNUSED */ 0000000000000000 // Delayed by 0/* 28 UNUSED */ 0000000000000000 // Delayed by 0/* 29 UNUSED */ 0000000000000000 // Delayed by 0/* 30 UNUSED */ 0000000000000000 // Delayed by 0/* 31 UNUSED */ 0000000000000000 // Delayed by 0/* 32 UNUSED */ 0000000000000000 // Delayed by 0/* 33 UNUSED */ 0000000000000000 // Delayed by 0/* 34 UNUSED */ 0000000000000000 // Delayed by 0/* 35 UNUSED */ 0000000000000000 // Delayed by 0//--------------------------------------------------------------------------//// FSM PATTERN 3: DOUBLE WORD READ//// Control Signals 0 02 3 3// (32 Signals) cdef01234567// --------------- -------------------------------- ------------------------------/* 0 CTRL_COMPLETE */ 000000100000 // Delayed by 1/* 1 CTRL_IS_WRITE */ 000000000000 // Delayed by 1/* 2 CTRL_DFI_RAS_N_0 */ 101111111111 // Delayed by 2/* 3 CTRL_DFI_CAS_N_0 */ 111111111111 // Delayed by 2/* 4 CTRL_DFI_WE_N_0 */ 111111111111 // Delayed by 2/* 5 UNUSED */ 000000000000 // Delayed by 0/* 6 UNUSED */ 000000000000 // Delayed by 0/* 7 UNUSED */ 000000000000 // Delayed by 0/* 8 CTRL_DP_WRFIFO_POP */ 000000000000 // Delayed by 1/* 9 UNUSED */ 000000000000 // Delayed by 0/* 10 UNUSED */ 000000000000 // Delayed by 0/* 11 UNUSED */ 000000000000 // Delayed by 0/* 12 CTRL_AP_COL_CNT_LOAD */ 000100000000 // Delayed by 1/* 13 CTRL_AP_COL_CNT_ENABLE */ 000010000000 // Delayed by 1/* 14 CTRL_AP_PRECHARGE_ADDR10 */ 000000001000 // Delayed by 1/* 15 CTRL_AP_ROW_COL_SEL */ 010000000000 // Delayed by 1/* 16 UNUSED */ 000000000000 // Delayed by 0/* 17 CTRL_REPEAT4 */ 000000000000 // Delayed by 1/* 18 CTRL_DFI_WRDATA_EN */ 000000000000 // Delayed by 2/* 19 CTRL_DFI_RDDATA_EN */ 000010000000 // Delayed by 2/* 20 CTRL_DFI_RAS_N_1 */ 111111110111 // Delayed by 2/* 21 CTRL_DFI_CAS_N_1 */ 111101111111 // Delayed by 2/* 22 CTRL_DFI_WE_N_1 */ 111111110111 // Delayed by 2/* 23 CTRL_AP_OTF_ADDR12 */ 000000000000 // Delayed by 1/* 24 UNUSED */ 000000000000 // Delayed by 0/* 25 UNUSED */ 000000000000 // Delayed by 0/* 26 UNUSED */ 000000000000 // Delayed by 0/* 27 UNUSED */ 000000000000 // Delayed by 0/* 28 UNUSED */ 000000000000 // Delayed by 0/* 29 UNUSED */ 000000000000 // Delayed by 0/* 30 UNUSED */ 000000000000 // Delayed by 0/* 31 UNUSED */ 000000000000 // Delayed by 0/* 32 UNUSED */ 000000000000 // Delayed by 0/* 33 UNUSED */ 000000000000 // Delayed by 0/* 34 UNUSED */ 000000000000 // Delayed by 0/* 35 UNUSED */ 000000000000 // Delayed by 0//--------------------------------------------------------------------------//// FSM PATTERN 4: CACHELINE 4 WRITE//// Control Signals 0 03 4 4// (32 Signals) 89abcdef01234567// --------------- -------------------------------- ------------------------------/* 0 CTRL_COMPLETE */ 0000000000100000 // Delayed by 1/* 1 CTRL_IS_WRITE */ 1111111111111111 // Delayed by 1/* 2 CTRL_DFI_RAS_N_0 */ 1011111111110111 // Delayed by 2/* 3 CTRL_DFI_CAS_N_0 */ 1111111111111111 // Delayed by 2/* 4 CTRL_DFI_WE_N_0 */ 1111111111110111 // Delayed by 2/* 5 UNUSED */ 0000000000000000 // Delayed by 0/* 6 UNUSED */ 0000000000000000 // Delayed by 0/* 7 UNUSED */ 0000000000000000 // Delayed by 0/* 8 CTRL_DP_WRFIFO_POP */ 0010000000000000 // Delayed by 1/* 9 UNUSED */ 0000000000000000 // Delayed by 0/* 10 UNUSED */ 0000000000000000 // Delayed by 0/* 11 UNUSED */ 0000000000000000 // Delayed by 0/* 12 CTRL_AP_COL_CNT_LOAD */ 0001000000000000 // Delayed by 1/* 13 CTRL_AP_COL_CNT_ENABLE */ 0000110000000000 // Delayed by 1/* 14 CTRL_AP_PRECHARGE_ADDR10 */ 0000000000001000 // Delayed by 1/* 15 CTRL_AP_ROW_COL_SEL */ 0100000000000000 // Delayed by 1/* 16 UNUSED */ 0000000000000000 // Delayed by 0/* 17 CTRL_REPEAT4 */ 0000000000000000 // Delayed by 1/* 18 CTRL_DFI_WRDATA_EN */ 0000100000000000 // Delayed by 2/* 19 CTRL_DFI_RDDATA_EN */ 0000000000000000 // Delayed by 2/* 20 CTRL_DFI_RAS_N_1 */ 1111111111111111 // Delayed by 2/* 21 CTRL_DFI_CAS_N_1 */ 1111011111111111 // Delayed by 2/* 22 CTRL_DFI_WE_N_1 */ 1111011111111111 // Delayed by 2/* 23 CTRL_AP_OTF_ADDR12 */ 0000000000000000 // Delayed by 1/* 24 UNUSED */ 0000000000000000 // Delayed by 0/* 25 UNUSED */ 0000000000000000 // Delayed by 0/* 26 UNUSED */ 0000000000000000 // Delayed by 0/* 27 UNUSED */ 0000000000000000 // Delayed by 0/* 28 UNUSED */ 0000000000000000 // Delayed by 0/* 29 UNUSED */ 0000000000000000 // Delayed by 0/* 30 UNUSED */ 0000000000000000 // Delayed by 0/* 31 UNUSED */ 0000000000000000 // Delayed by 0/* 32 UNUSED */ 0000000000000000 // Delayed by 0/* 33 UNUSED */ 0000000000000000 // Delayed by 0/* 34 UNUSED */ 0000000000000000 // Delayed by 0/* 35 UNUSED */ 0000000000000000 // Delayed by 0//--------------------------------------------------------------------------//// FSM PATTERN 5: CACHELINE 4 READ//// Control Signals 0 04 5 5// (32 Signals) 89abcdef0123// --------------- -------------------------------- ------------------------------/* 0 CTRL_COMPLETE */ 000000100000 // Delayed by 1/* 1 CTRL_IS_WRITE */ 000000000000 // Delayed by 1/* 2 CTRL_DFI_RAS_N_0 */ 101111111111 // Delayed by 2/* 3 CTRL_DFI_CAS_N_0 */ 111111111111 // Delayed by 2/* 4 CTRL_DFI_WE_N_0 */ 111111111111 // Delayed by 2/* 5 UNUSED */ 000000000000 // Delayed by 0/* 6 UNUSED */ 000000000000 // Delayed by 0/* 7 UNUSED */ 000000000000 // Delayed by 0/* 8 CTRL_DP_WRFIFO_POP */ 000000000000 // Delayed by 1/* 9 UNUSED */ 000000000000 // Delayed by 0/* 10 UNUSED */ 000000000000 // Delayed by 0/* 11 UNUSED */ 000000000000 // Delayed by 0/* 12 CTRL_AP_COL_CNT_LOAD */ 000100000000 // Delayed by 1/* 13 CTRL_AP_COL_CNT_ENABLE */ 000010000000 // Delayed by 1/* 14 CTRL_AP_PRECHARGE_ADDR10 */ 000000001000 // Delayed by 1/* 15 CTRL_AP_ROW_COL_SEL */ 010000000000 // Delayed by 1/* 16 UNUSED */ 000000000000 // Delayed by 0/* 17 CTRL_REPEAT4 */ 000000000000 // Delayed by 1/* 18 CTRL_DFI_WRDATA_EN */ 000000000000 // Delayed by 2/* 19 CTRL_DFI_RDDATA_EN */ 000010000000 // Delayed by 2/* 20 CTRL_DFI_RAS_N_1 */ 111111110111 // Delayed by 2/* 21 CTRL_DFI_CAS_N_1 */ 111101111111 // Delayed by 2/* 22 CTRL_DFI_WE_N_1 */ 111111110111 // Delayed by 2/* 23 CTRL_AP_OTF_ADDR12 */ 000000000000 // Delayed by 1/* 24 UNUSED */ 000000000000 // Delayed by 0/* 25 UNUSED */ 000000000000 // Delayed by 0/* 26 UNUSED */ 000000000000 // Delayed by 0/* 27 UNUSED */ 000000000000 // Delayed by 0/* 28 UNUSED */ 000000000000 // Delayed by 0/* 29 UNUSED */ 000000000000 // Delayed by 0/* 30 UNUSED */ 000000000000 // Delayed by 0/* 31 UNUSED */ 000000000000 // Delayed by 0/* 32 UNUSED */ 000000000000 // Delayed by 0/* 33 UNUSED */ 000000000000 // Delayed by 0/* 34 UNUSED */ 000000000000 // Delayed by 0/* 35 UNUSED */ 000000000000 // Delayed by 0//--------------------------------------------------------------------------//// FSM PATTERN 6: CACHELINE 8 WRITE//// Control Signals 0 05 6 6// (32 Signals) 456789abcdef0123// --------------- -------------------------------- ------------------------------/* 0 CTRL_COMPLETE */ 0000000000100000 // Delayed by 1/* 1 CTRL_IS_WRITE */ 1111111111111111 // Delayed by 1/* 2 CTRL_DFI_RAS_N_0 */ 1011111111110111 // Delayed by 2/* 3 CTRL_DFI_CAS_N_0 */ 1111111111111111 // Delayed by 2/* 4 CTRL_DFI_WE_N_0 */ 1111111111110111 // Delayed by 2/* 5 UNUSED */ 0000000000000000 // Delayed by 0/* 6 UNUSED */ 0000000000000000 // Delayed by 0/* 7 UNUSED */ 0000000000000000 // Delayed by 0/* 8 CTRL_DP_WRFIFO_POP */ 0011000000000000 // Delayed by 1/* 9 UNUSED */ 0000000000000000 // Delayed by 0/* 10 UNUSED */ 0000000000000000 // Delayed by 0/* 11 UNUSED */ 0000000000000000 // Delayed by 0/* 12 CTRL_AP_COL_CNT_LOAD */ 0001000000000000 // Delayed by 1/* 13 CTRL_AP_COL_CNT_ENABLE */ 0000101000000000 // Delayed by 1/* 14 CTRL_AP_PRECHARGE_ADDR10 */ 0000000000001000 // Delayed by 1/* 15 CTRL_AP_ROW_COL_SEL */ 0100000000000000 // Delayed by 1/* 16 UNUSED */ 0000000000000000 // Delayed by 0/* 17 CTRL_REPEAT4 */ 0000000000000000 // Delayed by 1/* 18 CTRL_DFI_WRDATA_EN */ 0000110000000000 // Delayed by 2/* 19 CTRL_DFI_RDDATA_EN */ 0000000000000000 // Delayed by 2/* 20 CTRL_DFI_RAS_N_1 */ 1111111111111111 // Delayed by 2/* 21 CTRL_DFI_CAS_N_1 */ 1111011111111111 // Delayed by 2/* 22 CTRL_DFI_WE_N_1 */ 1111011111111111 // Delayed by 2/* 23 CTRL_AP_OTF_ADDR12 */ 0000100000000000 // Delayed by 1/* 24 UNUSED */ 0000000000000000 // Delayed by 0/* 25 UNUSED */ 0000000000000000 // Delayed by 0/* 26 UNUSED */ 0000000000000000 // Delayed by 0/* 27 UNUSED */ 0000000000000000 // Delayed by 0/* 28 UNUSED */ 0000000000000000 // Delayed by 0/* 29 UNUSED */ 0000000000000000 // Delayed by 0/* 30 UNUSED */ 0000000000000000 // Delayed by 0/* 31 UNUSED */ 0000000000000000 // Delayed by 0/* 32 UNUSED */ 0000000000000000 // Delayed by 0/* 33 UNUSED */ 0000000000000000 // Delayed by 0/* 34 UNUSED */ 0000000000000000 // Delayed by 0/* 35 UNUSED */ 0000000000000000 // Delayed by 0//--------------------------------------------------------------------------//// FSM PATTERN 7: CACHELINE 8 READ//// Control Signals 0 06 6// (32 Signals) 456789abcdef// --------------- -------------------------------- ------------------------------/* 0 CTRL_COMPLETE */ 000000100000 // Delayed by 1/* 1 CTRL_IS_WRITE */ 000000000000 // Delayed by 1/* 2 CTRL_DFI_RAS_N_0 */ 101111111111 // Delayed by 2/* 3 CTRL_DFI_CAS_N_0 */ 111111111111 // Delayed by 2/* 4 CTRL_DFI_WE_N_0 */ 111111111111 // Delayed by 2/* 5 UNUSED */ 000000000000 // Delayed by 0/* 6 UNUSED */ 000000000000 // Delayed by 0/* 7 UNUSED */ 000000000000 // Delayed by 0/* 8 CTRL_DP_WRFIFO_POP */ 000000000000 // Delayed by 1/* 9 UNUSED */ 000000000000 // Delayed by 0/* 10 UNUSED */ 000000000000 // Delayed by 0/* 11 UNUSED */ 000000000000 // Delayed by 0/* 12 CTRL_AP_COL_CNT_LOAD */ 000100000000 // Delayed by 1/* 13 CTRL_AP_COL_CNT_ENABLE */ 000010000000 // Delayed by 1/* 14 CTRL_AP_PRECHARGE_ADDR10 */ 000000001000 // Delayed by 1/* 15 CTRL_AP_ROW_COL_SEL */ 010000000000 // Delayed by 1/* 16 UNUSED */ 000000000000 // Delayed by 0/* 17 CTRL_REPEAT4 */ 000000000000 // Delayed by 1/* 18 CTRL_DFI_WRDATA_EN */ 000000000000 // Delayed by 2/* 19 CTRL_DFI_RDDATA_EN */ 000011000000 // Delayed by 2/* 20 CTRL_DFI_RAS_N_1 */ 111111110111 // Delayed by 2/* 21 CTRL_DFI_CAS_N_1 */ 111101111111 // Delayed by 2/* 22 CTRL_DFI_WE_N_1 */ 111111110111 // Delayed by 2/* 23 CTRL_AP_OTF_ADDR12 */ 000010000000 // Delayed by 1/* 24 UNUSED */ 000000000000 // Delayed by 0/* 25 UNUSED */ 000000000000 // Delayed by 0/* 26 UNUSED */ 000000000000 // Delayed by 0/* 27 UNUSED */ 000000000000 // Delayed by 0/* 28 UNUSED */ 000000000000 // Delayed by 0/* 29 UNUSED */ 000000000000 // Delayed by 0/* 30 UNUSED */ 000000000000 // Delayed by 0/* 31 UNUSED */ 000000000000 // Delayed by 0/* 32 UNUSED */ 000000000000 // Delayed by 0/* 33 UNUSED */ 000000000000 // Delayed by 0/* 34 UNUSED */ 000000000000 // Delayed by 0/* 35 UNUSED */ 000000000000 // Delayed by 0//--------------------------------------------------------------------------//// FSM PATTERN 8: BURST 16 WRITE//// Control Signals 0 07 88// (32 Signals) 0123456789abcdef01// --------------- -------------------------------- ------------------------------/* 0 CTRL_COMPLETE */ 000000000000100000 // Delayed by 1/* 1 CTRL_IS_WRITE */ 111111111111111111 // Delayed by 1/* 2 CTRL_DFI_RAS_N_0 */ 101111111111110111 // Delayed by 2/* 3 CTRL_DFI_CAS_N_0 */ 111111111111111111 // Delayed by 2/* 4 CTRL_DFI_WE_N_0 */ 111111111111110111 // Delayed by 2/* 5 UNUSED */ 000000000000000000 // Delayed by 0/* 6 UNUSED */ 000000000000000000 // Delayed by 0/* 7 UNUSED */ 000000000000000000 // Delayed by 0/* 8 CTRL_DP_WRFIFO_POP */ 001111000000000000 // Delayed by 1/* 9 UNUSED */ 000000000000000000 // Delayed by 0/* 10 UNUSED */ 000000000000000000 // Delayed by 0/* 11 UNUSED */ 000000000000000000 // Delayed by 0/* 12 CTRL_AP_COL_CNT_LOAD */ 000100000000000000 // Delayed by 1/* 13 CTRL_AP_COL_CNT_ENABLE */ 000010101000000000 // Delayed by 1/* 14 CTRL_AP_PRECHARGE_ADDR10 */ 000000000000001000 // Delayed by 1/* 15 CTRL_AP_ROW_COL_SEL */ 010000000000000000 // Delayed by 1/* 16 UNUSED */ 000000000000000000 // Delayed by 0/* 17 CTRL_REPEAT4 */ 000000000000000000 // Delayed by 1/* 18 CTRL_DFI_WRDATA_EN */ 000011110000000000 // Delayed by 2/* 19 CTRL_DFI_RDDATA_EN */ 000000000000000000 // Delayed by 2/* 20 CTRL_DFI_RAS_N_1 */ 111111111111111111 // Delayed by 2/* 21 CTRL_DFI_CAS_N_1 */ 111101011111111111 // Delayed by 2/* 22 CTRL_DFI_WE_N_1 */ 111101011111111111 // Delayed by 2/* 23 CTRL_AP_OTF_ADDR12 */ 000010100000000000 // Delayed by 1/* 24 UNUSED */ 000000000000000000 // Delayed by 0/* 25 UNUSED */ 000000000000000000 // Delayed by 0/* 26 UNUSED */ 000000000000000000 // Delayed by 0/* 27 UNUSED */ 000000000000000000 // Delayed by 0/* 28 UNUSED */ 000000000000000000 // Delayed by 0/* 29 UNUSED */ 000000000000000000 // Delayed by 0/* 30 UNUSED */ 000000000000000000 // Delayed by 0/* 31 UNUSED */ 000000000000000000 // Delayed by 0/* 32 UNUSED */ 000000000000000000 // Delayed by 0/* 33 UNUSED */ 000000000000000000 // Delayed by 0/* 34 UNUSED */ 000000000000000000 // Delayed by 0/* 35 UNUSED */ 000000000000000000 // Delayed by 0//--------------------------------------------------------------------------//// FSM PATTERN 9: BURST 16 READ//// Control Signals 0 08 8// (32 Signals) 23456789abcde// --------------- -------------------------------- ------------------------------/* 0 CTRL_COMPLETE */ 0000000100000 // Delayed by 1/* 1 CTRL_IS_WRITE */ 0000000000000 // Delayed by 1/* 2 CTRL_DFI_RAS_N_0 */ 1011111111111 // Delayed by 2/* 3 CTRL_DFI_CAS_N_0 */ 1111111111111 // Delayed by 2/* 4 CTRL_DFI_WE_N_0 */ 1111111111111 // Delayed by 2/* 5 UNUSED */ 0000000000000 // Delayed by 0/* 6 UNUSED */ 0000000000000 // Delayed by 0/* 7 UNUSED */ 0000000000000 // Delayed by 0/* 8 CTRL_DP_WRFIFO_POP */ 0000000000000 // Delayed by 1/* 9 UNUSED */ 0000000000000 // Delayed by 0/* 10 UNUSED */ 0000000000000 // Delayed by 0/* 11 UNUSED */ 0000000000000 // Delayed by 0/* 12 CTRL_AP_COL_CNT_LOAD */ 0001000000000 // Delayed by 1/* 13 CTRL_AP_COL_CNT_ENABLE */ 0000101000000 // Delayed by 1/* 14 CTRL_AP_PRECHARGE_ADDR10 */ 0000000010000 // Delayed by 1/* 15 CTRL_AP_ROW_COL_SEL */ 0100000000000 // Delayed by 1/* 16 UNUSED */ 0000000000000 // Delayed by 0/* 17 CTRL_REPEAT4 */ 0000000000000 // Delayed by 1/* 18 CTRL_DFI_WRDATA_EN */ 0000000000000 // Delayed by 2/* 19 CTRL_DFI_RDDATA_EN */ 0000111100000 // Delayed by 2/* 20 CTRL_DFI_RAS_N_1 */ 1111111101111 // Delayed by 2/* 21 CTRL_DFI_CAS_N_1 */ 1111010111111 // Delayed by 2/* 22 CTRL_DFI_WE_N_1 */ 1111111101111 // Delayed by 2/* 23 CTRL_AP_OTF_ADDR12 */ 0000101000000 // Delayed by 1/* 24 UNUSED */ 0000000000000 // Delayed by 0/* 25 UNUSED */ 0000000000000 // Delayed by 0/* 26 UNUSED */ 0000000000000 // Delayed by 0/* 27 UNUSED */ 0000000000000 // Delayed by 0/* 28 UNUSED */ 0000000000000 // Delayed by 0/* 29 UNUSED */ 0000000000000 // Delayed by 0/* 30 UNUSED */ 0000000000000 // Delayed by 0/* 31 UNUSED */ 0000000000000 // Delayed by 0/* 32 UNUSED */ 0000000000000 // Delayed by 0/* 33 UNUSED */ 0000000000000 // Delayed by 0/* 34 UNUSED */ 0000000000000 // Delayed by 0/* 35 UNUSED */ 0000000000000 // Delayed by 0//--------------------------------------------------------------------------//// FSM PATTERN 10: BURST 32 WRITE//// Control Signals 0 089 a a// (32 Signals) f0123456789abcdef01234// --------------- -------------------------------- ------------------------------/* 0 CTRL_COMPLETE */ 0000000000000000100000 // Delayed by 1/* 1 CTRL_IS_WRITE */ 1111111111111111111111 // Delayed by 1/* 2 CTRL_DFI_RAS_N_0 */ 1011111111111111110111 // Delayed by 2/* 3 CTRL_DFI_CAS_N_0 */ 1111111111111111111111 // Delayed by 2/* 4 CTRL_DFI_WE_N_0 */ 1111111111111111110111 // Delayed by 2/* 5 UNUSED */ 0000000000000000000000 // Delayed by 0/* 6 UNUSED */ 0000000000000000000000 // Delayed by 0/* 7 UNUSED */ 0000000000000000000000 // Delayed by 0/* 8 CTRL_DP_WRFIFO_POP */ 0011111111000000000000 // Delayed by 1/* 9 UNUSED */ 0000000000000000000000 // Delayed by 0/* 10 UNUSED */ 0000000000000000000000 // Delayed by 0/* 11 UNUSED */ 0000000000000000000000 // Delayed by 0/* 12 CTRL_AP_COL_CNT_LOAD */ 0001000000000000000000 // Delayed by 1/* 13 CTRL_AP_COL_CNT_ENABLE */ 0000101010101000000000 // Delayed by 1/* 14 CTRL_AP_PRECHARGE_ADDR10 */ 0000000000000000001000 // Delayed by 1/* 15 CTRL_AP_ROW_COL_SEL */ 0100000000000000000000 // Delayed by 1/* 16 UNUSED */ 0000000000000000000000 // Delayed by 0/* 17 CTRL_REPEAT4 */ 0000000000000000000000 // Delayed by 1/* 18 CTRL_DFI_WRDATA_EN */ 0000111111110000000000 // Delayed by 2/* 19 CTRL_DFI_RDDATA_EN */ 0000000000000000000000 // Delayed by 2/* 20 CTRL_DFI_RAS_N_1 */ 1111111111111111111111 // Delayed by 2/* 21 CTRL_DFI_CAS_N_1 */ 1111010101011111111111 // Delayed by 2/* 22 CTRL_DFI_WE_N_1 */ 1111010101011111111111 // Delayed by 2/* 23 CTRL_AP_OTF_ADDR12 */ 0000101010100000000000 // Delayed by 1/* 24 UNUSED */ 0000000000000000000000 // Delayed by 0/* 25 UNUSED */ 0000000000000000000000 // Delayed by 0/* 26 UNUSED */ 0000000000000000000000 // Delayed by 0/* 27 UNUSED */ 0000000000000000000000 // Delayed by 0/* 28 UNUSED */ 0000000000000000000000 // Delayed by 0/* 29 UNUSED */ 0000000000000000000000 // Delayed by 0/* 30 UNUSED */ 0000000000000000000000 // Delayed by 0/* 31 UNUSED */ 0000000000000000000000 // Delayed by 0/* 32 UNUSED */ 0000000000000000000000 // Delayed by 0/* 33 UNUSED */ 0000000000000000000000 // Delayed by 0/* 34 UNUSED */ 0000000000000000000000 // Delayed by 0/* 35 UNUSED */ 0000000000000000000000 // Delayed by 0//--------------------------------------------------------------------------//// FSM PATTERN 11: BURST 32 READ//// Control Signals 0 0a b b// (32 Signals) 56789abcdef012345// --------------- -------------------------------- ------------------------------/* 0 CTRL_COMPLETE */ 00000000000100000 // Delayed by 1/* 1 CTRL_IS_WRITE */ 00000000000000000 // Delayed by 1/* 2 CTRL_DFI_RAS_N_0 */ 10111111111111111 // Delayed by 2/* 3 CTRL_DFI_CAS_N_0 */ 11111111111111111 // Delayed by 2/* 4 CTRL_DFI_WE_N_0 */ 11111111111111111 // Delayed by 2/* 5 UNUSED */ 00000000000000000 // Delayed by 0/* 6 UNUSED */ 00000000000000000 // Delayed by 0/* 7 UNUSED */ 00000000000000000 // Delayed by 0/* 8 CTRL_DP_WRFIFO_POP */ 00000000000000000 // Delayed by 1/* 9 UNUSED */ 00000000000000000 // Delayed by 0/* 10 UNUSED */ 00000000000000000 // Delayed by 0/* 11 UNUSED */ 00000000000000000 // Delayed by 0/* 12 CTRL_AP_COL_CNT_LOAD */ 00010000000000000 // Delayed by 1/* 13 CTRL_AP_COL_CNT_ENABLE */ 00001010101000000 // Delayed by 1/* 14 CTRL_AP_PRECHARGE_ADDR10 */ 00000000000010000 // Delayed by 1/* 15 CTRL_AP_ROW_COL_SEL */ 01000000000000000 // Delayed by 1/* 16 UNUSED */ 00000000000000000 // Delayed by 0/* 17 CTRL_REPEAT4 */ 00000000000000000 // Delayed by 1/* 18 CTRL_DFI_WRDATA_EN */ 00000000000000000 // Delayed by 2/* 19 CTRL_DFI_RDDATA_EN */ 00001111111100000 // Delayed by 2/* 20 CTRL_DFI_RAS_N_1 */ 11111111111101111 // Delayed by 2/* 21 CTRL_DFI_CAS_N_1 */ 11110101010111111 // Delayed by 2/* 22 CTRL_DFI_WE_N_1 */ 11111111111101111 // Delayed by 2/* 23 CTRL_AP_OTF_ADDR12 */ 00001010101000000 // Delayed by 1/* 24 UNUSED */ 00000000000000000 // Delayed by 0/* 25 UNUSED */ 00000000000000000 // Delayed by 0/* 26 UNUSED */ 00000000000000000 // Delayed by 0/* 27 UNUSED */ 00000000000000000 // Delayed by 0/* 28 UNUSED */ 00000000000000000 // Delayed by 0/* 29 UNUSED */ 00000000000000000 // Delayed by 0/* 30 UNUSED */ 00000000000000000 // Delayed by 0/* 31 UNUSED */ 00000000000000000 // Delayed by 0/* 32 UNUSED */ 00000000000000000 // Delayed by 0/* 33 UNUSED */ 00000000000000000 // Delayed by 0/* 34 UNUSED */ 00000000000000000 // Delayed by 0/* 35 UNUSED */ 00000000000000000 // Delayed by 0//--------------------------------------------------------------------------//// FSM PATTERN 12: BURST 64 WRITE//// Control Signals 0 0b c d d// (32 Signals) 6789abcdef0123456789abcdef0123// --------------- -------------------------------- ------------------------------/* 0 CTRL_COMPLETE */ 000000000000000000000000100000 // Delayed by 1/* 1 CTRL_IS_WRITE */ 111111111111111111111111111111 // Delayed by 1/* 2 CTRL_DFI_RAS_N_0 */ 101111111111111111111111110111 // Delayed by 2/* 3 CTRL_DFI_CAS_N_0 */ 111111111111111111111111111111 // Delayed by 2/* 4 CTRL_DFI_WE_N_0 */ 111111111111111111111111110111 // Delayed by 2/* 5 UNUSED */ 000000000000000000000000000000 // Delayed by 0/* 6 UNUSED */ 000000000000000000000000000000 // Delayed by 0/* 7 UNUSED */ 000000000000000000000000000000 // Delayed by 0/* 8 CTRL_DP_WRFIFO_POP */ 001111111111111111000000000000 // Delayed by 1/* 9 UNUSED */ 000000000000000000000000000000 // Delayed by 0/* 10 UNUSED */ 000000000000000000000000000000 // Delayed by 0/* 11 UNUSED */ 000000000000000000000000000000 // Delayed by 0/* 12 CTRL_AP_COL_CNT_LOAD */ 000100000000000000000000000000 // Delayed by 1/* 13 CTRL_AP_COL_CNT_ENABLE */ 000010101010101010101000000000 // Delayed by 1/* 14 CTRL_AP_PRECHARGE_ADDR10 */ 000000000000000000000000001000 // Delayed by 1/* 15 CTRL_AP_ROW_COL_SEL */ 010000000000000000000000000000 // Delayed by 1/* 16 UNUSED */ 000000000000000000000000000000 // Delayed by 0/* 17 CTRL_REPEAT4 */ 000000000000000000000000000000 // Delayed by 1/* 18 CTRL_DFI_WRDATA_EN */ 000011111111111111110000000000 // Delayed by 2/* 19 CTRL_DFI_RDDATA_EN */ 000000000000000000000000000000 // Delayed by 2/* 20 CTRL_DFI_RAS_N_1 */ 111111111111111111111111111111 // Delayed by 2/* 21 CTRL_DFI_CAS_N_1 */ 111101010101010101011111111111 // Delayed by 2/* 22 CTRL_DFI_WE_N_1 */ 111101010101010101011111111111 // Delayed by 2/* 23 CTRL_AP_OTF_ADDR12 */ 000010101010101010100000000000 // Delayed by 1/* 24 UNUSED */ 000000000000000000000000000000 // Delayed by 0/* 25 UNUSED */ 000000000000000000000000000000 // Delayed by 0/* 26 UNUSED */ 000000000000000000000000000000 // Delayed by 0/* 27 UNUSED */ 000000000000000000000000000000 // Delayed by 0/* 28 UNUSED */ 000000000000000000000000000000 // Delayed by 0/* 29 UNUSED */ 000000000000000000000000000000 // Delayed by 0/* 30 UNUSED */ 000000000000000000000000000000 // Delayed by 0/* 31 UNUSED */ 000000000000000000000000000000 // Delayed by 0/* 32 UNUSED */ 000000000000000000000000000000 // Delayed by 0/* 33 UNUSED */ 000000000000000000000000000000 // Delayed by 0/* 34 UNUSED */ 000000000000000000000000000000 // Delayed by 0/* 35 UNUSED */ 000000000000000000000000000000 // Delayed by 0//--------------------------------------------------------------------------//// FSM PATTERN 13: BURST 64 READ//// Control Signals 0 0d e e// (32 Signals) 456789abcdef0123456789abc// --------------- -------------------------------- ------------------------------/* 0 CTRL_COMPLETE */ 0000000000000000000100000 // Delayed by 1/* 1 CTRL_IS_WRITE */ 0000000000000000000000000 // Delayed by 1/* 2 CTRL_DFI_RAS_N_0 */ 1011111111111111111111111 // Delayed by 2/* 3 CTRL_DFI_CAS_N_0 */ 1111111111111111111111111 // Delayed by 2/* 4 CTRL_DFI_WE_N_0 */ 1111111111111111111111111 // Delayed by 2/* 5 UNUSED */ 0000000000000000000000000 // Delayed by 0/* 6 UNUSED */ 0000000000000000000000000 // Delayed by 0/* 7 UNUSED */ 0000000000000000000000000 // Delayed by 0/* 8 CTRL_DP_WRFIFO_POP */ 0000000000000000000000000 // Delayed by 1/* 9 UNUSED */ 0000000000000000000000000 // Delayed by 0/* 10 UNUSED */ 0000000000000000000000000 // Delayed by 0/* 11 UNUSED */ 0000000000000000000000000 // Delayed by 0/* 12 CTRL_AP_COL_CNT_LOAD */ 0001000000000000000000000 // Delayed by 1/* 13 CTRL_AP_COL_CNT_ENABLE */ 0000101010101010101000000 // Delayed by 1/* 14 CTRL_AP_PRECHARGE_ADDR10 */ 0000000000000000000010000 // Delayed by 1/* 15 CTRL_AP_ROW_COL_SEL */ 0100000000000000000000000 // Delayed by 1/* 16 UNUSED */ 0000000000000000000000000 // Delayed by 0/* 17 CTRL_REPEAT4 */ 0000000000000000000000000 // Delayed by 1/* 18 CTRL_DFI_WRDATA_EN */ 0000000000000000000000000 // Delayed by 2/* 19 CTRL_DFI_RDDATA_EN */ 0000111111111111111100000 // Delayed by 2/* 20 CTRL_DFI_RAS_N_1 */ 1111111111111111111101111 // Delayed by 2/* 21 CTRL_DFI_CAS_N_1 */ 1111010101010101010111111 // Delayed by 2/* 22 CTRL_DFI_WE_N_1 */ 1111111111111111111101111 // Delayed by 2/* 23 CTRL_AP_OTF_ADDR12 */ 0000101010101010101000000 // Delayed by 1/* 24 UNUSED */ 0000000000000000000000000 // Delayed by 0/* 25 UNUSED */ 0000000000000000000000000 // Delayed by 0/* 26 UNUSED */ 0000000000000000000000000 // Delayed by 0/* 27 UNUSED */ 0000000000000000000000000 // Delayed by 0/* 28 UNUSED */ 0000000000000000000000000 // Delayed by 0/* 29 UNUSED */ 0000000000000000000000000 // Delayed by 0/* 30 UNUSED */ 0000000000000000000000000 // Delayed by 0/* 31 UNUSED */ 0000000000000000000000000 // Delayed by 0/* 32 UNUSED */ 0000000000000000000000000 // Delayed by 0/* 33 UNUSED */ 0000000000000000000000000 // Delayed by 0/* 34 UNUSED */ 0000000000000000000000000 // Delayed by 0/* 35 UNUSED */ 0000000000000000000000000 // Delayed by 0//--------------------------------------------------------------------------//// FSM PATTERN 14: REFRESH//// Control Signals 0 1 1e f 0 0// (32 Signals) def0123456789abcdef0123456// --------------- -------------------------------- ------------------------------/* 0 CTRL_COMPLETE */ 00000000000000000000100000 // Delayed by 1/* 1 CTRL_IS_WRITE */ 00000000000000000000000000 // Delayed by 1/* 2 CTRL_DFI_RAS_N_0 */ 01111111111111111111111111 // Delayed by 2/* 3 CTRL_DFI_CAS_N_0 */ 11111111111111111111111111 // Delayed by 2/* 4 CTRL_DFI_WE_N_0 */ 01111111111111111111111111 // Delayed by 2/* 5 UNUSED */ 00000000000000000000000000 // Delayed by 0/* 6 UNUSED */ 00000000000000000000000000 // Delayed by 0/* 7 UNUSED */ 00000000000000000000000000 // Delayed by 0/* 8 CTRL_DP_WRFIFO_POP */ 00000000000000000000000000 // Delayed by 1/* 9 UNUSED */ 00000000000000000000000000 // Delayed by 0/* 10 UNUSED */ 00000000000000000000000000 // Delayed by 0/* 11 UNUSED */ 00000000000000000000000000 // Delayed by 0/* 12 CTRL_AP_COL_CNT_LOAD */ 00000000000000000000000000 // Delayed by 1/* 13 CTRL_AP_COL_CNT_ENABLE */ 00000000000000000000000000 // Delayed by 1/* 14 CTRL_AP_PRECHARGE_ADDR10 */ 10000000000000000000000000 // Delayed by 1/* 15 CTRL_AP_ROW_COL_SEL */ 00000000000000000000000000 // Delayed by 1/* 16 UNUSED */ 00000000000000000000000000 // Delayed by 0/* 17 CTRL_REPEAT4 */ 00000000000000000000000000 // Delayed by 1/* 18 CTRL_DFI_WRDATA_EN */ 00000000000000000000000000 // Delayed by 2/* 19 CTRL_DFI_RDDATA_EN */ 00000000000000000000000000 // Delayed by 2/* 20 CTRL_DFI_RAS_N_1 */ 11101111111111111111111111 // Delayed by 2/* 21 CTRL_DFI_CAS_N_1 */ 11101111111111111111111111 // Delayed by 2/* 22 CTRL_DFI_WE_N_1 */ 11111111111111111111111111 // Delayed by 2/* 23 CTRL_AP_OTF_ADDR12 */ 00000000000000000000000000 // Delayed by 1/* 24 UNUSED */ 00000000000000000000000000 // Delayed by 0/* 25 UNUSED */ 00000000000000000000000000 // Delayed by 0/* 26 UNUSED */ 00000000000000000000000000 // Delayed by 0/* 27 UNUSED */ 00000000000000000000000000 // Delayed by 0/* 28 UNUSED */ 00000000000000000000000000 // Delayed by 0/* 29 UNUSED */ 00000000000000000000000000 // Delayed by 0/* 30 UNUSED */ 00000000000000000000000000 // Delayed by 0/* 31 UNUSED */ 00000000000000000000000000 // Delayed by 0/* 32 UNUSED */ 00000000000000000000000000 // Delayed by 0/* 33 UNUSED */ 00000000000000000000000000 // Delayed by 0/* 34 UNUSED */ 00000000000000000000000000 // Delayed by 0/* 35 UNUSED */ 00000000000000000000000000 // Delayed by 0//--------------------------------------------------------------------------//// FSM PATTERN 15: NOP//// Control Signals 10// (32 Signals) 7// --------------- -------------------------------- ------------------------------/* 0 CTRL_COMPLETE */ 0 // Delayed by 1/* 1 CTRL_IS_WRITE */ 0 // Delayed by 1/* 2 CTRL_DFI_RAS_N_0 */ 1 // Delayed by 2/* 3 CTRL_DFI_CAS_N_0 */ 1 // Delayed by 2/* 4 CTRL_DFI_WE_N_0 */ 1 // Delayed by 2/* 5 UNUSED */ 0 // Delayed by 0/* 6 UNUSED */ 0 // Delayed by 0/* 7 UNUSED */ 0 // Delayed by 0/* 8 CTRL_DP_WRFIFO_POP */ 0 // Delayed by 1/* 9 UNUSED */ 0 // Delayed by 0/* 10 UNUSED */ 0 // Delayed by 0/* 11 UNUSED */ 0 // Delayed by 0/* 12 CTRL_AP_COL_CNT_LOAD */ 0 // Delayed by 1/* 13 CTRL_AP_COL_CNT_ENABLE */ 0 // Delayed by 1/* 14 CTRL_AP_PRECHARGE_ADDR10 */ 0 // Delayed by 1/* 15 CTRL_AP_ROW_COL_SEL */ 0 // Delayed by 1/* 16 UNUSED */ 0 // Delayed by 0/* 17 CTRL_REPEAT4 */ 0 // Delayed by 1/* 18 CTRL_DFI_WRDATA_EN */ 0 // Delayed by 2/* 19 CTRL_DFI_RDDATA_EN */ 0 // Delayed by 2/* 20 CTRL_DFI_RAS_N_1 */ 1 // Delayed by 2/* 21 CTRL_DFI_CAS_N_1 */ 1 // Delayed by 2/* 22 CTRL_DFI_WE_N_1 */ 1 // Delayed by 2/* 23 CTRL_AP_OTF_ADDR12 */ 0 // Delayed by 1/* 24 UNUSED */ 0 // Delayed by 0/* 25 UNUSED */ 0 // Delayed by 0/* 26 UNUSED */ 0 // Delayed by 0/* 27 UNUSED */ 0 // Delayed by 0/* 28 UNUSED */ 0 // Delayed by 0/* 29 UNUSED */ 0 // Delayed by 0/* 30 UNUSED */ 0 // Delayed by 0/* 31 UNUSED */ 0 // Delayed by 0/* 32 UNUSED */ 0 // Delayed by 0/* 33 UNUSED */ 0 // Delayed by 0/* 34 UNUSED */ 0 // Delayed by 0/* 35 UNUSED */ 0 // Delayed by 0//--------------------------------------------------------------------------//// FSM PATTERN 16: ZQCS//// Control Signals 1 10 1// (32 Signals) 89abcdef0// --------------- -------------------------------- ------------------------------/* 0 CTRL_COMPLETE */ 000100000 // Delayed by 1/* 1 CTRL_IS_WRITE */ 000000000 // Delayed by 1/* 2 CTRL_DFI_RAS_N_0 */ 111111111 // Delayed by 2/* 3 CTRL_DFI_CAS_N_0 */ 111111111 // Delayed by 2/* 4 CTRL_DFI_WE_N_0 */ 011111111 // Delayed by 2/* 5 UNUSED */ 000000000 // Delayed by 0/* 6 UNUSED */ 000000000 // Delayed by 0/* 7 UNUSED */ 000000000 // Delayed by 0/* 8 CTRL_DP_WRFIFO_POP */ 000000000 // Delayed by 1/* 9 UNUSED */ 000000000 // Delayed by 0/* 10 UNUSED */ 000000000 // Delayed by 0/* 11 UNUSED */ 000000000 // Delayed by 0/* 12 CTRL_AP_COL_CNT_LOAD */ 000000000 // Delayed by 1/* 13 CTRL_AP_COL_CNT_ENABLE */ 000000000 // Delayed by 1/* 14 CTRL_AP_PRECHARGE_ADDR10 */ 000000000 // Delayed by 1/* 15 CTRL_AP_ROW_COL_SEL */ 000000000 // Delayed by 1/* 16 UNUSED */ 000000000 // Delayed by 0/* 17 CTRL_REPEAT4 */ 010000000 // Delayed by 1/* 18 CTRL_DFI_WRDATA_EN */ 000000000 // Delayed by 2/* 19 CTRL_DFI_RDDATA_EN */ 000000000 // Delayed by 2/* 20 CTRL_DFI_RAS_N_1 */ 111111111 // Delayed by 2/* 21 CTRL_DFI_CAS_N_1 */ 111111111 // Delayed by 2/* 22 CTRL_DFI_WE_N_1 */ 111111111 // Delayed by 2/* 23 CTRL_AP_OTF_ADDR12 */ 000000000 // Delayed by 1/* 24 UNUSED */ 000000000 // Delayed by 0/* 25 UNUSED */ 000000000 // Delayed by 0/* 26 UNUSED */ 000000000 // Delayed by 0/* 27 UNUSED */ 000000000 // Delayed by 0/* 28 UNUSED */ 000000000 // Delayed by 0/* 29 UNUSED */ 000000000 // Delayed by 0/* 30 UNUSED */ 000000000 // Delayed by 0/* 31 UNUSED */ 000000000 // Delayed by 0/* 32 UNUSED */ 000000000 // Delayed by 0/* 33 UNUSED */ 000000000 // Delayed by 0/* 34 UNUSED */ 000000000 // Delayed by 0/* 35 UNUSED */ 000000000 // Delayed by 0