Subversion Repositories sata_controller_core

###################################################################
##
## Name     : npi_core
## Desc     : Microprocessor Peripheral Description
##          : Automatically generated by PsfUtility
##
###################################################################

BEGIN npi_core

## Peripheral Options
OPTION IPTYPE = PERIPHERAL
OPTION IMP_NETLIST = TRUE
OPTION HDL = VHDL
OPTION IP_GROUP = MICROBLAZE:PPC:USER
OPTION DESC = NPI_CORE
OPTION STYLE = MIX

## Native Port Interface for MPMC 
BUS_INTERFACE BUS = XIL_NPI,   BUS_STD = XIL_NPI,     BUS_TYPE = INITIATOR

## Generics
PARAMETER CHIPSCOPE        = false, DT = boolean
PARAMETER RAM_OFFSET       = 0x00,  DT = std_logic_vector
PARAMETER BLOCK_SIZE       = 1024,  DT = integer

## ChipScope ILA Controllers
PORT npi_if_ila_control    = "", DIR = I, VEC = [35:0]
PORT npi_if_tx_ila_control    = "", DIR = I, VEC = [35:0]
PORT npi_ila_control       = "", DIR = I, VEC = [35:0]

## Clock and Reset Signals
PORT MPMC_Clk           = "", DIR = I
PORT user_clk           = "", DIR = I
PORT reset              = "", DIR = I

PORT NPI_CORE_DIN       = "", DIR = I, VEC = [31:0]
PORT NPI_CORE_WE        = "", DIR = I
PORT NPI_CORE_FULL      = "", DIR = O
PORT NPI_CORE_DOUT      = "", DIR = O, VEC = [31:0]
PORT NPI_CORE_DOUT_WE   = "", DIR = O
PORT SATA_CORE_FULL     = "", DIR = I 
PORT req_type           = "", DIR = I, VEC = [1:0]     
PORT new_cmd            = "", DIR = I     
PORT num_read_bytes_in  = "", DIR = I, VEC = [31:0]        
PORT num_write_bytes_in = "", DIR = I, VEC = [31:0]          
PORT NPI_init_wr_addr_in = "", DIR = I, VEC = [31:0]    
PORT NPI_init_rd_addr_in = "", DIR = I, VEC = [31:0]    
PORT NPI_ready_for_cmd  = "", DIR = O       

## Native Port Interface PORT
PORT NPI_Addr              = "Addr",              DIR = O, BUS = XIL_NPI, VEC = [31:0], ENDIAN = LITTLE
PORT NPI_AddrReq           = "AddrReq",           DIR = O, BUS = XIL_NPI
PORT NPI_AddrAck           = "AddrAck",           DIR = I, BUS = XIL_NPI
PORT NPI_RNW               = "RNW",               DIR = O, BUS = XIL_NPI
PORT NPI_Size              = "Size",              DIR = O, BUS = XIL_NPI, VEC = [3:0],  ENDIAN = LITTLE
PORT NPI_WrFIFO_Data       = "WrFIFO_Data",       DIR = O, BUS = XIL_NPI, VEC = [63:0], ENDIAN = LITTLE
PORT NPI_WrFIFO_BE         = "WrFIFO_BE",         DIR = O, BUS = XIL_NPI, VEC = [7:0],  ENDIAN = LITTLE
PORT NPI_WrFIFO_Push       = "WrFIFO_Push",       DIR = O, BUS = XIL_NPI
PORT NPI_RdFIFO_Data       = "RdFIFO_Data",       DIR = I, BUS = XIL_NPI, VEC = [63:0], ENDIAN = LITTLE
PORT NPI_RdFIFO_Pop        = "RdFIFO_Pop",        DIR = O, BUS = XIL_NPI
PORT NPI_RdFIFO_RdWdAddr   = "RdFIFO_RdWdAddr",   DIR = I, BUS = XIL_NPI, VEC = [3:0],  ENDIAN = LITTLE
PORT NPI_WrFIFO_AlmostFull = "WrFIFO_AlmostFull", DIR = I, BUS = XIL_NPI
PORT NPI_WrFIFO_Flush      = "WrFIFO_Flush",      DIR = O, BUS = XIL_NPI
PORT NPI_WrFIFO_Empty      = "WrFIFO_Empty",      DIR = I, BUS = XIL_NPI
PORT NPI_RdFIFO_Empty      = "RdFIFO_Empty",      DIR = I, BUS = XIL_NPI
PORT NPI_RdFIFO_Flush      = "RdFIFO_Flush",      DIR = O, BUS = XIL_NPI
PORT NPI_RdModWr           = "RdModWr",           DIR = O, BUS = XIL_NPI
PORT NPI_InitDone          = "InitDone",          DIR = I, BUS = XIL_NPI
PORT NPI_RdFIFO_Latency    = "RdFIFO_Latency",    DIR = I, BUS = XIL_NPI, VEC = [1:0], ENDIAN = LITTLE

END