Subversion Repositories sata_controller_core

##############################################################
#
# Xilinx Core Generator version 12.2
# Date: Wed Jun 13 13:43:39 2012
#
##############################################################
#
#  This file contains the customisation parameters for a
#  Xilinx CORE Generator IP GUI. It is strongly recommended
#  that you do not manually alter this file as it may cause
#  unexpected and unsupported behavior.
#
##############################################################
#
# BEGIN Project Options
SET addpads = false
SET asysymbol = true
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = false
SET designentry = VHDL
SET device = xc6vlx240t
SET devicefamily = virtex6
SET flowvendor = Other
SET formalverification = false
SET foundationsym = false
SET implementationfiletype = Ngc
SET package = ff1156
SET removerpms = false
SET simulationfiles = Structural
SET speedgrade = -1
SET verilogsim = false
SET vhdlsim = true
# END Project Options
# BEGIN Select
SELECT ILA_(ChipScope_Pro_-_Integrated_Logic_Analyzer) family Xilinx,_Inc. 1.03.a
# END Select
# BEGIN Parameters
CSET component_name=sata_rx_frame_ila
CSET counter_width_1=Disabled
CSET counter_width_10=Disabled
CSET counter_width_11=Disabled
CSET counter_width_12=Disabled
CSET counter_width_13=Disabled
CSET counter_width_14=Disabled
CSET counter_width_15=Disabled
CSET counter_width_16=Disabled
CSET counter_width_2=Disabled
CSET counter_width_3=Disabled
CSET counter_width_4=Disabled
CSET counter_width_5=Disabled
CSET counter_width_6=Disabled
CSET counter_width_7=Disabled
CSET counter_width_8=Disabled
CSET counter_width_9=Disabled
CSET data_port_width=0
CSET data_same_as_trigger=true
CSET enable_storage_qualification=true
CSET enable_trigger_output_port=false
CSET exclude_from_data_storage_1=false
CSET exclude_from_data_storage_10=false
CSET exclude_from_data_storage_11=false
CSET exclude_from_data_storage_12=false
CSET exclude_from_data_storage_13=false
CSET exclude_from_data_storage_14=false
CSET exclude_from_data_storage_15=false
CSET exclude_from_data_storage_16=false
CSET exclude_from_data_storage_2=false
CSET exclude_from_data_storage_3=false
CSET exclude_from_data_storage_4=false
CSET exclude_from_data_storage_5=false
CSET exclude_from_data_storage_6=false
CSET exclude_from_data_storage_7=false
CSET exclude_from_data_storage_8=false
CSET exclude_from_data_storage_9=false
CSET match_type_1=basic_with_edges
CSET match_type_10=basic_with_edges
CSET match_type_11=basic_with_edges
CSET match_type_12=basic_with_edges
CSET match_type_13=basic_with_edges
CSET match_type_14=basic_with_edges
CSET match_type_15=basic_with_edges
CSET match_type_16=basic_with_edges
CSET match_type_2=basic_with_edges
CSET match_type_3=basic_with_edges
CSET match_type_4=basic_with_edges
CSET match_type_5=basic_with_edges
CSET match_type_6=basic_with_edges
CSET match_type_7=basic_with_edges
CSET match_type_8=basic_with_edges
CSET match_type_9=basic_with_edges
CSET match_units_1=1
CSET match_units_10=1
CSET match_units_11=1
CSET match_units_12=1
CSET match_units_13=1
CSET match_units_14=1
CSET match_units_15=1
CSET match_units_16=1
CSET match_units_2=1
CSET match_units_3=1
CSET match_units_4=1
CSET match_units_5=1
CSET match_units_6=1
CSET match_units_7=1
CSET match_units_8=1
CSET match_units_9=1
CSET max_sequence_levels=1
CSET number_of_trigger_ports=16
CSET sample_data_depth=1024
CSET sample_on=Rising
CSET trigger_port_width_1=4
CSET trigger_port_width_10=32
CSET trigger_port_width_11=32
CSET trigger_port_width_12=8
CSET trigger_port_width_13=16
CSET trigger_port_width_14=16
CSET trigger_port_width_15=16
CSET trigger_port_width_16=32
CSET trigger_port_width_2=32
CSET trigger_port_width_3=8
CSET trigger_port_width_4=4
CSET trigger_port_width_5=4
CSET trigger_port_width_6=8
CSET trigger_port_width_7=32
CSET trigger_port_width_8=32
CSET trigger_port_width_9=32
CSET use_rpms=true
# END Parameters
GENERATE
# CRC: 2a41b836