Subversion Repositories sata_controller_core

# ##############################################################################
# Created by Base System Builder Wizard for Xilinx EDK 12.2 Build EDK_MS2.63c
# Fri Aug  5 09:18:57 2011
# Target Board:  Xilinx Virtex 6 ML605 Evaluation Platform Rev D
# Family:    virtex6
# Device:    xc6vlx240t
# Package:   ff1156
# Speed Grade:  -1
# Processor number: 1
# Processor 1: microblaze_0
# System clock frequency: 100.0
# Debug Interface: On-Chip HW Debug Module
# ##############################################################################
 PARAMETER VERSION = 2.1.0


 PORT fpga_0_RS232_Uart_1_RX_pin = fpga_0_RS232_Uart_1_RX_pin, DIR = I
 PORT fpga_0_RS232_Uart_1_TX_pin = fpga_0_RS232_Uart_1_TX_pin, DIR = O
 PORT fpga_0_DDR3_SDRAM_DDR3_Clk_pin = fpga_0_DDR3_SDRAM_DDR3_Clk_pin, DIR = O
 PORT fpga_0_DDR3_SDRAM_DDR3_Clk_n_pin = fpga_0_DDR3_SDRAM_DDR3_Clk_n_pin, DIR = O
 PORT fpga_0_DDR3_SDRAM_DDR3_CE_pin = fpga_0_DDR3_SDRAM_DDR3_CE_pin, DIR = O
 PORT fpga_0_DDR3_SDRAM_DDR3_CS_n_pin = fpga_0_DDR3_SDRAM_DDR3_CS_n_pin, DIR = O
 PORT fpga_0_DDR3_SDRAM_DDR3_ODT_pin = fpga_0_DDR3_SDRAM_DDR3_ODT_pin, DIR = O
 PORT fpga_0_DDR3_SDRAM_DDR3_RAS_n_pin = fpga_0_DDR3_SDRAM_DDR3_RAS_n_pin, DIR = O
 PORT fpga_0_DDR3_SDRAM_DDR3_CAS_n_pin = fpga_0_DDR3_SDRAM_DDR3_CAS_n_pin, DIR = O
 PORT fpga_0_DDR3_SDRAM_DDR3_WE_n_pin = fpga_0_DDR3_SDRAM_DDR3_WE_n_pin, DIR = O
 PORT fpga_0_DDR3_SDRAM_DDR3_BankAddr_pin = fpga_0_DDR3_SDRAM_DDR3_BankAddr_pin, DIR = O, VEC = [2:0]
 PORT fpga_0_DDR3_SDRAM_DDR3_Addr_pin = fpga_0_DDR3_SDRAM_DDR3_Addr_pin, DIR = O, VEC = [12:0]
 PORT fpga_0_DDR3_SDRAM_DDR3_DQ_pin = fpga_0_DDR3_SDRAM_DDR3_DQ_pin, DIR = IO, VEC = [31:0]
 PORT fpga_0_DDR3_SDRAM_DDR3_DM_pin = fpga_0_DDR3_SDRAM_DDR3_DM_pin, DIR = O, VEC = [3:0]
 PORT fpga_0_DDR3_SDRAM_DDR3_Reset_n_pin = fpga_0_DDR3_SDRAM_DDR3_Reset_n_pin, DIR = O
 PORT fpga_0_DDR3_SDRAM_DDR3_DQS_pin = fpga_0_DDR3_SDRAM_DDR3_DQS_pin, DIR = IO, VEC = [3:0]
 PORT fpga_0_DDR3_SDRAM_DDR3_DQS_n_pin = fpga_0_DDR3_SDRAM_DDR3_DQS_n_pin, DIR = IO, VEC = [3:0]
 PORT fpga_0_clk_1_sys_clk_p_pin = dcm_clk_s, DIR = I, SIGIS = CLK, DIFFERENTIAL_POLARITY = P, CLK_FREQ = 200000000
 PORT fpga_0_clk_1_sys_clk_n_pin = dcm_clk_s, DIR = I, SIGIS = CLK, DIFFERENTIAL_POLARITY = N, CLK_FREQ = 200000000
 PORT fpga_0_rst_1_sys_rst_pin = sys_rst_s, DIR = I, SIGIS = RST, RST_POLARITY = 1
# # SATA Push Button Reset and New Command
# PORT GTX_RESET_IN = GTX_RESET_IN, DIR = IO
# PORT NEW_CMD = NEW_CMD, DIR = I
# # SATA LEDs
 PORT TILE0_PLLLKDET_OUT_N = TILE0_PLLLKDET_OUT_N, DIR = O
 PORT DCMLOCKED_OUT = DCMLOCKED_OUT, DIR = O
 PORT LINKUP_led = LINKUP_led, DIR = O
 PORT GEN2_led = GEN2_led, DIR = O
# # SATA GTX
 PORT FMC_HPC_DP2_C2M_N = TXN0_OUT, DIR = O
 PORT FMC_HPC_DP2_C2M_P = TXP0_OUT, DIR = O
 PORT FMC_HPC_DP2_M2C_N = RXN0_IN, DIR = I
 PORT FMC_HPC_DP2_M2C_P = RXP0_IN, DIR = I


# PORT TILE0_REFCLK_PAD_P_IN_pin = TILE0_REFCLK_PAD_P_IN, DIR = I
# PORT TILE0_REFCLK_PAD_N_IN_pin = TILE0_REFCLK_PAD_N_IN, DIR = I
BEGIN npi_core
 PARAMETER INSTANCE = npi_core_0
 PARAMETER HW_VER = 1.00.a
 PARAMETER CHIPSCOPE = true
 PARAMETER RAM_OFFSET = 0xd0
 PARAMETER BLOCK_SIZE = 512
 BUS_INTERFACE XIL_NPI = npi_complete_0_XIL_NPI
 PORT npi_if_ila_control = npi_if_ila_control
 PORT npi_if_tx_ila_control = npi_if_tx_ila_control
 PORT npi_ila_control = npi_ila_control
 PORT MPMC_Clk = clk_200_0000MHzMMCM0
 PORT user_clk = SATA_CORE_CLK_OUT
 PORT reset = sys_rst_s
 PORT NPI_CORE_DIN = SATA_CORE_DOUT
 PORT NPI_CORE_WE = SATA_CORE_DOUT_WE
 PORT NPI_CORE_DOUT = SATA_CORE_DIN
 PORT NPI_CORE_DOUT_WE = SATA_CORE_DIN_WE
 PORT SATA_CORE_FULL = SATA_CORE_FULL
 PORT req_type = NPI_CORE_REQ_TYPE
 PORT new_cmd = NPI_CORE_NEW_CMD
 PORT num_read_bytes_in = NPI_CORE_NUM_RD_BYTES
 PORT num_write_bytes_in = NPI_CORE_NUM_WR_BYTES
 PORT NPI_init_wr_addr_in = NPI_CORE_INIT_WR_ADDR
 PORT NPI_init_rd_addr_in = NPI_CORE_INIT_RD_ADDR
 PORT NPI_ready_for_cmd = NPI_CORE_READY_FOR_CMD
END

BEGIN sata_core
 PARAMETER INSTANCE = sata_core_0
 PARAMETER HW_VER = 1.00.a
 PARAMETER CHIPSCOPE = true
 PARAMETER DATA_WIDTH = 32
 PARAMETER C_BASEADDR = 0x70000000
 PARAMETER C_HIGHADDR = 0x7000FFFF
 BUS_INTERFACE SPLB = mb_plb
 PORT cmd_layer_ila_control = cmd_layer_ila_control
 PORT sata_rx_frame_ila_control = sata_rx_frame_ila_control
 PORT sata_tx_frame_ila_control = sata_tx_frame_ila_control
 PORT sata_phy_ila_control = sata_phy_ila_control
 PORT oob_control_ila_control = oob_control_ila_control
# PORT scrambler_ila_control = scrambler_ila_control
# PORT descrambler_ila_control = descrambler_ila_control
 PORT user_logic_ila_control = user_logic_ila_control
# PORT TILE0_REFCLK_PAD_P_IN = TILE0_REFCLK_PAD_P_IN
# PORT TILE0_REFCLK_PAD_N_IN = TILE0_REFCLK_PAD_N_IN
 PORT TILE0_PLLLKDET_OUT_N = TILE0_PLLLKDET_OUT_N
 PORT DCMLOCKED_OUT = DCMLOCKED_OUT
 PORT LINKUP_led = LINKUP_led
 PORT GEN2_led = GEN2_led
 PORT TXP0_OUT = TXP0_OUT
 PORT TXN0_OUT = TXN0_OUT
 PORT RXP0_IN = RXP0_IN
 PORT RXN0_IN = RXN0_IN
 PORT RESET = sys_bus_reset
 PORT CLKIN_150 = clk_150_0000MHz
# SATA-NPI Interface
 PORT SATA_CORE_DOUT = SATA_CORE_DOUT
 PORT SATA_CORE_DOUT_WE = SATA_CORE_DOUT_WE
 PORT SATA_CORE_CLK_OUT = SATA_CORE_CLK_OUT
 PORT SATA_CORE_DIN = SATA_CORE_DIN
 PORT SATA_CORE_DIN_WE = SATA_CORE_DIN_WE
 PORT SATA_CORE_FULL = SATA_CORE_FULL
 PORT NPI_CORE_REQ_TYPE = NPI_CORE_REQ_TYPE
 PORT NPI_CORE_NEW_CMD = NPI_CORE_NEW_CMD
 PORT NPI_CORE_NUM_RD_BYTES = NPI_CORE_NUM_RD_BYTES
 PORT NPI_CORE_NUM_WR_BYTES = NPI_CORE_NUM_WR_BYTES
 PORT NPI_CORE_INIT_WR_ADDR = NPI_CORE_INIT_WR_ADDR
 PORT NPI_CORE_INIT_RD_ADDR = NPI_CORE_INIT_RD_ADDR
 PORT NPI_CORE_READY_FOR_CMD = NPI_CORE_READY_FOR_CMD
END

BEGIN microblaze
 PARAMETER INSTANCE = microblaze_0
 PARAMETER C_DEBUG_ENABLED = 1
 PARAMETER HW_VER = 7.30.b
 BUS_INTERFACE DLMB = dlmb
 BUS_INTERFACE ILMB = ilmb
 BUS_INTERFACE DPLB = mb_plb
 BUS_INTERFACE IPLB = mb_plb
 BUS_INTERFACE DEBUG = microblaze_0_mdm_bus
 PORT MB_RESET = mb_reset
END

BEGIN plb_v46
 PARAMETER INSTANCE = mb_plb
 PARAMETER HW_VER = 1.04.a
 PORT PLB_Clk = clk_100_0000MHzMMCM0
 PORT SYS_Rst = sys_bus_reset
END

BEGIN lmb_v10
 PARAMETER INSTANCE = ilmb
 PARAMETER HW_VER = 1.00.a
 PORT LMB_Clk = clk_100_0000MHzMMCM0
 PORT SYS_Rst = sys_bus_reset
END

BEGIN lmb_v10
 PARAMETER INSTANCE = dlmb
 PARAMETER HW_VER = 1.00.a
 PORT LMB_Clk = clk_100_0000MHzMMCM0
 PORT SYS_Rst = sys_bus_reset
END

BEGIN lmb_bram_if_cntlr
 PARAMETER INSTANCE = dlmb_cntlr
 PARAMETER HW_VER = 2.10.b
 PARAMETER C_BASEADDR = 0x00000000
 PARAMETER C_HIGHADDR = 0x0003FFFF
 BUS_INTERFACE SLMB = dlmb
 BUS_INTERFACE BRAM_PORT = dlmb_port
END

BEGIN lmb_bram_if_cntlr
 PARAMETER INSTANCE = ilmb_cntlr
 PARAMETER HW_VER = 2.10.b
 PARAMETER C_BASEADDR = 0x00000000
 PARAMETER C_HIGHADDR = 0x0003FFFF
 BUS_INTERFACE SLMB = ilmb
 BUS_INTERFACE BRAM_PORT = ilmb_port
END

BEGIN bram_block
 PARAMETER INSTANCE = lmb_bram
 PARAMETER HW_VER = 1.00.a
 BUS_INTERFACE PORTA = ilmb_port
 BUS_INTERFACE PORTB = dlmb_port
END

BEGIN xps_uartlite
 PARAMETER INSTANCE = RS232_Uart_1
 PARAMETER C_BAUDRATE = 115200
 PARAMETER C_DATA_BITS = 8
 PARAMETER C_USE_PARITY = 0
 PARAMETER C_ODD_PARITY = 0
 PARAMETER HW_VER = 1.01.a
 PARAMETER C_BASEADDR = 0x84000000
 PARAMETER C_HIGHADDR = 0x8400ffff
 BUS_INTERFACE SPLB = mb_plb
 PORT RX = fpga_0_RS232_Uart_1_RX_pin
 PORT TX = fpga_0_RS232_Uart_1_TX_pin
END

BEGIN mpmc
 PARAMETER INSTANCE = DDR3_SDRAM
 PARAMETER C_NUM_PORTS = 2
 PARAMETER C_MMCM_EXT_LOC = MMCM_ADV_X0Y9
 PARAMETER C_MEM_TYPE = DDR3
 PARAMETER C_MEM_PARTNO = MT4JSF6464HY-1G1
 PARAMETER C_MEM_ODT_TYPE = 1
 PARAMETER C_MEM_REG_DIMM = 0
 PARAMETER C_MEM_CLK_WIDTH = 1
 PARAMETER C_MEM_ODT_WIDTH = 1
 PARAMETER C_MEM_CE_WIDTH = 1
 PARAMETER C_MEM_CS_N_WIDTH = 1
 PARAMETER C_MEM_DATA_WIDTH = 32
 PARAMETER C_MEM_NDQS_COL0 = 3
 PARAMETER C_MEM_NDQS_COL1 = 1
 PARAMETER C_MEM_DQS_LOC_COL0 = 0x000000000000000000000000000000020100
 PARAMETER C_MEM_DQS_LOC_COL1 = 0x000000000000000000000000000000000003
 PARAMETER C_PIM0_BASETYPE = 2
 PARAMETER HW_VER = 6.01.a
 PARAMETER C_MPMC_BASEADDR = 0x90000000
 PARAMETER C_MPMC_HIGHADDR = 0x9fffffff
 PARAMETER C_PIM1_BASETYPE = 4
 BUS_INTERFACE SPLB0 = mb_plb
 BUS_INTERFACE MPMC_PIM1 = npi_complete_0_XIL_NPI
 PORT MPMC_Clk0 = clk_200_0000MHzMMCM0
 PORT MPMC_Clk_200MHz = clk_200_0000MHzMMCM0
 PORT MPMC_Rst = sys_periph_reset
 PORT MPMC_Clk_Mem = clk_400_0000MHzMMCM0
 PORT MPMC_Clk_Rd_Base = clk_400_0000MHzMMCM0_nobuf_varphase
 PORT MPMC_DCM_PSEN = MPMC_DCM_PSEN
 PORT MPMC_DCM_PSINCDEC = MPMC_DCM_PSINCDEC
 PORT MPMC_DCM_PSDONE = MPMC_DCM_PSDONE
 PORT DDR3_Clk = fpga_0_DDR3_SDRAM_DDR3_Clk_pin
 PORT DDR3_Clk_n = fpga_0_DDR3_SDRAM_DDR3_Clk_n_pin
 PORT DDR3_CE = fpga_0_DDR3_SDRAM_DDR3_CE_pin
 PORT DDR3_CS_n = fpga_0_DDR3_SDRAM_DDR3_CS_n_pin
 PORT DDR3_ODT = fpga_0_DDR3_SDRAM_DDR3_ODT_pin
 PORT DDR3_RAS_n = fpga_0_DDR3_SDRAM_DDR3_RAS_n_pin
 PORT DDR3_CAS_n = fpga_0_DDR3_SDRAM_DDR3_CAS_n_pin
 PORT DDR3_WE_n = fpga_0_DDR3_SDRAM_DDR3_WE_n_pin
 PORT DDR3_BankAddr = fpga_0_DDR3_SDRAM_DDR3_BankAddr_pin
 PORT DDR3_Addr = fpga_0_DDR3_SDRAM_DDR3_Addr_pin
 PORT DDR3_DQ = fpga_0_DDR3_SDRAM_DDR3_DQ_pin
 PORT DDR3_DM = fpga_0_DDR3_SDRAM_DDR3_DM_pin
 PORT DDR3_Reset_n = fpga_0_DDR3_SDRAM_DDR3_Reset_n_pin
 PORT DDR3_DQS = fpga_0_DDR3_SDRAM_DDR3_DQS_pin
 PORT DDR3_DQS_n = fpga_0_DDR3_SDRAM_DDR3_DQS_n_pin
END

BEGIN clock_generator
 PARAMETER INSTANCE = clock_generator_0
 PARAMETER C_CLKIN_FREQ = 200000000
 PARAMETER C_CLKOUT0_FREQ = 100000000
 PARAMETER C_CLKOUT0_PHASE = 0
 PARAMETER C_CLKOUT0_GROUP = MMCM0
 PARAMETER C_CLKOUT0_BUF = TRUE
 PARAMETER C_CLKOUT1_FREQ = 200000000
 PARAMETER C_CLKOUT1_PHASE = 0
 PARAMETER C_CLKOUT1_GROUP = MMCM0
 PARAMETER C_CLKOUT1_BUF = TRUE
 PARAMETER C_CLKOUT2_FREQ = 400000000
 PARAMETER C_CLKOUT2_PHASE = 0
 PARAMETER C_CLKOUT2_GROUP = MMCM0
 PARAMETER C_CLKOUT2_BUF = TRUE
 PARAMETER C_CLKOUT3_FREQ = 400000000
 PARAMETER C_CLKOUT3_PHASE = 0
 PARAMETER C_CLKOUT3_GROUP = MMCM0
 PARAMETER C_CLKOUT3_BUF = FALSE
 PARAMETER C_CLKOUT3_VARIABLE_PHASE = TRUE
 PARAMETER C_PSDONE_GROUP = MMCM0
 PARAMETER C_CLKOUT4_FREQ = 150000000
 PARAMETER C_CLKOUT4_PHASE = 0
 PARAMETER C_CLKOUT4_GROUP = NONE
 PARAMETER C_CLKOUT4_BUF = TRUE
 PARAMETER C_EXT_RESET_HIGH = 1
 PARAMETER HW_VER = 4.00.a
 PORT CLKIN = dcm_clk_s
 PORT CLKOUT0 = clk_100_0000MHzMMCM0
 PORT CLKOUT1 = clk_200_0000MHzMMCM0
 PORT CLKOUT2 = clk_400_0000MHzMMCM0
 PORT CLKOUT3 = clk_400_0000MHzMMCM0_nobuf_varphase
 PORT CLKOUT4 = clk_150_0000MHz
 PORT PSCLK = clk_200_0000MHzMMCM0
 PORT PSEN = MPMC_DCM_PSEN
 PORT PSINCDEC = MPMC_DCM_PSINCDEC
 PORT PSDONE = MPMC_DCM_PSDONE
 PORT RST = sys_rst_s
 PORT LOCKED = Dcm_all_locked
END

BEGIN mdm
 PARAMETER INSTANCE = mdm_0
 PARAMETER C_MB_DBG_PORTS = 1
 PARAMETER C_USE_UART = 1
 PARAMETER C_UART_WIDTH = 8
 PARAMETER HW_VER = 1.00.g
 PARAMETER C_BASEADDR = 0x84400000
 PARAMETER C_HIGHADDR = 0x8440ffff
 BUS_INTERFACE SPLB = mb_plb
 BUS_INTERFACE MBDEBUG_0 = microblaze_0_mdm_bus
 PORT Debug_SYS_Rst = Debug_SYS_Rst
END

BEGIN proc_sys_reset
 PARAMETER INSTANCE = proc_sys_reset_0
 PARAMETER C_EXT_RESET_HIGH = 1
 PARAMETER HW_VER = 2.00.a
 PORT Slowest_sync_clk = clk_100_0000MHzMMCM0
 PORT Ext_Reset_In = sys_rst_s
 PORT MB_Debug_Sys_Rst = Debug_SYS_Rst
 PORT Dcm_locked = Dcm_all_locked
 PORT MB_Reset = mb_reset
 PORT Bus_Struct_Reset = sys_bus_reset
 PORT Peripheral_Reset = sys_periph_reset
END

BEGIN chipscope_icon
 PARAMETER INSTANCE = chipscope_icon_0
 PARAMETER HW_VER = 1.04.a
 PARAMETER C_NUM_CONTROL_PORTS = 9
 PORT control0 = oob_control_ila_control
 PORT control1 = sata_phy_ila_control
 PORT control2 = sata_rx_frame_ila_control
 PORT control3 = sata_tx_frame_ila_control
 PORT control4 = cmd_layer_ila_control
 PORT control5 = user_logic_ila_control
 PORT control6 = npi_ila_control
 PORT control7 = npi_if_ila_control
 PORT control8 = npi_if_tx_ila_control
END