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[/] [sdcard_mass_storage_controller/] [trunk/] [sim/] [rtl_sim/] [log/] [sdc_tb.log] - Rev 131
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========================== SD IP Core Testbench results ===========================******************************************************************************************************************************************************************************Heading: access_to_reg*******************************************************************************************************************************************************************************************************************************************************************At time: 2903Test: TEST 0: 32-BIT READ-WRITE REGISTERS ( VARIOUS BUS DELAYS )*FAILED* becauseRegister %h defaultvalue is not RSP ; 72**************************************************************************************************************************************************************************At time: 3215Test: TEST 0: 32-BIT READ-WRITE REGISTERS ( VARIOUS BUS DELAYS )*FAILED* becauseRegister %h defaultvalue is not RSP ; 28**************************************************************************************************************************************************************************At time: 3423Test: TEST 0: 32-BIT READ-WRITE REGISTERS ( VARIOUS BUS DELAYS )*FAILED* becauseRegister %h defaultvalue is not RSP ; 36*******************************************************************************************************************************************************************************************************************************************************************Heading: Send CMD*******************************************************************************************************************************************************************************************************************************************************************At time: 8077Test: 0: Send CMD, No Responsereported *SUCCESSFULL*!*******************************************************************************************************************************************************************************************************************************************************************Heading: access_to_reg*******************************************************************************************************************************************************************************************************************************************************************At time: 61507Test: 3.0: Init Seq, No Responsereported *SUCCESSFULL*!*******************************************************************************************************************************************************************************************************************************************************************Heading: access_to_reg*******************************************************************************************************************************************************************************************************************************************************************At time: 208147Test: 4.0: Send datareported *SUCCESSFULL*!**************************************************************************************************************************************************************************At time: 415419Test: 4.0: Send datareported *SUCCESSFULL*!*******************************************************************************************************************************************************************************************************************************************************************Heading: Send CMD, with simulated bus error on SD_CMD line*******************************************************************************************************************************************************************************************************************************************************************At time: 443473Test: Test 5 part 4: Send CMD2, 136-Bitreported *SUCCESSFULL*!*************************************************************************************
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