OpenCores
URL https://opencores.org/ocsvn/sdr_ctrl/sdr_ctrl/trunk

Subversion Repositories sdr_ctrl

[/] [sdr_ctrl/] [trunk/] [verif/] [run/] [run_modelsim] - Rev 38

Go to most recent revision | Compare with Previous | Blame | View Log

#!/bin/csh -f
#
# test all programs with SDRAM CONTROLLER
#

set failedm = 0; 
set all_testsm = 0;

set sdr_tests =(basic_test1 )
#set misc_tests=( )


echo " Compiling with MODELSIM in $1 $2 Mode "

./compile.modelsim $1 $2 | tee ../log/$1_$2_complie.log


if ($status != 0) then
  echo "#### Compile : FAILED"
  echo ""
  cat ../log/complie.log
  exit
else
  echo "#### Compile : PASSED"
endif


echo ""
echo "###########################################"
echo " Runing GMAC/SPI/UART test programs "
echo "###########################################"

set i = 0;
        echo "###########################################"
foreach run_test ($sdr_tests)
        @ i += 1;
        #echo ""
        echo "### Running test ${i}: ${run_test}"

        vsim -do run.do -c tb_$1 +${run_test} | tee  ../log/run.log
        if ($status != 0) then
          cat ../log/run.log
          exit
        else if (`tail ../log/run.log | grep PASSED` == "") then
          echo "### test ${i}: ${run_test} --> FAILED"
          @ failedm += 1;
          @ all_testsm += 1;
        else
          echo "### test ${i}: ${run_test} --> PASSED"
          @ all_testsm += 1;
        endif
  
        mv ../log/run.log ../log/$1_$2_${run_test}.log


end
    echo "###########################################"


set i = 0;
echo ""
echo "###########################################"
echo "###  Test Logs                            "
foreach run_test ($sdr_tests)
          @ i += 1;
          echo "   test ${i}: ../log/$1_$2_${run_test}.log"

end
    echo "###########################################"


echo ""
echo "###########################################"
echo "###  Test Summary                          "
echo "### "
echo "### Failed $failedm of $all_testsm $2 tests"
echo "###########################################"

Go to most recent revision | Compare with Previous | Blame | View Log

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.