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Subversion Repositories soc_auto_vbus
[/] [soc_auto_vbus/] [trunk/] [src/] [vBUS1_tb.vhd] - Rev 2
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library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity vBUS_TEST_B_TB is generic ( ADDR_WIDTH :integer := 4; DATA_WIDTH :integer := 4 ); end entity vBUS_TEST_B_TB; architecture behaviour of vBUS_TEST_B_TB is signal resN :std_logic; signal enaN :std_logic; signal strN :std_logic; signal rdN :std_logic := '1'; signal addr :std_logic_vector(ADDR_WIDTH-1 downto 0); signal data_wr :std_logic_vector(DATA_WIDTH-1 downto 0); signal data_rd :std_logic_vector(DATA_WIDTH-1 downto 0); begin process is begin resN <= '0'; wait for 10ns; resN <= '1'; wait; end process; process is begin enaN <= '1'; strN <= '1'; addr <= (others => '0'); data_wr <= (others => '0'); wait for 20 ns; for i in 0 to 9 loop data_wr <= data_wr + 10; wait for 5 ns; enaN <= '0'; wait for 5 ns; strN <= '0'; wait for 10 ns; strN <= '1'; wait for 5 ns; enaN <= '1'; wait for 5 ns; addr <= addr + 1; end loop; rdN <= not(rdN); end process; inst: entity work.vBUS_TEST_B generic map (ADDR_WIDTH, DATA_WIDTH) port map (resN, enaN, strN, rdN, addr, data_wr, data_rd); end behaviour; ------------------------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use work.vBUS.all; entity vBUS_TEST_A_TB is generic ( ADDR_WIDTH :integer := 3; DATA_WIDTH :integer := 4; ITEM_MODE :TvBUSnodeMode := WREG ); end entity vBUS_TEST_A_TB; architecture behaviour of vBUS_TEST_A_TB is signal resN :std_logic; signal enaN :std_logic; signal strN :std_logic; signal rdN :std_logic := '1'; signal addr :std_logic_vector(ADDR_WIDTH-1 downto 0); signal data_wr :std_logic_vector(DATA_WIDTH-1 downto 0); signal data_rd :std_logic_vector(DATA_WIDTH-1 downto 0); signal sdata_wr :std_logic_vector(DATA_WIDTH/2-1 downto 0); signal sena_wr :std_logic_vector(DATA_WIDTH/2-1 downto 0); signal ldata_wr :std_logic_vector(5*(DATA_WIDTH/2)-1 downto 0); signal lena_wr :std_logic_vector(5*(DATA_WIDTH/2)-1 downto 0); signal sdata_rd :std_logic_vector(DATA_WIDTH/2-1 downto 0); signal sena_rd :std_logic_vector(DATA_WIDTH/2-1 downto 0); signal ldata_rd :std_logic_vector(5*(DATA_WIDTH/2)-1 downto 0); signal lena_rd :std_logic_vector(5*(DATA_WIDTH/2)-1 downto 0); begin process is begin resN <= '0'; wait for 10ns; resN <= '1'; wait; end process; process is begin enaN <= '1'; strN <= '1'; addr <= (others => '0'); data_wr <= (others => '0'); sdata_rd <= (others => '0'); ldata_rd <= (others => '0'); wait for 0 ns; data_wr <= data_wr+18; sdata_rd <= sdata_rd+16#1#; ldata_rd <= ldata_rd+16#23456#; wait for 20 ns; for i in 0 to 2**ADDR_WIDTH-1 loop data_wr <= data_wr + 17; sdata_rd <= sdata_rd+16#1#; ldata_rd <= ldata_rd+16#11111#; wait for 5 ns; enaN <= '0'; wait for 5 ns; strN <= '0'; wait for 10 ns; strN <= '1'; wait for 5 ns; enaN <= '1'; wait for 5 ns; addr <= addr + 1; end loop; rdN <= not(rdN); end process; inst: entity work.vBUS_TEST_A generic map (ADDR_WIDTH, DATA_WIDTH, ITEM_MODE) port map (resN, enaN, strN, rdN, addr, data_wr, data_rd, sdata_wr, sena_wr, ldata_wr, lena_wr, sdata_rd, sena_rd, ldata_rd, lena_rd); end behaviour;