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[/] [socgen/] [trunk/] [Projects/] [digilentinc.com/] [Nexys2/] [ip/] [fpga/] [rtl/] [xml/] [Nexys2_fpga_jtag_design.xml] - Rev 135

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<?xml version="1.0" encoding="UTF-8"?>
<!--
//                                                                        //
// Author : John Eaton  Ouabache Designworks                              //
//                                                                        //
//   Copyright (C) 2010 Authors and OPENCORES.ORG                         //
//                                                                        //
//   This source file may be used and distributed without                 //
//   restriction provided that this copyright statement is not            //
//   removed from the file and that any derivative work contains          //
//   the original copyright notice and the associated disclaimer.         //
//                                                                        //
//   This source file is free software; you can redistribute it           //
//   and/or modify it under the terms of the GNU Lesser General           //
//   Public License as published by the Free Software Foundation;         //
//   either version 2.1 of the License, or (at your option) any           //
//   later version.                                                       //
//                                                                        //
//   This source is distributed in the hope that it will be               //
//   useful, but WITHOUT ANY WARRANTY; without even the implied           //
//   warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR              //
//   PURPOSE. See the GNU Lesser General Public License for more          //
//   details.                                                             //
//                                                                        //
//   You should have received a copy of the GNU Lesser General            //
//   Public License along with this source; if not, download it           //
//   from http://www.opencores.org/lgpl.shtml                             //
//                                                                        //
-->
<ipxact:design 
xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
<ipxact:vendor>digilentinc.com</ipxact:vendor>
<ipxact:library>Nexys2</ipxact:library>
<ipxact:name>fpga</ipxact:name>
<ipxact:version>jtag_design</ipxact:version>  


<ipxact:vendorExtensions>
<socgen:nodes>

<socgen:node>
<ipxact:name>jtag_tclk_pad_in</ipxact:name>
<ipxact:typeName>wire</ipxact:typeName>
<ipxact:wire></ipxact:wire>
</socgen:node>


<socgen:node>
<ipxact:name>jtag_trst_n_pad_in</ipxact:name>
<ipxact:typeName>wire</ipxact:typeName>
<ipxact:wire></ipxact:wire>
</socgen:node>


<socgen:node>
<ipxact:name>jtag_tdi_pad_in</ipxact:name>
<ipxact:typeName>wire</ipxact:typeName>
<ipxact:wire></ipxact:wire>
</socgen:node>

<socgen:node>
<ipxact:name>jtag_tms_pad_in</ipxact:name>
<ipxact:typeName>wire</ipxact:typeName>
<ipxact:wire></ipxact:wire>
</socgen:node>

<socgen:node>
<ipxact:name>jtag_tdo_pad_out</ipxact:name>
<ipxact:typeName>wire</ipxact:typeName>
<ipxact:wire></ipxact:wire>
</socgen:node>

<socgen:node>
<ipxact:name>jtag_tdo_pad_oe</ipxact:name>
<ipxact:typeName>wire</ipxact:typeName>
<ipxact:wire></ipxact:wire>
</socgen:node>



</socgen:nodes>
</ipxact:vendorExtensions>



 <ipxact:interconnections>






    <ipxact:interconnection>
      <ipxact:name>JTAG_TCK</ipxact:name>
       <ipxact:activeInterface componentRef="jtag_tclk_pad" busRef="pad_ring">
        <ipxact:portMaps>
          <ipxact:portMap>
          <ipxact:logicalPort><ipxact:name>PAD_in</ipxact:name>
          </ipxact:logicalPort>
          <ipxact:physicalPort><ipxact:name>JTAG_TCK</ipxact:name>
          </ipxact:physicalPort>
          </ipxact:portMap>
        </ipxact:portMaps>
       </ipxact:activeInterface>
        <ipxact:hierInterface busRef="JTAG_TCK"/>
    </ipxact:interconnection>


    <ipxact:interconnection>
      <ipxact:name>JTAG_TRESET_N</ipxact:name>
       <ipxact:activeInterface componentRef="jtag_trst_n_pad" busRef="pad_ring">
        <ipxact:portMaps>
          <ipxact:portMap>
          <ipxact:logicalPort><ipxact:name>PAD_in</ipxact:name>
          </ipxact:logicalPort>
          <ipxact:physicalPort><ipxact:name>JTAG_TRESET_N</ipxact:name>
          </ipxact:physicalPort>
          </ipxact:portMap>
        </ipxact:portMaps>
       </ipxact:activeInterface>
               <ipxact:hierInterface busRef="JTAG_TRESET_N"/>
    </ipxact:interconnection>



    <ipxact:interconnection>
      <ipxact:name>JTAG_TDI</ipxact:name>
       <ipxact:activeInterface componentRef="jtag_tdi_pad" busRef="pad_ring">
        <ipxact:portMaps>
          <ipxact:portMap>
          <ipxact:logicalPort><ipxact:name>PAD_in</ipxact:name>
          </ipxact:logicalPort>
          <ipxact:physicalPort><ipxact:name>JTAG_TDI</ipxact:name>
          </ipxact:physicalPort>
          </ipxact:portMap>
        </ipxact:portMaps>
       </ipxact:activeInterface>
               <ipxact:hierInterface busRef="JTAG_TDI"/>
    </ipxact:interconnection>


    <ipxact:interconnection>
      <ipxact:name>JTAG_TMS</ipxact:name>
       <ipxact:activeInterface componentRef="jtag_tms_pad" busRef="pad_ring">
        <ipxact:portMaps>
          <ipxact:portMap>
          <ipxact:logicalPort><ipxact:name>PAD_in</ipxact:name>
          </ipxact:logicalPort>
          <ipxact:physicalPort><ipxact:name>JTAG_TMS</ipxact:name>
          </ipxact:physicalPort>
          </ipxact:portMap>
        </ipxact:portMaps>
       </ipxact:activeInterface>
               <ipxact:hierInterface busRef="JTAG_TMS"/>
    </ipxact:interconnection>


    <ipxact:interconnection>
      <ipxact:name>JTAG_TDO</ipxact:name>
       <ipxact:activeInterface componentRef="jtag_tdo_pad" busRef="pad_ring">
        <ipxact:portMaps>
          <ipxact:portMap>
          <ipxact:logicalPort><ipxact:name>PAD_out</ipxact:name>
          </ipxact:logicalPort>
          <ipxact:physicalPort><ipxact:name>JTAG_TDO</ipxact:name>
          </ipxact:physicalPort>
          </ipxact:portMap>
        </ipxact:portMaps>
       </ipxact:activeInterface>
               <ipxact:hierInterface busRef="JTAG_TDO"/>
    </ipxact:interconnection>


</ipxact:interconnections>





  <ipxact:adHocConnections>






    <ipxact:adHocConnection>
      <ipxact:name>jtag_tclk_pad_in</ipxact:name>
      <ipxact:portReferences>
      <ipxact:internalPortReference componentRef="jtag_tap" portRef="tclk_pad_in"/>
      <ipxact:internalPortReference componentRef="jtag_tclk_pad" portRef="pad_in"/>
      </ipxact:portReferences>
    </ipxact:adHocConnection>






    <ipxact:adHocConnection>
      <ipxact:name>jtag_trst_n_pad_in</ipxact:name>
            <ipxact:portReferences>
      <ipxact:internalPortReference componentRef="jtag_tap" portRef="trst_n_pad_in"/>
      <ipxact:internalPortReference componentRef="jtag_trst_n_pad" portRef="pad_in"/>
            </ipxact:portReferences>
    </ipxact:adHocConnection>

    <ipxact:adHocConnection>
      <ipxact:name>jtag_tdi_pad_in</ipxact:name>
      <ipxact:portReferences>
      <ipxact:internalPortReference componentRef="jtag_tap" portRef="tdi_pad_in"/>
      <ipxact:internalPortReference componentRef="jtag_tdi_pad" portRef="pad_in"/>
      </ipxact:portReferences>
    </ipxact:adHocConnection>


    <ipxact:adHocConnection>
      <ipxact:name>jtag_tms_pad_in</ipxact:name>
      <ipxact:portReferences>
      <ipxact:internalPortReference componentRef="jtag_tap" portRef="tms_pad_in"/>
      <ipxact:internalPortReference componentRef="jtag_tms_pad" portRef="pad_in"/>
      </ipxact:portReferences>
    </ipxact:adHocConnection>

    <ipxact:adHocConnection>
      <ipxact:name>jtag_tdo_pad_out</ipxact:name>
      <ipxact:portReferences>
      <ipxact:internalPortReference componentRef="jtag_tap" portRef="tdo_pad_out"/>
      <ipxact:internalPortReference componentRef="jtag_tdo_pad" portRef="pad_out"/>
      </ipxact:portReferences>
    </ipxact:adHocConnection>


    <ipxact:adHocConnection>
      <ipxact:name>jtag_tdo_pad_oe</ipxact:name>
      <ipxact:portReferences>
      <ipxact:internalPortReference componentRef="jtag_tap" portRef="tdo_pad_oe"/>
      <ipxact:internalPortReference componentRef="jtag_tdo_pad" portRef="pad_oe"/>
      </ipxact:portReferences>
    </ipxact:adHocConnection>

  </ipxact:adHocConnections>



<ipxact:componentInstances>


<ipxact:componentInstance>
<ipxact:instanceName>jtag_tclk_pad</ipxact:instanceName> 
<ipxact:componentRef vendor="opencores.org" library="cde" name="pad" version="in_dig" />
</ipxact:componentInstance>

<ipxact:componentInstance>
<ipxact:instanceName>jtag_trst_n_pad</ipxact:instanceName> 
<ipxact:componentRef vendor="opencores.org" library="cde" name="pad" version="in_dig" />
</ipxact:componentInstance>

<ipxact:componentInstance>
<ipxact:instanceName>jtag_tdi_pad</ipxact:instanceName> 
<ipxact:componentRef vendor="opencores.org" library="cde" name="pad" version="in_dig" />
</ipxact:componentInstance>

<ipxact:componentInstance>
<ipxact:instanceName>jtag_tms_pad</ipxact:instanceName> 
<ipxact:componentRef vendor="opencores.org" library="cde" name="pad" version="in_dig" />
</ipxact:componentInstance>

<ipxact:componentInstance>
<ipxact:instanceName>jtag_tdo_pad</ipxact:instanceName> 
<ipxact:componentRef vendor="opencores.org" library="cde" name="pad" version="tri_dig" />
</ipxact:componentInstance>

</ipxact:componentInstances>

</ipxact:design>

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