Subversion Repositories socgen

v 20100214 1
B 300 0  3500 4300 3 60 0 0 -1 -1 0 -1 -1 -1 -1 -1
T 400 4450   5 10 1 1 0 0 1 1
device=axi_model_slave
T 400 4650 5 10 1 1 0 0 1 1
refdes=U?
T 400 4800    0 10 0 1 0 0 1 1
vendor=opencores.org
T 400 4800    0 10 0 1 0 0 1 1
library=Testbench
T 400 4800    0 10 0 1 0 0 1 1
component=axi_model
T 400 4800    0 10 0 1 0 0 1 1
version=slave
P 300 200 0 200 10 1 1 
{
T 400 200 5 10 1 1 0 1 1 1
pinnumber=axi_wstrb[3:0]
T 400 200 5 10 0 1 0 1 1 1
pinseq=1
}
P 300 400 0 400 10 1 1 
{
T 400 400 5 10 1 1 0 1 1 1
pinnumber=axi_wdata[31:0]
T 400 400 5 10 0 1 0 1 1 1
pinseq=2
}
P 300 600 0 600 10 1 1 
{
T 400 600 5 10 1 1 0 1 1 1
pinnumber=axi_awsize[2:0]
T 400 600 5 10 0 1 0 1 1 1
pinseq=3
}
P 300 800 0 800 10 1 1 
{
T 400 800 5 10 1 1 0 1 1 1
pinnumber=axi_awlen[7:0]
T 400 800 5 10 0 1 0 1 1 1
pinseq=4
}
P 300 1000 0 1000 10 1 1 
{
T 400 1000 5 10 1 1 0 1 1 1
pinnumber=axi_awid[11:0]
T 400 1000 5 10 0 1 0 1 1 1
pinseq=5
}
P 300 1200 0 1200 10 1 1 
{
T 400 1200 5 10 1 1 0 1 1 1
pinnumber=axi_awburst[1:0]
T 400 1200 5 10 0 1 0 1 1 1
pinseq=6
}
P 300 1400 0 1400 10 1 1 
{
T 400 1400 5 10 1 1 0 1 1 1
pinnumber=axi_awaddr[31:0]
T 400 1400 5 10 0 1 0 1 1 1
pinseq=7
}
P 300 1600 0 1600 10 1 1 
{
T 400 1600 5 10 1 1 0 1 1 1
pinnumber=axi_arsize[2:0]
T 400 1600 5 10 0 1 0 1 1 1
pinseq=8
}
P 300 1800 0 1800 10 1 1 
{
T 400 1800 5 10 1 1 0 1 1 1
pinnumber=axi_arlen[7:0]
T 400 1800 5 10 0 1 0 1 1 1
pinseq=9
}
P 300 2000 0 2000 10 1 1 
{
T 400 2000 5 10 1 1 0 1 1 1
pinnumber=axi_arid[11:0]
T 400 2000 5 10 0 1 0 1 1 1
pinseq=10
}
P 300 2200 0 2200 10 1 1 
{
T 400 2200 5 10 1 1 0 1 1 1
pinnumber=axi_arburst[1:0]
T 400 2200 5 10 0 1 0 1 1 1
pinseq=11
}
P 300 2400 0 2400 10 1 1 
{
T 400 2400 5 10 1 1 0 1 1 1
pinnumber=axi_araddr[31:0]
T 400 2400 5 10 0 1 0 1 1 1
pinseq=12
}
P 300 2600 0 2600 4 0 1  
{
T 400 2600 5 10 1 1 0 1 1 1 
pinnumber=reset
T 400 2600 5 10 0 1 0 1 1 1 
pinseq=13
}
P 300 2800 0 2800 4 0 1  
{
T 400 2800 5 10 1 1 0 1 1 1 
pinnumber=clk
T 400 2800 5 10 0 1 0 1 1 1 
pinseq=14
}
P 300 3000 0 3000 4 0 1  
{
T 400 3000 5 10 1 1 0 1 1 1 
pinnumber=axi_wvalid
T 400 3000 5 10 0 1 0 1 1 1 
pinseq=15
}
P 300 3200 0 3200 4 0 1  
{
T 400 3200 5 10 1 1 0 1 1 1 
pinnumber=axi_wlast
T 400 3200 5 10 0 1 0 1 1 1 
pinseq=16
}
P 300 3400 0 3400 4 0 1  
{
T 400 3400 5 10 1 1 0 1 1 1 
pinnumber=axi_rready
T 400 3400 5 10 0 1 0 1 1 1 
pinseq=17
}
P 300 3600 0 3600 4 0 1  
{
T 400 3600 5 10 1 1 0 1 1 1 
pinnumber=axi_bready
T 400 3600 5 10 0 1 0 1 1 1 
pinseq=18
}
P 300 3800 0 3800 4 0 1  
{
T 400 3800 5 10 1 1 0 1 1 1 
pinnumber=axi_awvalid
T 400 3800 5 10 0 1 0 1 1 1 
pinseq=19
}
P 300 4000 0 4000 4 0 1  
{
T 400 4000 5 10 1 1 0 1 1 1 
pinnumber=axi_arvalid
T 400 4000 5 10 0 1 0 1 1 1 
pinseq=20
}
P 3800 200 4100 200 10 1 1
{
T 3700 200 5  10 1 1 0 7 1 1 
pinnumber=axi_rid[11:0]
T 3700 200 5  10 0 1 0 7 1 1 
pinseq=21
}
P 3800 400 4100 400 10 1 1
{
T 3700 400 5  10 1 1 0 7 1 1 
pinnumber=axi_rdata[31:0]
T 3700 400 5  10 0 1 0 7 1 1 
pinseq=22
}
P 3800 600 4100 600 10 1 1
{
T 3700 600 5  10 1 1 0 7 1 1 
pinnumber=axi_bresp[1:0]
T 3700 600 5  10 0 1 0 7 1 1 
pinseq=23
}
P 3800 800 4100 800 10 1 1
{
T 3700 800 5  10 1 1 0 7 1 1 
pinnumber=axi_bid[11:0]
T 3700 800 5  10 0 1 0 7 1 1 
pinseq=24
}
P 3800 1000 4100 1000 4 0 1
{
T 3700 1000 5  10 1 1 0 7 1 1
pinnumber=axi_wready
T 3800 1000 5  10 0 1 0 7 1 1
pinseq=25
}
P 3800 1200 4100 1200 4 0 1
{
T 3700 1200 5  10 1 1 0 7 1 1
pinnumber=axi_rvalid
T 3800 1200 5  10 0 1 0 7 1 1
pinseq=26
}
P 3800 1400 4100 1400 4 0 1
{
T 3700 1400 5  10 1 1 0 7 1 1
pinnumber=axi_rlast
T 3800 1400 5  10 0 1 0 7 1 1
pinseq=27
}
P 3800 1600 4100 1600 4 0 1
{
T 3700 1600 5  10 1 1 0 7 1 1
pinnumber=axi_bvalid
T 3800 1600 5  10 0 1 0 7 1 1
pinseq=28
}
P 3800 1800 4100 1800 4 0 1
{
T 3700 1800 5  10 1 1 0 7 1 1
pinnumber=axi_awready
T 3800 1800 5  10 0 1 0 7 1 1
pinseq=29
}
P 3800 2000 4100 2000 4 0 1
{
T 3700 2000 5  10 1 1 0 7 1 1
pinnumber=axi_arready
T 3800 2000 5  10 0 1 0 7 1 1
pinseq=30
}