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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [pad/] [rtl/] [verilog/] [pad_se_dig] - Rev 135

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assign           pad_in  = PAD;



generate
    genvar                  i;

  if(SCMD)
    begin
    assign           PAD     = pad_oe[0] ? pad_out  : {WIDTH{1'bz}};
    end
  else
    begin
    for (i=0; i < WIDTH; i=i+1) 
      begin:m
      assign           PAD[i]     = pad_oe[i] ? pad_out[i]  : {1'bz};
      end    
    end

endgenerate
   




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