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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [reg/] [rtl/] [verilog/] [logic_set] - Rev 135

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always@(posedge clk or negedge preset_n)
begin
if(!preset_n)  Q <= 1'b1;
else
              Q <=  D;
   
end

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