URL
https://opencores.org/ocsvn/spacewiresystemc/spacewiresystemc/trunk
Subversion Repositories spacewiresystemc
[/] [spacewiresystemc/] [trunk/] [altera_work/] [spw_fifo_ulight/] [db/] [prev_cmp_spw_fifo_ulight.qmsg] - Rev 40
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{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1516735621447 ""}{ "Info" "IQEXE_START_BANNER_PRODUCT" "Shell Quartus Prime " "Running Quartus Prime Shell" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 17.1.1 Internal Build 593 12/11/2017 SJ Lite Edition " "Version 17.1.1 Internal Build 593 12/11/2017 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1516735621464 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Jan 23 17:27:00 2018 " "Processing started: Tue Jan 23 17:27:00 2018" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1516735621464 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Shell" 0 -1 1516735621464 ""}{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sh --ip_upgrade -variation_files ulight_fifo.qsys spw_fifo_ulight " "Command: quartus_sh --ip_upgrade -variation_files ulight_fifo.qsys spw_fifo_ulight" { } { } 0 0 "Command: %1!s!" 0 0 "Shell" 0 -1 1516735621464 ""}{ "Info" "IQEXE_START_BANNER_TCL_ARGS" "-variation_files ulight_fifo.qsys spw_fifo_ulight " "Quartus(args): -variation_files ulight_fifo.qsys spw_fifo_ulight" { } { } 0 0 "Quartus(args): %1!s!" 0 0 "Shell" 0 -1 1516735621464 ""}{ "Info" "IIPMAN_IPRGEN_BACKUP_FILE" "ulight_fifo.qsys ulight_fifo.BAK.qsys " "Backing up file \"ulight_fifo.qsys\" to \"ulight_fifo.BAK.qsys\"" { } { } 0 11902 "Backing up file \"%1!s!\" to \"%2!s!\"" 0 0 "Shell" 0 -1 1516735653410 ""}{ "Info" "IIPMAN_IPRGEN_BACKUP_FILE" "ulight_fifo/synthesis/ulight_fifo.v ulight_fifo.BAK.v " "Backing up file \"ulight_fifo/synthesis/ulight_fifo.v\" to \"ulight_fifo.BAK.v\"" { } { } 0 11902 "Backing up file \"%1!s!\" to \"%2!s!\"" 0 0 "Shell" 0 -1 1516735653455 ""}{ "Info" "IIPMAN_IPRGEN_START" "Qsys ulight_fifo.qsys " "Started upgrading IP component Qsys with file \"ulight_fifo.qsys\"" { } { } 0 11837 "Started upgrading IP component %1!s! with file \"%2!s!\"" 0 0 "Shell" 0 -1 1516735653457 ""}{ "Info" "" "" "2018.01.23.17:28:24 Info: Starting to upgrade the IP cores in the Platform Designer system" { } { } 0 0 "2018.01.23.17:28:24 Info: Starting to upgrade the IP cores in the Platform Designer system" 0 0 "Shell" 0 -1 1516735704060 ""}{ "Info" "" "" "2018.01.23.17:28:24 Info: Finished upgrading the ip cores" { } { } 0 0 "2018.01.23.17:28:24 Info: Finished upgrading the ip cores" 0 0 "Shell" 0 -1 1516735704118 ""}{ "Info" "ulight_fifo_generation.rpt" "" "2018.01.23.17:28:59 Info: Saving generation log to /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo" { } { } 0 0 "2018.01.23.17:28:59 Info: Saving generation log to /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo" 0 0 "Shell" 0 -1 1516735739162 ""}{ "Info" "" "" "2018.01.23.17:28:59 Info: Starting: Create simulation model" { } { } 0 0 "2018.01.23.17:28:59 Info: Starting: Create simulation model" 0 0 "Shell" 0 -1 1516735739163 ""}{ "Info" "ulight_fifo.qsys" "" "2018.01.23.17:28:59 Info: Loading spw_fifo_ulight" { } { } 0 0 "2018.01.23.17:28:59 Info: Loading spw_fifo_ulight" 0 0 "Shell" 0 -1 1516735739395 ""}{ "Info" "" "" "2018.01.23.17:28:59 Info: Reading input file" { } { } 0 0 "2018.01.23.17:28:59 Info: Reading input file" 0 0 "Shell" 0 -1 1516735739472 ""}{ "Info" "" "" "2018.01.23.17:28:59 Info: Adding auto_start \[altera_avalon_pio 17.1\]" { } { } 0 0 "2018.01.23.17:28:59 Info: Adding auto_start \[altera_avalon_pio 17.1\]" 0 0 "Shell" 0 -1 1516735739501 ""}{ "Info" "" "" "2018.01.23.17:28:59 Info: Parameterizing module auto_start" { } { } 0 0 "2018.01.23.17:28:59 Info: Parameterizing module auto_start" 0 0 "Shell" 0 -1 1516735739502 ""}{ "Info" "" "" "2018.01.23.17:28:59 Info: Adding clk_0 \[clock_source 17.1\]" { } { } 0 0 "2018.01.23.17:28:59 Info: Adding clk_0 \[clock_source 17.1\]" 0 0 "Shell" 0 -1 1516735739503 ""}{ "Info" "" "" "2018.01.23.17:28:59 Info: Parameterizing module clk_0" { } { } 0 0 "2018.01.23.17:28:59 Info: Parameterizing module clk_0" 0 0 "Shell" 0 -1 1516735739503 ""}{ "Info" "" "" "2018.01.23.17:28:59 Info: Adding clock_sel \[altera_avalon_pio 17.1\]" { } { } 0 0 "2018.01.23.17:28:59 Info: Adding clock_sel \[altera_avalon_pio 17.1\]" 0 0 "Shell" 0 -1 1516735739504 ""}{ "Info" "" "" "2018.01.23.17:28:59 Info: Parameterizing module clock_sel" { } { } 0 0 "2018.01.23.17:28:59 Info: Parameterizing module clock_sel" 0 0 "Shell" 0 -1 1516735739505 ""}{ "Info" "" "" "2018.01.23.17:28:59 Info: Adding counter_rx_fifo \[altera_avalon_pio 17.1\]" { } { } 0 0 "2018.01.23.17:28:59 Info: Adding counter_rx_fifo \[altera_avalon_pio 17.1\]" 0 0 "Shell" 0 -1 1516735739506 ""}{ "Info" "" "" "2018.01.23.17:28:59 Info: Parameterizing module counter_rx_fifo" { } { } 0 0 "2018.01.23.17:28:59 Info: Parameterizing module counter_rx_fifo" 0 0 "Shell" 0 -1 1516735739510 ""}{ "Info" "" "" "2018.01.23.17:28:59 Info: Adding counter_tx_fifo \[altera_avalon_pio 17.1\]" { } { } 0 0 "2018.01.23.17:28:59 Info: Adding counter_tx_fifo \[altera_avalon_pio 17.1\]" 0 0 "Shell" 0 -1 1516735739513 ""}{ "Info" "" "" "2018.01.23.17:28:59 Info: Parameterizing module counter_tx_fifo" { } { } 0 0 "2018.01.23.17:28:59 Info: Parameterizing module counter_tx_fifo" 0 0 "Shell" 0 -1 1516735739515 ""}{ "Info" "" "" "2018.01.23.17:28:59 Info: Adding data_flag_rx \[altera_avalon_pio 17.1\]" { } { } 0 0 "2018.01.23.17:28:59 Info: Adding data_flag_rx \[altera_avalon_pio 17.1\]" 0 0 "Shell" 0 -1 1516735739516 ""}{ "Info" "" "" "2018.01.23.17:28:59 Info: Parameterizing module data_flag_rx" { } { } 0 0 "2018.01.23.17:28:59 Info: Parameterizing module data_flag_rx" 0 0 "Shell" 0 -1 1516735739520 ""}{ "Info" "" "" "2018.01.23.17:28:59 Info: Adding data_info \[altera_avalon_pio 17.1\]" { } { } 0 0 "2018.01.23.17:28:59 Info: Adding data_info \[altera_avalon_pio 17.1\]" 0 0 "Shell" 0 -1 1516735739522 ""}{ "Info" "" "" "2018.01.23.17:28:59 Info: Parameterizing module data_info" { } { } 0 0 "2018.01.23.17:28:59 Info: Parameterizing module data_info" 0 0 "Shell" 0 -1 1516735739523 ""}{ "Info" "" "" "2018.01.23.17:28:59 Info: Adding data_read_en_rx \[altera_avalon_pio 17.1\]" { } { } 0 0 "2018.01.23.17:28:59 Info: Adding data_read_en_rx \[altera_avalon_pio 17.1\]" 0 0 "Shell" 0 -1 1516735739525 ""}{ "Info" "" "" "2018.01.23.17:28:59 Info: Parameterizing module data_read_en_rx" { } { } 0 0 "2018.01.23.17:28:59 Info: Parameterizing module data_read_en_rx" 0 0 "Shell" 0 -1 1516735739527 ""}{ "Info" "" "" "2018.01.23.17:28:59 Info: Adding fifo_empty_rx_status \[altera_avalon_pio 17.1\]" { } { } 0 0 "2018.01.23.17:28:59 Info: Adding fifo_empty_rx_status \[altera_avalon_pio 17.1\]" 0 0 "Shell" 0 -1 1516735739528 ""}{ "Info" "" "" "2018.01.23.17:28:59 Info: Parameterizing module fifo_empty_rx_status" { } { } 0 0 "2018.01.23.17:28:59 Info: Parameterizing module fifo_empty_rx_status" 0 0 "Shell" 0 -1 1516735739543 ""}{ "Info" "" "" "2018.01.23.17:28:59 Info: Adding fifo_empty_tx_status \[altera_avalon_pio 17.1\]" { } { } 0 0 "2018.01.23.17:28:59 Info: Adding fifo_empty_tx_status \[altera_avalon_pio 17.1\]" 0 0 "Shell" 0 -1 1516735739544 ""}{ "Info" "" "" "2018.01.23.17:28:59 Info: Parameterizing module fifo_empty_tx_status" { } { } 0 0 "2018.01.23.17:28:59 Info: Parameterizing module fifo_empty_tx_status" 0 0 "Shell" 0 -1 1516735739544 ""}{ "Info" "" "" "2018.01.23.17:28:59 Info: Adding fifo_full_rx_status \[altera_avalon_pio 17.1\]" { } { } 0 0 "2018.01.23.17:28:59 Info: Adding fifo_full_rx_status \[altera_avalon_pio 17.1\]" 0 0 "Shell" 0 -1 1516735739546 ""}{ "Info" "" "" "2018.01.23.17:28:59 Info: Parameterizing module fifo_full_rx_status" { } { } 0 0 "2018.01.23.17:28:59 Info: Parameterizing module fifo_full_rx_status" 0 0 "Shell" 0 -1 1516735739546 ""}{ "Info" "" "" "2018.01.23.17:28:59 Info: Adding fifo_full_tx_status \[altera_avalon_pio 17.1\]" { } { } 0 0 "2018.01.23.17:28:59 Info: Adding fifo_full_tx_status \[altera_avalon_pio 17.1\]" 0 0 "Shell" 0 -1 1516735739547 ""}{ "Info" "" "" "2018.01.23.17:28:59 Info: Parameterizing module fifo_full_tx_status" { } { } 0 0 "2018.01.23.17:28:59 Info: Parameterizing module fifo_full_tx_status" 0 0 "Shell" 0 -1 1516735739548 ""}{ "Info" "" "" "2018.01.23.17:28:59 Info: Adding fsm_info \[altera_avalon_pio 17.1\]" { } { } 0 0 "2018.01.23.17:28:59 Info: Adding fsm_info \[altera_avalon_pio 17.1\]" 0 0 "Shell" 0 -1 1516735739548 ""}{ "Info" "" "" "2018.01.23.17:28:59 Info: Parameterizing module fsm_info" { } { } 0 0 "2018.01.23.17:28:59 Info: Parameterizing module fsm_info" 0 0 "Shell" 0 -1 1516735739549 ""}{ "Info" "" "" "2018.01.23.17:28:59 Info: Adding hps_0 \[altera_hps 17.1\]" { } { } 0 0 "2018.01.23.17:28:59 Info: Adding hps_0 \[altera_hps 17.1\]" 0 0 "Shell" 0 -1 1516735739550 ""}{ "Info" "" "" "2018.01.23.17:28:59 Info: Parameterizing module hps_0" { } { } 0 0 "2018.01.23.17:28:59 Info: Parameterizing module hps_0" 0 0 "Shell" 0 -1 1516735739564 ""}{ "Info" "" "" "2018.01.23.17:28:59 Info: Adding led_pio_test \[altera_avalon_pio 17.1\]" { } { } 0 0 "2018.01.23.17:28:59 Info: Adding led_pio_test \[altera_avalon_pio 17.1\]" 0 0 "Shell" 0 -1 1516735739586 ""}{ "Info" "" "" "2018.01.23.17:28:59 Info: Parameterizing module led_pio_test" { } { } 0 0 "2018.01.23.17:28:59 Info: Parameterizing module led_pio_test" 0 0 "Shell" 0 -1 1516735739586 ""}{ "Info" "" "" "2018.01.23.17:28:59 Info: Adding link_disable \[altera_avalon_pio 17.1\]" { } { } 0 0 "2018.01.23.17:28:59 Info: Adding link_disable \[altera_avalon_pio 17.1\]" 0 0 "Shell" 0 -1 1516735739588 ""}{ "Info" "" "" "2018.01.23.17:28:59 Info: Parameterizing module link_disable" { } { } 0 0 "2018.01.23.17:28:59 Info: Parameterizing module link_disable" 0 0 "Shell" 0 -1 1516735739589 ""}{ "Info" "" "" "2018.01.23.17:28:59 Info: Adding link_start \[altera_avalon_pio 17.1\]" { } { } 0 0 "2018.01.23.17:28:59 Info: Adding link_start \[altera_avalon_pio 17.1\]" 0 0 "Shell" 0 -1 1516735739590 ""}{ "Info" "" "" "2018.01.23.17:28:59 Info: Parameterizing module link_start" { } { } 0 0 "2018.01.23.17:28:59 Info: Parameterizing module link_start" 0 0 "Shell" 0 -1 1516735739598 ""}{ "Info" "" "" "2018.01.23.17:28:59 Info: Adding pll_0 \[altera_pll 17.1\]" { } { } 0 0 "2018.01.23.17:28:59 Info: Adding pll_0 \[altera_pll 17.1\]" 0 0 "Shell" 0 -1 1516735739599 ""}{ "Info" "" "" "2018.01.23.17:28:59 Info: Parameterizing module pll_0" { } { } 0 0 "2018.01.23.17:28:59 Info: Parameterizing module pll_0" 0 0 "Shell" 0 -1 1516735739600 ""}{ "Info" "" "" "2018.01.23.17:28:59 Info: Adding timecode_ready_rx \[altera_avalon_pio 17.1\]" { } { } 0 0 "2018.01.23.17:28:59 Info: Adding timecode_ready_rx \[altera_avalon_pio 17.1\]" 0 0 "Shell" 0 -1 1516735739604 ""}{ "Info" "" "" "2018.01.23.17:28:59 Info: Parameterizing module timecode_ready_rx" { } { } 0 0 "2018.01.23.17:28:59 Info: Parameterizing module timecode_ready_rx" 0 0 "Shell" 0 -1 1516735739605 ""}{ "Info" "" "" "2018.01.23.17:28:59 Info: Adding timecode_rx \[altera_avalon_pio 17.1\]" { } { } 0 0 "2018.01.23.17:28:59 Info: Adding timecode_rx \[altera_avalon_pio 17.1\]" 0 0 "Shell" 0 -1 1516735739606 ""}{ "Info" "" "" "2018.01.23.17:28:59 Info: Parameterizing module timecode_rx" { } { } 0 0 "2018.01.23.17:28:59 Info: Parameterizing module timecode_rx" 0 0 "Shell" 0 -1 1516735739612 ""}{ "Info" "" "" "2018.01.23.17:28:59 Info: Adding timecode_tx_data \[altera_avalon_pio 17.1\]" { } { } 0 0 "2018.01.23.17:28:59 Info: Adding timecode_tx_data \[altera_avalon_pio 17.1\]" 0 0 "Shell" 0 -1 1516735739614 ""}{ "Info" "" "" "2018.01.23.17:28:59 Info: Parameterizing module timecode_tx_data" { } { } 0 0 "2018.01.23.17:28:59 Info: Parameterizing module timecode_tx_data" 0 0 "Shell" 0 -1 1516735739615 ""}{ "Info" "" "" "2018.01.23.17:28:59 Info: Adding timecode_tx_enable \[altera_avalon_pio 17.1\]" { } { } 0 0 "2018.01.23.17:28:59 Info: Adding timecode_tx_enable \[altera_avalon_pio 17.1\]" 0 0 "Shell" 0 -1 1516735739616 ""}{ "Info" "" "" "2018.01.23.17:28:59 Info: Parameterizing module timecode_tx_enable" { } { } 0 0 "2018.01.23.17:28:59 Info: Parameterizing module timecode_tx_enable" 0 0 "Shell" 0 -1 1516735739625 ""}{ "Info" "" "" "2018.01.23.17:28:59 Info: Adding timecode_tx_ready \[altera_avalon_pio 17.1\]" { } { } 0 0 "2018.01.23.17:28:59 Info: Adding timecode_tx_ready \[altera_avalon_pio 17.1\]" 0 0 "Shell" 0 -1 1516735739627 ""}{ "Info" "" "" "2018.01.23.17:28:59 Info: Parameterizing module timecode_tx_ready" { } { } 0 0 "2018.01.23.17:28:59 Info: Parameterizing module timecode_tx_ready" 0 0 "Shell" 0 -1 1516735739627 ""}{ "Info" "" "" "2018.01.23.17:28:59 Info: Adding write_data_fifo_tx \[altera_avalon_pio 17.1\]" { } { } 0 0 "2018.01.23.17:28:59 Info: Adding write_data_fifo_tx \[altera_avalon_pio 17.1\]" 0 0 "Shell" 0 -1 1516735739628 ""}{ "Info" "" "" "2018.01.23.17:28:59 Info: Parameterizing module write_data_fifo_tx" { } { } 0 0 "2018.01.23.17:28:59 Info: Parameterizing module write_data_fifo_tx" 0 0 "Shell" 0 -1 1516735739629 ""}{ "Info" "" "" "2018.01.23.17:28:59 Info: Adding write_en_tx \[altera_avalon_pio 17.1\]" { } { } 0 0 "2018.01.23.17:28:59 Info: Adding write_en_tx \[altera_avalon_pio 17.1\]" 0 0 "Shell" 0 -1 1516735739630 ""}{ "Info" "" "" "2018.01.23.17:28:59 Info: Parameterizing module write_en_tx" { } { } 0 0 "2018.01.23.17:28:59 Info: Parameterizing module write_en_tx" 0 0 "Shell" 0 -1 1516735739631 ""}{ "Info" "" "" "2018.01.23.17:28:59 Info: Building connections" { } { } 0 0 "2018.01.23.17:28:59 Info: Building connections" 0 0 "Shell" 0 -1 1516735739632 ""}{ "Info" "" "" "2018.01.23.17:28:59 Info: Parameterizing connections" { } { } 0 0 "2018.01.23.17:28:59 Info: Parameterizing connections" 0 0 "Shell" 0 -1 1516735739642 ""}{ "Info" "" "" "2018.01.23.17:28:59 Info: Validating" { } { } 0 0 "2018.01.23.17:28:59 Info: Validating" 0 0 "Shell" 0 -1 1516735739645 ""}{ "Info" "" "" "2018.01.23.17:29:08 Info: Done reading input file" { } { } 0 0 "2018.01.23.17:29:08 Info: Done reading input file" 0 0 "Shell" 0 -1 1516735748747 ""}{ "Info" "" "" "2018.01.23.17:29:12 Info: ulight_fifo.counter_rx_fifo: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation." { } { } 0 0 "2018.01.23.17:29:12 Info: ulight_fifo.counter_rx_fifo: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation." 0 0 "Shell" 0 -1 1516735752187 ""}{ "Info" "" "" "2018.01.23.17:29:12 Info: ulight_fifo.counter_tx_fifo: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation." { } { } 0 0 "2018.01.23.17:29:12 Info: ulight_fifo.counter_tx_fifo: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation." 0 0 "Shell" 0 -1 1516735752187 ""}{ "Info" "" "" "2018.01.23.17:29:12 Info: ulight_fifo.data_flag_rx: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.\n2018.01.23.17:29:12 Info: ulight_fifo.data_info: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.\n2018.01.23.17:29:12 Info: ulight_fifo.fifo_empty_rx_status: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.\n2018.01.23.17:29:12 Info: ulight_fifo.fifo_empty_tx_status: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.\n2018.01.23.17:29:12 Info: ulight_fifo.fifo_full_rx_status: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.\n2018.01.23.17:29:12 Info: ulight_fifo.fifo_full_tx_status: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.\n2018.01.23.17:29:12 Info: ulight_fifo.fsm_info: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.\n2018.01.23.17:29:12 Info: ulight_fifo.hps_0: HPS Main PLL counter settings: n = 0 m = 36" { } { } 0 0 "2018.01.23.17:29:12 Info: ulight_fifo.data_flag_rx: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.\n2018.01.23.17:29:12 Info: ulight_fifo.data_info: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.\n2018.01.23.17:29:12 Info: ulight_fifo.fifo_empty_rx_status: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.\n2018.01.23.17:29:12 Info: ulight_fifo.fifo_empty_tx_status: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.\n2018.01.23.17:29:12 Info: ulight_fifo.fifo_full_rx_status: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.\n2018.01.23.17:29:12 Info: ulight_fifo.fifo_full_tx_status: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.\n2018.01.23.17:29:12 Info: ulight_fifo.fsm_info: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.\n2018.01.23.17:29:12 Info: ulight_fifo.hps_0: HPS Main PLL counter settings: n = 0 m = 36" 0 0 "Shell" 0 -1 1516735752190 ""}{ "Info" "" "" "2018.01.23.17:29:12 Info: ulight_fifo.hps_0: HPS peripherial PLL counter settings: n = 0 m = 19" { } { } 0 0 "2018.01.23.17:29:12 Info: ulight_fifo.hps_0: HPS peripherial PLL counter settings: n = 0 m = 19" 0 0 "Shell" 0 -1 1516735752190 ""}{ "Info" "" "" "2018.01.23.17:29:12 Info: ulight_fifo.pll_0: The legal reference clock frequency is 5.0 MHz..800.0 MHz" { } { } 0 0 "2018.01.23.17:29:12 Info: ulight_fifo.pll_0: The legal reference clock frequency is 5.0 MHz..800.0 MHz" 0 0 "Shell" 0 -1 1516735752196 ""}{ "Warning" "" "" "2018.01.23.17:29:12 Warning: ulight_fifo.pll_0: 'refclk1' is not the same frequency as 'refclk'. You must run Timequest at both frequencies to ensure timing closure" { } { } 0 0 "2018.01.23.17:29:12 Warning: ulight_fifo.pll_0: 'refclk1' is not the same frequency as 'refclk'. You must run Timequest at both frequencies to ensure timing closure" 0 0 "Shell" 0 -1 1516735752197 ""}{ "Warning" "" "" "2018.01.23.17:29:12 Warning: ulight_fifo.pll_0: The period difference between refclk and refclk1 is greater than 20%, automatic clock loss detection will not work" { } { } 0 0 "2018.01.23.17:29:12 Warning: ulight_fifo.pll_0: The period difference between refclk and refclk1 is greater than 20%, automatic clock loss detection will not work" 0 0 "Shell" 0 -1 1516735752198 ""}{ "Info" "" "" "2018.01.23.17:29:12 Info: ulight_fifo.pll_0: Able to implement PLL with user settings" { } { } 0 0 "2018.01.23.17:29:12 Info: ulight_fifo.pll_0: Able to implement PLL with user settings" 0 0 "Shell" 0 -1 1516735752198 ""}{ "Warning" "" "" "2018.01.23.17:29:12 Warning: ulight_fifo.pll_0.refclk1: Signal refclk1 has unknown type refclk1" { } { } 0 0 "2018.01.23.17:29:12 Warning: ulight_fifo.pll_0.refclk1: Signal refclk1 has unknown type refclk1" 0 0 "Shell" 0 -1 1516735752198 ""}{ "Info" "" "" "2018.01.23.17:29:12 Info: ulight_fifo.timecode_ready_rx: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation." { } { } 0 0 "2018.01.23.17:29:12 Info: ulight_fifo.timecode_ready_rx: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation." 0 0 "Shell" 0 -1 1516735752199 ""}{ "Info" "" "" "2018.01.23.17:29:12 Info: ulight_fifo.timecode_rx: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation." { } { } 0 0 "2018.01.23.17:29:12 Info: ulight_fifo.timecode_rx: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation." 0 0 "Shell" 0 -1 1516735752199 ""}{ "Info" "" "" "2018.01.23.17:29:12 Info: ulight_fifo.timecode_tx_ready: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation." { } { } 0 0 "2018.01.23.17:29:12 Info: ulight_fifo.timecode_tx_ready: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation." 0 0 "Shell" 0 -1 1516735752200 ""}{ "Info" "" "" "2018.01.23.17:29:16 Info: ulight_fifo: Generating ulight_fifo \"ulight_fifo\" for SIM_VERILOG" { } { } 0 0 "2018.01.23.17:29:16 Info: ulight_fifo: Generating ulight_fifo \"ulight_fifo\" for SIM_VERILOG" 0 0 "Shell" 0 -1 1516735756855 ""}{ "Warning" "" "" "2018.01.23.17:29:35 Warning: ulight_fifo: \"No matching role found for clk_0:clk:clk_out (clk)\"" { } { } 0 0 "2018.01.23.17:29:35 Warning: ulight_fifo: \"No matching role found for clk_0:clk:clk_out (clk)\"" 0 0 "Shell" 0 -1 1516735775279 ""}{ "Warning" "" "" "2018.01.23.17:29:35 Warning: ulight_fifo: \"No matching role found for pll_0:refclk1:refclk1 (refclk1)\"" { } { } 0 0 "2018.01.23.17:29:35 Warning: ulight_fifo: \"No matching role found for pll_0:refclk1:refclk1 (refclk1)\"" 0 0 "Shell" 0 -1 1516735775279 ""}{ "Info" "" "" "2018.01.23.17:29:39 Info: auto_start: Starting RTL generation for module 'ulight_fifo_auto_start'" { } { } 0 0 "2018.01.23.17:29:39 Info: auto_start: Starting RTL generation for module 'ulight_fifo_auto_start'" 0 0 "Shell" 0 -1 1516735779023 ""}{ "Info" " ]" "" "2018.01.23.17:29:39 Info: auto_start: Generation command is \[exec /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/bin/perl -I /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/europa -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/perl_lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/common -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=ulight_fifo_auto_start --dir=/tmp/alt7554_7831099621877055177.dir/0002_auto_start_gen/ --quartus_dir=/home/felipe/intelFPGA_lite/17.1/quartus --verilog --config=/tmp/alt7554_7831099621877055177.dir/0002_auto_start_gen//ulight_fifo_auto_start_component_configuration.pl --do_build_sim=1 --sim_dir=/tmp/alt7554_7831099621877055177.dir/0002_auto_start_gen" { } { } 0 0 "2018.01.23.17:29:39 Info: auto_start: Generation command is \[exec /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/bin/perl -I /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/europa -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/perl_lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/common -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=ulight_fifo_auto_start --dir=/tmp/alt7554_7831099621877055177.dir/0002_auto_start_gen/ --quartus_dir=/home/felipe/intelFPGA_lite/17.1/quartus --verilog --config=/tmp/alt7554_7831099621877055177.dir/0002_auto_start_gen//ulight_fifo_auto_start_component_configuration.pl --do_build_sim=1 --sim_dir=/tmp/alt7554_7831099621877055177.dir/0002_auto_start_gen" 0 0 "Shell" 0 -1 1516735779023 ""}{ "Info" "" "" "2018.01.23.17:29:40 Info: auto_start: Done RTL generation for module 'ulight_fifo_auto_start'" { } { } 0 0 "2018.01.23.17:29:40 Info: auto_start: Done RTL generation for module 'ulight_fifo_auto_start'" 0 0 "Shell" 0 -1 1516735780647 ""}{ "Info" "" "" "2018.01.23.17:29:40 Info: auto_start: \"ulight_fifo\" instantiated altera_avalon_pio \"auto_start\"" { } { } 0 0 "2018.01.23.17:29:40 Info: auto_start: \"ulight_fifo\" instantiated altera_avalon_pio \"auto_start\"" 0 0 "Shell" 0 -1 1516735780650 ""}{ "Info" "" "" "2018.01.23.17:29:40 Info: clock_sel: Starting RTL generation for module 'ulight_fifo_clock_sel'" { } { } 0 0 "2018.01.23.17:29:40 Info: clock_sel: Starting RTL generation for module 'ulight_fifo_clock_sel'" 0 0 "Shell" 0 -1 1516735780733 ""}{ "Info" " ]" "" "2018.01.23.17:29:40 Info: clock_sel: Generation command is \[exec /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/bin/perl -I /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/europa -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/perl_lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/common -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=ulight_fifo_clock_sel --dir=/tmp/alt7554_7831099621877055177.dir/0003_clock_sel_gen/ --quartus_dir=/home/felipe/intelFPGA_lite/17.1/quartus --verilog --config=/tmp/alt7554_7831099621877055177.dir/0003_clock_sel_gen//ulight_fifo_clock_sel_component_configuration.pl --do_build_sim=1 --sim_dir=/tmp/alt7554_7831099621877055177.dir/0003_clock_sel_gen" { } { } 0 0 "2018.01.23.17:29:40 Info: clock_sel: Generation command is \[exec /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/bin/perl -I /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/europa -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/perl_lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/common -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=ulight_fifo_clock_sel --dir=/tmp/alt7554_7831099621877055177.dir/0003_clock_sel_gen/ --quartus_dir=/home/felipe/intelFPGA_lite/17.1/quartus --verilog --config=/tmp/alt7554_7831099621877055177.dir/0003_clock_sel_gen//ulight_fifo_clock_sel_component_configuration.pl --do_build_sim=1 --sim_dir=/tmp/alt7554_7831099621877055177.dir/0003_clock_sel_gen" 0 0 "Shell" 0 -1 1516735780733 ""}{ "Info" "" "" "2018.01.23.17:29:40 Info: clock_sel: Done RTL generation for module 'ulight_fifo_clock_sel'" { } { } 0 0 "2018.01.23.17:29:40 Info: clock_sel: Done RTL generation for module 'ulight_fifo_clock_sel'" 0 0 "Shell" 0 -1 1516735780886 ""}{ "Info" "" "" "2018.01.23.17:29:40 Info: clock_sel: \"ulight_fifo\" instantiated altera_avalon_pio \"clock_sel\"" { } { } 0 0 "2018.01.23.17:29:40 Info: clock_sel: \"ulight_fifo\" instantiated altera_avalon_pio \"clock_sel\"" 0 0 "Shell" 0 -1 1516735780888 ""}{ "Info" "" "" "2018.01.23.17:29:40 Info: counter_rx_fifo: Starting RTL generation for module 'ulight_fifo_counter_rx_fifo'" { } { } 0 0 "2018.01.23.17:29:40 Info: counter_rx_fifo: Starting RTL generation for module 'ulight_fifo_counter_rx_fifo'" 0 0 "Shell" 0 -1 1516735780972 ""}{ "Info" " ]" "" "2018.01.23.17:29:40 Info: counter_rx_fifo: Generation command is \[exec /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/bin/perl -I /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/europa -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/perl_lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/common -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=ulight_fifo_counter_rx_fifo --dir=/tmp/alt7554_7831099621877055177.dir/0004_counter_rx_fifo_gen/ --quartus_dir=/home/felipe/intelFPGA_lite/17.1/quartus --verilog --config=/tmp/alt7554_7831099621877055177.dir/0004_counter_rx_fifo_gen//ulight_fifo_counter_rx_fifo_component_configuration.pl --do_build_sim=1 --sim_dir=/tmp/alt7554_7831099621877055177.dir/0004_counter_rx_fifo_gen" { } { } 0 0 "2018.01.23.17:29:40 Info: counter_rx_fifo: Generation command is \[exec /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/bin/perl -I /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/europa -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/perl_lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/common -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=ulight_fifo_counter_rx_fifo --dir=/tmp/alt7554_7831099621877055177.dir/0004_counter_rx_fifo_gen/ --quartus_dir=/home/felipe/intelFPGA_lite/17.1/quartus --verilog --config=/tmp/alt7554_7831099621877055177.dir/0004_counter_rx_fifo_gen//ulight_fifo_counter_rx_fifo_component_configuration.pl --do_build_sim=1 --sim_dir=/tmp/alt7554_7831099621877055177.dir/0004_counter_rx_fifo_gen" 0 0 "Shell" 0 -1 1516735780972 ""}{ "Info" "" "" "2018.01.23.17:29:41 Info: counter_rx_fifo: Done RTL generation for module 'ulight_fifo_counter_rx_fifo'\n2018.01.23.17:29:41 Info: counter_rx_fifo: \"ulight_fifo\" instantiated altera_avalon_pio \"counter_rx_fifo\"" { } { } 0 0 "2018.01.23.17:29:41 Info: counter_rx_fifo: Done RTL generation for module 'ulight_fifo_counter_rx_fifo'\n2018.01.23.17:29:41 Info: counter_rx_fifo: \"ulight_fifo\" instantiated altera_avalon_pio \"counter_rx_fifo\"" 0 0 "Shell" 0 -1 1516735781099 ""}{ "Info" "" "" "2018.01.23.17:29:41 Info: data_flag_rx: Starting RTL generation for module 'ulight_fifo_data_flag_rx'" { } { } 0 0 "2018.01.23.17:29:41 Info: data_flag_rx: Starting RTL generation for module 'ulight_fifo_data_flag_rx'" 0 0 "Shell" 0 -1 1516735781242 ""}{ "Info" " ]" "" "2018.01.23.17:29:41 Info: data_flag_rx: Generation command is \[exec /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/bin/perl -I /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/europa -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/perl_lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/common -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=ulight_fifo_data_flag_rx --dir=/tmp/alt7554_7831099621877055177.dir/0005_data_flag_rx_gen/ --quartus_dir=/home/felipe/intelFPGA_lite/17.1/quartus --verilog --config=/tmp/alt7554_7831099621877055177.dir/0005_data_flag_rx_gen//ulight_fifo_data_flag_rx_component_configuration.pl --do_build_sim=1 --sim_dir=/tmp/alt7554_7831099621877055177.dir/0005_data_flag_rx_gen" { } { } 0 0 "2018.01.23.17:29:41 Info: data_flag_rx: Generation command is \[exec /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/bin/perl -I /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/europa -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/perl_lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/common -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=ulight_fifo_data_flag_rx --dir=/tmp/alt7554_7831099621877055177.dir/0005_data_flag_rx_gen/ --quartus_dir=/home/felipe/intelFPGA_lite/17.1/quartus --verilog --config=/tmp/alt7554_7831099621877055177.dir/0005_data_flag_rx_gen//ulight_fifo_data_flag_rx_component_configuration.pl --do_build_sim=1 --sim_dir=/tmp/alt7554_7831099621877055177.dir/0005_data_flag_rx_gen" 0 0 "Shell" 0 -1 1516735781242 ""}{ "Info" "" "" "2018.01.23.17:29:41 Info: data_flag_rx: Done RTL generation for module 'ulight_fifo_data_flag_rx'\n2018.01.23.17:29:41 Info: data_flag_rx: \"ulight_fifo\" instantiated altera_avalon_pio \"data_flag_rx\"" { } { } 0 0 "2018.01.23.17:29:41 Info: data_flag_rx: Done RTL generation for module 'ulight_fifo_data_flag_rx'\n2018.01.23.17:29:41 Info: data_flag_rx: \"ulight_fifo\" instantiated altera_avalon_pio \"data_flag_rx\"" 0 0 "Shell" 0 -1 1516735781379 ""}{ "Info" "" "" "2018.01.23.17:29:41 Info: data_info: Starting RTL generation for module 'ulight_fifo_data_info'" { } { } 0 0 "2018.01.23.17:29:41 Info: data_info: Starting RTL generation for module 'ulight_fifo_data_info'" 0 0 "Shell" 0 -1 1516735781502 ""}{ "Info" " ]" "" "2018.01.23.17:29:41 Info: data_info: Generation command is \[exec /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/bin/perl -I /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/europa -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/perl_lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/common -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=ulight_fifo_data_info --dir=/tmp/alt7554_7831099621877055177.dir/0006_data_info_gen/ --quartus_dir=/home/felipe/intelFPGA_lite/17.1/quartus --verilog --config=/tmp/alt7554_7831099621877055177.dir/0006_data_info_gen//ulight_fifo_data_info_component_configuration.pl --do_build_sim=1 --sim_dir=/tmp/alt7554_7831099621877055177.dir/0006_data_info_gen" { } { } 0 0 "2018.01.23.17:29:41 Info: data_info: Generation command is \[exec /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/bin/perl -I /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/europa -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/perl_lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/common -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=ulight_fifo_data_info --dir=/tmp/alt7554_7831099621877055177.dir/0006_data_info_gen/ --quartus_dir=/home/felipe/intelFPGA_lite/17.1/quartus --verilog --config=/tmp/alt7554_7831099621877055177.dir/0006_data_info_gen//ulight_fifo_data_info_component_configuration.pl --do_build_sim=1 --sim_dir=/tmp/alt7554_7831099621877055177.dir/0006_data_info_gen" 0 0 "Shell" 0 -1 1516735781502 ""}{ "Info" "" "" "2018.01.23.17:29:41 Info: data_info: Done RTL generation for module 'ulight_fifo_data_info'" { } { } 0 0 "2018.01.23.17:29:41 Info: data_info: Done RTL generation for module 'ulight_fifo_data_info'" 0 0 "Shell" 0 -1 1516735781634 ""}{ "Info" "" "" "2018.01.23.17:29:41 Info: data_info: \"ulight_fifo\" instantiated altera_avalon_pio \"data_info\"" { } { } 0 0 "2018.01.23.17:29:41 Info: data_info: \"ulight_fifo\" instantiated altera_avalon_pio \"data_info\"" 0 0 "Shell" 0 -1 1516735781635 ""}{ "Info" "" "" "2018.01.23.17:29:41 Info: fifo_empty_rx_status: Starting RTL generation for module 'ulight_fifo_fifo_empty_rx_status'" { } { } 0 0 "2018.01.23.17:29:41 Info: fifo_empty_rx_status: Starting RTL generation for module 'ulight_fifo_fifo_empty_rx_status'" 0 0 "Shell" 0 -1 1516735781751 ""}{ "Info" " ]" "" "2018.01.23.17:29:41 Info: fifo_empty_rx_status: Generation command is \[exec /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/bin/perl -I /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/europa -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/perl_lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/common -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=ulight_fifo_fifo_empty_rx_status --dir=/tmp/alt7554_7831099621877055177.dir/0007_fifo_empty_rx_status_gen/ --quartus_dir=/home/felipe/intelFPGA_lite/17.1/quartus --verilog --config=/tmp/alt7554_7831099621877055177.dir/0007_fifo_empty_rx_status_gen//ulight_fifo_fifo_empty_rx_status_component_configuration.pl --do_build_sim=1 --sim_dir=/tmp/alt7554_7831099621877055177.dir/0007_fifo_empty_rx_status_gen" { } { } 0 0 "2018.01.23.17:29:41 Info: fifo_empty_rx_status: Generation command is \[exec /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/bin/perl -I /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/europa -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/perl_lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/common -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=ulight_fifo_fifo_empty_rx_status --dir=/tmp/alt7554_7831099621877055177.dir/0007_fifo_empty_rx_status_gen/ --quartus_dir=/home/felipe/intelFPGA_lite/17.1/quartus --verilog --config=/tmp/alt7554_7831099621877055177.dir/0007_fifo_empty_rx_status_gen//ulight_fifo_fifo_empty_rx_status_component_configuration.pl --do_build_sim=1 --sim_dir=/tmp/alt7554_7831099621877055177.dir/0007_fifo_empty_rx_status_gen" 0 0 "Shell" 0 -1 1516735781752 ""}{ "Info" "" "" "2018.01.23.17:29:41 Info: fifo_empty_rx_status: Done RTL generation for module 'ulight_fifo_fifo_empty_rx_status'" { } { } 0 0 "2018.01.23.17:29:41 Info: fifo_empty_rx_status: Done RTL generation for module 'ulight_fifo_fifo_empty_rx_status'" 0 0 "Shell" 0 -1 1516735781904 ""}{ "Info" "" "" "2018.01.23.17:29:41 Info: fifo_empty_rx_status: \"ulight_fifo\" instantiated altera_avalon_pio \"fifo_empty_rx_status\"" { } { } 0 0 "2018.01.23.17:29:41 Info: fifo_empty_rx_status: \"ulight_fifo\" instantiated altera_avalon_pio \"fifo_empty_rx_status\"" 0 0 "Shell" 0 -1 1516735781906 ""}{ "Info" "" "" "2018.01.23.17:29:41 Info: hps_0: \"Running for module: hps_0\"" { } { } 0 0 "2018.01.23.17:29:41 Info: hps_0: \"Running for module: hps_0\"" 0 0 "Shell" 0 -1 1516735781908 ""}{ "Info" "" "" "2018.01.23.17:29:42 Info: hps_0: HPS Main PLL counter settings: n = 0 m = 36" { } { } 0 0 "2018.01.23.17:29:42 Info: hps_0: HPS Main PLL counter settings: n = 0 m = 36" 0 0 "Shell" 0 -1 1516735782735 ""}{ "Info" "" "" "2018.01.23.17:29:43 Info: hps_0: HPS peripherial PLL counter settings: n = 0 m = 19" { } { } 0 0 "2018.01.23.17:29:43 Info: hps_0: HPS peripherial PLL counter settings: n = 0 m = 19" 0 0 "Shell" 0 -1 1516735783333 ""}{ "Warning" "" "" "2018.01.23.17:29:43 Warning: hps_0: 1 or more output clock frequencies cannot be achieved precisely, consider revising desired output clock frequencies." { } { } 0 0 "2018.01.23.17:29:43 Warning: hps_0: 1 or more output clock frequencies cannot be achieved precisely, consider revising desired output clock frequencies." 0 0 "Shell" 0 -1 1516735783343 ""}{ "Warning" "" "" "2018.01.23.17:29:43 Warning: hps_0: ODT is disabled. Enabling ODT (Mode Register 1) may improve signal integrity" { } { } 0 0 "2018.01.23.17:29:43 Warning: hps_0: ODT is disabled. Enabling ODT (Mode Register 1) may improve signal integrity" 0 0 "Shell" 0 -1 1516735783636 ""}{ "Warning" "" "" "2018.01.23.17:29:43 Warning: hps_0: set_interface_assignment: Interface \"hps_io\" does not exist" { } { } 0 0 "2018.01.23.17:29:43 Warning: hps_0: set_interface_assignment: Interface \"hps_io\" does not exist" 0 0 "Shell" 0 -1 1516735783757 ""}{ "Info" "" "" "2018.01.23.17:29:44 Info: hps_0: \"ulight_fifo\" instantiated altera_hps \"hps_0\"" { } { } 0 0 "2018.01.23.17:29:44 Info: hps_0: \"ulight_fifo\" instantiated altera_hps \"hps_0\"" 0 0 "Shell" 0 -1 1516735784424 ""}{ "Info" " ]" "" "2018.01.23.17:29:44 Info: led_pio_test: Starting RTL generation for module 'ulight_fifo_led_pio_test'\n2018.01.23.17:29:44 Info: led_pio_test: Generation command is \[exec /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/bin/perl -I /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/europa -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/perl_lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/common -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=ulight_fifo_led_pio_test --dir=/tmp/alt7554_7831099621877055177.dir/0008_led_pio_test_gen/ --quartus_dir=/home/felipe/intelFPGA_lite/17.1/quartus --verilog --config=/tmp/alt7554_7831099621877055177.dir/0008_led_pio_test_gen//ulight_fifo_led_pio_test_component_configuration.pl --do_build_sim=1 --sim_dir=/tmp/alt7554_7831099621877055177.dir/0008_led_pio_test_gen" { } { } 0 0 "2018.01.23.17:29:44 Info: led_pio_test: Starting RTL generation for module 'ulight_fifo_led_pio_test'\n2018.01.23.17:29:44 Info: led_pio_test: Generation command is \[exec /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/bin/perl -I /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/europa -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/perl_lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/common -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=ulight_fifo_led_pio_test --dir=/tmp/alt7554_7831099621877055177.dir/0008_led_pio_test_gen/ --quartus_dir=/home/felipe/intelFPGA_lite/17.1/quartus --verilog --config=/tmp/alt7554_7831099621877055177.dir/0008_led_pio_test_gen//ulight_fifo_led_pio_test_component_configuration.pl --do_build_sim=1 --sim_dir=/tmp/alt7554_7831099621877055177.dir/0008_led_pio_test_gen" 0 0 "Shell" 0 -1 1516735784521 ""}{ "Info" "" "" "2018.01.23.17:29:44 Info: led_pio_test: Done RTL generation for module 'ulight_fifo_led_pio_test'\n2018.01.23.17:29:44 Info: led_pio_test: \"ulight_fifo\" instantiated altera_avalon_pio \"led_pio_test\"" { } { } 0 0 "2018.01.23.17:29:44 Info: led_pio_test: Done RTL generation for module 'ulight_fifo_led_pio_test'\n2018.01.23.17:29:44 Info: led_pio_test: \"ulight_fifo\" instantiated altera_avalon_pio \"led_pio_test\"" 0 0 "Shell" 0 -1 1516735784720 ""}{ "Info" "" "" "2018.01.23.17:29:44 Info: pll_0: Generating simgen model" { } { } 0 0 "2018.01.23.17:29:44 Info: pll_0: Generating simgen model" 0 0 "Shell" 0 -1 1516735784779 ""}{ "Info" "" "" "2018.01.23.17:30:12 Info: pll_0: Simgen was successful" { } { } 0 0 "2018.01.23.17:30:12 Info: pll_0: Simgen was successful" 0 0 "Shell" 0 -1 1516735812813 ""}{ "Info" "" "" "2018.01.23.17:30:12 Info: pll_0: \"ulight_fifo\" instantiated altera_pll \"pll_0\"" { } { } 0 0 "2018.01.23.17:30:12 Info: pll_0: \"ulight_fifo\" instantiated altera_pll \"pll_0\"" 0 0 "Shell" 0 -1 1516735812815 ""}{ "Info" "" "" "2018.01.23.17:30:12 Info: timecode_rx: Starting RTL generation for module 'ulight_fifo_timecode_rx'" { } { } 0 0 "2018.01.23.17:30:12 Info: timecode_rx: Starting RTL generation for module 'ulight_fifo_timecode_rx'" 0 0 "Shell" 0 -1 1516735812969 ""}{ "Info" " ]" "" "2018.01.23.17:30:12 Info: timecode_rx: Generation command is \[exec /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/bin/perl -I /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/europa -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/perl_lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/common -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=ulight_fifo_timecode_rx --dir=/tmp/alt7554_7831099621877055177.dir/0010_timecode_rx_gen/ --quartus_dir=/home/felipe/intelFPGA_lite/17.1/quartus --verilog --config=/tmp/alt7554_7831099621877055177.dir/0010_timecode_rx_gen//ulight_fifo_timecode_rx_component_configuration.pl --do_build_sim=1 --sim_dir=/tmp/alt7554_7831099621877055177.dir/0010_timecode_rx_gen" { } { } 0 0 "2018.01.23.17:30:12 Info: timecode_rx: Generation command is \[exec /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/bin/perl -I /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/europa -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/perl_lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/common -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=ulight_fifo_timecode_rx --dir=/tmp/alt7554_7831099621877055177.dir/0010_timecode_rx_gen/ --quartus_dir=/home/felipe/intelFPGA_lite/17.1/quartus --verilog --config=/tmp/alt7554_7831099621877055177.dir/0010_timecode_rx_gen//ulight_fifo_timecode_rx_component_configuration.pl --do_build_sim=1--sim_dir=/tmp/alt7554_7831099621877055177.dir/0010_timecode_rx_gen" 0 0 "Shell" 0 -1 1516735812970 ""}{ "Info" "" "" "2018.01.23.17:30:13 Info: timecode_rx: Done RTL generation for module 'ulight_fifo_timecode_rx'" { } { } 0 0 "2018.01.23.17:30:13 Info: timecode_rx: Done RTL generation for module 'ulight_fifo_timecode_rx'" 0 0 "Shell" 0 -1 1516735813142 ""}{ "Info" "" "" "2018.01.23.17:30:13 Info: timecode_rx: \"ulight_fifo\" instantiated altera_avalon_pio \"timecode_rx\"" { } { } 0 0 "2018.01.23.17:30:13 Info: timecode_rx: \"ulight_fifo\" instantiated altera_avalon_pio \"timecode_rx\"" 0 0 "Shell" 0 -1 1516735813144 ""}{ "Info" "" "" "2018.01.23.17:30:13 Info: timecode_tx_data: Starting RTL generation for module 'ulight_fifo_timecode_tx_data'" { } { } 0 0 "2018.01.23.17:30:13 Info: timecode_tx_data: Starting RTL generation for module 'ulight_fifo_timecode_tx_data'" 0 0 "Shell" 0 -1 1516735813212 ""}{ "Info" " ]" "" "2018.01.23.17:30:13 Info: timecode_tx_data: Generation command is \[exec /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/bin/perl -I /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/europa -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/perl_lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/common -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=ulight_fifo_timecode_tx_data --dir=/tmp/alt7554_7831099621877055177.dir/0011_timecode_tx_data_gen/ --quartus_dir=/home/felipe/intelFPGA_lite/17.1/quartus --verilog --config=/tmp/alt7554_7831099621877055177.dir/0011_timecode_tx_data_gen//ulight_fifo_timecode_tx_data_component_configuration.pl --do_build_sim=1 --sim_dir=/tmp/alt7554_7831099621877055177.dir/0011_timecode_tx_data_gen" { } { } 0 0 "2018.01.23.17:30:13 Info: timecode_tx_data: Generation command is \[exec /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/bin/perl -I /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/europa -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/perl_lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/common -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=ulight_fifo_timecode_tx_data --dir=/tmp/alt7554_7831099621877055177.dir/0011_timecode_tx_data_gen/ --quartus_dir=/home/felipe/intelFPGA_lite/17.1/quartus --verilog --config=/tmp/alt7554_7831099621877055177.dir/0011_timecode_tx_data_gen//ulight_fifo_timecode_tx_data_component_configuration.pl --do_build_sim=1 --sim_dir=/tmp/alt7554_7831099621877055177.dir/0011_timecode_tx_data_gen" 0 0 "Shell" 0 -1 1516735813212 ""}{ "Info" "" "" "2018.01.23.17:30:13 Info: timecode_tx_data: Done RTL generation for module 'ulight_fifo_timecode_tx_data'" { } { } 0 0 "2018.01.23.17:30:13 Info: timecode_tx_data: Done RTL generation for module 'ulight_fifo_timecode_tx_data'" 0 0 "Shell" 0 -1 1516735813329 ""}{ "Info" "" "" "2018.01.23.17:30:13 Info: timecode_tx_data: \"ulight_fifo\" instantiated altera_avalon_pio \"timecode_tx_data\"" { } { } 0 0 "2018.01.23.17:30:13 Info: timecode_tx_data: \"ulight_fifo\" instantiated altera_avalon_pio \"timecode_tx_data\"" 0 0 "Shell" 0 -1 1516735813330 ""}{ "Info" "" "" "2018.01.23.17:30:13 Info: write_data_fifo_tx: Starting RTL generation for module 'ulight_fifo_write_data_fifo_tx'" { } { } 0 0 "2018.01.23.17:30:13 Info: write_data_fifo_tx: Starting RTL generation for module 'ulight_fifo_write_data_fifo_tx'" 0 0 "Shell" 0 -1 1516735813400 ""}{ "Info" " ]" "" "2018.01.23.17:30:13 Info: write_data_fifo_tx: Generation command is \[exec /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/bin/perl -I /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/europa -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/perl_lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/common -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=ulight_fifo_write_data_fifo_tx --dir=/tmp/alt7554_7831099621877055177.dir/0012_write_data_fifo_tx_gen/ --quartus_dir=/home/felipe/intelFPGA_lite/17.1/quartus --verilog --config=/tmp/alt7554_7831099621877055177.dir/0012_write_data_fifo_tx_gen//ulight_fifo_write_data_fifo_tx_component_configuration.pl --do_build_sim=1--sim_dir=/tmp/alt7554_7831099621877055177.dir/0012_write_data_fifo_tx_gen" { } { } 0 0 "2018.01.23.17:30:13 Info: write_data_fifo_tx: Generation command is \[exec /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/bin/perl -I /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/europa -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/perl_lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/common -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=ulight_fifo_write_data_fifo_tx --dir=/tmp/alt7554_7831099621877055177.dir/0012_write_data_fifo_tx_gen/ --quartus_dir=/home/felipe/intelFPGA_lite/17.1/quartus --verilog --config=/tmp/alt7554_7831099621877055177.dir/0012_write_data_fifo_tx_gen//ulight_fifo_write_data_fifo_tx_component_configuration.pl --do_build_sim=1 --sim_dir=/tmp/alt7554_7831099621877055177.dir/0012_write_data_fifo_tx_gen" 0 0 "Shell" 0 -1 1516735813401 ""}{ "Info" "" "" "2018.01.23.17:30:13 Info: write_data_fifo_tx: Done RTL generation for module 'ulight_fifo_write_data_fifo_tx'" { } { } 0 0 "2018.01.23.17:30:13 Info: write_data_fifo_tx: Done RTL generation for module 'ulight_fifo_write_data_fifo_tx'" 0 0 "Shell" 0 -1 1516735813531 ""}{ "Info" "" "" "2018.01.23.17:30:13 Info: write_data_fifo_tx: \"ulight_fifo\" instantiated altera_avalon_pio \"write_data_fifo_tx\"" { } { } 0 0 "2018.01.23.17:30:13 Info: write_data_fifo_tx: \"ulight_fifo\" instantiated altera_avalon_pio \"write_data_fifo_tx\"" 0 0 "Shell" 0 -1 1516735813533 ""}{ "Info" "" "" "2018.01.23.17:30:15 Info: avalon_st_adapter: Inserting error_adapter: error_adapter_0" { } { } 0 0 "2018.01.23.17:30:15 Info: avalon_st_adapter: Inserting error_adapter: error_adapter_0" 0 0 "Shell" 0 -1 1516735815764 ""}{ "Info" "" "" "2018.01.23.17:30:15 Info: avalon_st_adapter_001: Inserting error_adapter: error_adapter_0" { } { } 0 0 "2018.01.23.17:30:15 Info: avalon_st_adapter_001: Inserting error_adapter: error_adapter_0" 0 0 "Shell" 0 -1 1516735815843 ""}{ "Info" "" "" "2018.01.23.17:30:15 Info: avalon_st_adapter_002: Inserting error_adapter: error_adapter_0" { } { } 0 0 "2018.01.23.17:30:15 Info: avalon_st_adapter_002: Inserting error_adapter: error_adapter_0" 0 0 "Shell" 0 -1 1516735815918 ""}{ "Info" "" "" "2018.01.23.17:30:15 Info: avalon_st_adapter_003: Inserting error_adapter: error_adapter_0" { } { } 0 0 "2018.01.23.17:30:15 Info: avalon_st_adapter_003: Inserting error_adapter: error_adapter_0" 0 0 "Shell" 0 -1 1516735815973 ""}{ "Info" "" "" "2018.01.23.17:30:16 Info: avalon_st_adapter_004: Inserting error_adapter: error_adapter_0" { } { } 0 0 "2018.01.23.17:30:16 Info: avalon_st_adapter_004: Inserting error_adapter: error_adapter_0" 0 0 "Shell" 0 -1 1516735816040 ""}{ "Info" "" "" "2018.01.23.17:30:16 Info: avalon_st_adapter_005: Inserting error_adapter: error_adapter_0" { } { } 0 0 "2018.01.23.17:30:16 Info: avalon_st_adapter_005: Inserting error_adapter: error_adapter_0" 0 0 "Shell" 0 -1 1516735816108 ""}{ "Info" "" "" "2018.01.23.17:30:16 Info: avalon_st_adapter_006: Inserting error_adapter: error_adapter_0" { } { } 0 0 "2018.01.23.17:30:16 Info: avalon_st_adapter_006: Inserting error_adapter: error_adapter_0" 0 0 "Shell" 0 -1 1516735816205 ""}{ "Info" "" "" "2018.01.23.17:30:16 Info: avalon_st_adapter_007: Inserting error_adapter: error_adapter_0" { } { } 0 0 "2018.01.23.17:30:16 Info: avalon_st_adapter_007: Inserting error_adapter: error_adapter_0" 0 0 "Shell" 0 -1 1516735816278 ""}{ "Info" "" "" "2018.01.23.17:30:16 Info: avalon_st_adapter_008: Inserting error_adapter: error_adapter_0" { } { } 0 0 "2018.01.23.17:30:16 Info: avalon_st_adapter_008: Inserting error_adapter: error_adapter_0" 0 0 "Shell" 0 -1 1516735816352 ""}{ "Info" "" "" "2018.01.23.17:30:16 Info: avalon_st_adapter_009: Inserting error_adapter: error_adapter_0" { } { } 0 0 "2018.01.23.17:30:16 Info: avalon_st_adapter_009: Inserting error_adapter: error_adapter_0" 0 0 "Shell" 0 -1 1516735816421 ""}{ "Info" "" "" "2018.01.23.17:30:16 Info: avalon_st_adapter_010: Inserting error_adapter: error_adapter_0" { } { } 0 0 "2018.01.23.17:30:16 Info: avalon_st_adapter_010: Inserting error_adapter: error_adapter_0" 0 0 "Shell" 0 -1 1516735816501 ""}{ "Info" "" "" "2018.01.23.17:30:16 Info: avalon_st_adapter_011: Inserting error_adapter: error_adapter_0" { } { } 0 0 "2018.01.23.17:30:16 Info: avalon_st_adapter_011: Inserting error_adapter: error_adapter_0" 0 0 "Shell" 0 -1 1516735816574 ""}{ "Info" "" "" "2018.01.23.17:30:16 Info: avalon_st_adapter_012: Inserting error_adapter: error_adapter_0" { } { } 0 0 "2018.01.23.17:30:16 Info: avalon_st_adapter_012: Inserting error_adapter: error_adapter_0" 0 0 "Shell" 0 -1 1516735816654 ""}{ "Info" "" "" "2018.01.23.17:30:16 Info: avalon_st_adapter_013: Inserting error_adapter: error_adapter_0" { } { } 0 0 "2018.01.23.17:30:16 Info: avalon_st_adapter_013: Inserting error_adapter: error_adapter_0" 0 0 "Shell" 0 -1 1516735816731 ""}{ "Info" "" "" "2018.01.23.17:30:16 Info: avalon_st_adapter_014: Inserting error_adapter: error_adapter_0" { } { } 0 0 "2018.01.23.17:30:16 Info: avalon_st_adapter_014: Inserting error_adapter: error_adapter_0" 0 0 "Shell" 0 -1 1516735816801 ""}{ "Info" "" "" "2018.01.23.17:30:16 Info: avalon_st_adapter_015: Inserting error_adapter: error_adapter_0" { } { } 0 0 "2018.01.23.17:30:16 Info: avalon_st_adapter_015: Inserting error_adapter: error_adapter_0" 0 0 "Shell" 0 -1 1516735816868 ""}{ "Info" "" "" "2018.01.23.17:30:16 Info: avalon_st_adapter_016: Inserting error_adapter: error_adapter_0" { } { } 0 0 "2018.01.23.17:30:16 Info: avalon_st_adapter_016: Inserting error_adapter: error_adapter_0" 0 0 "Shell" 0 -1 1516735816942 ""}{ "Info" "" "" "2018.01.23.17:30:17 Info: avalon_st_adapter_017: Inserting error_adapter: error_adapter_0" { } { } 0 0 "2018.01.23.17:30:17 Info: avalon_st_adapter_017: Inserting error_adapter: error_adapter_0" 0 0 "Shell" 0 -1 1516735817025 ""}{ "Info" "" "" "2018.01.23.17:30:17 Info: avalon_st_adapter_018: Inserting error_adapter: error_adapter_0" { } { } 0 0 "2018.01.23.17:30:17 Info: avalon_st_adapter_018: Inserting error_adapter: error_adapter_0" 0 0 "Shell" 0 -1 1516735817110 ""}{ "Info" "" "" "2018.01.23.17:30:17 Info: avalon_st_adapter_019: Inserting error_adapter: error_adapter_0" { } { } 0 0 "2018.01.23.17:30:17 Info: avalon_st_adapter_019: Inserting error_adapter: error_adapter_0" 0 0 "Shell" 0 -1 1516735817182 ""}{ "Info" "" "" "2018.01.23.17:30:17 Info: avalon_st_adapter_020: Inserting error_adapter: error_adapter_0" { } { } 0 0 "2018.01.23.17:30:17 Info: avalon_st_adapter_020: Inserting error_adapter: error_adapter_0" 0 0 "Shell" 0 -1 1516735817249 ""}{ "Info" "" "" "2018.01.23.17:30:17 Info: avalon_st_adapter_021: Inserting error_adapter: error_adapter_0" { } { } 0 0 "2018.01.23.17:30:17 Info: avalon_st_adapter_021: Inserting error_adapter: error_adapter_0" 0 0 "Shell" 0 -1 1516735817317 ""}{ "Info" "" "" "2018.01.23.17:30:20 Info: mm_interconnect_0: \"ulight_fifo\" instantiated altera_mm_interconnect \"mm_interconnect_0\"" { } { } 0 0 "2018.01.23.17:30:20 Info: mm_interconnect_0: \"ulight_fifo\" instantiated altera_mm_interconnect \"mm_interconnect_0\"" 0 0 "Shell" 0 -1 1516735820323 ""}{ "Info" "" "" "2018.01.23.17:30:20 Info: rst_controller: \"ulight_fifo\" instantiated altera_reset_controller \"rst_controller\"" { } { } 0 0 "2018.01.23.17:30:20 Info: rst_controller: \"ulight_fifo\" instantiated altera_reset_controller \"rst_controller\"" 0 0 "Shell" 0 -1 1516735820407 ""}{ "Info" "" "" "2018.01.23.17:30:20 Info: fpga_interfaces: \"hps_0\" instantiated altera_interface_generator \"fpga_interfaces\"" { } { } 0 0 "2018.01.23.17:30:20 Info: fpga_interfaces: \"hps_0\" instantiated altera_interface_generator \"fpga_interfaces\"" 0 0 "Shell" 0 -1 1516735820733 ""}{ "Info" "" "" "2018.01.23.17:30:20 Info: hps_io: \"hps_0\" instantiated altera_hps_io \"hps_io\"" { } { } 0 0 "2018.01.23.17:30:20 Info: hps_io: \"hps_0\" instantiated altera_hps_io \"hps_io\"" 0 0 "Shell" 0 -1 1516735820852 ""}{ "Info" "" "" "2018.01.23.17:30:20 Info: led_pio_test_s1_translator: \"mm_interconnect_0\" instantiated altera_merlin_slave_translator \"led_pio_test_s1_translator\"" { } { } 0 0 "2018.01.23.17:30:20 Info: led_pio_test_s1_translator: \"mm_interconnect_0\" instantiated altera_merlin_slave_translator \"led_pio_test_s1_translator\"" 0 0 "Shell" 0 -1 1516735820878 ""}{ "Info" "" "" "2018.01.23.17:30:20 Info: hps_0_h2f_axi_master_agent: \"mm_interconnect_0\" instantiated altera_merlin_axi_master_ni \"hps_0_h2f_axi_master_agent\"" { } { } 0 0 "2018.01.23.17:30:20 Info: hps_0_h2f_axi_master_agent: \"mm_interconnect_0\" instantiated altera_merlin_axi_master_ni \"hps_0_h2f_axi_master_agent\"" 0 0 "Shell" 0 -1 1516735820907 ""}{ "Info" "" "" "2018.01.23.17:30:20 Info: led_pio_test_s1_agent: \"mm_interconnect_0\" instantiated altera_merlin_slave_agent \"led_pio_test_s1_agent\"" { } { } 0 0 "2018.01.23.17:30:20 Info: led_pio_test_s1_agent: \"mm_interconnect_0\" instantiated altera_merlin_slave_agent \"led_pio_test_s1_agent\"" 0 0 "Shell" 0 -1 1516735820943 ""}{ "Info" "" "" "2018.01.23.17:30:21 Info: led_pio_test_s1_agent_rsp_fifo: \"mm_interconnect_0\" instantiated altera_avalon_sc_fifo \"led_pio_test_s1_agent_rsp_fifo\"" { } { } 0 0 "2018.01.23.17:30:21 Info: led_pio_test_s1_agent_rsp_fifo: \"mm_interconnect_0\" instantiated altera_avalon_sc_fifo \"led_pio_test_s1_agent_rsp_fifo\"" 0 0 "Shell" 0 -1 1516735821010 ""}{ "Info" "" "" "2018.01.23.17:30:21 Info: router: \"mm_interconnect_0\" instantiated altera_merlin_router \"router\"" { } { } 0 0 "2018.01.23.17:30:21 Info: router: \"mm_interconnect_0\" instantiated altera_merlin_router \"router\"" 0 0 "Shell" 0 -1 1516735821047 ""}{ "Info" "" "" "2018.01.23.17:30:21 Info: router_002: \"mm_interconnect_0\" instantiated altera_merlin_router \"router_002\"" { } { } 0 0 "2018.01.23.17:30:21 Info: router_002: \"mm_interconnect_0\" instantiated altera_merlin_router \"router_002\"" 0 0 "Shell" 0 -1 1516735821058 ""}{ "Info" "" "" "2018.01.23.17:30:21 Info: hps_0_h2f_axi_master_wr_limiter: \"mm_interconnect_0\" instantiated altera_merlin_traffic_limiter \"hps_0_h2f_axi_master_wr_limiter\"" { } { } 0 0 "2018.01.23.17:30:21 Info: hps_0_h2f_axi_master_wr_limiter: \"mm_interconnect_0\" instantiated altera_merlin_traffic_limiter \"hps_0_h2f_axi_master_wr_limiter\"" 0 0 "Shell" 0 -1 1516735821132 ""}{ "Info" "altera_avalon_sc_fifo.v" "" "2018.01.23.17:30:21 Info: Reusing file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/simulation/submodules" { } { } 0 0 "2018.01.23.17:30:21 Info: Reusing file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/simulation/submodules" 0 0 "Shell" 0 -1 1516735821135 ""}{ "Info" "" "" "2018.01.23.17:30:21 Info: led_pio_test_s1_burst_adapter: \"mm_interconnect_0\" instantiated altera_merlin_burst_adapter \"led_pio_test_s1_burst_adapter\"" { } { } 0 0 "2018.01.23.17:30:21 Info: led_pio_test_s1_burst_adapter: \"mm_interconnect_0\" instantiated altera_merlin_burst_adapter \"led_pio_test_s1_burst_adapter\"" 0 0 "Shell" 0 -1 1516735821258 ""}{ "Info" "altera_merlin_address_alignment.sv" "" "2018.01.23.17:30:21 Info: Reusing file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/simulation/submodules" { } { } 0 0 "2018.01.23.17:30:21 Info: Reusing file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/simulation/submodules" 0 0 "Shell" 0 -1 1516735821262 ""}{ "Info" "altera_avalon_st_pipeline_base.v" "" "2018.01.23.17:30:21 Info: Reusing file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/simulation/submodules" { } { } 0 0 "2018.01.23.17:30:21 Info: Reusing file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/simulation/submodules" 0 0 "Shell" 0 -1 1516735821263 ""}{ "Info" "" "" "2018.01.23.17:30:21 Info: cmd_demux: \"mm_interconnect_0\" instantiated altera_merlin_demultiplexer \"cmd_demux\"" { } { } 0 0 "2018.01.23.17:30:21 Info: cmd_demux: \"mm_interconnect_0\" instantiated altera_merlin_demultiplexer \"cmd_demux\"" 0 0 "Shell" 0 -1 1516735821319 ""}{ "Info" "" "" "2018.01.23.17:30:21 Info: cmd_mux: \"mm_interconnect_0\" instantiated altera_merlin_multiplexer \"cmd_mux\"" { } { } 0 0 "2018.01.23.17:30:21 Info: cmd_mux: \"mm_interconnect_0\" instantiated altera_merlin_multiplexer \"cmd_mux\"" 0 0 "Shell" 0 -1 1516735821334 ""}{ "Info" "" "" "2018.01.23.17:30:21 Info: rsp_demux: \"mm_interconnect_0\" instantiated altera_merlin_demultiplexer \"rsp_demux\"" { } { } 0 0 "2018.01.23.17:30:21 Info: rsp_demux: \"mm_interconnect_0\" instantiated altera_merlin_demultiplexer \"rsp_demux\"" 0 0 "Shell" 0 -1 1516735821340 ""}{ "Info" "" "" "2018.01.23.17:30:21 Info: rsp_mux: \"mm_interconnect_0\" instantiated altera_merlin_multiplexer \"rsp_mux\"" { } { } 0 0 "2018.01.23.17:30:21 Info: rsp_mux: \"mm_interconnect_0\" instantiated altera_merlin_multiplexer \"rsp_mux\"" 0 0 "Shell" 0 -1 1516735821360 ""}{ "Info" "altera_merlin_arbitrator.sv" "" "2018.01.23.17:30:21 Info: Reusing file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/simulation/submodules" { } { } 0 0 "2018.01.23.17:30:21 Info: Reusing file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/simulation/submodules" 0 0 "Shell" 0 -1 1516735821362 ""}{ "Info" "" "" "2018.01.23.17:30:21 Info: avalon_st_adapter: \"mm_interconnect_0\" instantiated altera_avalon_st_adapter \"avalon_st_adapter\"" { } { } 0 0 "2018.01.23.17:30:21 Info: avalon_st_adapter: \"mm_interconnect_0\" instantiated altera_avalon_st_adapter \"avalon_st_adapter\"" 0 0 "Shell" 0 -1 1516735821401 ""}{ "Info" "" "" "2018.01.23.17:30:21 Info: border: \"hps_io\" instantiated altera_interface_generator \"border\"" { } { } 0 0 "2018.01.23.17:30:21 Info: border: \"hps_io\" instantiated altera_interface_generator \"border\"" 0 0 "Shell" 0 -1 1516735821470 ""}{ "Info" "verbosity_pkg.sv" "" "2018.01.23.17:30:21 Info: Reusing file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/simulation/submodules" { } { } 0 0 "2018.01.23.17:30:21 Info: Reusing file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/simulation/submodules" 0 0 "Shell" 0 -1 1516735821471 ""}{ "Info" "avalon_utilities_pkg.sv" "" "2018.01.23.17:30:21 Info: Reusing file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/simulation/submodules" { } { } 0 0 "2018.01.23.17:30:21 Info: Reusing file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/simulation/submodules" 0 0 "Shell" 0 -1 1516735821471 ""}{ "Info" "avalon_mm_pkg.sv" "" "2018.01.23.17:30:21 Info: Reusing file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/simulation/submodules" { } { } 0 0 "2018.01.23.17:30:21 Info: Reusing file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/simulation/submodules" 0 0 "Shell" 0 -1 1516735821472 ""}{ "Info" "altera_avalon_mm_slave_bfm.sv" "" "2018.01.23.17:30:21 Info: Reusing file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/simulation/submodules" { } { } 0 0 "2018.01.23.17:30:21 Info: Reusing file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/simulation/submodules" 0 0 "Shell" 0 -1 1516735821474 ""}{ "Info" "altera_avalon_interrupt_sink.sv" "" "2018.01.23.17:30:21 Info: Reusing file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/simulation/submodules" { } { } 0 0 "2018.01.23.17:30:21 Info: Reusing file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/simulation/submodules" 0 0 "Shell" 0 -1 1516735821475 ""}{ "Info" "altera_avalon_clock_source.sv" "" "2018.01.23.17:30:21 Info: Reusing file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/simulation/submodules" { } { } 0 0 "2018.01.23.17:30:21 Info: Reusing file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/simulation/submodules" 0 0 "Shell" 0 -1 1516735821475 ""}{ "Info" "altera_avalon_reset_source.sv" "" "2018.01.23.17:30:21 Info: Reusing file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/simulation/submodules" { } { } 0 0 "2018.01.23.17:30:21 Info: Reusing file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/simulation/submodules" 0 0 "Shell" 0 -1 1516735821476 ""}{ "Info" "" "" "2018.01.23.17:30:21 Info: error_adapter_0: \"avalon_st_adapter\" instantiated error_adapter \"error_adapter_0\"" { } { } 0 0 "2018.01.23.17:30:21 Info: error_adapter_0: \"avalon_st_adapter\" instantiated error_adapter \"error_adapter_0\"" 0 0 "Shell" 0 -1 1516735821510 ""}{ "Info" "" "" "2018.01.23.17:30:21 Info: ulight_fifo: Done \"ulight_fifo\" with 32 modules, 58 files" { } { } 0 0 "2018.01.23.17:30:21 Info: ulight_fifo: Done \"ulight_fifo\" with 32 modules, 58 files" 0 0 "Shell" 0 -1 1516735821511 ""}{ "Info" "" "" "2018.01.23.17:30:21 Info: qsys-generate succeeded." { } { } 0 0 "2018.01.23.17:30:21 Info: qsys-generate succeeded." 0 0 "Shell" 0 -1 1516735821581 ""}{ "Info" "" "" "2018.01.23.17:30:21 Info: Finished: Create simulation model" { } { } 0 0 "2018.01.23.17:30:21 Info: Finished: Create simulation model" 0 0 "Shell" 0 -1 1516735821581 ""}{ "Info" "" "" "2018.01.23.17:30:21 Info: Starting: Create Modelsim Project." { } { } 0 0 "2018.01.23.17:30:21 Info: Starting: Create Modelsim Project." 0 0 "Shell" 0 -1 1516735821582 ""}{ "Info" " --use-relative-paths=true" "" "2018.01.23.17:30:21 Info: sim-script-gen --spd=/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/ulight_fifo.spd --output-directory=/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/simulation" { } { } 0 0 "2018.01.23.17:30:21 Info: sim-script-gen --spd=/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/ulight_fifo.spd --output-directory=/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/simulation" 0 0 "Shell" 0 -1 1516735821583 ""}{ "Info" " --use-relative-paths=true" "" "2018.01.23.17:30:21 Info: Doing: ip-make-simscript --spd=/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/ulight_fifo.spd --output-directory=/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/simulation" { } { } 0 0 "2018.01.23.17:30:21 Info: Doing: ip-make-simscript --spd=/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/ulight_fifo.spd --output-directory=/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/simulation" 0 0 "Shell" 0 -1 1516735821590 ""}{ "Info" " directory:" "" "2018.01.23.17:30:22 Info: Generating the following file(s) for MODELSIM simulator in /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/simulation" { } { } 0 0 "2018.01.23.17:30:22 Info: Generating the following file(s) for MODELSIM simulator in /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/simulation" 0 0 "Shell" 0 -1 1516735822982 ""}{ "Info" "msim_setup.tcl" "" "2018.01.23.17:30:22 Info: mentor" { } { } 0 0 "2018.01.23.17:30:22 Info: mentor" 0 0 "Shell" 0 -1 1516735822983 ""}{ "Info" " directory:" "" "2018.01.23.17:30:22 Info: Generating the following file(s) for VCS simulator in /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/simulation" { } { } 0 0 "2018.01.23.17:30:22 Info: Generating the following file(s) for VCS simulator in /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/simulation" 0 0 "Shell" 0 -1 1516735822995 ""}{ "Info" "vcs_setup.sh" "" "2018.01.23.17:30:22 Info: synopsys/vcs" { } { } 0 0 "2018.01.23.17:30:22 Info: synopsys/vcs" 0 0 "Shell" 0 -1 1516735822996 ""}{ "Info" " directory:" "" "2018.01.23.17:30:23 Info: Generating the following file(s) for VCSMX simulator in /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/simulation" { } { } 0 0 "2018.01.23.17:30:23 Info: Generating the following file(s) for VCSMX simulator in /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/simulation" 0 0 "Shell" 0 -1 1516735823007 ""}{ "Info" "synopsys_sim.setup" "" "2018.01.23.17:30:23 Info: synopsys/vcsmx" { } { } 0 0 "2018.01.23.17:30:23 Info: synopsys/vcsmx" 0 0 "Shell" 0 -1 1516735823054 ""}{ "Info" "vcsmx_setup.sh" "" "2018.01.23.17:30:23 Info: synopsys/vcsmx" { } { } 0 0 "2018.01.23.17:30:23 Info: synopsys/vcsmx" 0 0 "Shell" 0 -1 1516735823361 ""}{ "Info" " directory:" "" "2018.01.23.17:30:23 Info: Generating the following file(s) for NCSIM simulator in /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/simulation" { } { } 0 0 "2018.01.23.17:30:23 Info: Generating the following file(s) for NCSIM simulator in /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/simulation" 0 0 "Shell" 0 -1 1516735823387 ""}{ "Info" "cds.lib" "" "2018.01.23.17:30:23 Info: cadence" { } { } 0 0 "2018.01.23.17:30:23 Info: cadence" 0 0 "Shell" 0 -1 1516735823388 ""}{ "Info" "hdl.var" "" "2018.01.23.17:30:23 Info: cadence" { } { } 0 0 "2018.01.23.17:30:23 Info: cadence" 0 0 "Shell" 0 -1 1516735823404 ""}{ "Info" "ncsim_setup.sh" "" "2018.01.23.17:30:23 Info: cadence" { } { } 0 0 "2018.01.23.17:30:23 Info: cadence" 0 0 "Shell" 0 -1 1516735823411 ""}{ "Info" " directory" "" "2018.01.23.17:30:23 Info: 32 .cds.lib files in cadence/cds_libs" { } { } 0 0 "2018.01.23.17:30:23 Info: 32 .cds.lib files in cadence/cds_libs" 0 0 "Shell" 0 -1 1516735823411 ""}{ "Info" " directory:" "" "2018.01.23.17:30:23 Info: Generating the following file(s) for RIVIERA simulator in /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/simulation" { } { } 0 0 "2018.01.23.17:30:23 Info: Generating the following file(s) for RIVIERA simulator in /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/simulation" 0 0 "Shell" 0 -1 1516735823422 ""}{ "Info" "rivierapro_setup.tcl" "" "2018.01.23.17:30:23 Info: aldec" { } { } 0 0 "2018.01.23.17:30:23 Info: aldec" 0 0 "Shell" 0 -1 1516735823423 ""}{ "Info" "." "" "2018.01.23.17:30:23 Info: For information on how to simulate your IP, see the explanatory comments in the simulator-specific subdirectories under /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/simulation" { } { } 0 0 "2018.01.23.17:30:23 Info: For information on how to simulate your IP, see the explanatory comments in the simulator-specific subdirectories under /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/simulation" 0 0 "Shell" 0 -1 1516735823423 ""}{ "Info" "" "" "2018.01.23.17:30:23 Info: Regenerate these scripts whenever you make any change to any Quartus-generated IP in your project." { } { } 0 0 "2018.01.23.17:30:23 Info: Regenerate these scripts whenever you make any change to any Quartus-generated IP in your project." 0 0 "Shell" 0 -1 1516735823424 ""}{ "Info" "" "" "2018.01.23.17:30:23 Info: Finished: Create Modelsim Project." { } { } 0 0 "2018.01.23.17:30:23 Info: Finished: Create Modelsim Project." 0 0 "Shell" 0 -1 1516735823424 ""}{ "Info" "" "" "2018.01.23.17:30:23 Info: Starting: Create block symbol file (.bsf)" { } { } 0 0 "2018.01.23.17:30:23 Info: Starting: Create block symbol file (.bsf)" 0 0 "Shell" 0 -1 1516735823425 ""}{ "Info" "ulight_fifo.qsys" "" "2018.01.23.17:30:23 Info: Loading spw_fifo_ulight" { } { } 0 0 "2018.01.23.17:30:23 Info: Loading spw_fifo_ulight" 0 0 "Shell" 0 -1 1516735823430 ""}{ "Info" "" "" "2018.01.23.17:30:23 Info: Reading input file" { } { } 0 0 "2018.01.23.17:30:23 Info: Reading input file" 0 0 "Shell" 0 -1 1516735823456 ""}{ "Info" "" "" "2018.01.23.17:30:23 Info: Adding auto_start \[altera_avalon_pio 17.1\]" { } { } 0 0 "2018.01.23.17:30:23 Info: Adding auto_start \[altera_avalon_pio 17.1\]" 0 0 "Shell" 0 -1 1516735823461 ""}{ "Info" "" "" "2018.01.23.17:30:23 Info: Parameterizing module auto_start" { } { } 0 0 "2018.01.23.17:30:23 Info: Parameterizing module auto_start" 0 0 "Shell" 0 -1 1516735823461 ""}{ "Info" "" "" "2018.01.23.17:30:23 Info: Adding clk_0 \[clock_source 17.1\]" { } { } 0 0 "2018.01.23.17:30:23 Info: Adding clk_0 \[clock_source 17.1\]" 0 0 "Shell" 0 -1 1516735823462 ""}{ "Info" "" "" "2018.01.23.17:30:23 Info: Parameterizing module clk_0" { } { } 0 0 "2018.01.23.17:30:23 Info: Parameterizing module clk_0" 0 0 "Shell" 0 -1 1516735823463 ""}{ "Info" "" "" "2018.01.23.17:30:23 Info: Adding clock_sel \[altera_avalon_pio 17.1\]" { } { } 0 0 "2018.01.23.17:30:23 Info: Adding clock_sel \[altera_avalon_pio 17.1\]" 0 0 "Shell" 0 -1 1516735823464 ""}{ "Info" "" "" "2018.01.23.17:30:23 Info: Parameterizing module clock_sel" { } { } 0 0 "2018.01.23.17:30:23 Info: Parameterizing module clock_sel" 0 0 "Shell" 0 -1 1516735823464 ""}{ "Info" "" "" "2018.01.23.17:30:23 Info: Adding counter_rx_fifo \[altera_avalon_pio 17.1\]" { } { } 0 0 "2018.01.23.17:30:23 Info: Adding counter_rx_fifo \[altera_avalon_pio 17.1\]" 0 0 "Shell" 0 -1 1516735823465 ""}{ "Info" "" "" "2018.01.23.17:30:23 Info: Parameterizing module counter_rx_fifo" { } { } 0 0 "2018.01.23.17:30:23 Info: Parameterizing module counter_rx_fifo" 0 0 "Shell" 0 -1 1516735823466 ""}{ "Info" "" "" "2018.01.23.17:30:23 Info: Adding counter_tx_fifo \[altera_avalon_pio 17.1\]" { } { } 0 0 "2018.01.23.17:30:23 Info: Adding counter_tx_fifo \[altera_avalon_pio 17.1\]" 0 0 "Shell" 0 -1 1516735823466 ""}{ "Info" "" "" "2018.01.23.17:30:23 Info: Parameterizing module counter_tx_fifo" { } { } 0 0 "2018.01.23.17:30:23 Info: Parameterizing module counter_tx_fifo" 0 0 "Shell" 0 -1 1516735823467 ""}{ "Info" "" "" "2018.01.23.17:30:23 Info: Adding data_flag_rx \[altera_avalon_pio 17.1\]" { } { } 0 0 "2018.01.23.17:30:23 Info: Adding data_flag_rx \[altera_avalon_pio 17.1\]" 0 0 "Shell" 0 -1 1516735823468 ""}{ "Info" "" "" "2018.01.23.17:30:23 Info: Parameterizing module data_flag_rx" { } { } 0 0 "2018.01.23.17:30:23 Info: Parameterizing module data_flag_rx" 0 0 "Shell" 0 -1 1516735823472 ""}{ "Info" "" "" "2018.01.23.17:30:23 Info: Adding data_info \[altera_avalon_pio 17.1\]" { } { } 0 0 "2018.01.23.17:30:23 Info: Adding data_info \[altera_avalon_pio 17.1\]" 0 0 "Shell" 0 -1 1516735823473 ""}{ "Info" "" "" "2018.01.23.17:30:23 Info: Parameterizing module data_info" { } { } 0 0 "2018.01.23.17:30:23 Info: Parameterizing module data_info" 0 0 "Shell" 0 -1 1516735823474 ""}{ "Info" "" "" "2018.01.23.17:30:23 Info: Adding data_read_en_rx \[altera_avalon_pio 17.1\]" { } { } 0 0 "2018.01.23.17:30:23 Info: Adding data_read_en_rx \[altera_avalon_pio 17.1\]" 0 0 "Shell" 0 -1 1516735823475 ""}{ "Info" "" "" "2018.01.23.17:30:23 Info: Parameterizing module data_read_en_rx" { } { } 0 0 "2018.01.23.17:30:23 Info: Parameterizing module data_read_en_rx" 0 0 "Shell" 0 -1 1516735823475 ""}{ "Info" "" "" "2018.01.23.17:30:23 Info: Adding fifo_empty_rx_status \[altera_avalon_pio 17.1\]" { } { } 0 0 "2018.01.23.17:30:23 Info: Adding fifo_empty_rx_status \[altera_avalon_pio 17.1\]" 0 0 "Shell" 0 -1 1516735823476 ""}{ "Info" "" "" "2018.01.23.17:30:23 Info: Parameterizing module fifo_empty_rx_status" { } { } 0 0 "2018.01.23.17:30:23 Info: Parameterizing module fifo_empty_rx_status" 0 0 "Shell" 0 -1 1516735823477 ""}{ "Info" "" "" "2018.01.23.17:30:23 Info: Adding fifo_empty_tx_status \[altera_avalon_pio 17.1\]" { } { } 0 0 "2018.01.23.17:30:23 Info: Adding fifo_empty_tx_status \[altera_avalon_pio 17.1\]" 0 0 "Shell" 0 -1 1516735823484 ""}{ "Info" "" "" "2018.01.23.17:30:23 Info: Parameterizing module fifo_empty_tx_status" { } { } 0 0 "2018.01.23.17:30:23 Info: Parameterizing module fifo_empty_tx_status" 0 0 "Shell" 0 -1 1516735823484 ""}{ "Info" "" "" "2018.01.23.17:30:23 Info: Adding fifo_full_rx_status \[altera_avalon_pio 17.1\]" { } { } 0 0 "2018.01.23.17:30:23 Info: Adding fifo_full_rx_status \[altera_avalon_pio 17.1\]" 0 0 "Shell" 0 -1 1516735823486 ""}{ "Info" "" "" "2018.01.23.17:30:23 Info: Parameterizing module fifo_full_rx_status" { } { } 0 0 "2018.01.23.17:30:23 Info: Parameterizing module fifo_full_rx_status" 0 0 "Shell" 0 -1 1516735823487 ""}{ "Info" "" "" "2018.01.23.17:30:23 Info: Adding fifo_full_tx_status \[altera_avalon_pio 17.1\]" { } { } 0 0 "2018.01.23.17:30:23 Info: Adding fifo_full_tx_status \[altera_avalon_pio 17.1\]" 0 0 "Shell" 0 -1 1516735823488 ""}{ "Info" "" "" "2018.01.23.17:30:23 Info: Parameterizing module fifo_full_tx_status" { } { } 0 0 "2018.01.23.17:30:23 Info: Parameterizing module fifo_full_tx_status" 0 0 "Shell" 0 -1 1516735823488 ""}{ "Info" "" "" "2018.01.23.17:30:23 Info: Adding fsm_info \[altera_avalon_pio 17.1\]" { } { } 0 0 "2018.01.23.17:30:23 Info: Adding fsm_info \[altera_avalon_pio 17.1\]" 0 0 "Shell" 0 -1 1516735823489 ""}{ "Info" "" "" "2018.01.23.17:30:23 Info: Parameterizing module fsm_info" { } { } 0 0 "2018.01.23.17:30:23 Info: Parameterizing module fsm_info" 0 0 "Shell" 0 -1 1516735823490 ""}{ "Info" "" "" "2018.01.23.17:30:23 Info: Adding hps_0 \[altera_hps 17.1\]" { } { } 0 0 "2018.01.23.17:30:23 Info: Adding hps_0 \[altera_hps 17.1\]" 0 0 "Shell" 0 -1 1516735823491 ""}{ "Info" "" "" "2018.01.23.17:30:23 Info: Parameterizing module hps_0" { } { } 0 0 "2018.01.23.17:30:23 Info: Parameterizing module hps_0" 0 0 "Shell" 0 -1 1516735823496 ""}{ "Info" "" "" "2018.01.23.17:30:23 Info: Adding led_pio_test \[altera_avalon_pio 17.1\]" { } { } 0 0 "2018.01.23.17:30:23 Info: Adding led_pio_test \[altera_avalon_pio 17.1\]" 0 0 "Shell" 0 -1 1516735823514 ""}{ "Info" "" "" "2018.01.23.17:30:23 Info: Parameterizing module led_pio_test" { } { } 0 0 "2018.01.23.17:30:23 Info: Parameterizing module led_pio_test" 0 0 "Shell" 0 -1 1516735823515 ""}{ "Info" "" "" "2018.01.23.17:30:23 Info: Adding link_disable \[altera_avalon_pio 17.1\]" { } { } 0 0 "2018.01.23.17:30:23 Info: Adding link_disable \[altera_avalon_pio 17.1\]" 0 0 "Shell" 0 -1 1516735823516 ""}{ "Info" "" "" "2018.01.23.17:30:23 Info: Parameterizing module link_disable" { } { } 0 0 "2018.01.23.17:30:23 Info: Parameterizing module link_disable" 0 0 "Shell" 0 -1 1516735823517 ""}{ "Info" "" "" "2018.01.23.17:30:23 Info: Adding link_start \[altera_avalon_pio 17.1\]" { } { } 0 0 "2018.01.23.17:30:23 Info: Adding link_start \[altera_avalon_pio 17.1\]" 0 0 "Shell" 0 -1 1516735823518 ""}{ "Info" "" "" "2018.01.23.17:30:23 Info: Parameterizing module link_start" { } { } 0 0 "2018.01.23.17:30:23 Info: Parameterizing module link_start" 0 0 "Shell" 0 -1 1516735823518 ""}{ "Info" "" "" "2018.01.23.17:30:23 Info: Adding pll_0 \[altera_pll 17.1\]" { } { } 0 0 "2018.01.23.17:30:23 Info: Adding pll_0 \[altera_pll 17.1\]" 0 0 "Shell" 0 -1 1516735823519 ""}{ "Info" "" "" "2018.01.23.17:30:23 Info: Parameterizing module pll_0" { } { } 0 0 "2018.01.23.17:30:23 Info: Parameterizing module pll_0" 0 0 "Shell" 0 -1 1516735823521 ""}{ "Info" "" "" "2018.01.23.17:30:23 Info: Adding timecode_ready_rx \[altera_avalon_pio 17.1\]" { } { } 0 0 "2018.01.23.17:30:23 Info: Adding timecode_ready_rx \[altera_avalon_pio 17.1\]" 0 0 "Shell" 0 -1 1516735823524 ""}{ "Info" "" "" "2018.01.23.17:30:23 Info: Parameterizing module timecode_ready_rx" { } { } 0 0 "2018.01.23.17:30:23 Info: Parameterizing module timecode_ready_rx" 0 0 "Shell" 0 -1 1516735823524 ""}{ "Info" "" "" "2018.01.23.17:30:23 Info: Adding timecode_rx \[altera_avalon_pio 17.1\]" { } { } 0 0 "2018.01.23.17:30:23 Info: Adding timecode_rx \[altera_avalon_pio 17.1\]" 0 0 "Shell" 0 -1 1516735823531 ""}{ "Info" "" "" "2018.01.23.17:30:23 Info: Parameterizing module timecode_rx" { } { } 0 0 "2018.01.23.17:30:23 Info: Parameterizing module timecode_rx" 0 0 "Shell" 0 -1 1516735823531 ""}{ "Info" "" "" "2018.01.23.17:30:23 Info: Adding timecode_tx_data \[altera_avalon_pio 17.1\]" { } { } 0 0 "2018.01.23.17:30:23 Info: Adding timecode_tx_data \[altera_avalon_pio 17.1\]" 0 0 "Shell" 0 -1 1516735823532 ""}{ "Info" "" "" "2018.01.23.17:30:23 Info: Parameterizing module timecode_tx_data" { } { } 0 0 "2018.01.23.17:30:23 Info: Parameterizing module timecode_tx_data" 0 0 "Shell" 0 -1 1516735823533 ""}{ "Info" "" "" "2018.01.23.17:30:23 Info: Adding timecode_tx_enable \[altera_avalon_pio 17.1\]\n2018.01.23.17:30:23 Info: Parameterizing module timecode_tx_enable\n2018.01.23.17:30:23 Info: Adding timecode_tx_ready \[altera_avalon_pio 17.1\]" { } { } 0 0 "2018.01.23.17:30:23 Info: Adding timecode_tx_enable \[altera_avalon_pio 17.1\]\n2018.01.23.17:30:23 Info: Parameterizing module timecode_tx_enable\n2018.01.23.17:30:23 Info: Adding timecode_tx_ready \[altera_avalon_pio 17.1\]" 0 0 "Shell" 0 -1 1516735823539 ""}{ "Info" "" "" "2018.01.23.17:30:23 Info: Parameterizing module timecode_tx_ready" { } { } 0 0 "2018.01.23.17:30:23 Info: Parameterizing module timecode_tx_ready" 0 0 "Shell" 0 -1 1516735823542 ""}{ "Info" "" "" "2018.01.23.17:30:23 Info: Adding write_data_fifo_tx \[altera_avalon_pio 17.1\]" { } { } 0 0 "2018.01.23.17:30:23 Info: Adding write_data_fifo_tx \[altera_avalon_pio 17.1\]" 0 0 "Shell" 0 -1 1516735823543 ""}{ "Info" "" "" "2018.01.23.17:30:23 Info: Parameterizing module write_data_fifo_tx" { } { } 0 0 "2018.01.23.17:30:23 Info: Parameterizing module write_data_fifo_tx" 0 0 "Shell" 0 -1 1516735823543 ""}{ "Info" "" "" "2018.01.23.17:30:23 Info: Adding write_en_tx \[altera_avalon_pio 17.1\]" { } { } 0 0 "2018.01.23.17:30:23 Info: Adding write_en_tx \[altera_avalon_pio 17.1\]" 0 0 "Shell" 0 -1 1516735823544 ""}{ "Info" "" "" "2018.01.23.17:30:23 Info: Parameterizing module write_en_tx" { } { } 0 0 "2018.01.23.17:30:23 Info: Parameterizing module write_en_tx" 0 0 "Shell" 0 -1 1516735823546 ""}{ "Info" "" "" "2018.01.23.17:30:23 Info: Building connections" { } { } 0 0 "2018.01.23.17:30:23 Info: Building connections" 0 0 "Shell" 0 -1 1516735823547 ""}{ "Info" "" "" "2018.01.23.17:30:23 Info: Parameterizing connections" { } { } 0 0 "2018.01.23.17:30:23 Info: Parameterizing connections" 0 0 "Shell" 0 -1 1516735823550 ""}{ "Info" "" "" "2018.01.23.17:30:23 Info: Validating" { } { } 0 0 "2018.01.23.17:30:23 Info: Validating" 0 0 "Shell" 0 -1 1516735823560 ""}{ "Info" "" "" "2018.01.23.17:30:31 Info: Done reading input file" { } { } 0 0 "2018.01.23.17:30:31 Info: Done reading input file" 0 0 "Shell" 0 -1 1516735831710 ""}{ "Info" "" "" "2018.01.23.17:30:33 Info: ulight_fifo.counter_rx_fifo: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation." { } { } 0 0 "2018.01.23.17:30:33 Info: ulight_fifo.counter_rx_fifo: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation." 0 0 "Shell" 0 -1 1516735833912 ""}{ "Info" "" "" "2018.01.23.17:30:33 Info: ulight_fifo.counter_tx_fifo: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation." { } { } 0 0 "2018.01.23.17:30:33 Info: ulight_fifo.counter_tx_fifo: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation." 0 0 "Shell" 0 -1 1516735833913 ""}{ "Info" "" "" "2018.01.23.17:30:33 Info: ulight_fifo.data_flag_rx: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation." { } { } 0 0 "2018.01.23.17:30:33 Info: ulight_fifo.data_flag_rx: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation." 0 0 "Shell" 0 -1 1516735833913 ""}{ "Info" "" "" "2018.01.23.17:30:33 Info: ulight_fifo.data_info: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation." { } { } 0 0 "2018.01.23.17:30:33 Info: ulight_fifo.data_info: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation." 0 0 "Shell" 0 -1 1516735833913 ""}{ "Info" "" "" "2018.01.23.17:30:33 Info: ulight_fifo.fifo_empty_rx_status: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation." { } { } 0 0 "2018.01.23.17:30:33 Info: ulight_fifo.fifo_empty_rx_status: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation." 0 0 "Shell" 0 -1 1516735833913 ""}{ "Info" "" "" "2018.01.23.17:30:33 Info: ulight_fifo.fifo_empty_tx_status: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation." { } { } 0 0 "2018.01.23.17:30:33 Info: ulight_fifo.fifo_empty_tx_status: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation." 0 0 "Shell" 0 -1 1516735833913 ""}{ "Info" "" "" "2018.01.23.17:30:33 Info: ulight_fifo.fifo_full_rx_status: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation." { } { } 0 0 "2018.01.23.17:30:33 Info: ulight_fifo.fifo_full_rx_status: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation." 0 0 "Shell" 0 -1 1516735833913 ""}{ "Info" "" "" "2018.01.23.17:30:33 Info: ulight_fifo.fifo_full_tx_status: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation." { } { } 0 0 "2018.01.23.17:30:33 Info: ulight_fifo.fifo_full_tx_status: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation." 0 0 "Shell" 0 -1 1516735833913 ""}{ "Info" "" "" "2018.01.23.17:30:33 Info: ulight_fifo.fsm_info: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation." { } { } 0 0 "2018.01.23.17:30:33 Info: ulight_fifo.fsm_info: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation." 0 0 "Shell" 0 -1 1516735833914 ""}{ "Info" "" "" "2018.01.23.17:30:33 Info: ulight_fifo.hps_0: HPS Main PLL counter settings: n = 0 m = 36" { } { } 0 0 "2018.01.23.17:30:33 Info: ulight_fifo.hps_0: HPS Main PLL counter settings: n = 0 m = 36" 0 0 "Shell" 0 -1 1516735833914 ""}{ "Info" "" "" "2018.01.23.17:30:33 Info: ulight_fifo.hps_0: HPS peripherial PLL counter settings: n = 0 m = 19" { } { } 0 0 "2018.01.23.17:30:33 Info: ulight_fifo.hps_0: HPS peripherial PLL counter settings: n = 0 m = 19" 0 0 "Shell" 0 -1 1516735833914 ""}{ "Warning" "" "" "2018.01.23.17:30:33 Warning: ulight_fifo.hps_0: 1 or more output clock frequencies cannot be achieved precisely, consider revising desired output clock frequencies." { } { } 0 0 "2018.01.23.17:30:33 Warning: ulight_fifo.hps_0: 1 or more output clock frequencies cannot be achieved precisely, consider revising desired output clock frequencies." 0 0 "Shell" 0 -1 1516735833914 ""}{ "Warning" "" "" "2018.01.23.17:30:33 Warning: ulight_fifo.hps_0: ODT is disabled. Enabling ODT (Mode Register 1) may improve signal integrity" { } { } 0 0 "2018.01.23.17:30:33 Warning: ulight_fifo.hps_0: ODT is disabled. Enabling ODT (Mode Register 1) may improve signal integrity" 0 0 "Shell" 0 -1 1516735833914 ""}{ "Warning" "" "" "2018.01.23.17:30:33 Warning: ulight_fifo.hps_0: set_interface_assignment: Interface \"hps_io\" does not exist" { } { } 0 0 "2018.01.23.17:30:33 Warning: ulight_fifo.hps_0: set_interface_assignment: Interface \"hps_io\" does not exist" 0 0 "Shell" 0 -1 1516735833915 ""}{ "Info" "" "" "2018.01.23.17:30:33 Info: ulight_fifo.pll_0: The legal reference clock frequency is 5.0 MHz..800.0 MHz" { } { } 0 0 "2018.01.23.17:30:33 Info: ulight_fifo.pll_0: The legal reference clock frequency is 5.0 MHz..800.0 MHz" 0 0 "Shell" 0 -1 1516735833918 ""}{ "Warning" "" "" "2018.01.23.17:30:33 Warning: ulight_fifo.pll_0: 'refclk1' is not the same frequency as 'refclk'. You must run Timequest at both frequencies to ensure timing closure" { } { } 0 0 "2018.01.23.17:30:33 Warning: ulight_fifo.pll_0: 'refclk1' is not the same frequency as 'refclk'. You must run Timequest at both frequencies to ensure timing closure" 0 0 "Shell" 0 -1 1516735833918 ""}{ "Warning" "" "" "2018.01.23.17:30:33 Warning: ulight_fifo.pll_0: The period difference between refclk and refclk1 is greater than 20%, automatic clock loss detection will not work" { } { } 0 0 "2018.01.23.17:30:33 Warning: ulight_fifo.pll_0: The period difference between refclk and refclk1 is greater than 20%, automatic clock loss detection will not work" 0 0 "Shell" 0 -1 1516735833918 ""}{ "Info" "" "" "2018.01.23.17:30:33 Info: ulight_fifo.pll_0: Able to implement PLL with user settings" { } { } 0 0 "2018.01.23.17:30:33 Info: ulight_fifo.pll_0: Able to implement PLL with user settings" 0 0 "Shell" 0 -1 1516735833918 ""}{ "Warning" "" "" "2018.01.23.17:30:33 Warning: ulight_fifo.pll_0.refclk1: Signal refclk1 has unknown type refclk1" { } { } 0 0 "2018.01.23.17:30:33 Warning: ulight_fifo.pll_0.refclk1: Signal refclk1 has unknown type refclk1" 0 0 "Shell" 0 -1 1516735833918 ""}{ "Info" "" "" "2018.01.23.17:30:33 Info: ulight_fifo.timecode_ready_rx: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation." { } { } 0 0 "2018.01.23.17:30:33 Info: ulight_fifo.timecode_ready_rx: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation." 0 0 "Shell" 0 -1 1516735833919 ""}{ "Info" "" "" "2018.01.23.17:30:33 Info: ulight_fifo.timecode_rx: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation." { } { } 0 0 "2018.01.23.17:30:33 Info: ulight_fifo.timecode_rx: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation." 0 0 "Shell" 0 -1 1516735833919 ""}{ "Info" "" "" "2018.01.23.17:30:33 Info: ulight_fifo.timecode_tx_ready: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation." { } { } 0 0 "2018.01.23.17:30:33 Info: ulight_fifo.timecode_tx_ready: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation." 0 0 "Shell" 0 -1 1516735833919 ""}{ "Info" "" "" "2018.01.23.17:30:34 Info: qsys-generate succeeded." { } { } 0 0 "2018.01.23.17:30:34 Info: qsys-generate succeeded." 0 0 "Shell" 0 -1 1516735834875 ""}{ "Info" "" "" "2018.01.23.17:30:34 Info: Finished: Create block symbol file (.bsf)" { } { } 0 0 "2018.01.23.17:30:34 Info: Finished: Create block symbol file (.bsf)" 0 0 "Shell" 0 -1 1516735834876 ""}{ "Info" "" "" "2018.01.23.17:30:34 Info:" { } { } 0 0 "2018.01.23.17:30:34 Info:" 0 0 "Shell" 0 -1 1516735834876 ""}{ "Info" "" "" "2018.01.23.17:30:34 Info: Starting: Create HDL design files for synthesis" { } { } 0 0 "2018.01.23.17:30:34 Info: Starting: Create HDL design files for synthesis" 0 0 "Shell" 0 -1 1516735834876 ""}{ "Info" "ulight_fifo.qsys" "" "2018.01.23.17:30:34 Info: Loading spw_fifo_ulight" { } { } 0 0 "2018.01.23.17:30:34 Info: Loading spw_fifo_ulight" 0 0 "Shell" 0 -1 1516735834883 ""}{ "Info" "" "" "2018.01.23.17:30:34 Info: Reading input file" { } { } 0 0 "2018.01.23.17:30:34 Info: Reading input file" 0 0 "Shell" 0 -1 1516735834905 ""}{ "Info" "" "" "2018.01.23.17:30:34 Info: Adding auto_start \[altera_avalon_pio 17.1\]" { } { } 0 0 "2018.01.23.17:30:34 Info: Adding auto_start \[altera_avalon_pio 17.1\]" 0 0 "Shell" 0 -1 1516735834909 ""}{ "Info" "" "" "2018.01.23.17:30:34 Info: Parameterizing module auto_start" { } { } 0 0 "2018.01.23.17:30:34 Info: Parameterizing module auto_start" 0 0 "Shell" 0 -1 1516735834909 ""}{ "Info" "" "" "2018.01.23.17:30:34 Info: Adding clk_0 \[clock_source 17.1\]" { } { } 0 0 "2018.01.23.17:30:34 Info: Adding clk_0 \[clock_source 17.1\]" 0 0 "Shell" 0 -1 1516735834912 ""}{ "Info" "" "" "2018.01.23.17:30:34 Info: Parameterizing module clk_0" { } { } 0 0 "2018.01.23.17:30:34 Info: Parameterizing module clk_0" 0 0 "Shell" 0 -1 1516735834913 ""}{ "Info" "" "" "2018.01.23.17:30:34 Info: Adding clock_sel \[altera_avalon_pio 17.1\]" { } { } 0 0 "2018.01.23.17:30:34 Info: Adding clock_sel \[altera_avalon_pio 17.1\]" 0 0 "Shell" 0 -1 1516735834913 ""}{ "Info" "" "" "2018.01.23.17:30:34 Info: Parameterizing module clock_sel" { } { } 0 0 "2018.01.23.17:30:34 Info: Parameterizing module clock_sel" 0 0 "Shell" 0 -1 1516735834914 ""}{ "Info" "" "" "2018.01.23.17:30:34 Info: Adding counter_rx_fifo \[altera_avalon_pio 17.1\]" { } { } 0 0 "2018.01.23.17:30:34 Info: Adding counter_rx_fifo \[altera_avalon_pio 17.1\]" 0 0 "Shell" 0 -1 1516735834915 ""}{ "Info" "" "" "2018.01.23.17:30:34 Info: Parameterizing module counter_rx_fifo" { } { } 0 0 "2018.01.23.17:30:34 Info: Parameterizing module counter_rx_fifo" 0 0 "Shell" 0 -1 1516735834915 ""}{ "Info" "" "" "2018.01.23.17:30:34 Info: Adding counter_tx_fifo \[altera_avalon_pio 17.1\]" { } { } 0 0 "2018.01.23.17:30:34 Info: Adding counter_tx_fifo \[altera_avalon_pio 17.1\]" 0 0 "Shell" 0 -1 1516735834916 ""}{ "Info" "" "" "2018.01.23.17:30:34 Info: Parameterizing module counter_tx_fifo" { } { } 0 0 "2018.01.23.17:30:34 Info: Parameterizing module counter_tx_fifo" 0 0 "Shell" 0 -1 1516735834917 ""}{ "Info" "" "" "2018.01.23.17:30:34 Info: Adding data_flag_rx \[altera_avalon_pio 17.1\]" { } { } 0 0 "2018.01.23.17:30:34 Info: Adding data_flag_rx \[altera_avalon_pio 17.1\]" 0 0 "Shell" 0 -1 1516735834918 ""}{ "Info" "" "" "2018.01.23.17:30:34 Info: Parameterizing module data_flag_rx" { } { } 0 0 "2018.01.23.17:30:34 Info: Parameterizing module data_flag_rx" 0 0 "Shell" 0 -1 1516735834918 ""}{ "Info" "" "" "2018.01.23.17:30:34 Info: Adding data_info \[altera_avalon_pio 17.1\]" { } { } 0 0 "2018.01.23.17:30:34 Info: Adding data_info \[altera_avalon_pio 17.1\]" 0 0 "Shell" 0 -1 1516735834919 ""}{ "Info" "" "" "2018.01.23.17:30:34 Info: Parameterizing module data_info" { } { } 0 0 "2018.01.23.17:30:34 Info: Parameterizing module data_info" 0 0 "Shell" 0 -1 1516735834919 ""}{ "Info" "" "" "2018.01.23.17:30:34 Info: Adding data_read_en_rx \[altera_avalon_pio 17.1\]" { } { } 0 0 "2018.01.23.17:30:34 Info: Adding data_read_en_rx \[altera_avalon_pio 17.1\]" 0 0 "Shell" 0 -1 1516735834920 ""}{ "Info" "" "" "2018.01.23.17:30:34 Info: Parameterizing module data_read_en_rx" { } { } 0 0 "2018.01.23.17:30:34 Info: Parameterizing module data_read_en_rx" 0 0 "Shell" 0 -1 1516735834921 ""}{ "Info" "" "" "2018.01.23.17:30:34 Info: Adding fifo_empty_rx_status \[altera_avalon_pio 17.1\]" { } { } 0 0 "2018.01.23.17:30:34 Info: Adding fifo_empty_rx_status \[altera_avalon_pio 17.1\]" 0 0 "Shell" 0 -1 1516735834921 ""}{ "Info" "" "" "2018.01.23.17:30:34 Info: Parameterizing module fifo_empty_rx_status" { } { } 0 0 "2018.01.23.17:30:34 Info: Parameterizing module fifo_empty_rx_status" 0 0 "Shell" 0 -1 1516735834922 ""}{ "Info" "" "" "2018.01.23.17:30:34 Info: Adding fifo_empty_tx_status \[altera_avalon_pio 17.1\]" { } { } 0 0 "2018.01.23.17:30:34 Info: Adding fifo_empty_tx_status \[altera_avalon_pio 17.1\]" 0 0 "Shell" 0 -1 1516735834923 ""}{ "Info" "" "" "2018.01.23.17:30:34 Info: Parameterizing module fifo_empty_tx_status" { } { } 0 0 "2018.01.23.17:30:34 Info: Parameterizing module fifo_empty_tx_status" 0 0 "Shell" 0 -1 1516735834925 ""}{ "Info" "" "" "2018.01.23.17:30:34 Info: Adding fifo_full_rx_status \[altera_avalon_pio 17.1\]" { } { } 0 0 "2018.01.23.17:30:34 Info: Adding fifo_full_rx_status \[altera_avalon_pio 17.1\]" 0 0 "Shell" 0 -1 1516735834926 ""}{ "Info" "" "" "2018.01.23.17:30:34 Info: Parameterizing module fifo_full_rx_status" { } { } 0 0 "2018.01.23.17:30:34 Info: Parameterizing module fifo_full_rx_status" 0 0 "Shell" 0 -1 1516735834926 ""}{ "Info" "" "" "2018.01.23.17:30:34 Info: Adding fifo_full_tx_status \[altera_avalon_pio 17.1\]" { } { } 0 0 "2018.01.23.17:30:34 Info: Adding fifo_full_tx_status \[altera_avalon_pio 17.1\]" 0 0 "Shell" 0 -1 1516735834927 ""}{ "Info" "" "" "2018.01.23.17:30:34 Info: Parameterizing module fifo_full_tx_status\n2018.01.23.17:30:34 Info: Adding fsm_info \[altera_avalon_pio 17.1\]\n2018.01.23.17:30:34 Info: Parameterizing module fsm_info\n2018.01.23.17:30:34 Info: Adding hps_0 \[altera_hps 17.1\]" { } { } 0 0 "2018.01.23.17:30:34 Info: Parameterizing module fifo_full_tx_status\n2018.01.23.17:30:34 Info: Adding fsm_info \[altera_avalon_pio 17.1\]\n2018.01.23.17:30:34 Info: Parameterizing module fsm_info\n2018.01.23.17:30:34 Info: Adding hps_0 \[altera_hps 17.1\]" 0 0 "Shell" 0 -1 1516735834929 ""}{ "Info" "" "" "2018.01.23.17:30:34 Info: Parameterizing module hps_0" { } { } 0 0 "2018.01.23.17:30:34 Info: Parameterizing module hps_0" 0 0 "Shell" 0 -1 1516735834934 ""}{ "Info" "" "" "2018.01.23.17:30:34 Info: Adding led_pio_test \[altera_avalon_pio 17.1\]" { } { } 0 0 "2018.01.23.17:30:34 Info: Adding led_pio_test \[altera_avalon_pio 17.1\]" 0 0 "Shell" 0 -1 1516735834943 ""}{ "Info" "" "" "2018.01.23.17:30:34 Info: Parameterizing module led_pio_test" { } { } 0 0 "2018.01.23.17:30:34 Info: Parameterizing module led_pio_test" 0 0 "Shell" 0 -1 1516735834944 ""}{ "Info" "" "" "2018.01.23.17:30:34 Info: Adding link_disable \[altera_avalon_pio 17.1\]" { } { } 0 0 "2018.01.23.17:30:34 Info: Adding link_disable \[altera_avalon_pio 17.1\]" 0 0 "Shell" 0 -1 1516735834946 ""}{ "Info" "" "" "2018.01.23.17:30:34 Info: Parameterizing module link_disable" { } { } 0 0 "2018.01.23.17:30:34 Info: Parameterizing module link_disable" 0 0 "Shell" 0 -1 1516735834946 ""}{ "Info" "" "" "2018.01.23.17:30:34 Info: Adding link_start \[altera_avalon_pio 17.1\]" { } { } 0 0 "2018.01.23.17:30:34 Info: Adding link_start \[altera_avalon_pio 17.1\]" 0 0 "Shell" 0 -1 1516735834948 ""}{ "Info" "" "" "2018.01.23.17:30:34 Info: Parameterizing module link_start" { } { } 0 0 "2018.01.23.17:30:34 Info: Parameterizing module link_start" 0 0 "Shell" 0 -1 1516735834948 ""}{ "Info" "" "" "2018.01.23.17:30:34 Info: Adding pll_0 \[altera_pll 17.1\]" { } { } 0 0 "2018.01.23.17:30:34 Info: Adding pll_0 \[altera_pll 17.1\]" 0 0 "Shell" 0 -1 1516735834949 ""}{ "Info" "" "" "2018.01.23.17:30:34 Info: Parameterizing module pll_0" { } { } 0 0 "2018.01.23.17:30:34 Info: Parameterizing module pll_0" 0 0 "Shell" 0 -1 1516735834950 ""}{ "Info" "" "" "2018.01.23.17:30:34 Info: Adding timecode_ready_rx \[altera_avalon_pio 17.1\]" { } { } 0 0 "2018.01.23.17:30:34 Info: Adding timecode_ready_rx \[altera_avalon_pio 17.1\]" 0 0 "Shell" 0 -1 1516735834953 ""}{ "Info" "" "" "2018.01.23.17:30:34 Info: Parameterizing module timecode_ready_rx" { } { } 0 0 "2018.01.23.17:30:34 Info: Parameterizing module timecode_ready_rx" 0 0 "Shell" 0 -1 1516735834953 ""}{ "Info" "" "" "2018.01.23.17:30:34 Info: Adding timecode_rx \[altera_avalon_pio 17.1\]" { } { } 0 0 "2018.01.23.17:30:34 Info: Adding timecode_rx \[altera_avalon_pio 17.1\]" 0 0 "Shell" 0 -1 1516735834953 ""}{ "Info" "" "" "2018.01.23.17:30:34 Info: Parameterizing module timecode_rx" { } { } 0 0 "2018.01.23.17:30:34 Info: Parameterizing module timecode_rx" 0 0 "Shell" 0 -1 1516735834953 ""}{ "Info" "" "" "2018.01.23.17:30:34 Info: Adding timecode_tx_data \[altera_avalon_pio 17.1\]" { } { } 0 0 "2018.01.23.17:30:34 Info: Adding timecode_tx_data \[altera_avalon_pio 17.1\]" 0 0 "Shell" 0 -1 1516735834954 ""}{ "Info" "" "" "2018.01.23.17:30:34 Info: Parameterizing module timecode_tx_data" { } { } 0 0 "2018.01.23.17:30:34 Info: Parameterizing module timecode_tx_data" 0 0 "Shell" 0 -1 1516735834955 ""}{ "Info" "" "" "2018.01.23.17:30:34 Info: Adding timecode_tx_enable \[altera_avalon_pio 17.1\]\n2018.01.23.17:30:34 Info: Parameterizing module timecode_tx_enable\n2018.01.23.17:30:34 Info: Adding timecode_tx_ready \[altera_avalon_pio 17.1\]\n2018.01.23.17:30:34 Info: Parameterizing module timecode_tx_ready\n2018.01.23.17:30:34 Info: Adding write_data_fifo_tx \[altera_avalon_pio 17.1\]\n2018.01.23.17:30:34 Info: Parameterizing module write_data_fifo_tx" { } { } 0 0 "2018.01.23.17:30:34 Info: Adding timecode_tx_enable \[altera_avalon_pio 17.1\]\n2018.01.23.17:30:34 Info: Parameterizing module timecode_tx_enable\n2018.01.23.17:30:34 Info: Adding timecode_tx_ready \[altera_avalon_pio 17.1\]\n2018.01.23.17:30:34 Info: Parameterizing module timecode_tx_ready\n2018.01.23.17:30:34 Info: Adding write_data_fifo_tx \[altera_avalon_pio 17.1\]\n2018.01.23.17:30:34 Info: Parameterizing module write_data_fifo_tx" 0 0 "Shell" 0 -1 1516735834958 ""}{ "Info" "" "" "2018.01.23.17:30:34 Info: Adding write_en_tx \[altera_avalon_pio 17.1\]" { } { } 0 0 "2018.01.23.17:30:34 Info: Adding write_en_tx \[altera_avalon_pio 17.1\]" 0 0 "Shell" 0 -1 1516735834959 ""}{ "Info" "" "" "2018.01.23.17:30:34 Info: Parameterizing module write_en_tx" { } { } 0 0 "2018.01.23.17:30:34 Info: Parameterizing module write_en_tx" 0 0 "Shell" 0 -1 1516735834959 ""}{ "Info" "" "" "2018.01.23.17:30:34 Info: Building connections" { } { } 0 0 "2018.01.23.17:30:34 Info: Building connections" 0 0 "Shell" 0 -1 1516735834960 ""}{ "Info" "" "" "2018.01.23.17:30:34 Info: Parameterizing connections\n2018.01.23.17:30:34 Info: Validating" { } { } 0 0 "2018.01.23.17:30:34 Info: Parameterizing connections\n2018.01.23.17:30:34 Info: Validating" 0 0 "Shell" 0 -1 1516735834965 ""}{ "Info" "" "" "2018.01.23.17:30:41 Info: Done reading input file" { } { } 0 0 "2018.01.23.17:30:41 Info: Done reading input file" 0 0 "Shell" 0 -1 1516735841270 ""}{ "Info" "" "" "2018.01.23.17:30:43 Info: ulight_fifo.counter_rx_fifo: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation." { } { } 0 0 "2018.01.23.17:30:43 Info: ulight_fifo.counter_rx_fifo: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation." 0 0 "Shell" 0 -1 1516735843344 ""}{ "Info" "" "" "2018.01.23.17:30:43 Info: ulight_fifo.counter_tx_fifo: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation." { } { } 0 0 "2018.01.23.17:30:43 Info: ulight_fifo.counter_tx_fifo: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation." 0 0 "Shell" 0 -1 1516735843345 ""}{ "Info" "" "" "2018.01.23.17:30:43 Info: ulight_fifo.data_flag_rx: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation." { } { } 0 0 "2018.01.23.17:30:43 Info: ulight_fifo.data_flag_rx: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation." 0 0 "Shell" 0 -1 1516735843345 ""}{ "Info" "" "" "2018.01.23.17:30:43 Info: ulight_fifo.data_info: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation." { } { } 0 0 "2018.01.23.17:30:43 Info: ulight_fifo.data_info: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation." 0 0 "Shell" 0 -1 1516735843345 ""}{ "Info" "" "" "2018.01.23.17:30:43 Info: ulight_fifo.fifo_empty_rx_status: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation." { } { } 0 0 "2018.01.23.17:30:43 Info: ulight_fifo.fifo_empty_rx_status: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation." 0 0 "Shell" 0 -1 1516735843345 ""}{ "Info" "" "" "2018.01.23.17:30:43 Info: ulight_fifo.fifo_empty_tx_status: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation." { } { } 0 0 "2018.01.23.17:30:43 Info: ulight_fifo.fifo_empty_tx_status: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation." 0 0 "Shell" 0 -1 1516735843345 ""}{ "Info" "" "" "2018.01.23.17:30:43 Info: ulight_fifo.fifo_full_rx_status: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation." { } { } 0 0 "2018.01.23.17:30:43 Info: ulight_fifo.fifo_full_rx_status: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation." 0 0 "Shell" 0 -1 1516735843345 ""}{ "Info" "" "" "2018.01.23.17:30:43 Info: ulight_fifo.fifo_full_tx_status: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation." { } { } 0 0 "2018.01.23.17:30:43 Info: ulight_fifo.fifo_full_tx_status: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation." 0 0 "Shell" 0 -1 1516735843345 ""}{ "Info" "" "" "2018.01.23.17:30:43 Info: ulight_fifo.fsm_info: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation." { } { } 0 0 "2018.01.23.17:30:43 Info: ulight_fifo.fsm_info: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation." 0 0 "Shell" 0 -1 1516735843345 ""}{ "Info" "" "" "2018.01.23.17:30:43 Info: ulight_fifo.hps_0: HPS Main PLL counter settings: n = 0 m = 36" { } { } 0 0 "2018.01.23.17:30:43 Info: ulight_fifo.hps_0: HPS Main PLL counter settings: n = 0 m = 36" 0 0 "Shell" 0 -1 1516735843346 ""}{ "Info" "" "" "2018.01.23.17:30:43 Info: ulight_fifo.hps_0: HPS peripherial PLL counter settings: n = 0 m = 19" { } { } 0 0 "2018.01.23.17:30:43 Info: ulight_fifo.hps_0: HPS peripherial PLL counter settings: n = 0 m = 19" 0 0 "Shell" 0 -1 1516735843346 ""}{ "Warning" "" "" "2018.01.23.17:30:43 Warning: ulight_fifo.hps_0: 1 or more output clock frequencies cannot be achieved precisely, consider revising desired output clock frequencies." { } { } 0 0 "2018.01.23.17:30:43 Warning: ulight_fifo.hps_0: 1 or more output clock frequencies cannot be achieved precisely, consider revising desired output clock frequencies." 0 0 "Shell" 0 -1 1516735843346 ""}{ "Warning" "" "" "2018.01.23.17:30:43 Warning: ulight_fifo.hps_0: ODT is disabled. Enabling ODT (Mode Register 1) may improve signal integrity" { } { } 0 0 "2018.01.23.17:30:43 Warning: ulight_fifo.hps_0: ODT is disabled. Enabling ODT (Mode Register 1) may improve signal integrity" 0 0 "Shell" 0 -1 1516735843346 ""}{ "Warning" "" "" "2018.01.23.17:30:43 Warning: ulight_fifo.hps_0: set_interface_assignment: Interface \"hps_io\" does not exist" { } { } 0 0 "2018.01.23.17:30:43 Warning: ulight_fifo.hps_0: set_interface_assignment: Interface \"hps_io\" does not exist" 0 0 "Shell" 0 -1 1516735843346 ""}{ "Info" "" "" "2018.01.23.17:30:43 Info: ulight_fifo.pll_0: The legal reference clock frequency is 5.0 MHz..800.0 MHz" { } { } 0 0 "2018.01.23.17:30:43 Info: ulight_fifo.pll_0: The legal reference clock frequency is 5.0 MHz..800.0 MHz" 0 0 "Shell" 0 -1 1516735843348 ""}{ "Warning" "" "" "2018.01.23.17:30:43 Warning: ulight_fifo.pll_0: 'refclk1' is not the same frequency as 'refclk'. You must run Timequest at both frequencies to ensure timing closure" { } { } 0 0 "2018.01.23.17:30:43 Warning: ulight_fifo.pll_0: 'refclk1' is not the same frequency as 'refclk'. You must run Timequest at both frequencies to ensure timing closure" 0 0 "Shell" 0 -1 1516735843349 ""}{ "Warning" "" "" "2018.01.23.17:30:43 Warning: ulight_fifo.pll_0: The period difference between refclk and refclk1 is greater than 20%, automatic clock loss detection will not work" { } { } 0 0 "2018.01.23.17:30:43 Warning: ulight_fifo.pll_0: The period difference between refclk and refclk1 is greater than 20%, automatic clock loss detection will not work" 0 0 "Shell" 0 -1 1516735843349 ""}{ "Info" "" "" "2018.01.23.17:30:43 Info: ulight_fifo.pll_0: Able to implement PLL with user settings" { } { } 0 0 "2018.01.23.17:30:43 Info: ulight_fifo.pll_0: Able to implement PLL with user settings" 0 0 "Shell" 0 -1 1516735843349 ""}{ "Warning" "" "" "2018.01.23.17:30:43 Warning: ulight_fifo.pll_0.refclk1: Signal refclk1 has unknown type refclk1" { } { } 0 0 "2018.01.23.17:30:43 Warning: ulight_fifo.pll_0.refclk1: Signal refclk1 has unknown type refclk1" 0 0 "Shell" 0 -1 1516735843349 ""}{ "Info" "" "" "2018.01.23.17:30:43 Info: ulight_fifo.timecode_ready_rx: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation." { } { } 0 0 "2018.01.23.17:30:43 Info: ulight_fifo.timecode_ready_rx: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation." 0 0 "Shell" 0 -1 1516735843349 ""}{ "Info" "" "" "2018.01.23.17:30:43 Info: ulight_fifo.timecode_rx: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation." { } { } 0 0 "2018.01.23.17:30:43 Info: ulight_fifo.timecode_rx: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation." 0 0 "Shell" 0 -1 1516735843349 ""}{ "Info" "" "" "2018.01.23.17:30:43 Info: ulight_fifo.timecode_tx_ready: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation." { } { } 0 0 "2018.01.23.17:30:43 Info: ulight_fifo.timecode_tx_ready: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation." 0 0 "Shell" 0 -1 1516735843349 ""}{ "Info" "" "" "2018.01.23.17:30:46 Info: ulight_fifo: Generating ulight_fifo \"ulight_fifo\" for QUARTUS_SYNTH" { } { } 0 0 "2018.01.23.17:30:46 Info: ulight_fifo: Generating ulight_fifo \"ulight_fifo\" for QUARTUS_SYNTH" 0 0 "Shell" 0 -1 1516735846790 ""}{ "Warning" "" "" "2018.01.23.17:30:56 Warning: ulight_fifo: \"No matching role found for clk_0:clk:clk_out (clk)\"" { } { } 0 0 "2018.01.23.17:30:56 Warning: ulight_fifo: \"No matching role found for clk_0:clk:clk_out (clk)\"" 0 0 "Shell" 0 -1 1516735856250 ""}{ "Warning" "" "" "2018.01.23.17:30:56 Warning: ulight_fifo: \"No matching role found for pll_0:refclk1:refclk1 (refclk1)\"" { } { } 0 0 "2018.01.23.17:30:56 Warning: ulight_fifo: \"No matching role found for pll_0:refclk1:refclk1 (refclk1)\"" 0 0 "Shell" 0 -1 1516735856250 ""}{ "Info" "" "" "2018.01.23.17:30:58 Info: auto_start: Starting RTL generation for module 'ulight_fifo_auto_start'" { } { } 0 0 "2018.01.23.17:30:58 Info: auto_start: Starting RTL generation for module 'ulight_fifo_auto_start'" 0 0 "Shell" 0 -1 1516735858344 ""}{ "Info" "ulight_fifo_auto_start_component_configuration.pl --do_build_sim=0 ]" "" "2018.01.23.17:30:58 Info: auto_start: Generation command is \[exec /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/bin/perl -I /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/europa -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/perl_lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/common -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=ulight_fifo_auto_start --dir=/tmp/alt7554_7831099621877055177.dir/0030_auto_start_gen/ --quartus_dir=/home/felipe/intelFPGA_lite/17.1/quartus --verilog --config=/tmp/alt7554_7831099621877055177.dir/0030_auto_start_gen/" { } { } 0 0 "2018.01.23.17:30:58 Info:auto_start: Generation command is \[exec /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/bin/perl -I /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/europa -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/perl_lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/common -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=ulight_fifo_auto_start --dir=/tmp/alt7554_7831099621877055177.dir/0030_auto_start_gen/ --quartus_dir=/home/felipe/intelFPGA_lite/17.1/quartus --verilog --config=/tmp/alt7554_7831099621877055177.dir/0030_auto_start_gen/" 0 0 "Shell" 0 -1 1516735858345 ""}{ "Info" "" "" "2018.01.23.17:30:58 Info: auto_start: Done RTL generation for module 'ulight_fifo_auto_start'" { } { } 0 0 "2018.01.23.17:30:58 Info: auto_start: Done RTL generation for module 'ulight_fifo_auto_start'" 0 0 "Shell" 0 -1 1516735858460 ""}{ "Info" "" "" "2018.01.23.17:30:58 Info: auto_start: \"ulight_fifo\" instantiated altera_avalon_pio \"auto_start\"" { } { } 0 0 "2018.01.23.17:30:58 Info: auto_start: \"ulight_fifo\" instantiated altera_avalon_pio \"auto_start\"" 0 0 "Shell" 0 -1 1516735858461 ""}{ "Info" "" "" "2018.01.23.17:30:58 Info: clock_sel: Starting RTL generation for module 'ulight_fifo_clock_sel'" { } { } 0 0 "2018.01.23.17:30:58 Info: clock_sel: Starting RTL generation for module 'ulight_fifo_clock_sel'" 0 0 "Shell" 0 -1 1516735858554 ""}{ "Info" "ulight_fifo_clock_sel_component_configuration.pl --do_build_sim=0 ]" "" "2018.01.23.17:30:58 Info: clock_sel: Generation command is \[exec /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/bin/perl -I /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/europa -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/perl_lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/common -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=ulight_fifo_clock_sel --dir=/tmp/alt7554_7831099621877055177.dir/0031_clock_sel_gen/ --quartus_dir=/home/felipe/intelFPGA_lite/17.1/quartus --verilog --config=/tmp/alt7554_7831099621877055177.dir/0031_clock_sel_gen/" { } { } 0 0 "2018.01.23.17:30:58 Info: clock_sel: Generation command is \[exec /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/bin/perl -I /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/europa -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/perl_lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/common -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=ulight_fifo_clock_sel --dir=/tmp/alt7554_7831099621877055177.dir/0031_clock_sel_gen/ --quartus_dir=/home/felipe/intelFPGA_lite/17.1/quartus --verilog --config=/tmp/alt7554_7831099621877055177.dir/0031_clock_sel_gen/" 0 0 "Shell" 0 -1 1516735858555 ""}{ "Info" "" "" "2018.01.23.17:30:58 Info: clock_sel: Done RTL generation for module 'ulight_fifo_clock_sel'" { } { } 0 0 "2018.01.23.17:30:58 Info: clock_sel: Done RTL generation for module 'ulight_fifo_clock_sel'" 0 0 "Shell" 0 -1 1516735858668 ""}{ "Info" "" "" "2018.01.23.17:30:58 Info: clock_sel: \"ulight_fifo\" instantiated altera_avalon_pio \"clock_sel\"" { } { } 0 0 "2018.01.23.17:30:58 Info: clock_sel: \"ulight_fifo\" instantiated altera_avalon_pio \"clock_sel\"" 0 0 "Shell" 0 -1 1516735858670 ""}{ "Info" "" "" "2018.01.23.17:30:58 Info: counter_rx_fifo: Starting RTL generation for module 'ulight_fifo_counter_rx_fifo'" { } { } 0 0 "2018.01.23.17:30:58 Info: counter_rx_fifo: Starting RTL generation for module 'ulight_fifo_counter_rx_fifo'" 0 0 "Shell" 0 -1 1516735858778 ""}{ "Info" "ulight_fifo_counter_rx_fifo_component_configuration.pl --do_build_sim=0 ]" "" "2018.01.23.17:30:58 Info: counter_rx_fifo: Generation command is \[exec /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/bin/perl -I /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/europa -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/perl_lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/common -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=ulight_fifo_counter_rx_fifo --dir=/tmp/alt7554_7831099621877055177.dir/0032_counter_rx_fifo_gen/ --quartus_dir=/home/felipe/intelFPGA_lite/17.1/quartus --verilog --config=/tmp/alt7554_7831099621877055177.dir/0032_counter_rx_fifo_gen/" { } { } 0 0 "2018.01.23.17:30:58 Info: counter_rx_fifo: Generation command is \[exec /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/bin/perl -I /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/europa -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/perl_lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/common -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=ulight_fifo_counter_rx_fifo --dir=/tmp/alt7554_7831099621877055177.dir/0032_counter_rx_fifo_gen/ --quartus_dir=/home/felipe/intelFPGA_lite/17.1/quartus --verilog --config=/tmp/alt7554_7831099621877055177.dir/0032_counter_rx_fifo_gen/" 0 0 "Shell" 0 -1 1516735858778 ""}{ "Info" "" "" "2018.01.23.17:30:58 Info: counter_rx_fifo: Done RTL generation for module 'ulight_fifo_counter_rx_fifo'" { } { } 0 0 "2018.01.23.17:30:58 Info: counter_rx_fifo: Done RTL generation for module 'ulight_fifo_counter_rx_fifo'" 0 0 "Shell" 0 -1 1516735858895 ""}{ "Info" "" "" "2018.01.23.17:30:58 Info: counter_rx_fifo: \"ulight_fifo\" instantiated altera_avalon_pio \"counter_rx_fifo\"" { } { } 0 0 "2018.01.23.17:30:58 Info: counter_rx_fifo: \"ulight_fifo\" instantiated altera_avalon_pio \"counter_rx_fifo\"" 0 0 "Shell" 0 -1 1516735858898 ""}{ "Info" "" "" "2018.01.23.17:30:58 Info: data_flag_rx: Starting RTL generation for module 'ulight_fifo_data_flag_rx'" { } { } 0 0 "2018.01.23.17:30:58 Info: data_flag_rx: Starting RTL generation for module 'ulight_fifo_data_flag_rx'" 0 0 "Shell" 0 -1 1516735858988 ""}{ "Info" "ulight_fifo_data_flag_rx_component_configuration.pl --do_build_sim=0 ]" "" "2018.01.23.17:30:58 Info: data_flag_rx: Generation command is \[exec /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/bin/perl -I /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/europa -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/perl_lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/common -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=ulight_fifo_data_flag_rx --dir=/tmp/alt7554_7831099621877055177.dir/0033_data_flag_rx_gen/ --quartus_dir=/home/felipe/intelFPGA_lite/17.1/quartus --verilog --config=/tmp/alt7554_7831099621877055177.dir/0033_data_flag_rx_gen/" { } { } 0 0 "2018.01.23.17:30:58 Info: data_flag_rx: Generation command is \[exec /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/bin/perl -I /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/europa -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/perl_lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/common -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=ulight_fifo_data_flag_rx --dir=/tmp/alt7554_7831099621877055177.dir/0033_data_flag_rx_gen/ --quartus_dir=/home/felipe/intelFPGA_lite/17.1/quartus --verilog --config=/tmp/alt7554_7831099621877055177.dir/0033_data_flag_rx_gen/" 0 0 "Shell" 0 -1 1516735858988 ""}{ "Info" "" "" "2018.01.23.17:30:59 Info: data_flag_rx: Done RTL generation for module 'ulight_fifo_data_flag_rx'" { } { } 0 0 "2018.01.23.17:30:59 Info: data_flag_rx: Done RTL generation for module 'ulight_fifo_data_flag_rx'" 0 0 "Shell" 0 -1 1516735859104 ""}{ "Info" "" "" "2018.01.23.17:30:59 Info: data_flag_rx: \"ulight_fifo\" instantiated altera_avalon_pio \"data_flag_rx\"" { } { } 0 0 "2018.01.23.17:30:59 Info: data_flag_rx: \"ulight_fifo\" instantiated altera_avalon_pio \"data_flag_rx\"" 0 0 "Shell" 0 -1 1516735859105 ""}{ "Info" "" "" "2018.01.23.17:30:59 Info: data_info: Starting RTL generation for module 'ulight_fifo_data_info'" { } { } 0 0 "2018.01.23.17:30:59 Info: data_info: Starting RTL generation for module 'ulight_fifo_data_info'" 0 0 "Shell" 0 -1 1516735859198 ""}{ "Info" "ulight_fifo_data_info_component_configuration.pl --do_build_sim=0 ]" "" "2018.01.23.17:30:59 Info: data_info: Generation command is \[exec /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/bin/perl -I /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/europa -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/perl_lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/common -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=ulight_fifo_data_info --dir=/tmp/alt7554_7831099621877055177.dir/0034_data_info_gen/ --quartus_dir=/home/felipe/intelFPGA_lite/17.1/quartus --verilog --config=/tmp/alt7554_7831099621877055177.dir/0034_data_info_gen/" { } { } 0 0 "2018.01.23.17:30:59 Info: data_info: Generation command is \[exec /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/bin/perl -I /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/europa -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/perl_lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/common -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=ulight_fifo_data_info --dir=/tmp/alt7554_7831099621877055177.dir/0034_data_info_gen/ --quartus_dir=/home/felipe/intelFPGA_lite/17.1/quartus --verilog --config=/tmp/alt7554_7831099621877055177.dir/0034_data_info_gen/" 0 0 "Shell" 0 -1 1516735859199 ""}{ "Info" "" "" "2018.01.23.17:30:59 Info: data_info: Done RTL generation for module 'ulight_fifo_data_info'" { } { } 0 0 "2018.01.23.17:30:59 Info: data_info: Done RTL generation for module 'ulight_fifo_data_info'" 0 0 "Shell" 0 -1 1516735859311 ""}{ "Info" "" "" "2018.01.23.17:30:59 Info: data_info: \"ulight_fifo\" instantiated altera_avalon_pio \"data_info\"" { } { } 0 0 "2018.01.23.17:30:59 Info: data_info: \"ulight_fifo\" instantiated altera_avalon_pio \"data_info\"" 0 0 "Shell" 0 -1 1516735859312 ""}{ "Info" "" "" "2018.01.23.17:30:59 Info: fifo_empty_rx_status: Starting RTL generation for module 'ulight_fifo_fifo_empty_rx_status'" { } { } 0 0 "2018.01.23.17:30:59 Info: fifo_empty_rx_status: Starting RTL generation for module 'ulight_fifo_fifo_empty_rx_status'" 0 0 "Shell" 0 -1 1516735859420 ""}{ "Info" "ulight_fifo_fifo_empty_rx_status_component_configuration.pl --do_build_sim=0 ]" "" "2018.01.23.17:30:59 Info: fifo_empty_rx_status: Generation command is \[exec /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/bin/perl -I /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/europa -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/perl_lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/common -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=ulight_fifo_fifo_empty_rx_status --dir=/tmp/alt7554_7831099621877055177.dir/0035_fifo_empty_rx_status_gen/ --quartus_dir=/home/felipe/intelFPGA_lite/17.1/quartus --verilog --config=/tmp/alt7554_7831099621877055177.dir/0035_fifo_empty_rx_status_gen/" { } { } 0 0 "2018.01.23.17:30:59 Info: fifo_empty_rx_status: Generation command is \[exec /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/bin/perl -I /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/europa -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/perl_lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/common -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=ulight_fifo_fifo_empty_rx_status --dir=/tmp/alt7554_7831099621877055177.dir/0035_fifo_empty_rx_status_gen/ --quartus_dir=/home/felipe/intelFPGA_lite/17.1/quartus --verilog --config=/tmp/alt7554_7831099621877055177.dir/0035_fifo_empty_rx_status_gen/" 0 0 "Shell" 0 -1 1516735859420 ""}{ "Info" "" "" "2018.01.23.17:30:59 Info: fifo_empty_rx_status: Done RTL generation for module 'ulight_fifo_fifo_empty_rx_status'" { } { } 0 0 "2018.01.23.17:30:59 Info: fifo_empty_rx_status: Done RTL generation for module 'ulight_fifo_fifo_empty_rx_status'" 0 0 "Shell" 0 -1 1516735859548 ""}{ "Info" "" "" "2018.01.23.17:30:59 Info: fifo_empty_rx_status: \"ulight_fifo\" instantiated altera_avalon_pio \"fifo_empty_rx_status\"" { } { } 0 0 "2018.01.23.17:30:59 Info: fifo_empty_rx_status: \"ulight_fifo\" instantiated altera_avalon_pio \"fifo_empty_rx_status\"" 0 0 "Shell" 0 -1 1516735859548 ""}{ "Info" "" "" "2018.01.23.17:30:59 Info: hps_0: \"Running for module: hps_0\"" { } { } 0 0 "2018.01.23.17:30:59 Info: hps_0: \"Running for module: hps_0\"" 0 0 "Shell" 0 -1 1516735859549 ""}{ "Info" "" "" "2018.01.23.17:31:00 Info: hps_0: HPS Main PLL counter settings: n = 0 m = 36" { } { } 0 0 "2018.01.23.17:31:00 Info: hps_0: HPS Main PLL counter settings: n = 0 m = 36" 0 0 "Shell" 0 -1 1516735860279 ""}{ "Info" "" "" "2018.01.23.17:31:00 Info: hps_0: HPS peripherial PLL counter settings: n = 0 m = 19" { } { } 0 0 "2018.01.23.17:31:00 Info: hps_0: HPS peripherial PLL counter settings: n = 0 m = 19" 0 0 "Shell" 0 -1 1516735860805 ""}{ "Warning" "" "" "2018.01.23.17:31:00 Warning: hps_0: 1 or more output clock frequencies cannot be achieved precisely, consider revising desired output clock frequencies." { } { } 0 0 "2018.01.23.17:31:00 Warning: hps_0: 1 or more output clock frequencies cannot be achieved precisely, consider revising desired output clock frequencies." 0 0 "Shell" 0 -1 1516735860809 ""}{ "Warning" "" "" "2018.01.23.17:31:00 Warning: hps_0: ODT is disabled. Enabling ODT (Mode Register 1) may improve signal integrity" { } { } 0 0 "2018.01.23.17:31:00 Warning: hps_0: ODT is disabled. Enabling ODT (Mode Register 1) may improve signal integrity" 0 0 "Shell" 0 -1 1516735860825 ""}{ "Warning" "" "" "2018.01.23.17:31:00 Warning: hps_0: set_interface_assignment: Interface \"hps_io\" does not exist" { } { } 0 0 "2018.01.23.17:31:00 Warning: hps_0: set_interface_assignment: Interface \"hps_io\" does not exist" 0 0 "Shell" 0 -1 1516735860912 ""}{ "Info" "" "" "2018.01.23.17:31:01 Info: hps_0: \"ulight_fifo\" instantiated altera_hps \"hps_0\"" { } { } 0 0 "2018.01.23.17:31:01 Info: hps_0: \"ulight_fifo\" instantiated altera_hps \"hps_0\"" 0 0 "Shell" 0 -1 1516735861270 ""}{ "Info" "" "" "2018.01.23.17:31:01 Info: led_pio_test: Starting RTL generation for module 'ulight_fifo_led_pio_test'" { } { } 0 0 "2018.01.23.17:31:01 Info: led_pio_test: Starting RTL generation for module 'ulight_fifo_led_pio_test'" 0 0 "Shell" 0 -1 1516735861415 ""}{ "Info" "ulight_fifo_led_pio_test_component_configuration.pl --do_build_sim=0 ]" "" "2018.01.23.17:31:01 Info: led_pio_test: Generation command is \[exec /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/bin/perl -I /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/europa -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/perl_lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/common -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=ulight_fifo_led_pio_test --dir=/tmp/alt7554_7831099621877055177.dir/0036_led_pio_test_gen/ --quartus_dir=/home/felipe/intelFPGA_lite/17.1/quartus --verilog --config=/tmp/alt7554_7831099621877055177.dir/0036_led_pio_test_gen/" { } { } 0 0 "2018.01.23.17:31:01 Info: led_pio_test: Generation command is \[exec /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/bin/perl -I /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/europa -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/perl_lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/common -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=ulight_fifo_led_pio_test --dir=/tmp/alt7554_7831099621877055177.dir/0036_led_pio_test_gen/ --quartus_dir=/home/felipe/intelFPGA_lite/17.1/quartus --verilog --config=/tmp/alt7554_7831099621877055177.dir/0036_led_pio_test_gen/" 0 0 "Shell" 0 -1 1516735861415 ""}{ "Info" "" "" "2018.01.23.17:31:01 Info: led_pio_test: Done RTL generation for module 'ulight_fifo_led_pio_test'" { } { } 0 0 "2018.01.23.17:31:01 Info: led_pio_test: Done RTL generation for module 'ulight_fifo_led_pio_test'" 0 0 "Shell" 0 -1 1516735861536 ""}{ "Info" "" "" "2018.01.23.17:31:01 Info: led_pio_test: \"ulight_fifo\" instantiated altera_avalon_pio \"led_pio_test\"" { } { } 0 0 "2018.01.23.17:31:01 Info: led_pio_test: \"ulight_fifo\" instantiated altera_avalon_pio \"led_pio_test\"" 0 0 "Shell" 0 -1 1516735861537 ""}{ "Info" "" "" "2018.01.23.17:31:01 Info: pll_0: \"ulight_fifo\" instantiated altera_pll \"pll_0\"" { } { } 0 0 "2018.01.23.17:31:01 Info: pll_0: \"ulight_fifo\" instantiated altera_pll \"pll_0\"" 0 0 "Shell" 0 -1 1516735861569 ""}{ "Info" "" "" "2018.01.23.17:31:01 Info: timecode_rx: Starting RTL generation for module 'ulight_fifo_timecode_rx'" { } { } 0 0 "2018.01.23.17:31:01 Info: timecode_rx: Starting RTL generation for module 'ulight_fifo_timecode_rx'" 0 0 "Shell" 0 -1 1516735861676 ""}{ "Info" "ulight_fifo_timecode_rx_component_configuration.pl --do_build_sim=0 ]" "" "2018.01.23.17:31:01 Info: timecode_rx: Generation command is \[exec /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/bin/perl -I /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/europa -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/perl_lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/common -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=ulight_fifo_timecode_rx --dir=/tmp/alt7554_7831099621877055177.dir/0038_timecode_rx_gen/ --quartus_dir=/home/felipe/intelFPGA_lite/17.1/quartus --verilog --config=/tmp/alt7554_7831099621877055177.dir/0038_timecode_rx_gen/" { } { } 0 0 "2018.01.23.17:31:01Info: timecode_rx: Generation command is \[exec /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/bin/perl -I /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/europa -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/perl_lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/common -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=ulight_fifo_timecode_rx --dir=/tmp/alt7554_7831099621877055177.dir/0038_timecode_rx_gen/ --quartus_dir=/home/felipe/intelFPGA_lite/17.1/quartus --verilog --config=/tmp/alt7554_7831099621877055177.dir/0038_timecode_rx_gen/" 0 0 "Shell" 0 -1 1516735861676 ""}{ "Info" "" "" "2018.01.23.17:31:01 Info: timecode_rx: Done RTL generation for module 'ulight_fifo_timecode_rx'" { } { } 0 0 "2018.01.23.17:31:01 Info: timecode_rx: Done RTL generation for module 'ulight_fifo_timecode_rx'" 0 0 "Shell" 0 -1 1516735861788 ""}{ "Info" "" "" "2018.01.23.17:31:01 Info: timecode_rx: \"ulight_fifo\" instantiated altera_avalon_pio \"timecode_rx\"" { } { } 0 0 "2018.01.23.17:31:01 Info: timecode_rx: \"ulight_fifo\" instantiated altera_avalon_pio \"timecode_rx\"" 0 0 "Shell" 0 -1 1516735861789 ""}{ "Info" "" "" "2018.01.23.17:31:01 Info: timecode_tx_data: Starting RTL generation for module 'ulight_fifo_timecode_tx_data'" { } { } 0 0 "2018.01.23.17:31:01 Info: timecode_tx_data: Starting RTL generation for module 'ulight_fifo_timecode_tx_data'" 0 0 "Shell" 0 -1 1516735861875 ""}{ "Info" "ulight_fifo_timecode_tx_data_component_configuration.pl --do_build_sim=0 ]" "" "2018.01.23.17:31:01 Info: timecode_tx_data: Generation command is \[exec /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/bin/perl -I /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/europa -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/perl_lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/common -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=ulight_fifo_timecode_tx_data --dir=/tmp/alt7554_7831099621877055177.dir/0039_timecode_tx_data_gen/ --quartus_dir=/home/felipe/intelFPGA_lite/17.1/quartus --verilog --config=/tmp/alt7554_7831099621877055177.dir/0039_timecode_tx_data_gen/" { } { }0 0 "2018.01.23.17:31:01 Info: timecode_tx_data: Generation command is \[exec /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/bin/perl -I /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/europa -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/perl_lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/common -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=ulight_fifo_timecode_tx_data --dir=/tmp/alt7554_7831099621877055177.dir/0039_timecode_tx_data_gen/ --quartus_dir=/home/felipe/intelFPGA_lite/17.1/quartus --verilog --config=/tmp/alt7554_7831099621877055177.dir/0039_timecode_tx_data_gen/" 0 0 "Shell" 0 -1 1516735861876 ""}{ "Info" "" "" "2018.01.23.17:31:01 Info: timecode_tx_data: Done RTL generation for module 'ulight_fifo_timecode_tx_data'" { } { } 0 0 "2018.01.23.17:31:01 Info: timecode_tx_data: Done RTL generation for module 'ulight_fifo_timecode_tx_data'" 0 0 "Shell" 0 -1 1516735861988 ""}{ "Info" "" "" "2018.01.23.17:31:01 Info: timecode_tx_data: \"ulight_fifo\" instantiated altera_avalon_pio \"timecode_tx_data\"" { } { } 0 0 "2018.01.23.17:31:01 Info: timecode_tx_data: \"ulight_fifo\" instantiated altera_avalon_pio \"timecode_tx_data\"" 0 0 "Shell" 0 -1 1516735861989 ""}{ "Info" "" "" "2018.01.23.17:31:02 Info: write_data_fifo_tx: Starting RTL generation for module 'ulight_fifo_write_data_fifo_tx'" { } { } 0 0 "2018.01.23.17:31:02 Info: write_data_fifo_tx: Starting RTL generation for module 'ulight_fifo_write_data_fifo_tx'" 0 0 "Shell" 0 -1 1516735862097 ""}{ "Info" "ulight_fifo_write_data_fifo_tx_component_configuration.pl --do_build_sim=0 ]" "" "2018.01.23.17:31:02 Info: write_data_fifo_tx: Generation command is \[exec /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/bin/perl -I /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/europa -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/perl_lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/common -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=ulight_fifo_write_data_fifo_tx --dir=/tmp/alt7554_7831099621877055177.dir/0040_write_data_fifo_tx_gen/ --quartus_dir=/home/felipe/intelFPGA_lite/17.1/quartus --verilog --config=/tmp/alt7554_7831099621877055177.dir/0040_write_data_fifo_tx_gen/"{ } { } 0 0 "2018.01.23.17:31:02 Info: write_data_fifo_tx: Generation command is \[exec /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/bin/perl -I /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/europa -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/perl_lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/common -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=ulight_fifo_write_data_fifo_tx --dir=/tmp/alt7554_7831099621877055177.dir/0040_write_data_fifo_tx_gen/ --quartus_dir=/home/felipe/intelFPGA_lite/17.1/quartus --verilog --config=/tmp/alt7554_7831099621877055177.dir/0040_write_data_fifo_tx_gen/" 0 0 "Shell" 0 -1 1516735862097 ""}{ "Info" "" "" "2018.01.23.17:31:02 Info: write_data_fifo_tx: Done RTL generation for module 'ulight_fifo_write_data_fifo_tx'" { } { } 0 0 "2018.01.23.17:31:02 Info: write_data_fifo_tx: Done RTL generation for module 'ulight_fifo_write_data_fifo_tx'" 0 0 "Shell" 0 -1 1516735862210 ""}{ "Info" "" "" "2018.01.23.17:31:02 Info: write_data_fifo_tx: \"ulight_fifo\" instantiated altera_avalon_pio \"write_data_fifo_tx\"" { } { } 0 0 "2018.01.23.17:31:02 Info: write_data_fifo_tx: \"ulight_fifo\" instantiated altera_avalon_pio \"write_data_fifo_tx\"" 0 0 "Shell" 0 -1 1516735862211 ""}{ "Info" "" "" "2018.01.23.17:31:03 Info: avalon_st_adapter: Inserting error_adapter: error_adapter_0" { } { } 0 0 "2018.01.23.17:31:03 Info: avalon_st_adapter: Inserting error_adapter: error_adapter_0" 0 0 "Shell" 0 -1 1516735863534 ""}{ "Info" "" "" "2018.01.23.17:31:03 Info: avalon_st_adapter_001: Inserting error_adapter: error_adapter_0" { } { } 0 0 "2018.01.23.17:31:03 Info: avalon_st_adapter_001: Inserting error_adapter: error_adapter_0" 0 0 "Shell" 0 -1 1516735863572 ""}{ "Info" "" "" "2018.01.23.17:31:03 Info: avalon_st_adapter_002: Inserting error_adapter: error_adapter_0" { } { } 0 0 "2018.01.23.17:31:03 Info: avalon_st_adapter_002: Inserting error_adapter: error_adapter_0" 0 0 "Shell" 0 -1 1516735863611 ""}{ "Info" "" "" "2018.01.23.17:31:03 Info: avalon_st_adapter_003: Inserting error_adapter: error_adapter_0" { } { } 0 0 "2018.01.23.17:31:03 Info: avalon_st_adapter_003: Inserting error_adapter: error_adapter_0" 0 0 "Shell" 0 -1 1516735863671 ""}{ "Info" "" "" "2018.01.23.17:31:03 Info: avalon_st_adapter_004: Inserting error_adapter: error_adapter_0" { } { } 0 0 "2018.01.23.17:31:03 Info: avalon_st_adapter_004: Inserting error_adapter: error_adapter_0" 0 0 "Shell" 0 -1 1516735863741 ""}{ "Info" "" "" "2018.01.23.17:31:03 Info: avalon_st_adapter_005: Inserting error_adapter: error_adapter_0" { } { } 0 0 "2018.01.23.17:31:03 Info: avalon_st_adapter_005: Inserting error_adapter: error_adapter_0" 0 0 "Shell" 0 -1 1516735863801 ""}{ "Info" "" "" "2018.01.23.17:31:03 Info: avalon_st_adapter_006: Inserting error_adapter: error_adapter_0" { } { } 0 0 "2018.01.23.17:31:03 Info: avalon_st_adapter_006: Inserting error_adapter: error_adapter_0" 0 0 "Shell" 0 -1 1516735863855 ""}{ "Info" "" "" "2018.01.23.17:31:03 Info: avalon_st_adapter_007: Inserting error_adapter: error_adapter_0" { } { } 0 0 "2018.01.23.17:31:03 Info: avalon_st_adapter_007: Inserting error_adapter: error_adapter_0" 0 0 "Shell" 0 -1 1516735863921 ""}{ "Info" "" "" "2018.01.23.17:31:03 Info: avalon_st_adapter_008: Inserting error_adapter: error_adapter_0" { } { } 0 0 "2018.01.23.17:31:03 Info: avalon_st_adapter_008: Inserting error_adapter: error_adapter_0" 0 0 "Shell" 0 -1 1516735863979 ""}{ "Info" "" "" "2018.01.23.17:31:04 Info: avalon_st_adapter_009: Inserting error_adapter: error_adapter_0" { } { } 0 0 "2018.01.23.17:31:04 Info: avalon_st_adapter_009: Inserting error_adapter: error_adapter_0" 0 0 "Shell" 0 -1 1516735864040 ""}{ "Info" "" "" "2018.01.23.17:31:04 Info: avalon_st_adapter_010: Inserting error_adapter: error_adapter_0" { } { } 0 0 "2018.01.23.17:31:04 Info: avalon_st_adapter_010: Inserting error_adapter: error_adapter_0" 0 0 "Shell" 0 -1 1516735864101 ""}{ "Info" "" "" "2018.01.23.17:31:04 Info: avalon_st_adapter_011: Inserting error_adapter: error_adapter_0" { } { } 0 0 "2018.01.23.17:31:04 Info: avalon_st_adapter_011: Inserting error_adapter: error_adapter_0" 0 0 "Shell" 0 -1 1516735864161 ""}{ "Info" "" "" "2018.01.23.17:31:04 Info: avalon_st_adapter_012: Inserting error_adapter: error_adapter_0" { } { } 0 0 "2018.01.23.17:31:04 Info: avalon_st_adapter_012: Inserting error_adapter: error_adapter_0" 0 0 "Shell" 0 -1 1516735864253 ""}{ "Info" "" "" "2018.01.23.17:31:04 Info: avalon_st_adapter_013: Inserting error_adapter: error_adapter_0" { } { } 0 0 "2018.01.23.17:31:04 Info: avalon_st_adapter_013: Inserting error_adapter: error_adapter_0" 0 0 "Shell" 0 -1 1516735864297 ""}{ "Info" "" "" "2018.01.23.17:31:04 Info: avalon_st_adapter_014: Inserting error_adapter: error_adapter_0" { } { } 0 0 "2018.01.23.17:31:04 Info: avalon_st_adapter_014: Inserting error_adapter: error_adapter_0" 0 0 "Shell" 0 -1 1516735864334 ""}{ "Info" "" "" "2018.01.23.17:31:04 Info: avalon_st_adapter_015: Inserting error_adapter: error_adapter_0" { } { } 0 0 "2018.01.23.17:31:04 Info: avalon_st_adapter_015: Inserting error_adapter: error_adapter_0" 0 0 "Shell" 0 -1 1516735864391 ""}{ "Info" "" "" "2018.01.23.17:31:04 Info: avalon_st_adapter_016: Inserting error_adapter: error_adapter_0" { } { } 0 0 "2018.01.23.17:31:04 Info: avalon_st_adapter_016: Inserting error_adapter: error_adapter_0" 0 0 "Shell" 0 -1 1516735864443 ""}{ "Info" "" "" "2018.01.23.17:31:04 Info: avalon_st_adapter_017: Inserting error_adapter: error_adapter_0" { } { } 0 0 "2018.01.23.17:31:04 Info: avalon_st_adapter_017: Inserting error_adapter: error_adapter_0" 0 0 "Shell" 0 -1 1516735864499 ""}{ "Info" "" "" "2018.01.23.17:31:04 Info: avalon_st_adapter_018: Inserting error_adapter: error_adapter_0" { } { } 0 0 "2018.01.23.17:31:04 Info: avalon_st_adapter_018: Inserting error_adapter: error_adapter_0" 0 0 "Shell" 0 -1 1516735864548 ""}{ "Info" "" "" "2018.01.23.17:31:04 Info: avalon_st_adapter_019: Inserting error_adapter: error_adapter_0" { } { } 0 0 "2018.01.23.17:31:04 Info: avalon_st_adapter_019: Inserting error_adapter: error_adapter_0" 0 0 "Shell" 0 -1 1516735864595 ""}{ "Info" "" "" "2018.01.23.17:31:04 Info: avalon_st_adapter_020: Inserting error_adapter: error_adapter_0" { } { } 0 0 "2018.01.23.17:31:04 Info: avalon_st_adapter_020: Inserting error_adapter: error_adapter_0" 0 0 "Shell" 0 -1 1516735864650 ""}{ "Info" "" "" "2018.01.23.17:31:04 Info: avalon_st_adapter_021: Inserting error_adapter: error_adapter_0" { } { } 0 0 "2018.01.23.17:31:04 Info: avalon_st_adapter_021: Inserting error_adapter: error_adapter_0" 0 0 "Shell" 0 -1 1516735864729 ""}{ "Info" "" "" "2018.01.23.17:31:06 Info: mm_interconnect_0: \"ulight_fifo\" instantiated altera_mm_interconnect \"mm_interconnect_0\"" { } { } 0 0 "2018.01.23.17:31:06 Info: mm_interconnect_0: \"ulight_fifo\" instantiated altera_mm_interconnect \"mm_interconnect_0\"" 0 0 "Shell" 0 -1 1516735866289 ""}{ "Info" "" "" "2018.01.23.17:31:06 Info: rst_controller: \"ulight_fifo\" instantiated altera_reset_controller \"rst_controller\"" { } { } 0 0 "2018.01.23.17:31:06 Info: rst_controller: \"ulight_fifo\" instantiated altera_reset_controller \"rst_controller\"" 0 0 "Shell" 0 -1 1516735866293 ""}{ "Info" "" "" "2018.01.23.17:31:06 Info: fpga_interfaces: \"hps_0\" instantiated altera_interface_generator \"fpga_interfaces\"" { } { } 0 0 "2018.01.23.17:31:06 Info: fpga_interfaces: \"hps_0\" instantiated altera_interface_generator \"fpga_interfaces\"" 0 0 "Shell" 0 -1 1516735866347 ""}{ "Info" "" "" "2018.01.23.17:31:06 Info: hps_io: \"hps_0\" instantiated altera_hps_io \"hps_io\"" { } { } 0 0 "2018.01.23.17:31:06 Info: hps_io: \"hps_0\" instantiated altera_hps_io \"hps_io\"" 0 0 "Shell" 0 -1 1516735866457 ""}{ "Info" "" "" "2018.01.23.17:31:06 Info: led_pio_test_s1_translator: \"mm_interconnect_0\" instantiated altera_merlin_slave_translator \"led_pio_test_s1_translator\"" { } { } 0 0 "2018.01.23.17:31:06 Info: led_pio_test_s1_translator: \"mm_interconnect_0\" instantiated altera_merlin_slave_translator \"led_pio_test_s1_translator\"" 0 0 "Shell" 0 -1 1516735866458 ""}{ "Info" "" "" "2018.01.23.17:31:06 Info: hps_0_h2f_axi_master_agent: \"mm_interconnect_0\" instantiated altera_merlin_axi_master_ni \"hps_0_h2f_axi_master_agent\"" { } { } 0 0 "2018.01.23.17:31:06 Info: hps_0_h2f_axi_master_agent: \"mm_interconnect_0\" instantiated altera_merlin_axi_master_ni \"hps_0_h2f_axi_master_agent\"" 0 0 "Shell" 0 -1 1516735866460 ""}{ "Info" "" "" "2018.01.23.17:31:06 Info: led_pio_test_s1_agent: \"mm_interconnect_0\" instantiated altera_merlin_slave_agent \"led_pio_test_s1_agent\"" { } { } 0 0 "2018.01.23.17:31:06 Info: led_pio_test_s1_agent: \"mm_interconnect_0\" instantiated altera_merlin_slave_agent \"led_pio_test_s1_agent\"" 0 0 "Shell" 0 -1 1516735866461 ""}{ "Info" "" "" "2018.01.23.17:31:06 Info: led_pio_test_s1_agent_rsp_fifo: \"mm_interconnect_0\" instantiated altera_avalon_sc_fifo \"led_pio_test_s1_agent_rsp_fifo\"" { } { } 0 0 "2018.01.23.17:31:06 Info: led_pio_test_s1_agent_rsp_fifo: \"mm_interconnect_0\" instantiated altera_avalon_sc_fifo \"led_pio_test_s1_agent_rsp_fifo\"" 0 0 "Shell" 0 -1 1516735866463 ""}{ "Info" "" "" "2018.01.23.17:31:06 Info: router: \"mm_interconnect_0\" instantiated altera_merlin_router \"router\"" { } { } 0 0 "2018.01.23.17:31:06 Info: router: \"mm_interconnect_0\" instantiated altera_merlin_router \"router\"" 0 0 "Shell" 0 -1 1516735866471 ""}{ "Info" "" "" "2018.01.23.17:31:06 Info: router_002: \"mm_interconnect_0\" instantiated altera_merlin_router \"router_002\"" { } { } 0 0 "2018.01.23.17:31:06 Info: router_002: \"mm_interconnect_0\" instantiated altera_merlin_router \"router_002\"" 0 0 "Shell" 0 -1 1516735866481 ""}{ "Info" "" "" "2018.01.23.17:31:06 Info: hps_0_h2f_axi_master_wr_limiter: \"mm_interconnect_0\" instantiated altera_merlin_traffic_limiter \"hps_0_h2f_axi_master_wr_limiter\"" { } { } 0 0 "2018.01.23.17:31:06 Info: hps_0_h2f_axi_master_wr_limiter: \"mm_interconnect_0\" instantiated altera_merlin_traffic_limiter \"hps_0_h2f_axi_master_wr_limiter\"" 0 0 "Shell" 0 -1 1516735866484 ""}{ "Info" "altera_avalon_sc_fifo.v" "" "2018.01.23.17:31:06 Info: Reusing file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules" { } { } 0 0 "2018.01.23.17:31:06 Info: Reusing file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules" 0 0 "Shell" 0 -1 1516735866484 ""}{ "Info" "" "" "2018.01.23.17:31:06 Info: led_pio_test_s1_burst_adapter: \"mm_interconnect_0\" instantiated altera_merlin_burst_adapter \"led_pio_test_s1_burst_adapter\"" { } { } 0 0 "2018.01.23.17:31:06 Info: led_pio_test_s1_burst_adapter: \"mm_interconnect_0\" instantiated altera_merlin_burst_adapter \"led_pio_test_s1_burst_adapter\"" 0 0 "Shell" 0 -1 1516735866489 ""}{ "Info" "altera_merlin_address_alignment.sv" "" "2018.01.23.17:31:06 Info: Reusing file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules" { } { } 0 0 "2018.01.23.17:31:06 Info: Reusing file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules" 0 0 "Shell" 0 -1 1516735866490 ""}{ "Info" "altera_avalon_st_pipeline_base.v" "" "2018.01.23.17:31:06 Info: Reusing file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules" { } { } 0 0 "2018.01.23.17:31:06 Info: Reusing file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules" 0 0 "Shell" 0 -1 1516735866491 ""}{ "Info" "" "" "2018.01.23.17:31:06 Info: cmd_demux: \"mm_interconnect_0\" instantiated altera_merlin_demultiplexer \"cmd_demux\"" { } { } 0 0 "2018.01.23.17:31:06 Info: cmd_demux: \"mm_interconnect_0\" instantiated altera_merlin_demultiplexer \"cmd_demux\"" 0 0 "Shell" 0 -1 1516735866497 ""}{ "Info" "" "" "2018.01.23.17:31:06 Info: cmd_mux: \"mm_interconnect_0\" instantiated altera_merlin_multiplexer \"cmd_mux\"" { } { } 0 0 "2018.01.23.17:31:06 Info: cmd_mux: \"mm_interconnect_0\" instantiated altera_merlin_multiplexer \"cmd_mux\"" 0 0 "Shell" 0 -1 1516735866516 ""}{ "Info" "" "" "2018.01.23.17:31:06 Info: rsp_demux: \"mm_interconnect_0\" instantiated altera_merlin_demultiplexer \"rsp_demux\"" { } { } 0 0 "2018.01.23.17:31:06 Info: rsp_demux: \"mm_interconnect_0\" instantiated altera_merlin_demultiplexer \"rsp_demux\"" 0 0 "Shell" 0 -1 1516735866526 ""}{ "Info" "" "" "2018.01.23.17:31:06 Info: rsp_mux: \"mm_interconnect_0\" instantiated altera_merlin_multiplexer \"rsp_mux\"" { } { } 0 0 "2018.01.23.17:31:06 Info: rsp_mux: \"mm_interconnect_0\" instantiated altera_merlin_multiplexer \"rsp_mux\"" 0 0 "Shell" 0 -1 1516735866542 ""}{ "Info" "altera_merlin_arbitrator.sv" "" "2018.01.23.17:31:06 Info: Reusing file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules" { } { } 0 0 "2018.01.23.17:31:06 Info: Reusing file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules" 0 0 "Shell" 0 -1 1516735866544 ""}{ "Info" "" "" "2018.01.23.17:31:06 Info: avalon_st_adapter: \"mm_interconnect_0\" instantiated altera_avalon_st_adapter \"avalon_st_adapter\"" { } { } 0 0 "2018.01.23.17:31:06 Info: avalon_st_adapter: \"mm_interconnect_0\" instantiated altera_avalon_st_adapter \"avalon_st_adapter\"" 0 0 "Shell" 0 -1 1516735866567 ""}{ "Info" "" "" "2018.01.23.17:31:48 Info: border: \"hps_io\" instantiated altera_interface_generator \"border\"" { } { } 0 0 "2018.01.23.17:31:48 Info: border: \"hps_io\" instantiated altera_interface_generator \"border\"" 0 0 "Shell" 0 -1 1516735908549 ""}{ "Info" "" "" "2018.01.23.17:31:48 Info: error_adapter_0: \"avalon_st_adapter\" instantiated error_adapter \"error_adapter_0\"" { } { } 0 0 "2018.01.23.17:31:48 Info: error_adapter_0: \"avalon_st_adapter\" instantiated error_adapter \"error_adapter_0\"" 0 0 "Shell" 0 -1 1516735908640 ""}{ "Info" "" "" "2018.01.23.17:31:48 Info: ulight_fifo: Done \"ulight_fifo\" with 32 modules, 89 files" { } { } 0 0 "2018.01.23.17:31:48 Info: ulight_fifo: Done \"ulight_fifo\" with 32 modules, 89 files" 0 0 "Shell" 0 -1 1516735908640 ""}{ "Info" "" "" "2018.01.23.17:31:49 Info: qsys-generate succeeded." { } { } 0 0 "2018.01.23.17:31:49 Info: qsys-generate succeeded." 0 0 "Shell" 0 -1 1516735909794 ""}{ "Info" "" "" "2018.01.23.17:31:49 Info: Finished: Create HDL design files for synthesis" { } { } 0 0 "2018.01.23.17:31:49 Info: Finished: Create HDL design files for synthesis" 0 0 "Shell" 0 -1 1516735909794 ""}{ "Info" "IIPMAN_IPRGEN_SUCCESSFUL" "Qsys ulight_fifo.qsys " "Completed upgrading IP component Qsys with file \"ulight_fifo.qsys\"" { } { } 0 11131 "Completed upgrading IP component %1!s! with file \"%2!s!\"" 0 0 "Shell" 0 -1 1516735919862 ""}{ "Info" "IQEXE_TCL_SCRIPT_STATUS" "/home/felipe/intelFPGA_lite/17.1/quartus/common/tcl/internal/ip_regen/ip_regen.tcl " "Evaluation of Tcl script /home/felipe/intelFPGA_lite/17.1/quartus/common/tcl/internal/ip_regen/ip_regen.tcl was successful" { } { } 0 23030 "Evaluation of Tcl script %1!s! was successful" 0 0 "Shell" 0 -1 1516735929556 ""}{ "Info" "IQEXE_ERROR_COUNT" "Shell 0 s 30 s Quartus Prime " "Quartus Prime Shell was successful. 0 errors, 30 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "1063 " "Peak virtual memory: 1063 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1516735929557 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Jan 23 17:32:09 2018 " "Processing ended: Tue Jan 23 17:32:09 2018" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1516735929557 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:05:09 " "Elapsed time: 00:05:09" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1516735929557 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:08:27 " "Total CPU time (on all processors): 00:08:27" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1516735929557 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Shell" 0 -1 1516735929557 ""}