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https://opencores.org/ocsvn/spacewiresystemc/spacewiresystemc/trunk
Subversion Repositories spacewiresystemc
[/] [spacewiresystemc/] [trunk/] [altera_work/] [spw_fifo_ulight/] [db/] [spw_fifo_ulight.sta.qmsg] - Rev 40
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{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1517799469419 ""}{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus Prime " "Running Quartus Prime TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 17.1.1 Internal Build 593 12/11/2017 SJ Lite Edition " "Version 17.1.1 Internal Build 593 12/11/2017 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1517799469450 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon Feb 5 00:57:45 2018 " "Processing started: Mon Feb 5 00:57:45 2018" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1517799469450 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1517799469450 ""}{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta spw_fifo_ulight -c spw_fifo_ulight " "Command: quartus_sta spw_fifo_ulight -c spw_fifo_ulight" { } { } 0 0 "Command: %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1517799469451 ""}{ "Info" "0" "" "qsta_default_script.tcl version: #3" { } { } 0 0 "qsta_default_script.tcl version: #3" 0 0 "TimeQuest Timing Analyzer" 0 0 1517799471769 ""}{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "TimeQuest Timing Analyzer" 0 -1 1517799473399 ""}{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "TimeQuest Timing Analyzer" 0 -1 1517799473399 ""}{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1517799473513 ""}{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1517799473513 ""}{ "Info" "ISTA_SDC_FOUND" "sdc/spw_fifo_ulight.out.sdc " "Reading SDC File: 'sdc/spw_fifo_ulight.out.sdc'" { } { } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "TimeQuest Timing Analyzer" 0 -1 1517799474925 ""}{ "Info" "ISTA_SDC_FOUND" "ulight_fifo/synthesis/submodules/altera_reset_controller.sdc " "Reading SDC File: 'ulight_fifo/synthesis/submodules/altera_reset_controller.sdc'" { } { } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "TimeQuest Timing Analyzer" 0 -1 1517799475012 ""}{ "Info" "ISTA_UNKNOWN_UNATE_EDGE_ASSUMED_POS" "" "The following timing edges are non-unate. TimeQuest will assume pos-unate behavior for these edges in the clock network." { { "Info" "ISTA_CLOCK_MGR_INFO" "Cell: A_SPW_TOP\|SPW\|RX\|comb from: dataf to: combout " "Cell: A_SPW_TOP\|SPW\|RX\|comb from: dataf to: combout" { } { } 0 332098 "%1!s!" 0 0 "Design Software" 0 -1 1517799475087 ""} { "Info" "ISTA_CLOCK_MGR_INFO" "Cell: m_x\|comb from: dataa to: combout " "Cell: m_x\|comb from: dataa to: combout" { } { } 0 332098 "%1!s!" 0 0 "Design Software" 0 -1 1517799475087 ""} { "Info" "ISTA_CLOCK_MGR_INFO" "From: u0\|hps_0\|fpga_interfaces\|hps2fpga\|clk to: ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces\|hps2fpga~FF_3457 " "From: u0\|hps_0\|fpga_interfaces\|hps2fpga\|clk to: ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces\|hps2fpga~FF_3457" { } { } 0 332098 "%1!s!" 0 0 "Design Software" 0 -1 1517799475087 ""} {"Info" "ISTA_CLOCK_MGR_INFO" "Cell: u0\|pll_0\|altera_pll_i\|cyclonev_pll\|counter\[0\].output_counter from: vco0ph\[0\] to: divclk " "Cell: u0\|pll_0\|altera_pll_i\|cyclonev_pll\|counter\[0\].output_counter from: vco0ph\[0\] to: divclk" { } { } 0 332098 "%1!s!" 0 0 "Design Software" 0 -1 1517799475087 ""} { "Info" "ISTA_CLOCK_MGR_INFO" "Cell: u0\|pll_0\|altera_pll_i\|cyclonev_pll\|fpll_0\|REFCLK_SELECT from: clkin\[0\] to: clkout " "Cell: u0\|pll_0\|altera_pll_i\|cyclonev_pll\|fpll_0\|REFCLK_SELECT from: clkin\[0\] to: clkout" { } { } 0 332098 "%1!s!" 0 0 "Design Software" 0 -1 1517799475087 ""} { "Info" "ISTA_CLOCK_MGR_INFO" "Cell: u0\|pll_0\|altera_pll_i\|cyclonev_pll\|fpll_0\|fpll from: refclkin to: fbclk " "Cell: u0\|pll_0\|altera_pll_i\|cyclonev_pll\|fpll_0\|fpll from: refclkin to: fbclk" { } { } 0 332098 "%1!s!" 0 0 "Design Software" 0 -1 1517799475087 ""} } { } 0 332097 "The following timing edges are non-unate. TimeQuest will assume pos-unate behavior for these edges in the clock network." 0 0 "TimeQuest Timing Analyzer" 0 -1 1517799475087 ""}{ "Info" "ISTA_IGNORED_CLOCK_UNCERTAINTY" "" "The following assignments are ignored by the derive_clock_uncertainty command" { } { } 0 332152 "The following assignments are ignored by the derive_clock_uncertainty command" 0 0 "TimeQuest Timing Analyzer" 0 -1 1517799480099 ""}{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "TimeQuest Timing Analyzer" 0 0 1517799485632 ""}{ "Info" "0" "" "Analyzing Slow 1100mV 85C Model" { } { } 0 0 "Analyzing Slow 1100mV 85C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1517799485658 ""}{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Design Software" 0 -1 1517799486065 ""} } { } 1 332148 "Timing requirements not met" 0 0 "TimeQuest Timing Analyzer" 0 -1 1517799486065 ""}{ "Info" "ISTA_WORST_CASE_SLACK" "setup -4.369 " "Worst-case setup slack is -4.369" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799486066 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799486066 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -4.369 -113.702 clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_reduced_i " " -4.369 -113.702 clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_reduced_i " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799486066 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.697 -1112.931 clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_100_reduced_i " " -3.697 -1112.931 clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_100_reduced_i " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799486066 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.138 -13.527 spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_fsm_m:tx_fsm\|tx_dout_e " " -3.138 -13.527 spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_fsm_m:tx_fsm\|tx_dout_e " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799486066 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.473 -27.460 u0\|pll_0\|altera_pll_i\|cyclonev_pll\|counter\[0\].output_counter\|divclk " " -2.473 -27.460 u0\|pll_0\|altera_pll_i\|cyclonev_pll\|counter\[0\].output_counter\|divclk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799486066 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.037 -45.867 din_a " " -2.037 -45.867 din_a " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799486066 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.110 -2.017 FPGA_CLK1_50 " " -1.110 -2.017 FPGA_CLK1_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799486066 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1517799486066 ""}{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.322 " "Worst-case hold slack is 0.322" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799486139 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799486139 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.322 0.000 FPGA_CLK1_50 " " 0.322 0.000 FPGA_CLK1_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799486139 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.336 0.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_reduced_i " " 0.336 0.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_reduced_i " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799486139 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.393 0.000 u0\|pll_0\|altera_pll_i\|cyclonev_pll\|counter\[0\].output_counter\|divclk " " 0.393 0.000 u0\|pll_0\|altera_pll_i\|cyclonev_pll\|counter\[0\].output_counter\|divclk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799486139 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.470 0.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_100_reduced_i " " 0.470 0.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_100_reduced_i " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799486139 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.547 0.000 din_a " " 0.547 0.000 din_a " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799486139 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.624 0.000 spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_fsm_m:tx_fsm\|tx_dout_e " " 0.624 0.000 spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_fsm_m:tx_fsm\|tx_dout_e " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799486139 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1517799486139 ""}{ "Info" "ISTA_WORST_CASE_SLACK" "recovery -0.289 " "Worst-case recovery slack is -0.289" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799486164 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799486164 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.289 -4.795 spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_fsm_m:tx_fsm\|tx_dout_e " " -0.289 -4.795 spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_fsm_m:tx_fsm\|tx_dout_e " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799486164 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 5.248 0.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_100_reduced_i " "5.248 0.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_100_reduced_i " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799486164 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 14.466 0.000 FPGA_CLK1_50 " " 14.466 0.000 FPGA_CLK1_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799486164 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1517799486164 ""}{ "Info" "ISTA_WORST_CASE_SLACK" "removal 0.563 " "Worst-case removal slack is 0.563" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799486188 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799486188 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.563 0.000 FPGA_CLK1_50 " " 0.563 0.000 FPGA_CLK1_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799486188 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 1.308 0.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_100_reduced_i " " 1.308 0.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_100_reduced_i " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799486188 ""} {"Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 1.746 0.000 spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_fsm_m:tx_fsm\|tx_dout_e " " 1.746 0.000 spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_fsm_m:tx_fsm\|tx_dout_e " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799486188 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1517799486188 ""}{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 0.533 " "Worst-case minimum pulse width slack is 0.533" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799486194 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799486194 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.533 0.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_reduced_i " " 0.533 0.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_reduced_i " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799486194 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.575 0.000 u0\|pll_0\|altera_pll_i\|cyclonev_pll\|counter\[0\].output_counter\|divclk " " 0.575 0.000 u0\|pll_0\|altera_pll_i\|cyclonev_pll\|counter\[0\].output_counter\|divclk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799486194 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.994 0.000 din_a " " 0.994 0.000 din_a " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799486194 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 1.250 0.000 u0\|pll_0\|altera_pll_i\|cyclonev_pll\|fpll_0\|fpll\|vcoph\[0\] " " 1.250 0.000 u0\|pll_0\|altera_pll_i\|cyclonev_pll\|fpll_0\|fpll\|vcoph\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799486194 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 1.301 0.000 spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_fsm_m:tx_fsm\|tx_dout_e " " 1.301 0.000 spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_fsm_m:tx_fsm\|tx_dout_e " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799486194 ""} { "Info""ISTA_CREATE_TIMING_SUMMARY_INFO" " 3.952 0.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_100_reduced_i " " 3.952 0.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_100_reduced_i " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799486194 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 9.195 0.000 FPGA_CLK1_50 " " 9.195 0.000 FPGA_CLK1_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799486194 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1517799486194 ""}{ "Info" "ISTA_REPORT_METASTABILITY_INFO" "Report Metastability: Found 49 synchronizer chains. " "Report Metastability: Found 49 synchronizer chains." { { "Info" "ISTA_REPORT_METASTABILITY_INFO" "The design MTBF is not calculated because there are no specified synchronizers in the design. " "The design MTBF is not calculated because there are no specified synchronizers in the design." { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1517799486396 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Number of Synchronizer Chains Found: 49 " "Number of Synchronizer Chains Found: 49" { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1517799486396 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Shortest Synchronizer Chain: 2 Registers " "Shortest Synchronizer Chain: 2 Registers" { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1517799486396 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Fraction of Chains for which MTBFs Could Not be Calculated: 1.000 " "Fraction of Chains for which MTBFs Could Not be Calculated: 1.000" { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1517799486396 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Worst Case Available Settling Time: 12.091 ns " "Worst Case Available Settling Time: 12.091 ns" { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1517799486396 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" " " "" { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1517799486396 ""} } { } 0 332114 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1517799486396 ""}{ "Info" "0" "" "Analyzing Slow 1100mV 0C Model" { } { } 0 0 "Analyzing Slow 1100mV 0C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1517799486609 ""}{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "TimeQuest Timing Analyzer" 0 -1 1517799486697 ""}{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "TimeQuest Timing Analyzer" 0 -1 1517799497651 ""}{ "Info" "ISTA_UNKNOWN_UNATE_EDGE_ASSUMED_POS" "" "The following timing edges are non-unate. TimeQuest will assume pos-unate behavior for these edges in the clock network." { { "Info" "ISTA_CLOCK_MGR_INFO" "Cell: A_SPW_TOP\|SPW\|RX\|comb from: dataf to: combout " "Cell: A_SPW_TOP\|SPW\|RX\|comb from: dataf to: combout" { } { } 0 332098 "%1!s!" 0 0 "Design Software" 0 -1 1517799498179 ""} { "Info" "ISTA_CLOCK_MGR_INFO" "Cell: m_x\|comb from: dataa to: combout " "Cell: m_x\|comb from: dataa to: combout" { } { } 0 332098 "%1!s!" 0 0 "Design Software" 0 -1 1517799498179 ""} { "Info" "ISTA_CLOCK_MGR_INFO" "From: u0\|hps_0\|fpga_interfaces\|hps2fpga\|clk to: ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces\|hps2fpga~FF_3457 " "From: u0\|hps_0\|fpga_interfaces\|hps2fpga\|clk to: ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces\|hps2fpga~FF_3457" { } { } 0 332098 "%1!s!" 0 0 "Design Software" 0 -1 1517799498179 ""} {"Info" "ISTA_CLOCK_MGR_INFO" "Cell: u0\|pll_0\|altera_pll_i\|cyclonev_pll\|counter\[0\].output_counter from: vco0ph\[0\] to: divclk " "Cell: u0\|pll_0\|altera_pll_i\|cyclonev_pll\|counter\[0\].output_counter from: vco0ph\[0\] to: divclk" { } { } 0 332098 "%1!s!" 0 0 "Design Software" 0 -1 1517799498179 ""} { "Info" "ISTA_CLOCK_MGR_INFO" "Cell: u0\|pll_0\|altera_pll_i\|cyclonev_pll\|fpll_0\|REFCLK_SELECT from: clkin\[0\] to: clkout " "Cell: u0\|pll_0\|altera_pll_i\|cyclonev_pll\|fpll_0\|REFCLK_SELECT from: clkin\[0\] to: clkout" { } { } 0 332098 "%1!s!" 0 0 "Design Software" 0 -1 1517799498179 ""} { "Info" "ISTA_CLOCK_MGR_INFO" "Cell: u0\|pll_0\|altera_pll_i\|cyclonev_pll\|fpll_0\|fpll from: refclkin to: fbclk " "Cell: u0\|pll_0\|altera_pll_i\|cyclonev_pll\|fpll_0\|fpll from: refclkin to: fbclk" { } { } 0 332098 "%1!s!" 0 0 "Design Software" 0 -1 1517799498179 ""} } { } 0 332097 "The following timing edges are non-unate. TimeQuest will assume pos-unate behavior for these edges in the clock network." 0 0 "TimeQuest Timing Analyzer" 0 -1 1517799498179 ""}{ "Info" "ISTA_IGNORED_CLOCK_UNCERTAINTY" "" "The following assignments are ignored by the derive_clock_uncertainty command" { } { } 0 332152 "The following assignments are ignored by the derive_clock_uncertainty command" 0 0 "TimeQuest Timing Analyzer" 0 -1 1517799503229 ""}{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Design Software" 0 -1 1517799509026 ""} } { } 1 332148 "Timing requirements not met" 0 0 "TimeQuest Timing Analyzer" 0 -1 1517799509026 ""}{ "Info" "ISTA_WORST_CASE_SLACK" "setup -4.207 " "Worst-case setup slack is -4.207" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799509027 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799509027 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -4.207 -109.829 clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_reduced_i " " -4.207 -109.829 clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_reduced_i " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799509027 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.461 -1038.103 clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_100_reduced_i " " -3.461 -1038.103 clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_100_reduced_i " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799509027 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.976 -12.650 spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_fsm_m:tx_fsm\|tx_dout_e " " -2.976 -12.650 spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_fsm_m:tx_fsm\|tx_dout_e " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799509027 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.359 -27.122 u0\|pll_0\|altera_pll_i\|cyclonev_pll\|counter\[0\].output_counter\|divclk " " -2.359 -27.122 u0\|pll_0\|altera_pll_i\|cyclonev_pll\|counter\[0\].output_counter\|divclk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799509027 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.919 -41.436 din_a " " -1.919 -41.436 din_a " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799509027 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.765 -1.140 FPGA_CLK1_50 " " -0.765 -1.140 FPGA_CLK1_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799509027 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1517799509027 ""}{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.211 " "Worst-case hold slack is 0.211" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799509091 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799509091 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.211 0.000 FPGA_CLK1_50 " " 0.211 0.000 FPGA_CLK1_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799509091 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.325 0.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_reduced_i " " 0.325 0.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_reduced_i " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799509091 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.388 0.000 u0\|pll_0\|altera_pll_i\|cyclonev_pll\|counter\[0\].output_counter\|divclk " " 0.388 0.000 u0\|pll_0\|altera_pll_i\|cyclonev_pll\|counter\[0\].output_counter\|divclk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799509091 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.478 0.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_100_reduced_i " " 0.478 0.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_100_reduced_i " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799509091 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.530 0.000 din_a " " 0.530 0.000 din_a " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799509091 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.599 0.000 spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_fsm_m:tx_fsm\|tx_dout_e " " 0.599 0.000 spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_fsm_m:tx_fsm\|tx_dout_e " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799509091 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1517799509091 ""}{ "Info" "ISTA_WORST_CASE_SLACK" "recovery -0.346 " "Worst-case recovery slack is -0.346" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799509113 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799509113 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.346 -5.707 spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_fsm_m:tx_fsm\|tx_dout_e " " -0.346 -5.707 spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_fsm_m:tx_fsm\|tx_dout_e " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799509113 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 5.377 0.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_100_reduced_i " "5.377 0.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_100_reduced_i " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799509113 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 14.772 0.000 FPGA_CLK1_50 " " 14.772 0.000 FPGA_CLK1_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799509113 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1517799509113 ""}{ "Info" "ISTA_WORST_CASE_SLACK" "removal 0.464 " "Worst-case removal slack is 0.464" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799509140 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799509140 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.464 0.000 FPGA_CLK1_50 " " 0.464 0.000 FPGA_CLK1_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799509140 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 1.288 0.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_100_reduced_i " " 1.288 0.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_100_reduced_i " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799509140 ""} {"Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 1.777 0.000 spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_fsm_m:tx_fsm\|tx_dout_e " " 1.777 0.000 spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_fsm_m:tx_fsm\|tx_dout_e " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799509140 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1517799509140 ""}{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 0.499 " "Worst-case minimum pulse width slack is 0.499" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799509146 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799509146 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.499 0.000 u0\|pll_0\|altera_pll_i\|cyclonev_pll\|counter\[0\].output_counter\|divclk " " 0.499 0.000 u0\|pll_0\|altera_pll_i\|cyclonev_pll\|counter\[0\].output_counter\|divclk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799509146 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.523 0.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_reduced_i " " 0.5230.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_reduced_i " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799509146 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.986 0.000 din_a " " 0.986 0.000 din_a " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799509146 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 1.250 0.000 u0\|pll_0\|altera_pll_i\|cyclonev_pll\|fpll_0\|fpll\|vcoph\[0\] " " 1.250 0.000 u0\|pll_0\|altera_pll_i\|cyclonev_pll\|fpll_0\|fpll\|vcoph\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799509146 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 1.324 0.000 spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_fsm_m:tx_fsm\|tx_dout_e " " 1.324 0.000 spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_fsm_m:tx_fsm\|tx_dout_e " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799509146 ""} { "Info""ISTA_CREATE_TIMING_SUMMARY_INFO" " 3.980 0.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_100_reduced_i " " 3.980 0.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_100_reduced_i " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799509146 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 9.277 0.000 FPGA_CLK1_50 " " 9.277 0.000 FPGA_CLK1_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799509146 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1517799509146 ""}{ "Info" "ISTA_REPORT_METASTABILITY_INFO" "Report Metastability: Found 49 synchronizer chains. " "Report Metastability: Found 49 synchronizer chains." { { "Info" "ISTA_REPORT_METASTABILITY_INFO" "The design MTBF is not calculated because there are no specified synchronizers in the design. " "The design MTBF is not calculated because there are no specified synchronizers in the design." { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1517799509251 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Number of Synchronizer Chains Found: 49 " "Number of Synchronizer Chains Found: 49" { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1517799509251 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Shortest Synchronizer Chain: 2 Registers " "Shortest Synchronizer Chain: 2 Registers" { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1517799509251 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Fraction of Chains for which MTBFs Could Not be Calculated: 1.000 " "Fraction of Chains for which MTBFs Could Not be Calculated: 1.000" { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1517799509251 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Worst Case Available Settling Time: 12.233 ns " "Worst Case Available Settling Time: 12.233 ns" { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1517799509251 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" " " "" { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1517799509251 ""} } { } 0 332114 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1517799509251 ""}{ "Info" "0" "" "Analyzing Fast 1100mV 85C Model" { } { } 0 0 "Analyzing Fast 1100mV 85C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1517799509304 ""}{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "TimeQuest Timing Analyzer" 0 -1 1517799509697 ""}{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "TimeQuest Timing Analyzer" 0 -1 1517799519796 ""}{ "Info" "ISTA_UNKNOWN_UNATE_EDGE_ASSUMED_POS" "" "The following timing edges are non-unate. TimeQuest will assume pos-unate behavior for these edges in the clock network." { { "Info" "ISTA_CLOCK_MGR_INFO" "Cell: A_SPW_TOP\|SPW\|RX\|comb from: dataf to: combout " "Cell: A_SPW_TOP\|SPW\|RX\|comb from: dataf to: combout" { } { } 0 332098 "%1!s!" 0 0 "Design Software" 0 -1 1517799520325 ""} { "Info" "ISTA_CLOCK_MGR_INFO" "Cell: m_x\|comb from: dataa to: combout " "Cell: m_x\|comb from: dataa to: combout" { } { } 0 332098 "%1!s!" 0 0 "Design Software" 0 -1 1517799520325 ""} { "Info" "ISTA_CLOCK_MGR_INFO" "From: u0\|hps_0\|fpga_interfaces\|hps2fpga\|clk to: ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces\|hps2fpga~FF_3457 " "From: u0\|hps_0\|fpga_interfaces\|hps2fpga\|clk to: ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces\|hps2fpga~FF_3457" { } { } 0 332098 "%1!s!" 0 0 "Design Software" 0 -1 1517799520325 ""} {"Info" "ISTA_CLOCK_MGR_INFO" "Cell: u0\|pll_0\|altera_pll_i\|cyclonev_pll\|counter\[0\].output_counter from: vco0ph\[0\] to: divclk " "Cell: u0\|pll_0\|altera_pll_i\|cyclonev_pll\|counter\[0\].output_counter from: vco0ph\[0\] to: divclk" { } { } 0 332098 "%1!s!" 0 0 "Design Software" 0 -1 1517799520325 ""} { "Info" "ISTA_CLOCK_MGR_INFO" "Cell: u0\|pll_0\|altera_pll_i\|cyclonev_pll\|fpll_0\|REFCLK_SELECT from: clkin\[0\] to: clkout " "Cell: u0\|pll_0\|altera_pll_i\|cyclonev_pll\|fpll_0\|REFCLK_SELECT from: clkin\[0\] to: clkout" { } { } 0 332098 "%1!s!" 0 0 "Design Software" 0 -1 1517799520325 ""} { "Info" "ISTA_CLOCK_MGR_INFO" "Cell: u0\|pll_0\|altera_pll_i\|cyclonev_pll\|fpll_0\|fpll from: refclkin to: fbclk " "Cell: u0\|pll_0\|altera_pll_i\|cyclonev_pll\|fpll_0\|fpll from: refclkin to: fbclk" { } { } 0 332098 "%1!s!" 0 0 "Design Software" 0 -1 1517799520325 ""} } { } 0 332097 "The following timing edges are non-unate. TimeQuest will assume pos-unate behavior for these edges in the clock network." 0 0 "TimeQuest Timing Analyzer" 0 -1 1517799520325 ""}{ "Info" "ISTA_IGNORED_CLOCK_UNCERTAINTY" "" "The following assignments are ignored by the derive_clock_uncertainty command" { } { } 0 332152 "The following assignments are ignored by the derive_clock_uncertainty command" 0 0 "TimeQuest Timing Analyzer" 0 -1 1517799525307 ""}{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Design Software" 0 -1 1517799530934 ""} } { } 1 332148 "Timing requirements not met" 0 0 "TimeQuest Timing Analyzer" 0 -1 1517799530934 ""}{ "Info" "ISTA_WORST_CASE_SLACK" "setup -2.086 " "Worst-case setup slack is -2.086" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799530935 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799530935 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.086 -3.029 spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_fsm_m:tx_fsm\|tx_dout_e " " -2.086 -3.029 spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_fsm_m:tx_fsm\|tx_dout_e " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799530935 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.935 -13.800 clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_reduced_i " " -1.935-13.800 clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_reduced_i " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799530935 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.826 -329.386 clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_100_reduced_i " " -1.826 -329.386 clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_100_reduced_i " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799530935 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.068 -12.429 din_a " " -1.068 -12.429 din_a " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799530935 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.558 -5.149 u0\|pll_0\|altera_pll_i\|cyclonev_pll\|counter\[0\].output_counter\|divclk " " -0.558 -5.149 u0\|pll_0\|altera_pll_i\|cyclonev_pll\|counter\[0\].output_counter\|divclk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799530935 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.405 -0.405 FPGA_CLK1_50 " " -0.405 -0.405 FPGA_CLK1_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799530935 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1517799530935 ""}{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.122 " "Worst-case hold slack is 0.122" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799531001 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799531001 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.122 0.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_reduced_i " " 0.122 0.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_reduced_i " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799531001 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.175 0.000 FPGA_CLK1_50 " " 0.175 0.000 FPGA_CLK1_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799531001 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.179 0.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_100_reduced_i " " 0.179 0.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_100_reduced_i " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799531001 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.217 0.000 u0\|pll_0\|altera_pll_i\|cyclonev_pll\|counter\[0\].output_counter\|divclk " " 0.217 0.000 u0\|pll_0\|altera_pll_i\|cyclonev_pll\|counter\[0\].output_counter\|divclk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799531001 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.242 0.000 din_a " " 0.242 0.000 din_a " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799531001 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.302 0.000 spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_fsm_m:tx_fsm\|tx_dout_e " " 0.302 0.000 spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_fsm_m:tx_fsm\|tx_dout_e " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799531001 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1517799531001 ""}{ "Info" "ISTA_WORST_CASE_SLACK" "recovery 0.648 " "Worst-case recovery slack is 0.648" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799531027 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799531027 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.648 0.000 spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_fsm_m:tx_fsm\|tx_dout_e " " 0.648 0.000 spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_fsm_m:tx_fsm\|tx_dout_e " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799531027 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 6.842 0.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_100_reduced_i " "6.842 0.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_100_reduced_i " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799531027 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 16.136 0.000 FPGA_CLK1_50 " " 16.136 0.000 FPGA_CLK1_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799531027 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1517799531027 ""}{ "Info" "ISTA_WORST_CASE_SLACK" "removal 0.424 " "Worst-case removal slack is 0.424" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799531055 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799531055 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.424 0.000 FPGA_CLK1_50 " " 0.424 0.000 FPGA_CLK1_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799531055 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.665 0.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_100_reduced_i " " 0.665 0.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_100_reduced_i " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799531055 ""} {"Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.750 0.000 spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_fsm_m:tx_fsm\|tx_dout_e " " 0.750 0.000 spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_fsm_m:tx_fsm\|tx_dout_e " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799531055 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1517799531055 ""}{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 0.732 " "Worst-case minimum pulse width slack is 0.732" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799531061 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799531061 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.732 0.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_reduced_i " " 0.732 0.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_reduced_i " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799531061 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.833 0.000 u0\|pll_0\|altera_pll_i\|cyclonev_pll\|counter\[0\].output_counter\|divclk " " 0.833 0.000 u0\|pll_0\|altera_pll_i\|cyclonev_pll\|counter\[0\].output_counter\|divclk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799531061 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 1.215 0.000 din_a " " 1.215 0.000 din_a " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799531061 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 1.250 0.000 u0\|pll_0\|altera_pll_i\|cyclonev_pll\|fpll_0\|fpll\|vcoph\[0\] " " 1.250 0.000 u0\|pll_0\|altera_pll_i\|cyclonev_pll\|fpll_0\|fpll\|vcoph\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799531061 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 1.480 0.000 spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_fsm_m:tx_fsm\|tx_dout_e " " 1.480 0.000 spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_fsm_m:tx_fsm\|tx_dout_e " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799531061 ""} { "Info""ISTA_CREATE_TIMING_SUMMARY_INFO" " 4.240 0.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_100_reduced_i " " 4.240 0.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_100_reduced_i " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799531061 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 9.073 0.000 FPGA_CLK1_50 " " 9.073 0.000 FPGA_CLK1_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799531061 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1517799531061 ""}{ "Info" "ISTA_REPORT_METASTABILITY_INFO" "Report Metastability: Found 49 synchronizer chains. " "Report Metastability: Found 49 synchronizer chains." { { "Info" "ISTA_REPORT_METASTABILITY_INFO" "The design MTBF is not calculated because there are no specified synchronizers in the design. " "The design MTBF is not calculated because there are no specified synchronizers in the design." { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1517799531167 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Number of Synchronizer Chains Found: 49 " "Number of Synchronizer Chains Found: 49" { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1517799531167 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Shortest Synchronizer Chain: 2 Registers " "Shortest Synchronizer Chain: 2 Registers" { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1517799531167 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Fraction of Chains for which MTBFs Could Not be Calculated: 1.000 " "Fraction of Chains for which MTBFs Could Not be Calculated: 1.000" { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1517799531167 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Worst Case Available Settling Time: 14.729 ns " "Worst Case Available Settling Time: 14.729 ns" { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1517799531167 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" " " "" { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1517799531167 ""} } { } 0 332114 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1517799531167 ""}{ "Info" "0" "" "Analyzing Fast 1100mV 0C Model" { } { } 0 0 "Analyzing Fast 1100mV 0C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1517799531222 ""}{ "Info" "ISTA_UNKNOWN_UNATE_EDGE_ASSUMED_POS" "" "The following timing edges are non-unate. TimeQuest will assume pos-unate behavior for these edges in the clock network." { { "Info" "ISTA_CLOCK_MGR_INFO" "Cell: A_SPW_TOP\|SPW\|RX\|comb from: dataf to: combout " "Cell: A_SPW_TOP\|SPW\|RX\|comb from: dataf to: combout" { } { } 0 332098 "%1!s!" 0 0 "Design Software" 0 -1 1517799531779 ""} { "Info" "ISTA_CLOCK_MGR_INFO" "Cell: m_x\|comb from: dataa to: combout " "Cell: m_x\|comb from: dataa to: combout" { } { } 0 332098 "%1!s!" 0 0 "Design Software" 0 -1 1517799531779 ""} { "Info" "ISTA_CLOCK_MGR_INFO" "From: u0\|hps_0\|fpga_interfaces\|hps2fpga\|clk to: ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces\|hps2fpga~FF_3457 " "From: u0\|hps_0\|fpga_interfaces\|hps2fpga\|clk to: ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces\|hps2fpga~FF_3457" { } { } 0 332098 "%1!s!" 0 0 "Design Software" 0 -1 1517799531779 ""} {"Info" "ISTA_CLOCK_MGR_INFO" "Cell: u0\|pll_0\|altera_pll_i\|cyclonev_pll\|counter\[0\].output_counter from: vco0ph\[0\] to: divclk " "Cell: u0\|pll_0\|altera_pll_i\|cyclonev_pll\|counter\[0\].output_counter from: vco0ph\[0\] to: divclk" { } { } 0 332098 "%1!s!" 0 0 "Design Software" 0 -1 1517799531779 ""} { "Info" "ISTA_CLOCK_MGR_INFO" "Cell: u0\|pll_0\|altera_pll_i\|cyclonev_pll\|fpll_0\|REFCLK_SELECT from: clkin\[0\] to: clkout " "Cell: u0\|pll_0\|altera_pll_i\|cyclonev_pll\|fpll_0\|REFCLK_SELECT from: clkin\[0\] to: clkout" { } { } 0 332098 "%1!s!" 0 0 "Design Software" 0 -1 1517799531779 ""} { "Info" "ISTA_CLOCK_MGR_INFO" "Cell: u0\|pll_0\|altera_pll_i\|cyclonev_pll\|fpll_0\|fpll from: refclkin to: fbclk " "Cell: u0\|pll_0\|altera_pll_i\|cyclonev_pll\|fpll_0\|fpll from: refclkin to: fbclk" { } { } 0 332098 "%1!s!" 0 0 "Design Software" 0 -1 1517799531779 ""} } { } 0 332097 "The following timing edges are non-unate. TimeQuest will assume pos-unate behavior for these edges in the clock network." 0 0 "TimeQuest Timing Analyzer" 0 -1 1517799531779 ""}{ "Info" "ISTA_IGNORED_CLOCK_UNCERTAINTY" "" "The following assignments are ignored by the derive_clock_uncertainty command" { } { } 0 332152 "The following assignments are ignored by the derive_clock_uncertainty command" 0 0 "TimeQuest Timing Analyzer" 0 -1 1517799536621 ""}{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Design Software" 0 -1 1517799542119 ""} } { } 1 332148 "Timing requirements not met" 0 0 "TimeQuest Timing Analyzer" 0 -1 1517799542119 ""}{ "Info" "ISTA_WORST_CASE_SLACK" "setup -1.794 " "Worst-case setup slack is -1.794" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799542120 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799542120 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.794 -2.071 spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_fsm_m:tx_fsm\|tx_dout_e " " -1.794 -2.071 spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_fsm_m:tx_fsm\|tx_dout_e " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799542120 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.717 -6.939 clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_reduced_i " " -1.717-6.939 clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_reduced_i " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799542120 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.507 -230.983 clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_100_reduced_i " " -1.507 -230.983 clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_100_reduced_i " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799542120 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.704 -5.641 din_a " " -0.704 -5.641 din_a " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799542120 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.395 -3.443 u0\|pll_0\|altera_pll_i\|cyclonev_pll\|counter\[0\].output_counter\|divclk " " -0.395 -3.443 u0\|pll_0\|altera_pll_i\|cyclonev_pll\|counter\[0\].output_counter\|divclk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799542120 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.113 -0.113 FPGA_CLK1_50 " " -0.113 -0.113 FPGA_CLK1_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799542120 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1517799542120 ""}{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.104 " "Worst-case hold slack is 0.104" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799542183 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799542183 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.104 0.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_reduced_i " " 0.104 0.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_reduced_i " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799542183 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.164 0.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_100_reduced_i " " 0.164 0.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_100_reduced_i " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799542183 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.166 0.000 FPGA_CLK1_50 " " 0.166 0.000 FPGA_CLK1_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799542183 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.199 0.000 u0\|pll_0\|altera_pll_i\|cyclonev_pll\|counter\[0\].output_counter\|divclk " " 0.199 0.000 u0\|pll_0\|altera_pll_i\|cyclonev_pll\|counter\[0\].output_counter\|divclk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799542183 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.208 0.000 din_a " " 0.208 0.000 din_a " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799542183 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.263 0.000 spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_fsm_m:tx_fsm\|tx_dout_e " " 0.263 0.000 spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_fsm_m:tx_fsm\|tx_dout_e " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799542183 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1517799542183 ""}{ "Info" "ISTA_WORST_CASE_SLACK" "recovery 0.654 " "Worst-case recovery slack is 0.654" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799542205 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799542205 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.654 0.000 spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_fsm_m:tx_fsm\|tx_dout_e " " 0.654 0.000 spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_fsm_m:tx_fsm\|tx_dout_e " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799542205 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 7.148 0.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_100_reduced_i " "7.148 0.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_100_reduced_i " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799542205 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 16.628 0.000 FPGA_CLK1_50 " " 16.628 0.000 FPGA_CLK1_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799542205 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1517799542205 ""}{ "Info" "ISTA_WORST_CASE_SLACK" "removal 0.327 " "Worst-case removal slack is 0.327" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799542234 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799542234 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.327 0.000 FPGA_CLK1_50 " " 0.327 0.000 FPGA_CLK1_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799542234 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.616 0.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_100_reduced_i " " 0.616 0.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_100_reduced_i " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799542234 ""} {"Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.684 0.000 spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_fsm_m:tx_fsm\|tx_dout_e " " 0.684 0.000 spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_fsm_m:tx_fsm\|tx_dout_e " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799542234 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1517799542234 ""}{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 0.757 " "Worst-case minimum pulse width slack is 0.757" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799542244 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799542244 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.757 0.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_reduced_i " " 0.757 0.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_reduced_i " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799542244 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.823 0.000 u0\|pll_0\|altera_pll_i\|cyclonev_pll\|counter\[0\].output_counter\|divclk " " 0.823 0.000 u0\|pll_0\|altera_pll_i\|cyclonev_pll\|counter\[0\].output_counter\|divclk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799542244 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 1.250 0.000 u0\|pll_0\|altera_pll_i\|cyclonev_pll\|fpll_0\|fpll\|vcoph\[0\] " " 1.250 0.000 u0\|pll_0\|altera_pll_i\|cyclonev_pll\|fpll_0\|fpll\|vcoph\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799542244 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 1.293 0.000 din_a " " 1.293 0.000 din_a " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799542244 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 1.525 0.000 spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_fsm_m:tx_fsm\|tx_dout_e " " 1.525 0.000 spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_fsm_m:tx_fsm\|tx_dout_e " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799542244 ""} { "Info""ISTA_CREATE_TIMING_SUMMARY_INFO" " 4.335 0.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_100_reduced_i " " 4.335 0.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_100_reduced_i " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799542244 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 9.039 0.000 FPGA_CLK1_50 " " 9.039 0.000 FPGA_CLK1_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799542244 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1517799542244 ""}{ "Info" "ISTA_REPORT_METASTABILITY_INFO" "Report Metastability: Found 49 synchronizer chains. " "Report Metastability: Found 49 synchronizer chains." { { "Info" "ISTA_REPORT_METASTABILITY_INFO" "The design MTBF is not calculated because there are no specified synchronizers in the design. " "The design MTBF is not calculated because there are no specified synchronizers in the design." { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1517799542362 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Number of Synchronizer Chains Found: 49 " "Number of Synchronizer Chains Found: 49" { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1517799542362 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Shortest Synchronizer Chain: 2 Registers " "Shortest Synchronizer Chain: 2 Registers" { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1517799542362 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Fraction of Chains for which MTBFs Could Not be Calculated: 1.000 " "Fraction of Chains for which MTBFs Could Not be Calculated: 1.000" { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1517799542362 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Worst Case Available Settling Time: 15.223 ns " "Worst Case Available Settling Time: 15.223 ns" { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1517799542362 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" " " "" { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1517799542362 ""} } { } 0 332114 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1517799542362 ""}{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "TimeQuest Timing Analyzer" 0 -1 1517799544068 ""}{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "TimeQuest Timing Analyzer" 0 -1 1517799544068 ""}{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 5 s Quartus Prime " "Quartus Prime TimeQuest Timing Analyzer was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "1444 " "Peak virtual memory: 1444 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1517799544184 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Feb 5 00:59:04 2018 " "Processing ended: Mon Feb 5 00:59:04 2018" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1517799544184 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:01:19 " "Elapsed time: 00:01:19" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1517799544184 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:01:24 " "Total CPU time (on all processors): 00:01:24" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1517799544184 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1517799544184 ""}