Subversion Repositories spacewiresystemc

{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1505474300667 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus Prime " "Running Quartus Prime TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 17.0.1 Build 598 06/07/2017 SJ Lite Edition " "Version 17.0.1 Build 598 06/07/2017 SJ Lite Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1505474300677 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Sep 15 08:18:16 2017 " "Processing started: Fri Sep 15 08:18:16 2017" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1505474300677 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1505474300677 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta spw_fifo_ulight -c spw_fifo_ulight " "Command: quartus_sta spw_fifo_ulight -c spw_fifo_ulight" {  } {  } 0 0 "Command: %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1505474300678 ""}
{ "Info" "0" "" "qsta_default_script.tcl version: #1" {  } {  } 0 0 "qsta_default_script.tcl version: #1" 0 0 "TimeQuest Timing Analyzer" 0 0 1505474300762 ""}
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "TimeQuest Timing Analyzer" 0 -1 1505474302382 ""}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "TimeQuest Timing Analyzer" 0 -1 1505474302382 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1505474302439 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1505474302439 ""}
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "TimeQuest Timing Analyzer" 0 -1 1505474302585 ""}
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "TimeQuest Timing Analyzer" 0 -1 1505474310743 ""}
{ "Info" "ISTA_SDC_FOUND" "sdc/spw_fifo_ulight.out.sdc " "Reading SDC File: 'sdc/spw_fifo_ulight.out.sdc'" {  } {  } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "TimeQuest Timing Analyzer" 0 -1 1505474311778 ""}
{ "Info" "ISTA_SDC_FOUND" "ulight_fifo/synthesis/submodules/altera_reset_controller.sdc " "Reading SDC File: 'ulight_fifo/synthesis/submodules/altera_reset_controller.sdc'" {  } {  } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "TimeQuest Timing Analyzer" 0 -1 1505474311869 ""}
{ "Info" "ISTA_UNKNOWN_UNATE_EDGE_ASSUMED_POS" "" "The following timing edges are non-unate.  TimeQuest will assume pos-unate behavior for these edges in the clock network." { { "Info" "ISTA_CLOCK_MGR_INFO" "Cell: A_SPW_TOP\|SPW\|RX\|always3~0  from: dataf  to: combout " "Cell: A_SPW_TOP\|SPW\|RX\|always3~0  from: dataf  to: combout" {  } {  } 0 332098 "%1!s!" 0 0 "Design Software" 0 -1 1505474311944 ""} { "Info" "ISTA_CLOCK_MGR_INFO" "Cell: m_x\|always3~0  from: dataf  to: combout " "Cell: m_x\|always3~0  from: dataf  to: combout" {  } {  } 0 332098 "%1!s!" 0 0 "Design Software" 0 -1 1505474311944 ""} { "Info" "ISTA_CLOCK_MGR_INFO" "From: u0\|hps_0\|fpga_interfaces\|hps2fpga\|clk  to: ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces\|hps2fpga~FF_3457 " "From: u0\|hps_0\|fpga_interfaces\|hps2fpga\|clk  to: ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces\|hps2fpga~FF_3457" {  } {  } 0 332098 "%1!s!" 0 0 "Design Software" 0 -1 1505474311944 ""} { "Info" "ISTA_CLOCK_MGR_INFO" "Cell: u0\|pll_0\|altera_pll_i\|cyclonev_pll\|counter\[0\].output_counter  from: vco0ph\[0\]  to: divclk " "Cell: u0\|pll_0\|altera_pll_i\|cyclonev_pll\|counter\[0\].output_counter  from: vco0ph\[0\]  to: divclk" {  } {  } 0 332098 "%1!s!" 0 0 "Design Software" 0 -1 1505474311944 ""} { "Info" "ISTA_CLOCK_MGR_INFO" "Cell: u0\|pll_0\|altera_pll_i\|cyclonev_pll\|fpll_0\|REFCLK_SELECT  from: clkin\[0\]  to: clkout " "Cell: u0\|pll_0\|altera_pll_i\|cyclonev_pll\|fpll_0\|REFCLK_SELECT  from: clkin\[0\]  to: clkout" {  } {  } 0 332098 "%1!s!" 0 0 "Design Software" 0 -1 1505474311944 ""} { "Info" "ISTA_CLOCK_MGR_INFO" "Cell: u0\|pll_0\|altera_pll_i\|cyclonev_pll\|fpll_0\|fpll  from: refclkin  to: fbclk " "Cell: u0\|pll_0\|altera_pll_i\|cyclonev_pll\|fpll_0\|fpll  from: refclkin  to: fbclk" {  } {  } 0 332098 "%1!s!" 0 0 "Design Software" 0 -1 1505474311944 ""}  } {  } 0 332097 "The following timing edges are non-unate.  TimeQuest will assume pos-unate behavior for these edges in the clock network." 0 0 "TimeQuest Timing Analyzer" 0 -1 1505474311944 ""}
{ "Info" "ISTA_IGNORED_CLOCK_UNCERTAINTY" "" "The following assignments are ignored by the derive_clock_uncertainty command" {  } {  } 0 332152 "The following assignments are ignored by the derive_clock_uncertainty command" 0 0 "TimeQuest Timing Analyzer" 0 -1 1505474312732 ""}
{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" {  } {  } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "TimeQuest Timing Analyzer" 0 0 1505474314242 ""}
{ "Info" "0" "" "Analyzing Slow 1100mV 85C Model" {  } {  } 0 0 "Analyzing Slow 1100mV 85C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1505474314279 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "setup 1.196 " "Worst-case setup slack is 1.196" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1505474314528 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1505474314528 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    1.196               0.000 FPGA_CLK1_50  " "    1.196               0.000 FPGA_CLK1_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1505474314528 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1505474314528 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.271 " "Worst-case hold slack is 0.271" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1505474314573 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1505474314573 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.271               0.000 FPGA_CLK1_50  " "    0.271               0.000 FPGA_CLK1_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1505474314573 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1505474314573 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "recovery 4.785 " "Worst-case recovery slack is 4.785" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1505474314595 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1505474314595 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    4.785               0.000 FPGA_CLK1_50  " "    4.785               0.000 FPGA_CLK1_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1505474314595 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1505474314595 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "removal 0.979 " "Worst-case removal slack is 0.979" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1505474314613 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1505474314613 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.979               0.000 FPGA_CLK1_50  " "    0.979               0.000 FPGA_CLK1_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1505474314613 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1505474314613 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 0.538 " "Worst-case minimum pulse width slack is 0.538" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1505474314618 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1505474314618 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.538               0.000 u0\|pll_0\|altera_pll_i\|cyclonev_pll\|counter\[0\].output_counter\|divclk  " "    0.538               0.000 u0\|pll_0\|altera_pll_i\|cyclonev_pll\|counter\[0\].output_counter\|divclk " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1505474314618 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.597               0.000 din_a  " "    0.597               0.000 din_a " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1505474314618 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.657               0.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_reduced_i  " "    0.657               0.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_reduced_i " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1505474314618 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.679               0.000 spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_dout_e  " "    0.679               0.000 spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_dout_e " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1505474314618 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    1.084               0.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_100_reduced_i  " "    1.084               0.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_100_reduced_i " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1505474314618 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    1.250               0.000 u0\|pll_0\|altera_pll_i\|cyclonev_pll\|fpll_0\|fpll\|vcoph\[0\]  " "    1.250               0.000 u0\|pll_0\|altera_pll_i\|cyclonev_pll\|fpll_0\|fpll\|vcoph\[0\] " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1505474314618 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    4.202               0.000 FPGA_CLK1_50  " "    4.202               0.000 FPGA_CLK1_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1505474314618 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1505474314618 ""}
{ "Info" "ISTA_REPORT_METASTABILITY_INFO" "Report Metastability: Found 59 synchronizer chains. " "Report Metastability: Found 59 synchronizer chains." { { "Info" "ISTA_REPORT_METASTABILITY_INFO" "The design MTBF is not calculated because there are no specified synchronizers in the design. " "The design MTBF is not calculated because there are no specified synchronizers in the design." {  } {  } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1505474314745 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Number of Synchronizer Chains Found: 59 " "Number of Synchronizer Chains Found: 59" {  } {  } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1505474314745 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Shortest Synchronizer Chain: 2 Registers " "Shortest Synchronizer Chain: 2 Registers" {  } {  } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1505474314745 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Fraction of Chains for which MTBFs Could Not be Calculated: 1.000 " "Fraction of Chains for which MTBFs Could Not be Calculated: 1.000" {  } {  } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1505474314745 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Worst Case Available Settling Time: 12.106 ns " "Worst Case Available Settling Time: 12.106 ns" {  } {  } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1505474314745 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" " " "" {  } {  } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1505474314745 ""}  } {  } 0 332114 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1505474314745 ""}
{ "Info" "0" "" "Analyzing Slow 1100mV 0C Model" {  } {  } 0 0 "Analyzing Slow 1100mV 0C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1505474314753 ""}
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "TimeQuest Timing Analyzer" 0 -1 1505474314901 ""}
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "TimeQuest Timing Analyzer" 0 -1 1505474322895 ""}
{ "Info" "ISTA_UNKNOWN_UNATE_EDGE_ASSUMED_POS" "" "The following timing edges are non-unate.  TimeQuest will assume pos-unate behavior for these edges in the clock network." { { "Info" "ISTA_CLOCK_MGR_INFO" "Cell: A_SPW_TOP\|SPW\|RX\|always3~0  from: dataf  to: combout " "Cell: A_SPW_TOP\|SPW\|RX\|always3~0  from: dataf  to: combout" {  } {  } 0 332098 "%1!s!" 0 0 "Design Software" 0 -1 1505474323422 ""} { "Info" "ISTA_CLOCK_MGR_INFO" "Cell: m_x\|always3~0  from: dataf  to: combout " "Cell: m_x\|always3~0  from: dataf  to: combout" {  } {  } 0 332098 "%1!s!" 0 0 "Design Software" 0 -1 1505474323422 ""} { "Info" "ISTA_CLOCK_MGR_INFO" "From: u0\|hps_0\|fpga_interfaces\|hps2fpga\|clk  to: ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces\|hps2fpga~FF_3457 " "From: u0\|hps_0\|fpga_interfaces\|hps2fpga\|clk  to: ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces\|hps2fpga~FF_3457" {  } {  } 0 332098 "%1!s!" 0 0 "Design Software" 0 -1 1505474323422 ""} { "Info" "ISTA_CLOCK_MGR_INFO" "Cell: u0\|pll_0\|altera_pll_i\|cyclonev_pll\|counter\[0\].output_counter  from: vco0ph\[0\]  to: divclk " "Cell: u0\|pll_0\|altera_pll_i\|cyclonev_pll\|counter\[0\].output_counter  from: vco0ph\[0\]  to: divclk" {  } {  } 0 332098 "%1!s!" 0 0 "Design Software" 0 -1 1505474323422 ""} { "Info" "ISTA_CLOCK_MGR_INFO" "Cell: u0\|pll_0\|altera_pll_i\|cyclonev_pll\|fpll_0\|REFCLK_SELECT  from: clkin\[0\]  to: clkout " "Cell: u0\|pll_0\|altera_pll_i\|cyclonev_pll\|fpll_0\|REFCLK_SELECT  from: clkin\[0\]  to: clkout" {  } {  } 0 332098 "%1!s!" 0 0 "Design Software" 0 -1 1505474323422 ""} { "Info" "ISTA_CLOCK_MGR_INFO" "Cell: u0\|pll_0\|altera_pll_i\|cyclonev_pll\|fpll_0\|fpll  from: refclkin  to: fbclk " "Cell: u0\|pll_0\|altera_pll_i\|cyclonev_pll\|fpll_0\|fpll  from: refclkin  to: fbclk" {  } {  } 0 332098 "%1!s!" 0 0 "Design Software" 0 -1 1505474323422 ""}  } {  } 0 332097 "The following timing edges are non-unate.  TimeQuest will assume pos-unate behavior for these edges in the clock network." 0 0 "TimeQuest Timing Analyzer" 0 -1 1505474323422 ""}
{ "Info" "ISTA_IGNORED_CLOCK_UNCERTAINTY" "" "The following assignments are ignored by the derive_clock_uncertainty command" {  } {  } 0 332152 "The following assignments are ignored by the derive_clock_uncertainty command" 0 0 "TimeQuest Timing Analyzer" 0 -1 1505474324158 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "setup 1.204 " "Worst-case setup slack is 1.204" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1505474325760 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1505474325760 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    1.204               0.000 FPGA_CLK1_50  " "    1.204               0.000 FPGA_CLK1_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1505474325760 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1505474325760 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.253 " "Worst-case hold slack is 0.253" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1505474325799 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1505474325799 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.253               0.000 FPGA_CLK1_50  " "    0.253               0.000 FPGA_CLK1_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1505474325799 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1505474325799 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "recovery 4.852 " "Worst-case recovery slack is 4.852" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1505474325813 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1505474325813 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    4.852               0.000 FPGA_CLK1_50  " "    4.852               0.000 FPGA_CLK1_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1505474325813 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1505474325813 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "removal 0.920 " "Worst-case removal slack is 0.920" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1505474325827 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1505474325827 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.920               0.000 FPGA_CLK1_50  " "    0.920               0.000 FPGA_CLK1_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1505474325827 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1505474325827 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 0.465 " "Worst-case minimum pulse width slack is 0.465" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1505474325834 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1505474325834 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.465               0.000 u0\|pll_0\|altera_pll_i\|cyclonev_pll\|counter\[0\].output_counter\|divclk  " "    0.465               0.000 u0\|pll_0\|altera_pll_i\|cyclonev_pll\|counter\[0\].output_counter\|divclk " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1505474325834 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.633               0.000 din_a  " "    0.633               0.000 din_a " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1505474325834 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.663               0.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_reduced_i  " "    0.663               0.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_reduced_i " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1505474325834 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.716               0.000 spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_dout_e  " "    0.716               0.000 spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_dout_e " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1505474325834 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    1.117               0.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_100_reduced_i  " "    1.117               0.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_100_reduced_i " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1505474325834 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    1.250               0.000 u0\|pll_0\|altera_pll_i\|cyclonev_pll\|fpll_0\|fpll\|vcoph\[0\]  " "    1.250               0.000 u0\|pll_0\|altera_pll_i\|cyclonev_pll\|fpll_0\|fpll\|vcoph\[0\] " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1505474325834 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    4.284               0.000 FPGA_CLK1_50  " "    4.284               0.000 FPGA_CLK1_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1505474325834 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1505474325834 ""}
{ "Info" "ISTA_REPORT_METASTABILITY_INFO" "Report Metastability: Found 59 synchronizer chains. " "Report Metastability: Found 59 synchronizer chains." { { "Info" "ISTA_REPORT_METASTABILITY_INFO" "The design MTBF is not calculated because there are no specified synchronizers in the design. " "The design MTBF is not calculated because there are no specified synchronizers in the design." {  } {  } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1505474325905 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Number of Synchronizer Chains Found: 59 " "Number of Synchronizer Chains Found: 59" {  } {  } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1505474325905 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Shortest Synchronizer Chain: 2 Registers " "Shortest Synchronizer Chain: 2 Registers" {  } {  } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1505474325905 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Fraction of Chains for which MTBFs Could Not be Calculated: 1.000 " "Fraction of Chains for which MTBFs Could Not be Calculated: 1.000" {  } {  } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1505474325905 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Worst Case Available Settling Time: 12.241 ns " "Worst Case Available Settling Time: 12.241 ns" {  } {  } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1505474325905 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" " " "" {  } {  } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1505474325905 ""}  } {  } 0 332114 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1505474325905 ""}
{ "Info" "0" "" "Analyzing Fast 1100mV 85C Model" {  } {  } 0 0 "Analyzing Fast 1100mV 85C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1505474325912 ""}
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "TimeQuest Timing Analyzer" 0 -1 1505474326188 ""}
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "TimeQuest Timing Analyzer" 0 -1 1505474334571 ""}
{ "Info" "ISTA_UNKNOWN_UNATE_EDGE_ASSUMED_POS" "" "The following timing edges are non-unate.  TimeQuest will assume pos-unate behavior for these edges in the clock network." { { "Info" "ISTA_CLOCK_MGR_INFO" "Cell: A_SPW_TOP\|SPW\|RX\|always3~0  from: dataf  to: combout " "Cell: A_SPW_TOP\|SPW\|RX\|always3~0  from: dataf  to: combout" {  } {  } 0 332098 "%1!s!" 0 0 "Design Software" 0 -1 1505474335087 ""} { "Info" "ISTA_CLOCK_MGR_INFO" "Cell: m_x\|always3~0  from: dataf  to: combout " "Cell: m_x\|always3~0  from: dataf  to: combout" {  } {  } 0 332098 "%1!s!" 0 0 "Design Software" 0 -1 1505474335087 ""} { "Info" "ISTA_CLOCK_MGR_INFO" "From: u0\|hps_0\|fpga_interfaces\|hps2fpga\|clk  to: ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces\|hps2fpga~FF_3457 " "From: u0\|hps_0\|fpga_interfaces\|hps2fpga\|clk  to: ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces\|hps2fpga~FF_3457" {  } {  } 0 332098 "%1!s!" 0 0 "Design Software" 0 -1 1505474335087 ""} { "Info" "ISTA_CLOCK_MGR_INFO" "Cell: u0\|pll_0\|altera_pll_i\|cyclonev_pll\|counter\[0\].output_counter  from: vco0ph\[0\]  to: divclk " "Cell: u0\|pll_0\|altera_pll_i\|cyclonev_pll\|counter\[0\].output_counter  from: vco0ph\[0\]  to: divclk" {  } {  } 0 332098 "%1!s!" 0 0 "Design Software" 0 -1 1505474335087 ""} { "Info" "ISTA_CLOCK_MGR_INFO" "Cell: u0\|pll_0\|altera_pll_i\|cyclonev_pll\|fpll_0\|REFCLK_SELECT  from: clkin\[0\]  to: clkout " "Cell: u0\|pll_0\|altera_pll_i\|cyclonev_pll\|fpll_0\|REFCLK_SELECT  from: clkin\[0\]  to: clkout" {  } {  } 0 332098 "%1!s!" 0 0 "Design Software" 0 -1 1505474335087 ""} { "Info" "ISTA_CLOCK_MGR_INFO" "Cell: u0\|pll_0\|altera_pll_i\|cyclonev_pll\|fpll_0\|fpll  from: refclkin  to: fbclk " "Cell: u0\|pll_0\|altera_pll_i\|cyclonev_pll\|fpll_0\|fpll  from: refclkin  to: fbclk" {  } {  } 0 332098 "%1!s!" 0 0 "Design Software" 0 -1 1505474335087 ""}  } {  } 0 332097 "The following timing edges are non-unate.  TimeQuest will assume pos-unate behavior for these edges in the clock network." 0 0 "TimeQuest Timing Analyzer" 0 -1 1505474335087 ""}
{ "Info" "ISTA_IGNORED_CLOCK_UNCERTAINTY" "" "The following assignments are ignored by the derive_clock_uncertainty command" {  } {  } 0 332152 "The following assignments are ignored by the derive_clock_uncertainty command" 0 0 "TimeQuest Timing Analyzer" 0 -1 1505474335856 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "setup 4.542 " "Worst-case setup slack is 4.542" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1505474337423 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1505474337423 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    4.542               0.000 FPGA_CLK1_50  " "    4.542               0.000 FPGA_CLK1_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1505474337423 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1505474337423 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.162 " "Worst-case hold slack is 0.162" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1505474337464 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1505474337464 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.162               0.000 FPGA_CLK1_50  " "    0.162               0.000 FPGA_CLK1_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1505474337464 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1505474337464 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "recovery 6.857 " "Worst-case recovery slack is 6.857" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1505474337482 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1505474337482 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    6.857               0.000 FPGA_CLK1_50  " "    6.857               0.000 FPGA_CLK1_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1505474337482 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1505474337482 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "removal 0.574 " "Worst-case removal slack is 0.574" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1505474337498 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1505474337498 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.574               0.000 FPGA_CLK1_50  " "    0.574               0.000 FPGA_CLK1_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1505474337498 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1505474337498 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 0.799 " "Worst-case minimum pulse width slack is 0.799" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1505474337504 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1505474337504 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.799               0.000 u0\|pll_0\|altera_pll_i\|cyclonev_pll\|counter\[0\].output_counter\|divclk  " "    0.799               0.000 u0\|pll_0\|altera_pll_i\|cyclonev_pll\|counter\[0\].output_counter\|divclk " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1505474337504 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.812               0.000 din_a  " "    0.812               0.000 din_a " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1505474337504 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.897               0.000 spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_dout_e  " "    0.897               0.000 spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_dout_e " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1505474337504 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.920               0.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_reduced_i  " "    0.920               0.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_reduced_i " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1505474337504 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    1.250               0.000 u0\|pll_0\|altera_pll_i\|cyclonev_pll\|fpll_0\|fpll\|vcoph\[0\]  " "    1.250               0.000 u0\|pll_0\|altera_pll_i\|cyclonev_pll\|fpll_0\|fpll\|vcoph\[0\] " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1505474337504 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    1.333               0.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_100_reduced_i  " "    1.333               0.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_100_reduced_i " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1505474337504 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    4.076               0.000 FPGA_CLK1_50  " "    4.076               0.000 FPGA_CLK1_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1505474337504 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1505474337504 ""}
{ "Info" "ISTA_REPORT_METASTABILITY_INFO" "Report Metastability: Found 59 synchronizer chains. " "Report Metastability: Found 59 synchronizer chains." { { "Info" "ISTA_REPORT_METASTABILITY_INFO" "The design MTBF is not calculated because there are no specified synchronizers in the design. " "The design MTBF is not calculated because there are no specified synchronizers in the design." {  } {  } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1505474337576 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Number of Synchronizer Chains Found: 59 " "Number of Synchronizer Chains Found: 59" {  } {  } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1505474337576 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Shortest Synchronizer Chain: 2 Registers " "Shortest Synchronizer Chain: 2 Registers" {  } {  } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1505474337576 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Fraction of Chains for which MTBFs Could Not be Calculated: 1.000 " "Fraction of Chains for which MTBFs Could Not be Calculated: 1.000" {  } {  } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1505474337576 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Worst Case Available Settling Time: 15.202 ns " "Worst Case Available Settling Time: 15.202 ns" {  } {  } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1505474337576 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" " " "" {  } {  } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1505474337576 ""}  } {  } 0 332114 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1505474337576 ""}
{ "Info" "0" "" "Analyzing Fast 1100mV 0C Model" {  } {  } 0 0 "Analyzing Fast 1100mV 0C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1505474337586 ""}
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "TimeQuest Timing Analyzer" 0 -1 1505474337830 ""}
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "TimeQuest Timing Analyzer" 0 -1 1505474345644 ""}
{ "Info" "ISTA_UNKNOWN_UNATE_EDGE_ASSUMED_POS" "" "The following timing edges are non-unate.  TimeQuest will assume pos-unate behavior for these edges in the clock network." { { "Info" "ISTA_CLOCK_MGR_INFO" "Cell: A_SPW_TOP\|SPW\|RX\|always3~0  from: dataf  to: combout " "Cell: A_SPW_TOP\|SPW\|RX\|always3~0  from: dataf  to: combout" {  } {  } 0 332098 "%1!s!" 0 0 "Design Software" 0 -1 1505474346174 ""} { "Info" "ISTA_CLOCK_MGR_INFO" "Cell: m_x\|always3~0  from: dataf  to: combout " "Cell: m_x\|always3~0  from: dataf  to: combout" {  } {  } 0 332098 "%1!s!" 0 0 "Design Software" 0 -1 1505474346174 ""} { "Info" "ISTA_CLOCK_MGR_INFO" "From: u0\|hps_0\|fpga_interfaces\|hps2fpga\|clk  to: ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces\|hps2fpga~FF_3457 " "From: u0\|hps_0\|fpga_interfaces\|hps2fpga\|clk  to: ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces\|hps2fpga~FF_3457" {  } {  } 0 332098 "%1!s!" 0 0 "Design Software" 0 -1 1505474346174 ""} { "Info" "ISTA_CLOCK_MGR_INFO" "Cell: u0\|pll_0\|altera_pll_i\|cyclonev_pll\|counter\[0\].output_counter  from: vco0ph\[0\]  to: divclk " "Cell: u0\|pll_0\|altera_pll_i\|cyclonev_pll\|counter\[0\].output_counter  from: vco0ph\[0\]  to: divclk" {  } {  } 0 332098 "%1!s!" 0 0 "Design Software" 0 -1 1505474346174 ""} { "Info" "ISTA_CLOCK_MGR_INFO" "Cell: u0\|pll_0\|altera_pll_i\|cyclonev_pll\|fpll_0\|REFCLK_SELECT  from: clkin\[0\]  to: clkout " "Cell: u0\|pll_0\|altera_pll_i\|cyclonev_pll\|fpll_0\|REFCLK_SELECT  from: clkin\[0\]  to: clkout" {  } {  } 0 332098 "%1!s!" 0 0 "Design Software" 0 -1 1505474346174 ""} { "Info" "ISTA_CLOCK_MGR_INFO" "Cell: u0\|pll_0\|altera_pll_i\|cyclonev_pll\|fpll_0\|fpll  from: refclkin  to: fbclk " "Cell: u0\|pll_0\|altera_pll_i\|cyclonev_pll\|fpll_0\|fpll  from: refclkin  to: fbclk" {  } {  } 0 332098 "%1!s!" 0 0 "Design Software" 0 -1 1505474346174 ""}  } {  } 0 332097 "The following timing edges are non-unate.  TimeQuest will assume pos-unate behavior for these edges in the clock network." 0 0 "TimeQuest Timing Analyzer" 0 -1 1505474346174 ""}
{ "Info" "ISTA_IGNORED_CLOCK_UNCERTAINTY" "" "The following assignments are ignored by the derive_clock_uncertainty command" {  } {  } 0 332152 "The following assignments are ignored by the derive_clock_uncertainty command" 0 0 "TimeQuest Timing Analyzer" 0 -1 1505474346947 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "setup 5.038 " "Worst-case setup slack is 5.038" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1505474348554 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1505474348554 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    5.038               0.000 FPGA_CLK1_50  " "    5.038               0.000 FPGA_CLK1_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1505474348554 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1505474348554 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.146 " "Worst-case hold slack is 0.146" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1505474348602 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1505474348602 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.146               0.000 FPGA_CLK1_50  " "    0.146               0.000 FPGA_CLK1_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1505474348602 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1505474348602 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "recovery 7.031 " "Worst-case recovery slack is 7.031" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1505474348616 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1505474348616 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    7.031               0.000 FPGA_CLK1_50  " "    7.031               0.000 FPGA_CLK1_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1505474348616 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1505474348616 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "removal 0.524 " "Worst-case removal slack is 0.524" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1505474348631 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1505474348631 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.524               0.000 FPGA_CLK1_50  " "    0.524               0.000 FPGA_CLK1_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1505474348631 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1505474348631 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 0.793 " "Worst-case minimum pulse width slack is 0.793" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1505474348637 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1505474348637 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.793               0.000 u0\|pll_0\|altera_pll_i\|cyclonev_pll\|counter\[0\].output_counter\|divclk  " "    0.793               0.000 u0\|pll_0\|altera_pll_i\|cyclonev_pll\|counter\[0\].output_counter\|divclk " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1505474348637 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.828               0.000 din_a  " "    0.828               0.000 din_a " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1505474348637 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.961               0.000 spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_dout_e  " "    0.961               0.000 spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_dout_e " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1505474348637 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.969               0.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_reduced_i  " "    0.969               0.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_reduced_i " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1505474348637 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    1.250               0.000 u0\|pll_0\|altera_pll_i\|cyclonev_pll\|fpll_0\|fpll\|vcoph\[0\]  " "    1.250               0.000 u0\|pll_0\|altera_pll_i\|cyclonev_pll\|fpll_0\|fpll\|vcoph\[0\] " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1505474348637 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    1.399               0.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_100_reduced_i  " "    1.399               0.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_100_reduced_i " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1505474348637 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    4.039               0.000 FPGA_CLK1_50  " "    4.039               0.000 FPGA_CLK1_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1505474348637 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1505474348637 ""}
{ "Info" "ISTA_REPORT_METASTABILITY_INFO" "Report Metastability: Found 59 synchronizer chains. " "Report Metastability: Found 59 synchronizer chains." { { "Info" "ISTA_REPORT_METASTABILITY_INFO" "The design MTBF is not calculated because there are no specified synchronizers in the design. " "The design MTBF is not calculated because there are no specified synchronizers in the design." {  } {  } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1505474348722 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Number of Synchronizer Chains Found: 59 " "Number of Synchronizer Chains Found: 59" {  } {  } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1505474348722 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Shortest Synchronizer Chain: 2 Registers " "Shortest Synchronizer Chain: 2 Registers" {  } {  } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1505474348722 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Fraction of Chains for which MTBFs Could Not be Calculated: 1.000 " "Fraction of Chains for which MTBFs Could Not be Calculated: 1.000" {  } {  } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1505474348722 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Worst Case Available Settling Time: 15.621 ns " "Worst Case Available Settling Time: 15.621 ns" {  } {  } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1505474348722 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" " " "" {  } {  } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1505474348722 ""}  } {  } 0 332114 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1505474348722 ""}
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "TimeQuest Timing Analyzer" 0 -1 1505474350120 ""}
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "TimeQuest Timing Analyzer" 0 -1 1505474350121 ""}
{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 1  Quartus Prime " "Quartus Prime TimeQuest Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "1351 " "Peak virtual memory: 1351 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1505474350295 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Sep 15 08:19:10 2017 " "Processing ended: Fri Sep 15 08:19:10 2017" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1505474350295 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:54 " "Elapsed time: 00:00:54" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1505474350295 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:01:15 " "Total CPU time (on all processors): 00:01:15" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1505474350295 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1505474350295 ""}