URL
https://opencores.org/ocsvn/spacewiresystemc/spacewiresystemc/trunk
Subversion Repositories spacewiresystemc
[/] [spacewiresystemc/] [trunk/] [altera_work/] [spw_fifo_ulight/] [output_files/] [spw_fifo_ulight.flow.rpt] - Rev 40
Compare with Previous | Blame | View Log
Flow report for spw_fifo_ulightMon Feb 5 00:59:12 2018Quartus Prime Version 17.1.1 Internal Build 593 12/11/2017 SJ Lite Edition---------------------; Table of Contents ;---------------------1. Legal Notice2. Flow Summary3. Flow Settings4. Flow Non-Default Global Settings5. Flow Elapsed Time6. Flow OS Summary7. Flow Log8. Flow Messages9. Flow Suppressed Messages----------------; Legal Notice ;----------------Copyright (C) 2017 Intel Corporation. All rights reserved.Your use of Intel Corporation's design tools, logic functionsand other software and tools, and its AMPP partner logicfunctions, and any output files from any of the foregoing(including device programming or simulation files), and anyassociated documentation or information are expressly subjectto the terms and conditions of the Intel Program LicenseSubscription Agreement, the Intel Quartus Prime License Agreement,the Intel FPGA IP License Agreement, or other applicable licenseagreement, including, without limitation, that your use is forthe sole purpose of programming logic devices manufactured byIntel and sold by Intel or its authorized distributors. Pleaserefer to the applicable agreement for further details.+----------------------------------------------------------------------------------------+; Flow Summary ;+---------------------------------+------------------------------------------------------+; Flow Status ; Successful - Mon Feb 5 00:59:12 2018 ;; Quartus Prime Version ; 17.1.1 Internal Build 593 12/11/2017 SJ Lite Edition ;; Revision Name ; spw_fifo_ulight ;; Top-level Entity Name ; SPW_ULIGHT_FIFO ;; Family ; Cyclone V ;; Device ; 5CSEMA4U23C6 ;; Timing Models ; Final ;; Logic utilization (in ALMs) ; 3,362 / 15,880 ( 21 % ) ;; Total registers ; 4633 ;; Total pins ; 19 / 314 ( 6 % ) ;; Total virtual pins ; 0 ;; Total block memory bits ; 0 / 2,764,800 ( 0 % ) ;; Total DSP Blocks ; 0 / 84 ( 0 % ) ;; Total HSSI RX PCSs ; 0 ;; Total HSSI PMA RX Deserializers ; 0 ;; Total HSSI TX PCSs ; 0 ;; Total HSSI PMA TX Serializers ; 0 ;; Total PLLs ; 1 / 5 ( 20 % ) ;; Total DLLs ; 0 / 4 ( 0 % ) ;+---------------------------------+------------------------------------------------------++-----------------------------------------+; Flow Settings ;+-------------------+---------------------+; Option ; Setting ;+-------------------+---------------------+; Start date & time ; 02/05/2018 00:47:03 ;; Main task ; Compilation ;; Revision Name ; spw_fifo_ulight ;+-------------------+---------------------++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Flow Non-Default Global Settings ;+---------------------------------------------------+---------------------------------------------------------------------------+--------------------+---------------------------------+-----------------------------------+; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ;+---------------------------------------------------+---------------------------------------------------------------------------+--------------------+---------------------------------+-----------------------------------+; ALLOW_REGISTER_DUPLICATION ; Off ; On ; -- ; -- ;; ALLOW_REGISTER_MERGING ; Off ; On ; -- ; -- ;; ALLOW_REGISTER_RETIMING ; Off ; On ; -- ; -- ;; ALLOW_SHIFT_REGISTER_MERGING_ACROSS_HIERARCHIES ; Off ; Auto ; -- ; -- ;; ALLOW_SYNCH_CTRL_USAGE ; Off ; On ; -- ; -- ;; ALM_REGISTER_PACKING_EFFORT ; High ; Medium ; -- ; -- ;; AUTO_DELAY_CHAINS_FOR_HIGH_FANOUT_INPUT_PINS ; On ; Off ; -- ; -- ;; AUTO_DSP_RECOGNITION ; Off ; On ; -- ; -- ;; AUTO_RAM_RECOGNITION ; Off ; On ; -- ; -- ;; AUTO_ROM_RECOGNITION ; Off ; On ; -- ; -- ;; AUTO_SHIFT_REGISTER_RECOGNITION ; Off ; Auto ; -- ; -- ;; BLOCK_RAM_TO_MLAB_CELL_CONVERSION ; Off ; On ; -- ; -- ;; COMPILER_SIGNATURE_ID ; 31032335263289.151779881804543 ; -- ; -- ; -- ;; DISABLE_REGISTER_MERGING_ACROSS_HIERARCHIES ; Off ; Auto ; -- ; -- ;; EDA_BOARD_DESIGN_SIGNAL_INTEGRITY_TOOL ; HSPICE (Signal Integrity) ; <None> ; -- ; -- ;; EDA_BOARD_DESIGN_TIMING_TOOL ; Stamp (Timing) ; <None> ; -- ; -- ;; EDA_INPUT_DATA_FORMAT ; Edif ; -- ; -- ; eda_design_synthesis ;; EDA_OUTPUT_DATA_FORMAT ; Stamp ; -- ; -- ; eda_board_design_timing ;; EDA_OUTPUT_DATA_FORMAT ; None ; -- ; -- ; eda_simulation ;; EDA_OUTPUT_DATA_FORMAT ; Hspice ; -- ; -- ; eda_board_design_signal_integrity ;; EDA_OUTPUT_DATA_FORMAT ; None ; -- ; -- ; eda_board_design_symbol ;; EDA_RUN_TOOL_AUTOMATICALLY ; Off ; -- ; -- ; eda_simulation ;; EDA_RUN_TOOL_AUTOMATICALLY ; Off ; -- ; -- ; eda_design_synthesis ;; EDA_TIME_SCALE ; 1 ps ; -- ; -- ; eda_simulation ;; ENABLE_SIGNALTAP ; Off ; -- ; -- ; -- ;; HPS_ISW_FILE ; ulight_fifo/synthesis/submodules/sequencer/sdram_io.pre.h ; -- ; ulight_fifo_hps_0_hps_io_border ; -- ;; HPS_ISW_FILE ; ulight_fifo/synthesis/submodules/sequencer/alt_types.pre.h ; -- ; ulight_fifo_hps_0_hps_io_border ; -- ;; HPS_ISW_FILE ; ulight_fifo/synthesis/submodules/sequencer/system.pre.h ; -- ; ulight_fifo_hps_0_hps_io_border ; -- ;; HPS_ISW_FILE ; ulight_fifo/synthesis/submodules/sequencer/sequencer.pre.c ; -- ; ulight_fifo_hps_0_hps_io_border ; -- ;; HPS_ISW_FILE ; ulight_fifo/synthesis/submodules/sequencer/sequencer.pre.h ; -- ; ulight_fifo_hps_0_hps_io_border ; -- ;; HPS_ISW_FILE ; ulight_fifo/synthesis/submodules/sequencer/tclrpt.pre.c ; -- ; ulight_fifo_hps_0_hps_io_border ; -- ;; HPS_ISW_FILE ; ulight_fifo/synthesis/submodules/sequencer/tclrpt.pre.h ; -- ; ulight_fifo_hps_0_hps_io_border ; -- ;; HPS_ISW_FILE ; ulight_fifo/synthesis/submodules/sequencer/sequencer_defines.pre.h ; -- ; ulight_fifo_hps_0_hps_io_border ; -- ;; HPS_ISW_FILE ; ulight_fifo/synthesis/submodules/sequencer/sequencer_auto_ac_init.pre.c ; -- ; ulight_fifo_hps_0_hps_io_border ; -- ;; HPS_ISW_FILE ; ulight_fifo/synthesis/submodules/sequencer/sequencer_auto_inst_init.pre.c ; -- ; ulight_fifo_hps_0_hps_io_border ; -- ;; HPS_ISW_FILE ; ulight_fifo/synthesis/submodules/sequencer/sequencer_auto.pre.h ; -- ; ulight_fifo_hps_0_hps_io_border ; -- ;; HPS_ISW_FILE ; ulight_fifo/synthesis/submodules/sequencer/emif.pre.xml ; -- ; ulight_fifo_hps_0_hps_io_border ; -- ;; HPS_ISW_FILE ; ulight_fifo/synthesis/submodules/hps.pre.xml ; -- ; ulight_fifo_hps_0_hps_io_border ; -- ;; HPS_PARTITION ; On ; -- ; ulight_fifo_hps_0_hps_io_border ; -- ;; INFER_RAMS_FROM_RAW_LOGIC ; Off ; On ; -- ; -- ;; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ;; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ;; MISC_FILE ; ulight_fifo/synthesis/../ulight_fifo.cmp ; -- ; -- ; -- ;; MISC_FILE ; ulight_fifo/synthesis/ulight_fifo_hps_0_hps.svd ; -- ; -- ; -- ;; MISC_FILE ; ulight_fifo/synthesis/../../ulight_fifo.qsys ; -- ; -- ; -- ;; MISC_FILE ; ulight_fifo/synthesis/submodules/sequencer/sdram_io.pre.h ; -- ; -- ; -- ;; MISC_FILE ; ulight_fifo/synthesis/submodules/sequencer/alt_types.pre.h ; -- ; -- ; -- ;; MISC_FILE ; ulight_fifo/synthesis/submodules/sequencer/system.pre.h ; -- ; -- ; -- ;; MISC_FILE ; ulight_fifo/synthesis/submodules/sequencer/sequencer.pre.c ; -- ; -- ; -- ;; MISC_FILE ; ulight_fifo/synthesis/submodules/sequencer/sequencer.pre.h ; -- ; -- ; -- ;; MISC_FILE ; ulight_fifo/synthesis/submodules/sequencer/tclrpt.pre.c ; -- ; -- ; -- ;; MISC_FILE ; ulight_fifo/synthesis/submodules/sequencer/tclrpt.pre.h ; -- ; -- ; -- ;; MISC_FILE ; ulight_fifo/synthesis/submodules/sequencer/sequencer_defines.pre.h ; -- ; -- ; -- ;; MISC_FILE ; ulight_fifo/synthesis/submodules/sequencer/sequencer_auto_ac_init.pre.c ; -- ; -- ; -- ;; MISC_FILE ; ulight_fifo/synthesis/submodules/sequencer/sequencer_auto_inst_init.pre.c ; -- ; -- ; -- ;; MISC_FILE ; ulight_fifo/synthesis/submodules/sequencer/sequencer_auto.pre.h ; -- ; -- ; -- ;; MISC_FILE ; ulight_fifo/synthesis/submodules/sequencer/emif.pre.xml ; -- ; -- ; -- ;; MISC_FILE ; ulight_fifo/synthesis/submodules/hps.pre.xml ; -- ; -- ; -- ;; MUX_RESTRUCTURE ; Off ; Auto ; -- ; -- ;; OPTIMIZATION_MODE ; High Performance Effort ; Balanced ; -- ; -- ;; OPTIMIZE_FOR_METASTABILITY ; Off ; On ; -- ; -- ;; OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING ; Pack All IO Registers ; Normal ; -- ; -- ;; OPTIMIZE_POWER_DURING_FITTING ; Extra effort ; Normal compilation ; -- ; -- ;; PARTITION_COLOR ; -- (Not supported for targeted family) ; -- ; SPW_ULIGHT_FIFO ; Top ;; PARTITION_FITTER_PRESERVATION_LEVEL ; -- (Not supported for targeted family) ; -- ; SPW_ULIGHT_FIFO ; Top ;; PARTITION_NETLIST_TYPE ; -- (Not supported for targeted family) ; -- ; SPW_ULIGHT_FIFO ; Top ;; PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING ; On ; Off ; -- ; -- ;; PHYSICAL_SYNTHESIS_COMBO_LOGIC ; On ; Off ; -- ; -- ;; PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA ; On ; Off ; -- ; -- ;; PHYSICAL_SYNTHESIS_EFFORT ; Extra ; Normal ; -- ; -- ;; PLACEMENT_EFFORT_MULTIPLIER ; 4.0 ; 1.0 ; -- ; -- ;; POWER_BOARD_THERMAL_MODEL ; None (CONSERVATIVE) ; -- ; -- ; -- ;; POWER_PRESET_COOLING_SOLUTION ; 23 MM HEAT SINK WITH 200 LFPM AIRFLOW ; -- ; -- ; -- ;; PROJECT_OUTPUT_DIRECTORY ; output_files ; -- ; -- ; -- ;; REMOVE_DUPLICATE_REGISTERS ; Off ; On ; -- ; -- ;; ROUTER_LCELL_INSERTION_AND_LOGIC_DUPLICATION ; Off ; Auto ; -- ; -- ;; ROUTER_REGISTER_DUPLICATION ; Off ; Auto ; -- ; -- ;; ROUTER_TIMING_OPTIMIZATION_LEVEL ; MAXIMUM ; Normal ; -- ; -- ;; SAFE_STATE_MACHINE ; On ; Off ; -- ; -- ;; SHIFT_REGISTER_RECOGNITION_ACLR_SIGNAL ; Off ; On ; -- ; -- ;; SLD_FILE ; ulight_fifo/synthesis/ulight_fifo.regmap ; -- ; -- ; -- ;; SLD_FILE ; ulight_fifo/synthesis/ulight_fifo.debuginfo ; -- ; -- ; -- ;; SLD_INFO ; QSYS_NAME ulight_fifo HAS_SOPCINFO 1 GENERATION_ID 1516735843 ; -- ; ulight_fifo ; -- ;; SOPCINFO_FILE ; ulight_fifo/synthesis/../../ulight_fifo.sopcinfo ; -- ; -- ; -- ;; STATE_MACHINE_PROCESSING ; One-Hot ; Auto ; -- ; -- ;; SYNTHESIS_ONLY_QIP ; On ; -- ; -- ; -- ;; SYNTH_GATED_CLOCK_CONVERSION ; On ; Off ; -- ; -- ;; SYNTH_PROTECT_SDC_CONSTRAINT ; On ; Off ; -- ; -- ;; SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM ; Off ; On ; -- ; -- ;; TOP_LEVEL_ENTITY ; SPW_ULIGHT_FIFO ; spw_fifo_ulight ; -- ; -- ;; USE_SIGNALTAP_FILE ; output_files/stp2.stp ; -- ; -- ; -- ;+---------------------------------------------------+---------------------------------------------------------------------------+--------------------+---------------------------------+-----------------------------------++-------------------------------------------------------------------------------------------------------------------------------+; Flow Elapsed Time ;+---------------------------+--------------+-------------------------+---------------------+------------------------------------+; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;+---------------------------+--------------+-------------------------+---------------------+------------------------------------+; Analysis & Synthesis ; 00:01:23 ; 1.3 ; 1287 MB ; 00:01:52 ;; Fitter ; 00:05:06 ; 1.1 ; 2473 MB ; 00:08:48 ;; Assembler ; 00:00:19 ; 1.0 ; 1044 MB ; 00:00:11 ;; TimeQuest Timing Analyzer ; 00:01:19 ; 1.2 ; 1444 MB ; 00:01:24 ;; EDA Netlist Writer ; 00:00:06 ; 1.0 ; 1244 MB ; 00:00:06 ;; Total ; 00:08:13 ; -- ; -- ; 00:12:21 ;+---------------------------+--------------+-------------------------+---------------------+------------------------------------++-----------------------------------------------------------------------------------------+; Flow OS Summary ;+---------------------------+------------------+------------+------------+----------------+; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ;+---------------------------+------------------+------------+------------+----------------+; Analysis & Synthesis ; linux-hjij.suse ; SUSE LINUX ; 42 ; x86_64 ;; Fitter ; linux-hjij.suse ; SUSE LINUX ; 42 ; x86_64 ;; Assembler ; linux-hjij.suse ; SUSE LINUX ; 42 ; x86_64 ;; TimeQuest Timing Analyzer ; linux-hjij.suse ; SUSE LINUX ; 42 ; x86_64 ;; EDA Netlist Writer ; linux-hjij.suse ; SUSE LINUX ; 42 ; x86_64 ;+---------------------------+------------------+------------+------------+----------------+------------; Flow Log ;------------quartus_map --read_settings_files=on --write_settings_files=off spw_fifo_ulight -c spw_fifo_ulightquartus_fit --read_settings_files=off --write_settings_files=off spw_fifo_ulight -c spw_fifo_ulightquartus_asm --read_settings_files=off --write_settings_files=off spw_fifo_ulight -c spw_fifo_ulightquartus_sta spw_fifo_ulight -c spw_fifo_ulightquartus_eda --read_settings_files=off --write_settings_files=off spw_fifo_ulight -c spw_fifo_ulight