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[/] [spacewiresystemc/] [trunk/] [altera_work/] [spw_fifo_ulight/] [output_files/] [spw_fifo_ulight.map.rpt] - Rev 40
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Analysis & Synthesis report for spw_fifo_ulightMon Feb 5 00:52:10 2018Quartus Prime Version 17.1.1 Internal Build 593 12/11/2017 SJ Lite Edition---------------------; Table of Contents ;---------------------1. Legal Notice2. Analysis & Synthesis Summary3. Analysis & Synthesis Settings4. Parallel Compilation5. Analysis & Synthesis Source Files Read6. Analysis & Synthesis Resource Usage Summary7. Analysis & Synthesis Resource Utilization by Entity8. Analysis & Synthesis IP Cores Summary9. State Machine - |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state10. State Machine - |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state11. State Machine - |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state12. State Machine - |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state13. State Machine - |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state14. State Machine - |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state15. State Machine - |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state16. State Machine - |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state17. State Machine - |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state18. State Machine - |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state19. State Machine - |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state20. State Machine - |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state21. State Machine - |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state22. State Machine - |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state23. State Machine - |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state24. State Machine - |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state25. State Machine - |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state26. State Machine - |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state27. State Machine - |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state28. State Machine - |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state29. State Machine - |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state30. State Machine - |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state31. State Machine - |SPW_ULIGHT_FIFO|detector_tokens:m_x|state_data_process32. State Machine - |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|state_open_slot33. State Machine - |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|state_data_write34. State Machine - |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|state_data_read35. State Machine - |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i|dps_extra_kick:dps_extra_inst|dps_current_state36. State Machine - |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|state_data_read37. State Machine - |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|state_tx38. State Machine - |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_send:tx_fct_snd|state_fct_send39. State Machine - |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_send:tx_fct_snd|state_fct_send_p40. State Machine - |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_counter:tx_fct_cnt|state_fct_p41. State Machine - |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|state_data_write42. State Machine - |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_counter:tx_fct_cnt|state_fct_receive43. State Machine - |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|state_fsm44. Registers Protected by Synthesis45. Registers Removed During Synthesis46. Removed Registers Triggering Further Register Optimizations47. General Register Statistics48. Inverted Register Statistics49. Multiplexer Restructuring Statistics (No Restructuring Performed)50. Source assignments for ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll51. Source assignments for ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p052. Source assignments for ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|altddio_out:clock_gen[0].umem_ck_pad53. Source assignments for ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|altddio_out:clock_gen[0].umem_ck_pad|ddio_out_uqe:auto_generated54. Source assignments for ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_altdqdqs:dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_acv_connect_to_hard_phy_cyclonev:altdq_dqs2_inst55. Source assignments for ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|altera_mem_if_hard_memory_controller_top_cyclonev:c056. Source assignments for ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|altera_mem_if_oct_cyclonev:oct57. Source assignments for ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|altera_mem_if_dll_cyclonev:dll58. Source assignments for ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i59. Source assignments for ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i|altera_pll_dps_lcell_comb:lcell_cntsel_int_060. Source assignments for ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i|altera_pll_dps_lcell_comb:lcell_cntsel_int_161. Source assignments for ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i|altera_pll_dps_lcell_comb:lcell_cntsel_int_262. Source assignments for ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i|altera_pll_dps_lcell_comb:lcell_cntsel_int_363. Source assignments for ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i|altera_pll_dps_lcell_comb:lcell_cntsel_int_464. Source assignments for ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_demux:cmd_demux65. Source assignments for ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_demux:cmd_demux_00166. Source assignments for ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux67. Source assignments for ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_00168. Source assignments for ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_00269. Source assignments for ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_00370. Source assignments for ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_00471. Source assignments for ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_00572. Source assignments for ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_00673. Source assignments for ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_00774. Source assignments for ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_00875. Source assignments for ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_00976. Source assignments for ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_01077. Source assignments for ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_01178. Source assignments for ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_01279. Source assignments for ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_01380. Source assignments for ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_01481. Source assignments for ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_01582. Source assignments for ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_01683. Source assignments for ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_01784. Source assignments for ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_01885. Source assignments for ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_01986. Source assignments for ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_02087. Source assignments for ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_02188. Source assignments for ulight_fifo:u0|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq189. Source assignments for ulight_fifo:u0|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_req_sync_uq190. Source assignments for ulight_fifo:u0|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq191. Source assignments for ulight_fifo:u0|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_req_sync_uq192. Source assignments for spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|rx_data_receive:rx_dtarcv93. Source assignments for spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_counter:tx_fct_cnt94. Source assignments for spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_send:tx_fct_snd95. Source assignments for spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data96. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_hps_0:hps_097. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll98. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p099. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy100. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_ldc:memphy_ldc101. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads102. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads103. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|hps_sdram_p0_acv_ldc:address_gen[0].acv_ac_ldc104. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|hps_sdram_p0_acv_ldc:address_gen[1].acv_ac_ldc105. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|hps_sdram_p0_acv_ldc:address_gen[2].acv_ac_ldc106. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|hps_sdram_p0_acv_ldc:address_gen[3].acv_ac_ldc107. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|hps_sdram_p0_acv_ldc:address_gen[4].acv_ac_ldc108. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|hps_sdram_p0_acv_ldc:address_gen[5].acv_ac_ldc109. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|hps_sdram_p0_acv_ldc:address_gen[6].acv_ac_ldc110. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|hps_sdram_p0_acv_ldc:address_gen[7].acv_ac_ldc111. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|hps_sdram_p0_acv_ldc:address_gen[8].acv_ac_ldc112. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|hps_sdram_p0_acv_ldc:address_gen[9].acv_ac_ldc113. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|hps_sdram_p0_acv_ldc:address_gen[10].acv_ac_ldc114. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|hps_sdram_p0_acv_ldc:address_gen[11].acv_ac_ldc115. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|hps_sdram_p0_acv_ldc:address_gen[12].acv_ac_ldc116. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|hps_sdram_p0_acv_ldc:address_gen[13].acv_ac_ldc117. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|hps_sdram_p0_acv_ldc:address_gen[14].acv_ac_ldc118. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|hps_sdram_p0_acv_ldc:address_gen[15].acv_ac_ldc119. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|hps_sdram_p0_acv_ldc:address_gen[16].acv_ac_ldc120. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|hps_sdram_p0_acv_ldc:address_gen[17].acv_ac_ldc121. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|hps_sdram_p0_acv_ldc:address_gen[18].acv_ac_ldc122. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|hps_sdram_p0_acv_ldc:address_gen[19].acv_ac_ldc123. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|hps_sdram_p0_acv_ldc:address_gen[20].acv_ac_ldc124. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|hps_sdram_p0_acv_ldc:address_gen[21].acv_ac_ldc125. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|hps_sdram_p0_acv_ldc:address_gen[22].acv_ac_ldc126. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|hps_sdram_p0_generic_ddio:uaddress_pad127. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|hps_sdram_p0_generic_ddio:ubank_pad128. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|hps_sdram_p0_generic_ddio:ucmd_pad129. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|hps_sdram_p0_generic_ddio:ureset_n_pad130. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|altddio_out:clock_gen[0].umem_ck_pad131. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_altdqdqs:dq_ddio[0].ubidir_dq_dqs132. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_altdqdqs:dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_acv_connect_to_hard_phy_cyclonev:altdq_dqs2_inst133. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|altera_mem_if_hhp_qseq_synth_top:seq134. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|altera_mem_if_hard_memory_controller_top_cyclonev:c0135. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|altera_mem_if_oct_cyclonev:oct136. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|altera_mem_if_dll_cyclonev:dll137. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i138. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:led_pio_test_s1_translator139. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_rx_s1_translator140. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_ready_rx_s1_translator141. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:data_flag_rx_s1_translator142. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:data_read_en_rx_s1_translator143. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_full_rx_status_s1_translator144. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_empty_rx_status_s1_translator145. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:link_start_s1_translator146. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:auto_start_s1_translator147. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:link_disable_s1_translator148. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:write_data_fifo_tx_s1_translator149. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:write_en_tx_s1_translator150. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_full_tx_status_s1_translator151. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_empty_tx_status_s1_translator152. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_data_s1_translator153. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_enable_s1_translator154. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_ready_s1_translator155. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:data_info_s1_translator156. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:clock_sel_s1_translator157. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fsm_info_s1_translator158. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:counter_tx_fifo_s1_translator159. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:counter_rx_fifo_s1_translator160. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_axi_master_ni:hps_0_h2f_axi_master_agent161. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_axi_master_ni:hps_0_h2f_axi_master_agent|altera_merlin_address_alignment:align_address_to_size162. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:led_pio_test_s1_agent163. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:led_pio_test_s1_agent|altera_merlin_burst_uncompressor:uncompressor164. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rsp_fifo165. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo166. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_rx_s1_agent167. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_rx_s1_agent|altera_merlin_burst_uncompressor:uncompressor168. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rsp_fifo169. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rdata_fifo170. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_ready_rx_s1_agent171. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_ready_rx_s1_agent|altera_merlin_burst_uncompressor:uncompressor172. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rsp_fifo173. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo174. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:data_flag_rx_s1_agent175. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:data_flag_rx_s1_agent|altera_merlin_burst_uncompressor:uncompressor176. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rsp_fifo177. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo178. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:data_read_en_rx_s1_agent179. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:data_read_en_rx_s1_agent|altera_merlin_burst_uncompressor:uncompressor180. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rsp_fifo181. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo182. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fifo_full_rx_status_s1_agent183. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fifo_full_rx_status_s1_agent|altera_merlin_burst_uncompressor:uncompressor184. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rsp_fifo185. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo186. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fifo_empty_rx_status_s1_agent187. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fifo_empty_rx_status_s1_agent|altera_merlin_burst_uncompressor:uncompressor188. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rsp_fifo189. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo190. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:link_start_s1_agent191. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:link_start_s1_agent|altera_merlin_burst_uncompressor:uncompressor192. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rsp_fifo193. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo194. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:auto_start_s1_agent195. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:auto_start_s1_agent|altera_merlin_burst_uncompressor:uncompressor196. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rsp_fifo197. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo198. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:link_disable_s1_agent199. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:link_disable_s1_agent|altera_merlin_burst_uncompressor:uncompressor200. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rsp_fifo201. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo202. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:write_data_fifo_tx_s1_agent203. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:write_data_fifo_tx_s1_agent|altera_merlin_burst_uncompressor:uncompressor204. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rsp_fifo205. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rdata_fifo206. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:write_en_tx_s1_agent207. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:write_en_tx_s1_agent|altera_merlin_burst_uncompressor:uncompressor208. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rsp_fifo209. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo210. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fifo_full_tx_status_s1_agent211. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fifo_full_tx_status_s1_agent|altera_merlin_burst_uncompressor:uncompressor212. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rsp_fifo213. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo214. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fifo_empty_tx_status_s1_agent215. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fifo_empty_tx_status_s1_agent|altera_merlin_burst_uncompressor:uncompressor216. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rsp_fifo217. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rdata_fifo218. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_tx_data_s1_agent219. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_tx_data_s1_agent|altera_merlin_burst_uncompressor:uncompressor220. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rsp_fifo221. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rdata_fifo222. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_tx_enable_s1_agent223. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_tx_enable_s1_agent|altera_merlin_burst_uncompressor:uncompressor224. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rsp_fifo225. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rdata_fifo226. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_tx_ready_s1_agent227. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_tx_ready_s1_agent|altera_merlin_burst_uncompressor:uncompressor228. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rsp_fifo229. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rdata_fifo230. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:data_info_s1_agent231. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:data_info_s1_agent|altera_merlin_burst_uncompressor:uncompressor232. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rsp_fifo233. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo234. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:clock_sel_s1_agent235. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:clock_sel_s1_agent|altera_merlin_burst_uncompressor:uncompressor236. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rsp_fifo237. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rdata_fifo238. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fsm_info_s1_agent239. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fsm_info_s1_agent|altera_merlin_burst_uncompressor:uncompressor240. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rsp_fifo241. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo242. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:counter_tx_fifo_s1_agent243. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:counter_tx_fifo_s1_agent|altera_merlin_burst_uncompressor:uncompressor244. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rsp_fifo245. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rdata_fifo246. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:counter_rx_fifo_s1_agent247. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:counter_rx_fifo_s1_agent|altera_merlin_burst_uncompressor:uncompressor248. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rsp_fifo249. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo250. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_router:router|ulight_fifo_mm_interconnect_0_router_default_decode:the_default_decode251. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_router:router_001|ulight_fifo_mm_interconnect_0_router_default_decode:the_default_decode252. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_router_002:router_002|ulight_fifo_mm_interconnect_0_router_002_default_decode:the_default_decode253. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_router_002:router_003|ulight_fifo_mm_interconnect_0_router_002_default_decode:the_default_decode254. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_router_002:router_004|ulight_fifo_mm_interconnect_0_router_002_default_decode:the_default_decode255. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_router_002:router_005|ulight_fifo_mm_interconnect_0_router_002_default_decode:the_default_decode256. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_router_002:router_006|ulight_fifo_mm_interconnect_0_router_002_default_decode:the_default_decode257. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_router_002:router_007|ulight_fifo_mm_interconnect_0_router_002_default_decode:the_default_decode258. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_router_002:router_008|ulight_fifo_mm_interconnect_0_router_002_default_decode:the_default_decode259. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_router_002:router_009|ulight_fifo_mm_interconnect_0_router_002_default_decode:the_default_decode260. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_router_002:router_010|ulight_fifo_mm_interconnect_0_router_002_default_decode:the_default_decode261. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_router_002:router_011|ulight_fifo_mm_interconnect_0_router_002_default_decode:the_default_decode262. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_router_002:router_012|ulight_fifo_mm_interconnect_0_router_002_default_decode:the_default_decode263. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_router_002:router_013|ulight_fifo_mm_interconnect_0_router_002_default_decode:the_default_decode264. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_router_002:router_014|ulight_fifo_mm_interconnect_0_router_002_default_decode:the_default_decode265. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_router_002:router_015|ulight_fifo_mm_interconnect_0_router_002_default_decode:the_default_decode266. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_router_002:router_016|ulight_fifo_mm_interconnect_0_router_002_default_decode:the_default_decode267. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_router_002:router_017|ulight_fifo_mm_interconnect_0_router_002_default_decode:the_default_decode268. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_router_002:router_018|ulight_fifo_mm_interconnect_0_router_002_default_decode:the_default_decode269. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_router_002:router_019|ulight_fifo_mm_interconnect_0_router_002_default_decode:the_default_decode270. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_router_002:router_020|ulight_fifo_mm_interconnect_0_router_002_default_decode:the_default_decode271. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_router_002:router_021|ulight_fifo_mm_interconnect_0_router_002_default_decode:the_default_decode272. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_router_002:router_022|ulight_fifo_mm_interconnect_0_router_002_default_decode:the_default_decode273. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_router_002:router_023|ulight_fifo_mm_interconnect_0_router_002_default_decode:the_default_decode274. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_traffic_limiter:hps_0_h2f_axi_master_wr_limiter275. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_traffic_limiter:hps_0_h2f_axi_master_rd_limiter276. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter277. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter278. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size279. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_burstwrap_increment:the_burstwrap_increment280. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min281. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ab_sub282. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ab_sub|altera_merlin_burst_adapter_adder:subtract283. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ac_sub284. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ac_sub|altera_merlin_burst_adapter_adder:subtract285. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:bc_sub286. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:bc_sub|altera_merlin_burst_adapter_adder:subtract287. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:da_sub288. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:da_sub|altera_merlin_burst_adapter_adder:subtract289. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:db_sub290. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:db_sub|altera_merlin_burst_adapter_adder:subtract291. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:dc_sub292. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:dc_sub|altera_merlin_burst_adapter_adder:subtract293. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter294. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter295. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size296. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_burstwrap_increment:the_burstwrap_increment297. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min298. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ab_sub299. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ab_sub|altera_merlin_burst_adapter_adder:subtract300. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ac_sub301. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ac_sub|altera_merlin_burst_adapter_adder:subtract302. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:bc_sub303. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:bc_sub|altera_merlin_burst_adapter_adder:subtract304. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:da_sub305. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:da_sub|altera_merlin_burst_adapter_adder:subtract306. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:db_sub307. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:db_sub|altera_merlin_burst_adapter_adder:subtract308. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:dc_sub309. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:dc_sub|altera_merlin_burst_adapter_adder:subtract310. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter311. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter312. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size313. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_burstwrap_increment:the_burstwrap_increment314. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min315. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ab_sub316. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ab_sub|altera_merlin_burst_adapter_adder:subtract317. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ac_sub318. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ac_sub|altera_merlin_burst_adapter_adder:subtract319. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:bc_sub320. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:bc_sub|altera_merlin_burst_adapter_adder:subtract321. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:da_sub322. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:da_sub|altera_merlin_burst_adapter_adder:subtract323. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:db_sub324. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:db_sub|altera_merlin_burst_adapter_adder:subtract325. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:dc_sub326. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:dc_sub|altera_merlin_burst_adapter_adder:subtract327. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter328. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter329. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size330. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_burstwrap_increment:the_burstwrap_increment331. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min332. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ab_sub333. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ab_sub|altera_merlin_burst_adapter_adder:subtract334. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ac_sub335. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ac_sub|altera_merlin_burst_adapter_adder:subtract336. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:bc_sub337. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:bc_sub|altera_merlin_burst_adapter_adder:subtract338. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:da_sub339. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:da_sub|altera_merlin_burst_adapter_adder:subtract340. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:db_sub341. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:db_sub|altera_merlin_burst_adapter_adder:subtract342. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:dc_sub343. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:dc_sub|altera_merlin_burst_adapter_adder:subtract344. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter345. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter346. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size347. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_burstwrap_increment:the_burstwrap_increment348. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min349. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ab_sub350. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ab_sub|altera_merlin_burst_adapter_adder:subtract351. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ac_sub352. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ac_sub|altera_merlin_burst_adapter_adder:subtract353. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:bc_sub354. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:bc_sub|altera_merlin_burst_adapter_adder:subtract355. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:da_sub356. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:da_sub|altera_merlin_burst_adapter_adder:subtract357. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:db_sub358. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:db_sub|altera_merlin_burst_adapter_adder:subtract359. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:dc_sub360. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:dc_sub|altera_merlin_burst_adapter_adder:subtract361. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter362. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter363. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size364. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_burstwrap_increment:the_burstwrap_increment365. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min366. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ab_sub367. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ab_sub|altera_merlin_burst_adapter_adder:subtract368. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ac_sub369. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ac_sub|altera_merlin_burst_adapter_adder:subtract370. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:bc_sub371. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:bc_sub|altera_merlin_burst_adapter_adder:subtract372. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:da_sub373. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:da_sub|altera_merlin_burst_adapter_adder:subtract374. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:db_sub375. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:db_sub|altera_merlin_burst_adapter_adder:subtract376. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:dc_sub377. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:dc_sub|altera_merlin_burst_adapter_adder:subtract378. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter379. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter380. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size381. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_burstwrap_increment:the_burstwrap_increment382. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min383. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ab_sub384. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ab_sub|altera_merlin_burst_adapter_adder:subtract385. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ac_sub386. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ac_sub|altera_merlin_burst_adapter_adder:subtract387. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:bc_sub388. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:bc_sub|altera_merlin_burst_adapter_adder:subtract389. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:da_sub390. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:da_sub|altera_merlin_burst_adapter_adder:subtract391. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:db_sub392. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:db_sub|altera_merlin_burst_adapter_adder:subtract393. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:dc_sub394. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:dc_sub|altera_merlin_burst_adapter_adder:subtract395. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter396. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter397. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size398. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_burstwrap_increment:the_burstwrap_increment399. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min400. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ab_sub401. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ab_sub|altera_merlin_burst_adapter_adder:subtract402. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ac_sub403. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ac_sub|altera_merlin_burst_adapter_adder:subtract404. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:bc_sub405. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:bc_sub|altera_merlin_burst_adapter_adder:subtract406. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:da_sub407. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:da_sub|altera_merlin_burst_adapter_adder:subtract408. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:db_sub409. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:db_sub|altera_merlin_burst_adapter_adder:subtract410. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:dc_sub411. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:dc_sub|altera_merlin_burst_adapter_adder:subtract412. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter413. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter414. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size415. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_burstwrap_increment:the_burstwrap_increment416. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min417. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ab_sub418. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ab_sub|altera_merlin_burst_adapter_adder:subtract419. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ac_sub420. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ac_sub|altera_merlin_burst_adapter_adder:subtract421. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:bc_sub422. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:bc_sub|altera_merlin_burst_adapter_adder:subtract423. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:da_sub424. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:da_sub|altera_merlin_burst_adapter_adder:subtract425. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:db_sub426. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:db_sub|altera_merlin_burst_adapter_adder:subtract427. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:dc_sub428. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:dc_sub|altera_merlin_burst_adapter_adder:subtract429. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter430. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter431. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size432. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_burstwrap_increment:the_burstwrap_increment433. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min434. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ab_sub435. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ab_sub|altera_merlin_burst_adapter_adder:subtract436. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ac_sub437. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ac_sub|altera_merlin_burst_adapter_adder:subtract438. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:bc_sub439. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:bc_sub|altera_merlin_burst_adapter_adder:subtract440. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:da_sub441. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:da_sub|altera_merlin_burst_adapter_adder:subtract442. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:db_sub443. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:db_sub|altera_merlin_burst_adapter_adder:subtract444. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:dc_sub445. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:dc_sub|altera_merlin_burst_adapter_adder:subtract446. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter447. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter448. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size449. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_burstwrap_increment:the_burstwrap_increment450. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min451. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ab_sub452. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ab_sub|altera_merlin_burst_adapter_adder:subtract453. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ac_sub454. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ac_sub|altera_merlin_burst_adapter_adder:subtract455. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:bc_sub456. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:bc_sub|altera_merlin_burst_adapter_adder:subtract457. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:da_sub458. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:da_sub|altera_merlin_burst_adapter_adder:subtract459. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:db_sub460. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:db_sub|altera_merlin_burst_adapter_adder:subtract461. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:dc_sub462. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:dc_sub|altera_merlin_burst_adapter_adder:subtract463. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter464. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter465. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size466. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_burstwrap_increment:the_burstwrap_increment467. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min468. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ab_sub469. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ab_sub|altera_merlin_burst_adapter_adder:subtract470. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ac_sub471. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ac_sub|altera_merlin_burst_adapter_adder:subtract472. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:bc_sub473. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:bc_sub|altera_merlin_burst_adapter_adder:subtract474. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:da_sub475. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:da_sub|altera_merlin_burst_adapter_adder:subtract476. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:db_sub477. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:db_sub|altera_merlin_burst_adapter_adder:subtract478. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:dc_sub479. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:dc_sub|altera_merlin_burst_adapter_adder:subtract480. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter481. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter482. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size483. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_burstwrap_increment:the_burstwrap_increment484. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min485. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ab_sub486. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ab_sub|altera_merlin_burst_adapter_adder:subtract487. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ac_sub488. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ac_sub|altera_merlin_burst_adapter_adder:subtract489. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:bc_sub490. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:bc_sub|altera_merlin_burst_adapter_adder:subtract491. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:da_sub492. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:da_sub|altera_merlin_burst_adapter_adder:subtract493. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:db_sub494. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:db_sub|altera_merlin_burst_adapter_adder:subtract495. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:dc_sub496. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:dc_sub|altera_merlin_burst_adapter_adder:subtract497. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter498. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter499. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size500. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_burstwrap_increment:the_burstwrap_increment501. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min502. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ab_sub503. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ab_sub|altera_merlin_burst_adapter_adder:subtract504. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ac_sub505. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ac_sub|altera_merlin_burst_adapter_adder:subtract506. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:bc_sub507. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:bc_sub|altera_merlin_burst_adapter_adder:subtract508. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:da_sub509. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:da_sub|altera_merlin_burst_adapter_adder:subtract510. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:db_sub511. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:db_sub|altera_merlin_burst_adapter_adder:subtract512. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:dc_sub513. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:dc_sub|altera_merlin_burst_adapter_adder:subtract514. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter515. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter516. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size517. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_burstwrap_increment:the_burstwrap_increment518. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min519. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ab_sub520. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ab_sub|altera_merlin_burst_adapter_adder:subtract521. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ac_sub522. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ac_sub|altera_merlin_burst_adapter_adder:subtract523. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:bc_sub524. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:bc_sub|altera_merlin_burst_adapter_adder:subtract525. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:da_sub526. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:da_sub|altera_merlin_burst_adapter_adder:subtract527. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:db_sub528. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:db_sub|altera_merlin_burst_adapter_adder:subtract529. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:dc_sub530. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:dc_sub|altera_merlin_burst_adapter_adder:subtract531. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter532. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter533. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size534. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_burstwrap_increment:the_burstwrap_increment535. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min536. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ab_sub537. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ab_sub|altera_merlin_burst_adapter_adder:subtract538. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ac_sub539. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ac_sub|altera_merlin_burst_adapter_adder:subtract540. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:bc_sub541. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:bc_sub|altera_merlin_burst_adapter_adder:subtract542. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:da_sub543. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:da_sub|altera_merlin_burst_adapter_adder:subtract544. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:db_sub545. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:db_sub|altera_merlin_burst_adapter_adder:subtract546. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:dc_sub547. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:dc_sub|altera_merlin_burst_adapter_adder:subtract548. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter549. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter550. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size551. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_burstwrap_increment:the_burstwrap_increment552. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min553. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ab_sub554. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ab_sub|altera_merlin_burst_adapter_adder:subtract555. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ac_sub556. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ac_sub|altera_merlin_burst_adapter_adder:subtract557. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:bc_sub558. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:bc_sub|altera_merlin_burst_adapter_adder:subtract559. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:da_sub560. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:da_sub|altera_merlin_burst_adapter_adder:subtract561. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:db_sub562. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:db_sub|altera_merlin_burst_adapter_adder:subtract563. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:dc_sub564. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:dc_sub|altera_merlin_burst_adapter_adder:subtract565. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter566. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter567. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size568. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_burstwrap_increment:the_burstwrap_increment569. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min570. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ab_sub571. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ab_sub|altera_merlin_burst_adapter_adder:subtract572. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ac_sub573. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ac_sub|altera_merlin_burst_adapter_adder:subtract574. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:bc_sub575. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:bc_sub|altera_merlin_burst_adapter_adder:subtract576. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:da_sub577. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:da_sub|altera_merlin_burst_adapter_adder:subtract578. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:db_sub579. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:db_sub|altera_merlin_burst_adapter_adder:subtract580. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:dc_sub581. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:dc_sub|altera_merlin_burst_adapter_adder:subtract582. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter583. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter584. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size585. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_burstwrap_increment:the_burstwrap_increment586. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min587. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ab_sub588. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ab_sub|altera_merlin_burst_adapter_adder:subtract589. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ac_sub590. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ac_sub|altera_merlin_burst_adapter_adder:subtract591. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:bc_sub592. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:bc_sub|altera_merlin_burst_adapter_adder:subtract593. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:da_sub594. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:da_sub|altera_merlin_burst_adapter_adder:subtract595. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:db_sub596. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:db_sub|altera_merlin_burst_adapter_adder:subtract597. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:dc_sub598. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:dc_sub|altera_merlin_burst_adapter_adder:subtract599. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter600. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter601. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size602. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_burstwrap_increment:the_burstwrap_increment603. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min604. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ab_sub605. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ab_sub|altera_merlin_burst_adapter_adder:subtract606. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ac_sub607. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ac_sub|altera_merlin_burst_adapter_adder:subtract608. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:bc_sub609. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:bc_sub|altera_merlin_burst_adapter_adder:subtract610. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:da_sub611. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:da_sub|altera_merlin_burst_adapter_adder:subtract612. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:db_sub613. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:db_sub|altera_merlin_burst_adapter_adder:subtract614. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:dc_sub615. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:dc_sub|altera_merlin_burst_adapter_adder:subtract616. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter617. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter618. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size619. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_burstwrap_increment:the_burstwrap_increment620. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min621. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ab_sub622. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ab_sub|altera_merlin_burst_adapter_adder:subtract623. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ac_sub624. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ac_sub|altera_merlin_burst_adapter_adder:subtract625. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:bc_sub626. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:bc_sub|altera_merlin_burst_adapter_adder:subtract627. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:da_sub628. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:da_sub|altera_merlin_burst_adapter_adder:subtract629. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:db_sub630. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:db_sub|altera_merlin_burst_adapter_adder:subtract631. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:dc_sub632. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:dc_sub|altera_merlin_burst_adapter_adder:subtract633. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter634. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter635. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size636. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_burstwrap_increment:the_burstwrap_increment637. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min638. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ab_sub639. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ab_sub|altera_merlin_burst_adapter_adder:subtract640. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ac_sub641. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ac_sub|altera_merlin_burst_adapter_adder:subtract642. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:bc_sub643. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:bc_sub|altera_merlin_burst_adapter_adder:subtract644. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:da_sub645. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:da_sub|altera_merlin_burst_adapter_adder:subtract646. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:db_sub647. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:db_sub|altera_merlin_burst_adapter_adder:subtract648. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:dc_sub649. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:dc_sub|altera_merlin_burst_adapter_adder:subtract650. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux|altera_merlin_arbitrator:arb651. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder652. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_001|altera_merlin_arbitrator:arb653. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_001|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder654. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_002|altera_merlin_arbitrator:arb655. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_002|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder656. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_003|altera_merlin_arbitrator:arb657. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_003|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder658. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_004|altera_merlin_arbitrator:arb659. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_004|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder660. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_005|altera_merlin_arbitrator:arb661. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_005|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder662. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_006|altera_merlin_arbitrator:arb663. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_006|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder664. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_007|altera_merlin_arbitrator:arb665. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_007|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder666. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_008|altera_merlin_arbitrator:arb667. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_008|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder668. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_009|altera_merlin_arbitrator:arb669. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_009|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder670. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_010|altera_merlin_arbitrator:arb671. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_010|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder672. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_011|altera_merlin_arbitrator:arb673. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_011|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder674. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_012|altera_merlin_arbitrator:arb675. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_012|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder676. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_013|altera_merlin_arbitrator:arb677. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_013|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder678. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_014|altera_merlin_arbitrator:arb679. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_014|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder680. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_015|altera_merlin_arbitrator:arb681. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_015|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder682. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_016|altera_merlin_arbitrator:arb683. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_016|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder684. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_017|altera_merlin_arbitrator:arb685. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_017|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder686. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_018|altera_merlin_arbitrator:arb687. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_018|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder688. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_019|altera_merlin_arbitrator:arb689. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_019|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder690. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_020|altera_merlin_arbitrator:arb691. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_020|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder692. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_021|altera_merlin_arbitrator:arb693. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_021|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder694. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_mux:rsp_mux|altera_merlin_arbitrator:arb695. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_mux:rsp_mux|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder696. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_mux:rsp_mux_001|altera_merlin_arbitrator:arb697. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_mux:rsp_mux_001|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder698. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter699. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_001700. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_002701. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_003702. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_004703. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_005704. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_006705. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_007706. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_008707. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_009708. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_010709. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_011710. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_012711. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_013712. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_014713. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_015714. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_016715. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_017716. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_018717. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_019718. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_020719. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_021720. Parameter Settings for User Entity Instance: ulight_fifo:u0|altera_reset_controller:rst_controller721. Parameter Settings for User Entity Instance: ulight_fifo:u0|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1722. Parameter Settings for User Entity Instance: ulight_fifo:u0|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_req_sync_uq1723. Parameter Settings for User Entity Instance: ulight_fifo:u0|altera_reset_controller:rst_controller_001724. Parameter Settings for User Entity Instance: ulight_fifo:u0|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1725. Parameter Settings for User Entity Instance: ulight_fifo:u0|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_req_sync_uq1726. Parameter Settings for User Entity Instance: spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data727. Parameter Settings for User Entity Instance: spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx728. Parameter Settings for User Entity Instance: spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data729. Parameter Settings for User Entity Instance: spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx730. Port Connectivity Checks: "detector_tokens:m_x|bit_capture_control:capture_c"731. Port Connectivity Checks: "detector_tokens:m_x|bit_capture_data:capture_d"732. Port Connectivity Checks: "ulight_fifo:u0|altera_reset_controller:rst_controller_001"733. Port Connectivity Checks: "ulight_fifo:u0|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_req_sync_uq1"734. Port Connectivity Checks: "ulight_fifo:u0|altera_reset_controller:rst_controller"735. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_mux:rsp_mux|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder"736. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder"737. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:dc_sub"738. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:db_sub"739. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:da_sub"740. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:bc_sub"741. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ac_sub"742. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ab_sub|altera_merlin_burst_adapter_adder:subtract"743. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ab_sub"744. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min"745. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size"746. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_router_002:router_002|ulight_fifo_mm_interconnect_0_router_002_default_decode:the_default_decode"747. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_router:router|ulight_fifo_mm_interconnect_0_router_default_decode:the_default_decode"748. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo"749. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rsp_fifo"750. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:counter_rx_fifo_s1_agent"751. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rdata_fifo"752. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rsp_fifo"753. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:counter_tx_fifo_s1_agent"754. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo"755. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rsp_fifo"756. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fsm_info_s1_agent"757. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rdata_fifo"758. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rsp_fifo"759. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:clock_sel_s1_agent"760. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo"761. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rsp_fifo"762. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:data_info_s1_agent"763. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rdata_fifo"764. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rsp_fifo"765. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_tx_ready_s1_agent"766. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rdata_fifo"767. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rsp_fifo"768. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_tx_enable_s1_agent"769. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rdata_fifo"770. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rsp_fifo"771. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_tx_data_s1_agent"772. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rdata_fifo"773. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rsp_fifo"774. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fifo_empty_tx_status_s1_agent"775. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo"776. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rsp_fifo"777. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fifo_full_tx_status_s1_agent"778. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo"779. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rsp_fifo"780. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:write_en_tx_s1_agent"781. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rdata_fifo"782. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rsp_fifo"783. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:write_data_fifo_tx_s1_agent"784. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo"785. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rsp_fifo"786. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:link_disable_s1_agent"787. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo"788. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rsp_fifo"789. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:auto_start_s1_agent"790. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo"791. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rsp_fifo"792. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:link_start_s1_agent"793. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo"794. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rsp_fifo"795. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fifo_empty_rx_status_s1_agent"796. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo"797. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rsp_fifo"798. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fifo_full_rx_status_s1_agent"799. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo"800. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rsp_fifo"801. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:data_read_en_rx_s1_agent"802. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo"803. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rsp_fifo"804. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:data_flag_rx_s1_agent"805. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo"806. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rsp_fifo"807. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_ready_rx_s1_agent"808. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rdata_fifo"809. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rsp_fifo"810. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_rx_s1_agent"811. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo"812. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rsp_fifo"813. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:led_pio_test_s1_agent"814. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_axi_master_ni:hps_0_h2f_axi_master_agent|altera_merlin_address_alignment:align_address_to_size"815. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_axi_master_ni:hps_0_h2f_axi_master_agent"816. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:counter_rx_fifo_s1_translator"817. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:counter_tx_fifo_s1_translator"818. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fsm_info_s1_translator"819. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:clock_sel_s1_translator"820. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:data_info_s1_translator"821. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_ready_s1_translator"822. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_enable_s1_translator"823. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_data_s1_translator"824. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_empty_tx_status_s1_translator"825. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_full_tx_status_s1_translator"826. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:write_en_tx_s1_translator"827. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:write_data_fifo_tx_s1_translator"828. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:link_disable_s1_translator"829. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:auto_start_s1_translator"830. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:link_start_s1_translator"831. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_empty_rx_status_s1_translator"832. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_full_rx_status_s1_translator"833. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:data_read_en_rx_s1_translator"834. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:data_flag_rx_s1_translator"835. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_ready_rx_s1_translator"836. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_rx_s1_translator"837. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:led_pio_test_s1_translator"838. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i"839. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_pll_0:pll_0"840. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|altera_mem_if_hard_memory_controller_top_cyclonev:c0"841. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_altdqdqs:dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_acv_connect_to_hard_phy_cyclonev:altdq_dqs2_inst"842. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_altdqdqs:dq_ddio[0].ubidir_dq_dqs"843. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|hps_sdram_p0_generic_ddio:ureset_n_pad"844. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|hps_sdram_p0_generic_ddio:ucmd_pad"845. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|hps_sdram_p0_generic_ddio:ubank_pad"846. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|hps_sdram_p0_generic_ddio:uaddress_pad"847. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|hps_sdram_p0_acv_ldc:address_gen[22].acv_ac_ldc"848. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|hps_sdram_p0_acv_ldc:address_gen[21].acv_ac_ldc"849. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|hps_sdram_p0_acv_ldc:address_gen[20].acv_ac_ldc"850. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|hps_sdram_p0_acv_ldc:address_gen[19].acv_ac_ldc"851. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|hps_sdram_p0_acv_ldc:address_gen[18].acv_ac_ldc"852. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|hps_sdram_p0_acv_ldc:address_gen[17].acv_ac_ldc"853. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|hps_sdram_p0_acv_ldc:address_gen[16].acv_ac_ldc"854. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|hps_sdram_p0_acv_ldc:address_gen[15].acv_ac_ldc"855. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|hps_sdram_p0_acv_ldc:address_gen[14].acv_ac_ldc"856. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|hps_sdram_p0_acv_ldc:address_gen[13].acv_ac_ldc"857. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|hps_sdram_p0_acv_ldc:address_gen[12].acv_ac_ldc"858. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|hps_sdram_p0_acv_ldc:address_gen[11].acv_ac_ldc"859. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|hps_sdram_p0_acv_ldc:address_gen[10].acv_ac_ldc"860. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|hps_sdram_p0_acv_ldc:address_gen[9].acv_ac_ldc"861. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|hps_sdram_p0_acv_ldc:address_gen[8].acv_ac_ldc"862. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|hps_sdram_p0_acv_ldc:address_gen[7].acv_ac_ldc"863. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|hps_sdram_p0_acv_ldc:address_gen[6].acv_ac_ldc"864. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|hps_sdram_p0_acv_ldc:address_gen[5].acv_ac_ldc"865. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|hps_sdram_p0_acv_ldc:address_gen[4].acv_ac_ldc"866. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|hps_sdram_p0_acv_ldc:address_gen[3].acv_ac_ldc"867. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|hps_sdram_p0_acv_ldc:address_gen[2].acv_ac_ldc"868. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|hps_sdram_p0_acv_ldc:address_gen[1].acv_ac_ldc"869. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|hps_sdram_p0_acv_ldc:address_gen[0].acv_ac_ldc"870. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads"871. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads"872. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_ldc:memphy_ldc"873. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0"874. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst"875. Port Connectivity Checks: "ulight_fifo:u0"876. Post-Synthesis Netlist Statistics for Top Partition877. Post-Synthesis Netlist Statistics for Partition ulight_fifo_hps_0_hps_io_border:border878. Elapsed Time Per Partition879. Analysis & Synthesis Messages880. Analysis & Synthesis Suppressed Messages----------------; Legal Notice ;----------------Copyright (C) 2017 Intel Corporation. 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Pleaserefer to the applicable agreement for further details.+----------------------------------------------------------------------------------------+; Analysis & Synthesis Summary ;+---------------------------------+------------------------------------------------------+; Analysis & Synthesis Status ; Successful - Mon Feb 5 00:52:09 2018 ;; Quartus Prime Version ; 17.1.1 Internal Build 593 12/11/2017 SJ Lite Edition ;; Revision Name ; spw_fifo_ulight ;; Top-level Entity Name ; SPW_ULIGHT_FIFO ;; Family ; Cyclone V ;; Logic utilization (in ALMs) ; N/A ;; Total registers ; 4628 ;; Total pins ; 15 ;; Total virtual pins ; 0 ;; Total block memory bits ; 0 ;; Total DSP Blocks ; 0 ;; Total HSSI RX PCSs ; 0 ;; Total HSSI PMA RX Deserializers ; 0 ;; Total HSSI TX PCSs ; 0 ;; Total HSSI PMA TX Serializers ; 0 ;; Total PLLs ; 1 ;; Total DLLs ; 0 ;+---------------------------------+------------------------------------------------------++---------------------------------------------------------------------------------------------------------------------------+; Analysis & Synthesis Settings ;+---------------------------------------------------------------------------------+--------------------+--------------------+; Option ; Setting ; Default Value ;+---------------------------------------------------------------------------------+--------------------+--------------------+; Device ; 5CSEMA4U23C6 ; ;; Top-level entity name ; SPW_ULIGHT_FIFO ; spw_fifo_ulight ;; Family name ; Cyclone V ; Cyclone V ;; Restructure Multiplexers ; Off ; Auto ;; State Machine Processing ; One-Hot ; Auto ;; Safe State Machine ; On ; Off ;; Infer RAMs from Raw Logic ; Off ; On ;; Remove Duplicate Registers ; Off ; On ;; Auto ROM Replacement ; Off ; On ;; Auto RAM Replacement ; Off ; On ;; Auto DSP Block Replacement ; Off ; On ;; Auto Shift Register Replacement ; Off ; Auto ;; Allow Shift Register Merging across Hierarchies ; Off ; Auto ;; Allow Synchronous Control Signals ; Off ; On ;; Auto Gated Clock Conversion ; On ; Off ;; SDC constraint protection ; On ; Off ;; Shift Register Replacement - Allow Asynchronous Clear Signal ; Off ; On ;; Disable Register Merging Across Hierarchies ; Off ; Auto ;; Resource Aware Inference For Block RAM ; Off ; On ;; Use smart compilation ; Off ; Off ;; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On ; On ;; Enable compact report table ; Off ; Off ;; MLAB Add Timing Constraints For Mixed-Port Feed-Through Mode Setting Don't Care ; Off ; Off ;; Create Debugging Nodes for IP Cores ; Off ; Off ;; Preserve fewer node names ; On ; On ;; Intel FPGA IP Evaluation Mode ; Enable ; Enable ;; Verilog Version ; Verilog_2001 ; Verilog_2001 ;; VHDL Version ; VHDL_1993 ; VHDL_1993 ;; Extract Verilog State Machines ; On ; On ;; Extract VHDL State Machines ; On ; On ;; Ignore Verilog initial constructs ; Off ; Off ;; Iteration limit for constant Verilog loops ; 5000 ; 5000 ;; Iteration limit for non-constant Verilog loops ; 250 ; 250 ;; Add Pass-Through Logic to Inferred RAMs ; On ; On ;; Parallel Synthesis ; On ; On ;; DSP Block Balancing ; Auto ; Auto ;; NOT Gate Push-Back ; On ; On ;; Power-Up Don't Care ; On ; On ;; Remove Redundant Logic Cells ; Off ; Off ;; Ignore CARRY Buffers ; Off ; Off ;; Ignore CASCADE Buffers ; Off ; Off ;; Ignore GLOBAL Buffers ; Off ; Off ;; Ignore ROW GLOBAL Buffers ; Off ; Off ;; Ignore LCELL Buffers ; Off ; Off ;; Ignore SOFT Buffers ; On ; On ;; Limit AHDL Integers to 32 Bits ; Off ; Off ;; Optimization Technique ; Balanced ; Balanced ;; Carry Chain Length ; 70 ; 70 ;; Auto Carry Chains ; On ; On ;; Auto Open-Drain Pins ; On ; On ;; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ;; Auto Clock Enable Replacement ; On ; On ;; Strict RAM Replacement ; Off ; Off ;; Force Use of Synchronous Clear Signals ; Off ; Off ;; Auto Resource Sharing ; Off ; Off ;; Allow Any RAM Size For Recognition ; Off ; Off ;; Allow Any ROM Size For Recognition ; Off ; Off ;; Allow Any Shift Register Size For Recognition ; Off ; Off ;; Use LogicLock Constraints during Resource Balancing ; On ; On ;; Ignore translate_off and synthesis_off directives ; Off ; Off ;; Timing-Driven Synthesis ; On ; On ;; Report Parameter Settings ; On ; On ;; Report Source Assignments ; On ; On ;; Report Connectivity Checks ; On ; On ;; Ignore Maximum Fan-Out Assignments ; Off ; Off ;; Synchronization Register Chain Length ; 3 ; 3 ;; Power Optimization During Synthesis ; Normal compilation ; Normal compilation ;; HDL message level ; Level2 ; Level2 ;; Suppress Register Optimization Related Messages ; Off ; Off ;; Number of Removed Registers Reported in Synthesis Report ; 5000 ; 5000 ;; Number of Swept Nodes Reported in Synthesis Report ; 5000 ; 5000 ;; Number of Inverted Registers Reported in Synthesis Report ; 100 ; 100 ;; Clock MUX Protection ; On ; On ;; Block Design Naming ; Auto ; Auto ;; Synthesis Effort ; Auto ; Auto ;; Pre-Mapping Resynthesis Optimization ; Off ; Off ;; Analysis & Synthesis Message Level ; Medium ; Medium ;; Automatic Parallel Synthesis ; On ; On ;; Partial Reconfiguration Bitstream ID ; Off ; Off ;+---------------------------------------------------------------------------------+--------------------+--------------------++------------------------------------------+; Parallel Compilation ;+----------------------------+-------------+; Processors ; Number ;+----------------------------+-------------+; Number detected on machine ; 4 ;; Maximum allowed ; 2 ;; ; ;; Average used ; 1.33 ;; Maximum used ; 2 ;; ; ;; Usage by Processor ; % Time Used ;; Processor 1 ; 100.0% ;; Processor 2 ; 32.8% ;+----------------------------+-------------++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Analysis & Synthesis Source Files Read ;+-----------------------------------------------------------------------------------------------------+-----------------+------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------+; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ;+-----------------------------------------------------------------------------------------------------+-----------------+------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------+; ../../rtl/RTL_VB/tx_fsm_m.v ; yes ; User Verilog HDL File ; /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/tx_fsm_m.v ; ;; ../../rtl/RTL_VB/tx_fct_send.v ; yes ; User Verilog HDL File ; /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/tx_fct_send.v ; ;; ../../rtl/RTL_VB/tx_fct_counter.v ; yes ; User Verilog HDL File ; /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/tx_fct_counter.v ; ;; ../../rtl/RTL_VB/tx_data_send.v ; yes ; User Verilog HDL File ; /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/tx_data_send.v ; ;; ../../rtl/RTL_VB/rx_data_receive.v ; yes ; User Verilog HDL File ; /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/rx_data_receive.v ; ;; ../../rtl/RTL_VB/rx_data_control_p.v ; yes ; User Verilog HDL File ; /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/rx_data_control_p.v ; ;; ../../rtl/RTL_VB/rx_data_buffer_data_w.v ; yes ; User Verilog HDL File ; /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/rx_data_buffer_data_w.v ; ;; ../../rtl/RTL_VB/rx_control_data_rdy.v ; yes ; User Verilog HDL File ; /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/rx_control_data_rdy.v ; ;; ../../rtl/RTL_VB/rx_buffer_fsm.v ; yes ; User Verilog HDL File ; /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/rx_buffer_fsm.v ; ;; ../../rtl/RTL_VB/mem_data.v ; yes ; User Verilog HDL File ; /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/mem_data.v ; ;; ../../rtl/RTL_VB/counter_neg.v ; yes ; User Verilog HDL File ; /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/counter_neg.v ; ;; ../../rtl/RTL_VB/bitc_capture_control.v ; yes ; User Verilog HDL File ; /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/bitc_capture_control.v ; ;; ../../rtl/RTL_VB/bit_capture_data.v ; yes ; User Verilog HDL File ; /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/bit_capture_data.v ; ;; ../../rtl/RTL_VB/tx_spw.v ; yes ; User Verilog HDL File ; /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/tx_spw.v ; ;; ../../rtl/RTL_VB/top_spw_ultra_light.v ; yes ; User Verilog HDL File ; /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/top_spw_ultra_light.v ; ;; ../../rtl/RTL_VB/spw_ulight_con_top_x.v ; yes ; User Verilog HDL File ; /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/spw_ulight_con_top_x.v ; ;; ../../rtl/RTL_VB/rx_spw.v ; yes ; User Verilog HDL File ; /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/rx_spw.v ; ;; ../../rtl/RTL_VB/fsm_spw.v ; yes ; User Verilog HDL File ; /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/fsm_spw.v ; ;; ../../rtl/RTL_VB/fifo_tx.v ; yes ; User Verilog HDL File ; /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/fifo_tx.v ; ;; ../../rtl/RTL_VB/fifo_rx.v ; yes ; User Verilog HDL File ; /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/fifo_rx.v ; ;; ../../rtl/DEBUG_VERILOG/debounce.v ; yes ; User Verilog HDL File ; /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/DEBUG_VERILOG/debounce.v ; ;; ../../rtl/DEBUG_VERILOG/detector_tokens.v ; yes ; User Verilog HDL File ; /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/DEBUG_VERILOG/detector_tokens.v ; ;; ../../rtl/DEBUG_VERILOG/clock_reduce.v ; yes ; User Verilog HDL File ; /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/DEBUG_VERILOG/clock_reduce.v ; ;; ulight_fifo/synthesis/ulight_fifo.v ; yes ; User Verilog HDL File ; /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/ulight_fifo.v ; ulight_fifo ;; ulight_fifo/synthesis/submodules/altera_reset_controller.v ; yes ; User Verilog HDL File ; /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_reset_controller.v ; ulight_fifo ;; ulight_fifo/synthesis/submodules/altera_reset_synchronizer.v ; yes ; User Verilog HDL File ; /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_reset_synchronizer.v ; ulight_fifo ;; ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0.v ; yes ; User Verilog HDL File ; /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0.v ; ulight_fifo ;; ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_avalon_st_adapter.v ; yes ; User Verilog HDL File ; /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_avalon_st_adapter.v ; ulight_fifo ;; ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_avalon_st_adapter_error_adapter_0.sv ; yes ; User SystemVerilog HDL File ; /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_avalon_st_adapter_error_adapter_0.sv ; ulight_fifo ;; ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_rsp_mux.sv ; yes ; User SystemVerilog HDL File ; /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_rsp_mux.sv ; ulight_fifo ;; ulight_fifo/synthesis/submodules/altera_merlin_arbitrator.sv ; yes ; User SystemVerilog HDL File ; /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_arbitrator.sv ; ulight_fifo ;; ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_rsp_demux.sv ; yes ; User SystemVerilog HDL File ; /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_rsp_demux.sv ; ulight_fifo ;; ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_cmd_mux.sv ; yes ; User SystemVerilog HDL File ; /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_cmd_mux.sv ; ulight_fifo ;; ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_cmd_demux.sv ; yes ; User SystemVerilog HDL File ; /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_cmd_demux.sv ; ulight_fifo ;; ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter.sv ; yes ; User SystemVerilog HDL File ; /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter.sv ; ulight_fifo ;; ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv ; yes ; User SystemVerilog HDL File ; /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv ; ulight_fifo ;; ulight_fifo/synthesis/submodules/altera_merlin_address_alignment.sv ; yes ; User SystemVerilog HDL File ; /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_address_alignment.sv ; ulight_fifo ;; ulight_fifo/synthesis/submodules/altera_merlin_traffic_limiter.sv ; yes ; User SystemVerilog HDL File ; /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_traffic_limiter.sv ; ulight_fifo ;; ulight_fifo/synthesis/submodules/altera_avalon_sc_fifo.v ; yes ; User SystemVerilog HDL File ; /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_avalon_sc_fifo.v ; ulight_fifo ;; ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_router_002.sv ; yes ; User SystemVerilog HDL File ; /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_router_002.sv ; ulight_fifo ;; ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_router.sv ; yes ; User SystemVerilog HDL File ; /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_router.sv ; ulight_fifo ;; ulight_fifo/synthesis/submodules/altera_merlin_slave_agent.sv ; yes ; User SystemVerilog HDL File ; /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_slave_agent.sv ; ulight_fifo ;; ulight_fifo/synthesis/submodules/altera_merlin_burst_uncompressor.sv ; yes ; User SystemVerilog HDL File ; /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_burst_uncompressor.sv ; ulight_fifo ;; ulight_fifo/synthesis/submodules/altera_merlin_axi_master_ni.sv ; yes ; User SystemVerilog HDL File ; /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_axi_master_ni.sv ; ulight_fifo ;; ulight_fifo/synthesis/submodules/altera_merlin_slave_translator.sv ; yes ; User SystemVerilog HDL File ; /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_slave_translator.sv ; ulight_fifo ;; ulight_fifo/synthesis/submodules/ulight_fifo_write_data_fifo_tx.v ; yes ; User Verilog HDL File ; /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_write_data_fifo_tx.v ; ulight_fifo ;; ulight_fifo/synthesis/submodules/ulight_fifo_timecode_tx_data.v ; yes ; User Verilog HDL File ; /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_timecode_tx_data.v ; ulight_fifo ;; ulight_fifo/synthesis/submodules/ulight_fifo_timecode_rx.v ; yes ; User Verilog HDL File ; /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_timecode_rx.v ; ulight_fifo ;; ulight_fifo/synthesis/submodules/ulight_fifo_pll_0.v ; yes ; User Verilog HDL File ; /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_pll_0.v ; ulight_fifo ;; ulight_fifo/synthesis/submodules/ulight_fifo_led_pio_test.v ; yes ; User Verilog HDL File ; /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_led_pio_test.v ; ulight_fifo ;; ulight_fifo/synthesis/submodules/ulight_fifo_hps_0.v ; yes ; User Verilog HDL File ; /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_hps_0.v ; ulight_fifo ;; ulight_fifo/synthesis/submodules/ulight_fifo_hps_0_hps_io.v ; yes ; User Verilog HDL File ; /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_hps_0_hps_io.v ; ulight_fifo ;; ulight_fifo/synthesis/submodules/hps_sdram.v ; yes ; User Verilog HDL File ; /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram.v ; ulight_fifo ;; ulight_fifo/synthesis/submodules/hps_sdram_pll.sv ; yes ; User SystemVerilog HDL File ; /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_pll.sv ; ulight_fifo ;; ulight_fifo/synthesis/submodules/hps_sdram_p0_clock_pair_generator.v ; yes ; User Verilog HDL File ; /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_clock_pair_generator.v ; ulight_fifo ;; ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_addr_cmd_pads.v ; yes ; User Verilog HDL File ; /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_addr_cmd_pads.v ; ulight_fifo ;; ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_memphy.v ; yes ; User Verilog HDL File ; /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_memphy.v ; ulight_fifo ;; ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_ldc.v ; yes ; User Verilog HDL File ; /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_ldc.v ; ulight_fifo ;; ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_io_pads.v ; yes ; User Verilog HDL File ; /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_io_pads.v ; ulight_fifo ;; ulight_fifo/synthesis/submodules/hps_sdram_p0_generic_ddio.v ; yes ; User Verilog HDL File ; /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_generic_ddio.v ; ulight_fifo ;; ulight_fifo/synthesis/submodules/hps_sdram_p0.sv ; yes ; User SystemVerilog HDL File ; /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0.sv ; ulight_fifo ;; ulight_fifo/synthesis/submodules/hps_sdram_p0_altdqdqs.v ; yes ; User Verilog HDL File ; /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_altdqdqs.v ; ulight_fifo ;; ulight_fifo/synthesis/submodules/altdq_dqs2_acv_connect_to_hard_phy_cyclonev.sv ; yes ; User SystemVerilog HDL File ; /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altdq_dqs2_acv_connect_to_hard_phy_cyclonev.sv ; ulight_fifo ;; ulight_fifo/synthesis/submodules/altera_mem_if_hhp_qseq_synth_top.v ; yes ; User Verilog HDL File ; /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_mem_if_hhp_qseq_synth_top.v ; ulight_fifo ;; ulight_fifo/synthesis/submodules/altera_mem_if_hard_memory_controller_top_cyclonev.sv ; yes ; User SystemVerilog HDL File ; /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_mem_if_hard_memory_controller_top_cyclonev.sv ; ulight_fifo ;; ulight_fifo/synthesis/submodules/altera_mem_if_oct_cyclonev.sv ; yes ; User SystemVerilog HDL File ; /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_mem_if_oct_cyclonev.sv ; ulight_fifo ;; ulight_fifo/synthesis/submodules/altera_mem_if_dll_cyclonev.sv ; yes ; User SystemVerilog HDL File ; /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_mem_if_dll_cyclonev.sv ; ulight_fifo ;; ulight_fifo/synthesis/submodules/ulight_fifo_hps_0_hps_io_border.sv ; yes ; User SystemVerilog HDL File ; /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_hps_0_hps_io_border.sv ; ulight_fifo ;; ulight_fifo/synthesis/submodules/ulight_fifo_hps_0_fpga_interfaces.sv ; yes ; User SystemVerilog HDL File ; /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_hps_0_fpga_interfaces.sv ; ulight_fifo ;; ulight_fifo/synthesis/submodules/ulight_fifo_fifo_empty_rx_status.v ; yes ; User Verilog HDL File ; /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_fifo_empty_rx_status.v ; ulight_fifo ;; ulight_fifo/synthesis/submodules/ulight_fifo_data_info.v ; yes ; User Verilog HDL File ; /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_data_info.v ; ulight_fifo ;; ulight_fifo/synthesis/submodules/ulight_fifo_data_flag_rx.v ; yes ; User Verilog HDL File ; /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_data_flag_rx.v ; ulight_fifo ;; ulight_fifo/synthesis/submodules/ulight_fifo_counter_rx_fifo.v ; yes ; User Verilog HDL File ; /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_counter_rx_fifo.v ; ulight_fifo ;; ulight_fifo/synthesis/submodules/ulight_fifo_clock_sel.v ; yes ; User Verilog HDL File ; /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_clock_sel.v ; ulight_fifo ;; ulight_fifo/synthesis/submodules/ulight_fifo_auto_start.v ; yes ; User Verilog HDL File ; /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_auto_start.v ; ulight_fifo ;; top_rtl/spw_fifo_ulight.v ; yes ; User Verilog HDL File ; /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/top_rtl/spw_fifo_ulight.v ; ;; altddio_out.tdf ; yes ; Megafunction ; /home/felipe/intelFPGA_lite/17.1/quartus/libraries/megafunctions/altddio_out.tdf ; ;; aglobal171.inc ; yes ; Megafunction ; /home/felipe/intelFPGA_lite/17.1/quartus/libraries/megafunctions/aglobal171.inc ; ;; stratix_ddio.inc ; yes ; Megafunction ; /home/felipe/intelFPGA_lite/17.1/quartus/libraries/megafunctions/stratix_ddio.inc ; ;; cyclone_ddio.inc ; yes ; Megafunction ; /home/felipe/intelFPGA_lite/17.1/quartus/libraries/megafunctions/cyclone_ddio.inc ; ;; lpm_mux.inc ; yes ; Megafunction ; /home/felipe/intelFPGA_lite/17.1/quartus/libraries/megafunctions/lpm_mux.inc ; ;; stratix_lcell.inc ; yes ; Megafunction ; /home/felipe/intelFPGA_lite/17.1/quartus/libraries/megafunctions/stratix_lcell.inc ; ;; db/ddio_out_uqe.tdf ; yes ; Auto-Generated Megafunction ; /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/db/ddio_out_uqe.tdf ; ;; altera_pll.v ; yes ; Megafunction ; /home/felipe/intelFPGA_lite/17.1/quartus/libraries/megafunctions/altera_pll.v ; ;; altera_pll_dps_lcell_comb.v ; yes ; Megafunction ; /home/felipe/intelFPGA_lite/17.1/quartus/libraries/megafunctions/altera_pll_dps_lcell_comb.v ; ;; altera_cyclonev_pll.v ; yes ; Megafunction ; /home/felipe/intelFPGA_lite/17.1/quartus/libraries/megafunctions/altera_cyclonev_pll.v ; ;+-----------------------------------------------------------------------------------------------------+-----------------+------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------++------------------------------------------------------------------+; Analysis & Synthesis Resource Usage Summary ;+---------------------------------------------+--------------------+; Resource ; Usage ;+---------------------------------------------+--------------------+; Estimate of Logic utilization (ALMs needed) ; 3510 ;; ; ;; Combinational ALUT usage for logic ; 5406 ;; -- 7 input functions ; 72 ;; -- 6 input functions ; 1282 ;; -- 5 input functions ; 907 ;; -- 4 input functions ; 1517 ;; -- <=3 input functions ; 1628 ;; ; ;; Dedicated logic registers ; 4628 ;; ; ;; I/O pins ; 15 ;; ; ;; Total DSP Blocks ; 0 ;; ; ;; Total PLLs ; 1 ;; -- Fractional PLLs ; 1 ;; ; ;; Maximum fan-out node ; FPGA_CLK1_50~input ;; Maximum fan-out ; 3069 ;; Total fan-out ; 39569 ;; Average fan-out ; 3.93 ;+---------------------------------------------+--------------------++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Analysis & Synthesis Resource Utilization by Entity ;+-----------------------------------------------------------------------------------------------+---------------------+---------------------------+-------------------+------------+------+--------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------+--------------+; Compilation Hierarchy Node ; Combinational ALUTs ; Dedicated Logic Registers ; Block Memory Bits ; DSP Blocks ; Pins ; Virtual Pins ; Full Hierarchy Name ; Entity Name ; Library Name ;+-----------------------------------------------------------------------------------------------+---------------------+---------------------------+-------------------+------------+------+--------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------+--------------+; |SPW_ULIGHT_FIFO ; 5406 (0) ; 4628 (0) ; 0 ; 0 ; 15 ; 0 ; |SPW_ULIGHT_FIFO ; SPW_ULIGHT_FIFO ; work ;; |clock_reduce:R_400_to_2_5_10_100_200_300MHZ| ; 175 (175) ; 24 (24) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|clock_reduce:R_400_to_2_5_10_100_200_300MHZ ; clock_reduce ; work ;; |debounce_db:db_system_spwulight_b| ; 37 (37) ; 18 (18) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|debounce_db:db_system_spwulight_b ; debounce_db ; work ;; |detector_tokens:m_x| ; 27 (17) ; 38 (16) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|detector_tokens:m_x ; detector_tokens ; work ;; |bit_capture_control:capture_c| ; 0 (0) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|detector_tokens:m_x|bit_capture_control:capture_c ; bit_capture_control ; work ;; |bit_capture_data:capture_d| ; 0 (0) ; 10 (10) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|detector_tokens:m_x|bit_capture_data:capture_d ; bit_capture_data ; work ;; |counter_neg:cnt_neg| ; 10 (10) ; 8 (8) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|detector_tokens:m_x|counter_neg:cnt_neg ; counter_neg ; work ;; |spw_ulight_con_top_x:A_SPW_TOP| ; 1025 (1) ; 1499 (0) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP ; spw_ulight_con_top_x ; work ;; |fifo_rx:rx_data| ; 340 (87) ; 633 (48) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data ; fifo_rx ; work ;; |mem_data:mem_dta_fifo_tx| ; 253 (253) ; 585 (585) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx ; mem_data ; work ;; |fifo_tx:tx_data| ; 299 (46) ; 627 (42) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data ; fifo_tx ; work ;; |mem_data:mem_dta_fifo_tx| ; 253 (253) ; 585 (585) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx ; mem_data ; work ;; |top_spw_ultra_light:SPW| ; 385 (0) ; 239 (0) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW ; top_spw_ultra_light ; work ;; |FSM_SPW:FSM| ; 118 (118) ; 59 (59) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM ; FSM_SPW ; work ;; |RX_SPW:RX| ; 60 (2) ; 75 (1) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX ; RX_SPW ; work ;; |bit_capture_control:capture_c| ; 0 (0) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|bit_capture_control:capture_c ; bit_capture_control ; work ;; |bit_capture_data:capture_d| ; 0 (0) ; 10 (10) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|bit_capture_data:capture_d ; bit_capture_data ; work ;; |counter_neg:cnt_neg| ; 12 (12) ; 8 (8) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|counter_neg:cnt_neg ; counter_neg ; work ;; |rx_buffer_fsm:buffer_fsm| ; 2 (2) ; 3 (3) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|rx_buffer_fsm:buffer_fsm ; rx_buffer_fsm ; work ;; |rx_control_data_rdy:control_data_rdy| ; 4 (4) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|rx_control_data_rdy:control_data_rdy ; rx_control_data_rdy ; work ;; |rx_data_buffer_data_w:buffer_data_flag| ; 3 (3) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|rx_data_buffer_data_w:buffer_data_flag ; rx_data_buffer_data_w ; work ;; |rx_data_control_p:data_control| ; 9 (9) ; 19 (19) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|rx_data_control_p:data_control ; rx_data_control_p ; work ;; |rx_data_receive:rx_dtarcv| ; 28 (28) ; 24 (24) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|rx_data_receive:rx_dtarcv ; rx_data_receive ; work ;; |TX_SPW:TX| ; 207 (0) ; 105 (0) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX ; TX_SPW ; work ;; |tx_data_send:tx_data_snd| ; 30 (30) ; 29 (29) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_data_send:tx_data_snd ; tx_data_send ; work ;; |tx_fsm_m:tx_fsm| ; 177 (125) ; 76 (43) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm ; tx_fsm_m ; work ;; |tx_fct_counter:tx_fct_cnt| ; 33 (33) ; 22 (22) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_counter:tx_fct_cnt ; tx_fct_counter ; work ;; |tx_fct_send:tx_fct_snd| ; 19 (19) ; 11 (11) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_send:tx_fct_snd ; tx_fct_send ; work ;; |ulight_fifo:u0| ; 4142 (0) ; 3049 (0) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0 ; ulight_fifo ; ulight_fifo ;; |altera_reset_controller:rst_controller_001| ; 0 (0) ; 3 (0) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|altera_reset_controller:rst_controller_001 ; altera_reset_controller ; ulight_fifo ;; |altera_reset_synchronizer:alt_rst_sync_uq1| ; 0 (0) ; 3 (3) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1 ; altera_reset_synchronizer ; ulight_fifo ;; |altera_reset_controller:rst_controller| ; 0 (0) ; 3 (0) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|altera_reset_controller:rst_controller ; altera_reset_controller ; ulight_fifo ;; |altera_reset_synchronizer:alt_rst_sync_uq1| ; 0 (0) ; 3 (3) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1 ; altera_reset_synchronizer ; ulight_fifo ;; |ulight_fifo_auto_start:auto_start| ; 2 (2) ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_auto_start:auto_start ; ulight_fifo_auto_start ; ulight_fifo ;; |ulight_fifo_auto_start:data_read_en_rx| ; 2 (2) ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_auto_start:data_read_en_rx ; ulight_fifo_auto_start ; ulight_fifo ;; |ulight_fifo_auto_start:link_disable| ; 2 (2) ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_auto_start:link_disable ; ulight_fifo_auto_start ; ulight_fifo ;; |ulight_fifo_auto_start:link_start| ; 2 (2) ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_auto_start:link_start ; ulight_fifo_auto_start ; ulight_fifo ;; |ulight_fifo_auto_start:timecode_tx_enable| ; 2 (2) ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_auto_start:timecode_tx_enable ; ulight_fifo_auto_start ; ulight_fifo ;; |ulight_fifo_auto_start:write_en_tx| ; 2 (2) ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_auto_start:write_en_tx ; ulight_fifo_auto_start ; ulight_fifo ;; |ulight_fifo_clock_sel:clock_sel| ; 4 (4) ; 3 (3) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_clock_sel:clock_sel ; ulight_fifo_clock_sel ; ulight_fifo ;; |ulight_fifo_counter_rx_fifo:counter_rx_fifo| ; 6 (6) ; 6 (6) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_counter_rx_fifo:counter_rx_fifo ; ulight_fifo_counter_rx_fifo ; ulight_fifo ;; |ulight_fifo_counter_rx_fifo:counter_tx_fifo| ; 6 (6) ; 6 (6) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_counter_rx_fifo:counter_tx_fifo ; ulight_fifo_counter_rx_fifo ; ulight_fifo ;; |ulight_fifo_counter_rx_fifo:fsm_info| ; 5 (5) ; 5 (5) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_counter_rx_fifo:fsm_info ; ulight_fifo_counter_rx_fifo ; ulight_fifo ;; |ulight_fifo_data_flag_rx:data_flag_rx| ; 9 (9) ; 9 (9) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_data_flag_rx:data_flag_rx ; ulight_fifo_data_flag_rx ; ulight_fifo ;; |ulight_fifo_data_info:data_info| ; 3 (3) ; 3 (3) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_data_info:data_info ; ulight_fifo_data_info ; ulight_fifo ;; |ulight_fifo_fifo_empty_rx_status:fifo_empty_rx_status| ; 1 (1) ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_empty_rx_status ; ulight_fifo_fifo_empty_rx_status ; ulight_fifo ;; |ulight_fifo_fifo_empty_rx_status:fifo_empty_tx_status| ; 1 (1) ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_empty_tx_status ; ulight_fifo_fifo_empty_rx_status ; ulight_fifo ;; |ulight_fifo_fifo_empty_rx_status:fifo_full_rx_status| ; 1 (1) ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_full_rx_status ; ulight_fifo_fifo_empty_rx_status ; ulight_fifo ;; |ulight_fifo_fifo_empty_rx_status:fifo_full_tx_status| ; 1 (1) ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_full_tx_status ; ulight_fifo_fifo_empty_rx_status ; ulight_fifo ;; |ulight_fifo_fifo_empty_rx_status:timecode_ready_rx| ; 1 (1) ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:timecode_ready_rx ; ulight_fifo_fifo_empty_rx_status ; ulight_fifo ;; |ulight_fifo_fifo_empty_rx_status:timecode_tx_ready| ; 1 (1) ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:timecode_tx_ready ; ulight_fifo_fifo_empty_rx_status ; ulight_fifo ;; |ulight_fifo_hps_0:hps_0| ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_hps_0:hps_0 ; ulight_fifo_hps_0 ; ulight_fifo ;; |ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces| ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces ; ulight_fifo_hps_0_fpga_interfaces ; ulight_fifo ;; |ulight_fifo_led_pio_test:led_pio_test| ; 6 (6) ; 5 (5) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_led_pio_test:led_pio_test ; ulight_fifo_led_pio_test ; ulight_fifo ;; |ulight_fifo_mm_interconnect_0:mm_interconnect_0| ; 4058 (0) ; 2969 (0) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0 ; ulight_fifo_mm_interconnect_0 ; ulight_fifo ;; |altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo| ; 6 (6) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;; |altera_avalon_sc_fifo:auto_start_s1_agent_rsp_fifo| ; 26 (26) ; 46 (46) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rsp_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;; |altera_avalon_sc_fifo:clock_sel_s1_agent_rdata_fifo| ; 7 (7) ; 8 (8) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rdata_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;; |altera_avalon_sc_fifo:clock_sel_s1_agent_rsp_fifo| ; 26 (26) ; 46 (46) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rsp_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;; |altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo| ; 10 (10) ; 14 (14) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;; |altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rsp_fifo| ; 25 (25) ; 42 (42) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rsp_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;; |altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rdata_fifo| ; 10 (10) ; 14 (14) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rdata_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;; |altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rsp_fifo| ; 25 (25) ; 42 (42) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rsp_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;; |altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo| ; 14 (14) ; 20 (20) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;; |altera_avalon_sc_fifo:data_flag_rx_s1_agent_rsp_fifo| ; 25 (25) ; 42 (42) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rsp_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;; |altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo| ; 7 (7) ; 8 (8) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;; |altera_avalon_sc_fifo:data_info_s1_agent_rsp_fifo| ; 25 (25) ; 42 (42) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rsp_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;; |altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo| ; 6 (6) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;; |altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rsp_fifo| ; 26 (26) ; 46 (46) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rsp_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;; |altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo| ; 5 (5) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;; |altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rsp_fifo| ; 25 (25) ; 42 (42) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rsp_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;; |altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rdata_fifo| ; 5 (5) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rdata_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;; |altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rsp_fifo| ; 25 (25) ; 42 (42) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rsp_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;; |altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo| ; 5 (5) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;; |altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rsp_fifo| ; 25 (25) ; 42 (42) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rsp_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;; |altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo| ; 5 (5) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;; |altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rsp_fifo| ; 25 (25) ; 42 (42) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rsp_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;; |altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo| ; 9 (9) ; 12 (12) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;; |altera_avalon_sc_fifo:fsm_info_s1_agent_rsp_fifo| ; 25 (25) ; 42 (42) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rsp_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;; |altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo| ; 10 (10) ; 12 (12) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;; |altera_avalon_sc_fifo:led_pio_test_s1_agent_rsp_fifo| ; 26 (26) ; 46 (46) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rsp_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;; |altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo| ; 6 (6) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;; |altera_avalon_sc_fifo:link_disable_s1_agent_rsp_fifo| ; 26 (26) ; 46 (46) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rsp_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;; |altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo| ; 6 (6) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;; |altera_avalon_sc_fifo:link_start_s1_agent_rsp_fifo| ; 26 (26) ; 46 (46) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rsp_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;; |altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo| ; 5 (5) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;; |altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rsp_fifo| ; 25 (25) ; 42 (42) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rsp_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;; |altera_avalon_sc_fifo:timecode_rx_s1_agent_rdata_fifo| ; 12 (12) ; 18 (18) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rdata_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;; |altera_avalon_sc_fifo:timecode_rx_s1_agent_rsp_fifo| ; 25 (25) ; 42 (42) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rsp_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;; |altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rdata_fifo| ; 13 (13) ; 18 (18) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rdata_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;; |altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rsp_fifo| ; 26 (26) ; 46 (46) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rsp_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;; |altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rdata_fifo| ; 6 (6) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rdata_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;; |altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rsp_fifo| ; 26 (26) ; 46 (46) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rsp_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;; |altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rdata_fifo| ; 5 (5) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rdata_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;; |altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rsp_fifo| ; 25 (25) ; 42 (42) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rsp_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;; |altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rdata_fifo| ; 14 (14) ; 20 (20) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rdata_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;; |altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rsp_fifo| ; 26 (26) ; 46 (46) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rsp_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;; |altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo| ; 6 (6) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;; |altera_avalon_sc_fifo:write_en_tx_s1_agent_rsp_fifo| ; 26 (26) ; 46 (46) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rsp_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;; |altera_merlin_axi_master_ni:hps_0_h2f_axi_master_agent| ; 116 (57) ; 26 (6) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_axi_master_ni:hps_0_h2f_axi_master_agent ; altera_merlin_axi_master_ni ; ulight_fifo ;; |altera_merlin_address_alignment:align_address_to_size| ; 59 (59) ; 20 (20) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_axi_master_ni:hps_0_h2f_axi_master_agent|altera_merlin_address_alignment:align_address_to_size ; altera_merlin_address_alignment ; ulight_fifo ;; |altera_merlin_burst_adapter:auto_start_s1_burst_adapter| ; 67 (0) ; 62 (0) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter ; altera_merlin_burst_adapter ; ulight_fifo ;; |altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter| ; 67 (66) ; 62 (62) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ; altera_merlin_burst_adapter_13_1 ; ulight_fifo ;; |altera_merlin_address_alignment:align_address_to_size| ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size ; altera_merlin_address_alignment ; ulight_fifo ;; |altera_merlin_burst_adapter:clock_sel_s1_burst_adapter| ; 65 (0) ; 64 (0) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter ; altera_merlin_burst_adapter ; ulight_fifo ;; |altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter| ; 65 (64) ; 64 (64) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ; altera_merlin_burst_adapter_13_1 ; ulight_fifo ;; |altera_merlin_address_alignment:align_address_to_size| ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size ; altera_merlin_address_alignment ; ulight_fifo ;; |altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter| ; 58 (0) ; 60 (0) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter ; altera_merlin_burst_adapter ; ulight_fifo ;; |altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter| ; 58 (57) ; 60 (60) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ; altera_merlin_burst_adapter_13_1 ; ulight_fifo ;; |altera_merlin_address_alignment:align_address_to_size| ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size ; altera_merlin_address_alignment ; ulight_fifo ;; |altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter| ; 58 (0) ; 60 (0) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter ; altera_merlin_burst_adapter ; ulight_fifo ;; |altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter| ; 58 (57) ; 60 (60) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ; altera_merlin_burst_adapter_13_1 ; ulight_fifo ;; |altera_merlin_address_alignment:align_address_to_size| ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size ; altera_merlin_address_alignment ; ulight_fifo ;; |altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter| ; 58 (0) ; 60 (0) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter ; altera_merlin_burst_adapter ; ulight_fifo ;; |altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter| ; 58 (57) ; 60 (60) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ; altera_merlin_burst_adapter_13_1 ; ulight_fifo ;; |altera_merlin_address_alignment:align_address_to_size| ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size ; altera_merlin_address_alignment ; ulight_fifo ;; |altera_merlin_burst_adapter:data_info_s1_burst_adapter| ; 58 (0) ; 60 (0) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter ; altera_merlin_burst_adapter ; ulight_fifo ;; |altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter| ; 58 (57) ; 60 (60) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ; altera_merlin_burst_adapter_13_1 ; ulight_fifo ;; |altera_merlin_address_alignment:align_address_to_size| ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size ; altera_merlin_address_alignment ; ulight_fifo ;; |altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter| ; 67 (0) ; 62 (0) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter ; altera_merlin_burst_adapter ; ulight_fifo ;; |altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter| ; 67 (66) ; 62 (62) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ; altera_merlin_burst_adapter_13_1 ; ulight_fifo ;; |altera_merlin_address_alignment:align_address_to_size| ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size ; altera_merlin_address_alignment ; ulight_fifo ;; |altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter| ; 58 (0) ; 60 (0) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter ; altera_merlin_burst_adapter ; ulight_fifo ;; |altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter| ; 58 (57) ; 60 (60) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ; altera_merlin_burst_adapter_13_1 ; ulight_fifo ;; |altera_merlin_address_alignment:align_address_to_size| ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size ; altera_merlin_address_alignment ; ulight_fifo ;; |altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter| ; 58 (0) ; 60 (0) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter ; altera_merlin_burst_adapter ; ulight_fifo ;; |altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter| ; 58 (57) ; 60 (60) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ; altera_merlin_burst_adapter_13_1 ; ulight_fifo ;; |altera_merlin_address_alignment:align_address_to_size| ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size ; altera_merlin_address_alignment ; ulight_fifo ;; |altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter| ; 58 (0) ; 60 (0) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter ; altera_merlin_burst_adapter ; ulight_fifo ;; |altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter| ; 58 (57) ; 60 (60) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ; altera_merlin_burst_adapter_13_1 ; ulight_fifo ;; |altera_merlin_address_alignment:align_address_to_size| ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size ; altera_merlin_address_alignment ; ulight_fifo ;; |altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter| ; 58 (0) ; 60 (0) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter ; altera_merlin_burst_adapter ; ulight_fifo ;; |altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter| ; 58 (57) ; 60 (60) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ; altera_merlin_burst_adapter_13_1 ; ulight_fifo ;; |altera_merlin_address_alignment:align_address_to_size| ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size ; altera_merlin_address_alignment ; ulight_fifo ;; |altera_merlin_burst_adapter:fsm_info_s1_burst_adapter| ; 59 (0) ; 60 (0) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter ; altera_merlin_burst_adapter ; ulight_fifo ;; |altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter| ; 59 (58) ; 60 (60) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ; altera_merlin_burst_adapter_13_1 ; ulight_fifo ;; |altera_merlin_address_alignment:align_address_to_size| ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size ; altera_merlin_address_alignment ; ulight_fifo ;; |altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter| ; 67 (0) ; 66 (0) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter ; altera_merlin_burst_adapter ; ulight_fifo ;; |altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter| ; 67 (66) ; 66 (66) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ; altera_merlin_burst_adapter_13_1 ; ulight_fifo ;; |altera_merlin_address_alignment:align_address_to_size| ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size ; altera_merlin_address_alignment ; ulight_fifo ;; |altera_merlin_burst_adapter:link_disable_s1_burst_adapter| ; 67 (0) ; 62 (0) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter ; altera_merlin_burst_adapter ; ulight_fifo ;; |altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter| ; 67 (66) ; 62 (62) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ; altera_merlin_burst_adapter_13_1 ; ulight_fifo ;; |altera_merlin_address_alignment:align_address_to_size| ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size ; altera_merlin_address_alignment ; ulight_fifo ;; |altera_merlin_burst_adapter:link_start_s1_burst_adapter| ; 67 (0) ; 62 (0) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter ; altera_merlin_burst_adapter ; ulight_fifo ;; |altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter| ; 67 (66) ; 62 (62) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ; altera_merlin_burst_adapter_13_1 ; ulight_fifo ;; |altera_merlin_address_alignment:align_address_to_size| ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size ; altera_merlin_address_alignment ; ulight_fifo ;; |altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter| ; 58 (0) ; 60 (0) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter ; altera_merlin_burst_adapter ; ulight_fifo ;; |altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter| ; 58 (57) ; 60 (60) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ; altera_merlin_burst_adapter_13_1 ; ulight_fifo ;; |altera_merlin_address_alignment:align_address_to_size| ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size ; altera_merlin_address_alignment ; ulight_fifo ;; |altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter| ; 58 (0) ; 60 (0) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter ; altera_merlin_burst_adapter ; ulight_fifo ;; |altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter| ; 58 (57) ; 60 (60) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ; altera_merlin_burst_adapter_13_1 ; ulight_fifo ;; |altera_merlin_address_alignment:align_address_to_size| ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size ; altera_merlin_address_alignment ; ulight_fifo ;; |altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter| ; 67 (0) ; 69 (0) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter ; altera_merlin_burst_adapter ; ulight_fifo ;; |altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter| ; 67 (66) ; 69 (69) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ; altera_merlin_burst_adapter_13_1 ; ulight_fifo ;; |altera_merlin_address_alignment:align_address_to_size| ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size ; altera_merlin_address_alignment ; ulight_fifo ;; |altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter| ; 68 (0) ; 62 (0) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter ; altera_merlin_burst_adapter ; ulight_fifo ;; |altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter| ; 68 (67) ; 62 (62) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ; altera_merlin_burst_adapter_13_1 ; ulight_fifo ;; |altera_merlin_address_alignment:align_address_to_size| ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size ; altera_merlin_address_alignment ; ulight_fifo ;; |altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter| ; 58 (0) ; 60 (0) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter ; altera_merlin_burst_adapter ; ulight_fifo ;; |altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter| ; 58 (57) ; 60 (60) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ; altera_merlin_burst_adapter_13_1 ; ulight_fifo ;; |altera_merlin_address_alignment:align_address_to_size| ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size ; altera_merlin_address_alignment ; ulight_fifo ;; |altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter| ; 67 (0) ; 70 (0) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter ; altera_merlin_burst_adapter ; ulight_fifo ;; |altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter| ; 67 (66) ; 70 (70) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ; altera_merlin_burst_adapter_13_1 ; ulight_fifo ;; |altera_merlin_address_alignment:align_address_to_size| ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size ; altera_merlin_address_alignment ; ulight_fifo ;; |altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter| ; 67 (0) ; 62 (0) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter ; altera_merlin_burst_adapter ; ulight_fifo ;; |altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter| ; 67 (66) ; 62 (62) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ; altera_merlin_burst_adapter_13_1 ; ulight_fifo ;; |altera_merlin_address_alignment:align_address_to_size| ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size ; altera_merlin_address_alignment ; ulight_fifo ;; |altera_merlin_slave_agent:auto_start_s1_agent| ; 28 (11) ; 7 (0) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:auto_start_s1_agent ; altera_merlin_slave_agent ; ulight_fifo ;; |altera_merlin_burst_uncompressor:uncompressor| ; 17 (17) ; 7 (7) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:auto_start_s1_agent|altera_merlin_burst_uncompressor:uncompressor ; altera_merlin_burst_uncompressor ; ulight_fifo ;; |altera_merlin_slave_agent:clock_sel_s1_agent| ; 27 (11) ; 7 (0) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:clock_sel_s1_agent ; altera_merlin_slave_agent ; ulight_fifo ;; |altera_merlin_burst_uncompressor:uncompressor| ; 16 (16) ; 7 (7) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:clock_sel_s1_agent|altera_merlin_burst_uncompressor:uncompressor ; altera_merlin_burst_uncompressor ; ulight_fifo ;; |altera_merlin_slave_agent:counter_rx_fifo_s1_agent| ; 24 (7) ; 7 (0) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:counter_rx_fifo_s1_agent ; altera_merlin_slave_agent ; ulight_fifo ;; |altera_merlin_burst_uncompressor:uncompressor| ; 17 (17) ; 7 (7) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:counter_rx_fifo_s1_agent|altera_merlin_burst_uncompressor:uncompressor ; altera_merlin_burst_uncompressor ; ulight_fifo ;; |altera_merlin_slave_agent:counter_tx_fifo_s1_agent| ; 24 (7) ; 7 (0) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:counter_tx_fifo_s1_agent ; altera_merlin_slave_agent ; ulight_fifo ;; |altera_merlin_burst_uncompressor:uncompressor| ; 17 (17) ; 7 (7) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:counter_tx_fifo_s1_agent|altera_merlin_burst_uncompressor:uncompressor ; altera_merlin_burst_uncompressor ; ulight_fifo ;; |altera_merlin_slave_agent:data_flag_rx_s1_agent| ; 23 (6) ; 7 (0) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:data_flag_rx_s1_agent ; altera_merlin_slave_agent ; ulight_fifo ;; |altera_merlin_burst_uncompressor:uncompressor| ; 17 (17) ; 7 (7) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:data_flag_rx_s1_agent|altera_merlin_burst_uncompressor:uncompressor ; altera_merlin_burst_uncompressor ; ulight_fifo ;; |altera_merlin_slave_agent:data_info_s1_agent| ; 23 (6) ; 7 (0) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:data_info_s1_agent ; altera_merlin_slave_agent ; ulight_fifo ;; |altera_merlin_burst_uncompressor:uncompressor| ; 17 (17) ; 7 (7) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:data_info_s1_agent|altera_merlin_burst_uncompressor:uncompressor ; altera_merlin_burst_uncompressor ; ulight_fifo ;; |altera_merlin_slave_agent:data_read_en_rx_s1_agent| ; 28 (11) ; 7 (0) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:data_read_en_rx_s1_agent ; altera_merlin_slave_agent ; ulight_fifo ;; |altera_merlin_burst_uncompressor:uncompressor| ; 17 (17) ; 7 (7) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:data_read_en_rx_s1_agent|altera_merlin_burst_uncompressor:uncompressor ; altera_merlin_burst_uncompressor ; ulight_fifo ;; |altera_merlin_slave_agent:fifo_empty_rx_status_s1_agent| ; 23 (6) ; 7 (0) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fifo_empty_rx_status_s1_agent ; altera_merlin_slave_agent ; ulight_fifo ;; |altera_merlin_burst_uncompressor:uncompressor| ; 17 (17) ; 7 (7) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fifo_empty_rx_status_s1_agent|altera_merlin_burst_uncompressor:uncompressor ; altera_merlin_burst_uncompressor ; ulight_fifo ;; |altera_merlin_slave_agent:fifo_empty_tx_status_s1_agent| ; 24 (7) ; 7 (0) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fifo_empty_tx_status_s1_agent ; altera_merlin_slave_agent ; ulight_fifo ;; |altera_merlin_burst_uncompressor:uncompressor| ; 17 (17) ; 7 (7) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fifo_empty_tx_status_s1_agent|altera_merlin_burst_uncompressor:uncompressor ; altera_merlin_burst_uncompressor ; ulight_fifo ;; |altera_merlin_slave_agent:fifo_full_rx_status_s1_agent| ; 23 (6) ; 7 (0) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fifo_full_rx_status_s1_agent ; altera_merlin_slave_agent ; ulight_fifo ;; |altera_merlin_burst_uncompressor:uncompressor| ; 17 (17) ; 7 (7) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fifo_full_rx_status_s1_agent|altera_merlin_burst_uncompressor:uncompressor ; altera_merlin_burst_uncompressor ; ulight_fifo ;; |altera_merlin_slave_agent:fifo_full_tx_status_s1_agent| ; 23 (6) ; 7 (0) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fifo_full_tx_status_s1_agent ; altera_merlin_slave_agent ; ulight_fifo ;; |altera_merlin_burst_uncompressor:uncompressor| ; 17 (17) ; 7 (7) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fifo_full_tx_status_s1_agent|altera_merlin_burst_uncompressor:uncompressor ; altera_merlin_burst_uncompressor ; ulight_fifo ;; |altera_merlin_slave_agent:fsm_info_s1_agent| ; 23 (6) ; 7 (0) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fsm_info_s1_agent ; altera_merlin_slave_agent ; ulight_fifo ;; |altera_merlin_burst_uncompressor:uncompressor| ; 17 (17) ; 7 (7) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fsm_info_s1_agent|altera_merlin_burst_uncompressor:uncompressor ; altera_merlin_burst_uncompressor ; ulight_fifo ;; |altera_merlin_slave_agent:led_pio_test_s1_agent| ; 28 (11) ; 7 (0) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:led_pio_test_s1_agent ; altera_merlin_slave_agent ; ulight_fifo ;; |altera_merlin_burst_uncompressor:uncompressor| ; 17 (17) ; 7 (7) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:led_pio_test_s1_agent|altera_merlin_burst_uncompressor:uncompressor ; altera_merlin_burst_uncompressor ; ulight_fifo ;; |altera_merlin_slave_agent:link_disable_s1_agent| ; 28 (11) ; 7 (0) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:link_disable_s1_agent ; altera_merlin_slave_agent ; ulight_fifo ;; |altera_merlin_burst_uncompressor:uncompressor| ; 17 (17) ; 7 (7) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:link_disable_s1_agent|altera_merlin_burst_uncompressor:uncompressor ; altera_merlin_burst_uncompressor ; ulight_fifo ;; |altera_merlin_slave_agent:link_start_s1_agent| ; 28 (11) ; 7 (0) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:link_start_s1_agent ; altera_merlin_slave_agent ; ulight_fifo ;; |altera_merlin_burst_uncompressor:uncompressor| ; 17 (17) ; 7 (7) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:link_start_s1_agent|altera_merlin_burst_uncompressor:uncompressor ; altera_merlin_burst_uncompressor ; ulight_fifo ;; |altera_merlin_slave_agent:timecode_ready_rx_s1_agent| ; 23 (6) ; 7 (0) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_ready_rx_s1_agent ; altera_merlin_slave_agent ; ulight_fifo ;; |altera_merlin_burst_uncompressor:uncompressor| ; 17 (17) ; 7 (7) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_ready_rx_s1_agent|altera_merlin_burst_uncompressor:uncompressor ; altera_merlin_burst_uncompressor ; ulight_fifo ;; |altera_merlin_slave_agent:timecode_rx_s1_agent| ; 23 (6) ; 7 (0) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_rx_s1_agent ; altera_merlin_slave_agent ; ulight_fifo ;; |altera_merlin_burst_uncompressor:uncompressor| ; 17 (17) ; 7 (7) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_rx_s1_agent|altera_merlin_burst_uncompressor:uncompressor ; altera_merlin_burst_uncompressor ; ulight_fifo ;; |altera_merlin_slave_agent:timecode_tx_data_s1_agent| ; 28 (11) ; 7 (0) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_tx_data_s1_agent ; altera_merlin_slave_agent ; ulight_fifo ;; |altera_merlin_burst_uncompressor:uncompressor| ; 17 (17) ; 7 (7) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_tx_data_s1_agent|altera_merlin_burst_uncompressor:uncompressor ; altera_merlin_burst_uncompressor ; ulight_fifo ;; |altera_merlin_slave_agent:timecode_tx_enable_s1_agent| ; 28 (11) ; 7 (0) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_tx_enable_s1_agent ; altera_merlin_slave_agent ; ulight_fifo ;; |altera_merlin_burst_uncompressor:uncompressor| ; 17 (17) ; 7 (7) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_tx_enable_s1_agent|altera_merlin_burst_uncompressor:uncompressor ; altera_merlin_burst_uncompressor ; ulight_fifo ;; |altera_merlin_slave_agent:timecode_tx_ready_s1_agent| ; 24 (7) ; 7 (0) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_tx_ready_s1_agent ; altera_merlin_slave_agent ; ulight_fifo ;; |altera_merlin_burst_uncompressor:uncompressor| ; 17 (17) ; 7 (7) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_tx_ready_s1_agent|altera_merlin_burst_uncompressor:uncompressor ; altera_merlin_burst_uncompressor ; ulight_fifo ;; |altera_merlin_slave_agent:write_data_fifo_tx_s1_agent| ; 28 (11) ; 7 (0) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:write_data_fifo_tx_s1_agent ; altera_merlin_slave_agent ; ulight_fifo ;; |altera_merlin_burst_uncompressor:uncompressor| ; 17 (17) ; 7 (7) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:write_data_fifo_tx_s1_agent|altera_merlin_burst_uncompressor:uncompressor ; altera_merlin_burst_uncompressor ; ulight_fifo ;; |altera_merlin_slave_agent:write_en_tx_s1_agent| ; 28 (11) ; 7 (0) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:write_en_tx_s1_agent ; altera_merlin_slave_agent ; ulight_fifo ;; |altera_merlin_burst_uncompressor:uncompressor| ; 17 (17) ; 7 (7) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:write_en_tx_s1_agent|altera_merlin_burst_uncompressor:uncompressor ; altera_merlin_burst_uncompressor ; ulight_fifo ;; |altera_merlin_slave_translator:auto_start_s1_translator| ; 5 (5) ; 5 (5) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:auto_start_s1_translator ; altera_merlin_slave_translator ; ulight_fifo ;; |altera_merlin_slave_translator:clock_sel_s1_translator| ; 5 (5) ; 7 (7) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:clock_sel_s1_translator ; altera_merlin_slave_translator ; ulight_fifo ;; |altera_merlin_slave_translator:counter_rx_fifo_s1_translator| ; 2 (2) ; 9 (9) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:counter_rx_fifo_s1_translator ; altera_merlin_slave_translator ; ulight_fifo ;; |altera_merlin_slave_translator:counter_tx_fifo_s1_translator| ; 2 (2) ; 9 (9) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:counter_tx_fifo_s1_translator ; altera_merlin_slave_translator ; ulight_fifo ;; |altera_merlin_slave_translator:data_flag_rx_s1_translator| ; 2 (2) ; 12 (12) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:data_flag_rx_s1_translator ; altera_merlin_slave_translator ; ulight_fifo ;; |altera_merlin_slave_translator:data_info_s1_translator| ; 2 (2) ; 6 (6) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:data_info_s1_translator ; altera_merlin_slave_translator ; ulight_fifo ;; |altera_merlin_slave_translator:data_read_en_rx_s1_translator| ; 5 (5) ; 5 (5) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:data_read_en_rx_s1_translator ; altera_merlin_slave_translator ; ulight_fifo ;; |altera_merlin_slave_translator:fifo_empty_rx_status_s1_translator| ; 2 (2) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_empty_rx_status_s1_translator ; altera_merlin_slave_translator ; ulight_fifo ;; |altera_merlin_slave_translator:fifo_empty_tx_status_s1_translator| ; 2 (2) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_empty_tx_status_s1_translator ; altera_merlin_slave_translator ; ulight_fifo ;; |altera_merlin_slave_translator:fifo_full_rx_status_s1_translator| ; 2 (2) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_full_rx_status_s1_translator ; altera_merlin_slave_translator ; ulight_fifo ;; |altera_merlin_slave_translator:fifo_full_tx_status_s1_translator| ; 2 (2) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_full_tx_status_s1_translator ; altera_merlin_slave_translator ; ulight_fifo ;; |altera_merlin_slave_translator:fsm_info_s1_translator| ; 2 (2) ; 8 (8) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fsm_info_s1_translator ; altera_merlin_slave_translator ; ulight_fifo ;; |altera_merlin_slave_translator:led_pio_test_s1_translator| ; 5 (5) ; 9 (9) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:led_pio_test_s1_translator ; altera_merlin_slave_translator ; ulight_fifo ;; |altera_merlin_slave_translator:link_disable_s1_translator| ; 5 (5) ; 5 (5) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:link_disable_s1_translator ; altera_merlin_slave_translator ; ulight_fifo ;; |altera_merlin_slave_translator:link_start_s1_translator| ; 5 (5) ; 5 (5) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:link_start_s1_translator ; altera_merlin_slave_translator ; ulight_fifo ;; |altera_merlin_slave_translator:timecode_ready_rx_s1_translator| ; 2 (2) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_ready_rx_s1_translator ; altera_merlin_slave_translator ; ulight_fifo ;; |altera_merlin_slave_translator:timecode_rx_s1_translator| ; 2 (2) ; 11 (11) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_rx_s1_translator ; altera_merlin_slave_translator ; ulight_fifo ;; |altera_merlin_slave_translator:timecode_tx_data_s1_translator| ; 5 (5) ; 12 (12) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_data_s1_translator ; altera_merlin_slave_translator ; ulight_fifo ;; |altera_merlin_slave_translator:timecode_tx_enable_s1_translator| ; 5 (5) ; 5 (5) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_enable_s1_translator ; altera_merlin_slave_translator ; ulight_fifo ;; |altera_merlin_slave_translator:timecode_tx_ready_s1_translator| ; 2 (2) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_ready_s1_translator ; altera_merlin_slave_translator ; ulight_fifo ;; |altera_merlin_slave_translator:write_data_fifo_tx_s1_translator| ; 5 (5) ; 13 (13) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:write_data_fifo_tx_s1_translator ; altera_merlin_slave_translator ; ulight_fifo ;; |altera_merlin_slave_translator:write_en_tx_s1_translator| ; 5 (5) ; 5 (5) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:write_en_tx_s1_translator ; altera_merlin_slave_translator ; ulight_fifo ;; |altera_merlin_traffic_limiter:hps_0_h2f_axi_master_rd_limiter| ; 12 (12) ; 30 (30) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_traffic_limiter:hps_0_h2f_axi_master_rd_limiter ; altera_merlin_traffic_limiter ; ulight_fifo ;; |altera_merlin_traffic_limiter:hps_0_h2f_axi_master_wr_limiter| ; 14 (14) ; 18 (18) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_traffic_limiter:hps_0_h2f_axi_master_wr_limiter ; altera_merlin_traffic_limiter ; ulight_fifo ;; |ulight_fifo_mm_interconnect_0_cmd_demux:cmd_demux_001| ; 46 (46) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_demux:cmd_demux_001 ; ulight_fifo_mm_interconnect_0_cmd_demux ; ulight_fifo ;; |ulight_fifo_mm_interconnect_0_cmd_demux:cmd_demux| ; 35 (35) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_demux:cmd_demux ; ulight_fifo_mm_interconnect_0_cmd_demux ; ulight_fifo ;; |ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_001| ; 22 (22) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_001 ; ulight_fifo_mm_interconnect_0_cmd_mux ; ulight_fifo ;; |ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_002| ; 22 (22) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_002 ; ulight_fifo_mm_interconnect_0_cmd_mux ; ulight_fifo ;; |ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_003| ; 22 (22) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_003 ; ulight_fifo_mm_interconnect_0_cmd_mux ; ulight_fifo ;; |ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_004| ; 33 (29) ; 5 (3) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_004 ; ulight_fifo_mm_interconnect_0_cmd_mux ; ulight_fifo ;; |altera_merlin_arbitrator:arb| ; 4 (4) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_004|altera_merlin_arbitrator:arb ; altera_merlin_arbitrator ; ulight_fifo ;; |ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_005| ; 22 (22) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_005 ; ulight_fifo_mm_interconnect_0_cmd_mux ; ulight_fifo ;; |ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_006| ; 22 (22) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_006 ; ulight_fifo_mm_interconnect_0_cmd_mux ; ulight_fifo ;; |ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_007| ; 34 (29) ; 5 (3) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_007 ; ulight_fifo_mm_interconnect_0_cmd_mux ; ulight_fifo ;; |altera_merlin_arbitrator:arb| ; 5 (5) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_007|altera_merlin_arbitrator:arb ; altera_merlin_arbitrator ; ulight_fifo ;; |ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_008| ; 33 (29) ; 5 (3) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_008 ; ulight_fifo_mm_interconnect_0_cmd_mux ; ulight_fifo ;; |altera_merlin_arbitrator:arb| ; 4 (4) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_008|altera_merlin_arbitrator:arb ; altera_merlin_arbitrator ; ulight_fifo ;; |ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_009| ; 34 (29) ; 5 (3) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_009 ; ulight_fifo_mm_interconnect_0_cmd_mux ; ulight_fifo ;; |altera_merlin_arbitrator:arb| ; 5 (5) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_009|altera_merlin_arbitrator:arb ; altera_merlin_arbitrator ; ulight_fifo ;; |ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_010| ; 42 (37) ; 5 (3) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_010 ; ulight_fifo_mm_interconnect_0_cmd_mux ; ulight_fifo ;; |altera_merlin_arbitrator:arb| ; 5 (5) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_010|altera_merlin_arbitrator:arb ; altera_merlin_arbitrator ; ulight_fifo ;; |ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_011| ; 34 (29) ; 5 (3) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_011 ; ulight_fifo_mm_interconnect_0_cmd_mux ; ulight_fifo ;; |altera_merlin_arbitrator:arb| ; 5 (5) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_011|altera_merlin_arbitrator:arb ; altera_merlin_arbitrator ; ulight_fifo ;; |ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_012| ; 22 (22) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_012 ; ulight_fifo_mm_interconnect_0_cmd_mux ; ulight_fifo ;; |ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_013| ; 22 (22) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_013 ; ulight_fifo_mm_interconnect_0_cmd_mux ; ulight_fifo ;; |ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_014| ; 40 (35) ; 5 (3) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_014 ; ulight_fifo_mm_interconnect_0_cmd_mux ; ulight_fifo ;; |altera_merlin_arbitrator:arb| ; 5 (5) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_014|altera_merlin_arbitrator:arb ; altera_merlin_arbitrator ; ulight_fifo ;; |ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_015| ; 33 (28) ; 5 (3) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_015 ; ulight_fifo_mm_interconnect_0_cmd_mux ; ulight_fifo ;; |altera_merlin_arbitrator:arb| ; 5 (5) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_015|altera_merlin_arbitrator:arb ; altera_merlin_arbitrator ; ulight_fifo ;; |ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_016| ; 22 (22) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_016 ; ulight_fifo_mm_interconnect_0_cmd_mux ; ulight_fifo ;; |ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_017| ; 22 (22) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_017 ; ulight_fifo_mm_interconnect_0_cmd_mux ; ulight_fifo ;; |ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_018| ; 35 (31) ; 5 (3) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_018 ; ulight_fifo_mm_interconnect_0_cmd_mux ; ulight_fifo ;; |altera_merlin_arbitrator:arb| ; 4 (4) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_018|altera_merlin_arbitrator:arb ; altera_merlin_arbitrator ; ulight_fifo ;; |ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_019| ; 22 (22) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_019 ; ulight_fifo_mm_interconnect_0_cmd_mux ; ulight_fifo ;; |ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_020| ; 22 (22) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_020 ; ulight_fifo_mm_interconnect_0_cmd_mux ; ulight_fifo ;; |ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_021| ; 22 (22) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_021 ; ulight_fifo_mm_interconnect_0_cmd_mux ; ulight_fifo ;; |ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux| ; 37 (32) ; 5 (3) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux ; ulight_fifo_mm_interconnect_0_cmd_mux ; ulight_fifo ;; |altera_merlin_arbitrator:arb| ; 5 (5) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux|altera_merlin_arbitrator:arb ; altera_merlin_arbitrator ; ulight_fifo ;; |ulight_fifo_mm_interconnect_0_router:router_001| ; 40 (40) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_router:router_001 ; ulight_fifo_mm_interconnect_0_router ; ulight_fifo ;; |ulight_fifo_mm_interconnect_0_router:router| ; 28 (28) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_router:router ; ulight_fifo_mm_interconnect_0_router ; ulight_fifo ;; |ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_004| ; 3 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_004 ; ulight_fifo_mm_interconnect_0_rsp_demux ; ulight_fifo ;; |ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_007| ; 3 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_007 ; ulight_fifo_mm_interconnect_0_rsp_demux ; ulight_fifo ;; |ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_008| ; 3 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_008 ; ulight_fifo_mm_interconnect_0_rsp_demux ; ulight_fifo ;; |ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_009| ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_009 ; ulight_fifo_mm_interconnect_0_rsp_demux ; ulight_fifo ;; |ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_010| ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_010 ; ulight_fifo_mm_interconnect_0_rsp_demux ; ulight_fifo ;; |ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_011| ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_011 ; ulight_fifo_mm_interconnect_0_rsp_demux ; ulight_fifo ;; |ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_014| ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_014 ; ulight_fifo_mm_interconnect_0_rsp_demux ; ulight_fifo ;; |ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_015| ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_015 ; ulight_fifo_mm_interconnect_0_rsp_demux ; ulight_fifo ;; |ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_018| ; 3 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_018 ; ulight_fifo_mm_interconnect_0_rsp_demux ; ulight_fifo ;; |ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux| ; 3 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux ; ulight_fifo_mm_interconnect_0_rsp_demux ; ulight_fifo ;; |ulight_fifo_mm_interconnect_0_rsp_mux:rsp_mux_001| ; 294 (294) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_mux:rsp_mux_001 ; ulight_fifo_mm_interconnect_0_rsp_mux ; ulight_fifo ;; |ulight_fifo_mm_interconnect_0_rsp_mux:rsp_mux| ; 88 (88) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_mux:rsp_mux ; ulight_fifo_mm_interconnect_0_rsp_mux ; ulight_fifo ;; |ulight_fifo_pll_0:pll_0| ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_pll_0:pll_0 ; ulight_fifo_pll_0 ; ulight_fifo ;; |altera_pll:altera_pll_i| ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i ; altera_pll ; work ;; |altera_cyclonev_pll:cyclonev_pll| ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i|altera_cyclonev_pll:cyclonev_pll ; altera_cyclonev_pll ; work ;; |altera_cyclonev_pll_base:fpll_0| ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i|altera_cyclonev_pll:cyclonev_pll|altera_cyclonev_pll_base:fpll_0 ; altera_cyclonev_pll_base ; work ;; |ulight_fifo_timecode_rx:timecode_rx| ; 8 (8) ; 8 (8) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_timecode_rx:timecode_rx ; ulight_fifo_timecode_rx ; ulight_fifo ;; |ulight_fifo_timecode_tx_data:timecode_tx_data| ; 9 (9) ; 8 (8) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_timecode_tx_data:timecode_tx_data ; ulight_fifo_timecode_tx_data ; ulight_fifo ;; |ulight_fifo_write_data_fifo_tx:write_data_fifo_tx| ; 10 (10) ; 9 (9) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_write_data_fifo_tx:write_data_fifo_tx ; ulight_fifo_write_data_fifo_tx ; ulight_fifo ;+-----------------------------------------------------------------------------------------------+---------------------+---------------------------+-------------------+------------+------+--------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------+--------------+Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Analysis & Synthesis IP Cores Summary ;+--------+--------------------------------+---------+--------------+--------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------+; Vendor ; IP Core Name ; Version ; Release Date ; License Type ; Entity Instance ; IP Include File ;+--------+--------------------------------+---------+--------------+--------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------+; N/A ; Qsys ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0 ; ulight_fifo.qsys ;; Altera ; altera_avalon_pio ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_auto_start:auto_start ; ulight_fifo.qsys ;; Altera ; altera_avalon_pio ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_clock_sel:clock_sel ; ulight_fifo.qsys ;; Altera ; altera_avalon_pio ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_counter_rx_fifo:counter_rx_fifo ; ulight_fifo.qsys ;; Altera ; altera_avalon_pio ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_counter_rx_fifo:counter_tx_fifo ; ulight_fifo.qsys ;; Altera ; altera_avalon_pio ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_data_flag_rx:data_flag_rx ; ulight_fifo.qsys ;; Altera ; altera_avalon_pio ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_data_info:data_info ; ulight_fifo.qsys ;; Altera ; altera_avalon_pio ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_auto_start:data_read_en_rx ; ulight_fifo.qsys ;; Altera ; altera_avalon_pio ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_empty_rx_status ; ulight_fifo.qsys ;; Altera ; altera_avalon_pio ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_empty_tx_status ; ulight_fifo.qsys ;; Altera ; altera_avalon_pio ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_full_rx_status ; ulight_fifo.qsys ;; Altera ; altera_avalon_pio ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_full_tx_status ; ulight_fifo.qsys ;; Altera ; altera_avalon_pio ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_counter_rx_fifo:fsm_info ; ulight_fifo.qsys ;; Altera ; altera_hps ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_hps_0:hps_0 ; ulight_fifo.qsys ;; Altera ; altera_hps_io ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io ; ulight_fifo.qsys ;; Altera ; altera_avalon_pio ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_led_pio_test:led_pio_test ; ulight_fifo.qsys ;; Altera ; altera_avalon_pio ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_auto_start:link_disable ; ulight_fifo.qsys ;; Altera ; altera_avalon_pio ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_auto_start:link_start ; ulight_fifo.qsys ;; Altera ; altera_mm_interconnect ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0 ; ulight_fifo.qsys ;; Altera ; altera_merlin_slave_agent ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:auto_start_s1_agent ; ulight_fifo.qsys ;; Altera ; altera_avalon_sc_fifo ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo ; ulight_fifo.qsys ;; Altera ; altera_avalon_sc_fifo ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rsp_fifo ; ulight_fifo.qsys ;; Altera ; altera_merlin_burst_adapter ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter ; ulight_fifo.qsys ;; Altera ; altera_merlin_slave_translator ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:auto_start_s1_translator ; ulight_fifo.qsys ;; Altera ; altera_avalon_st_adapter ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter ; ulight_fifo.qsys ;; Altera ; error_adapter ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter|ulight_fifo_mm_interconnect_0_avalon_st_adapter_error_adapter_0:error_adapter_0 ; ulight_fifo.qsys ;; Altera ; altera_avalon_st_adapter ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_001 ; ulight_fifo.qsys ;; Altera ; error_adapter ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_001|ulight_fifo_mm_interconnect_0_avalon_st_adapter_error_adapter_0:error_adapter_0 ; ulight_fifo.qsys ;; Altera ; altera_avalon_st_adapter ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_002 ; ulight_fifo.qsys ;; Altera ; error_adapter ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_002|ulight_fifo_mm_interconnect_0_avalon_st_adapter_error_adapter_0:error_adapter_0 ; ulight_fifo.qsys ;; Altera ; altera_avalon_st_adapter ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_003 ; ulight_fifo.qsys ;; Altera ; error_adapter ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_003|ulight_fifo_mm_interconnect_0_avalon_st_adapter_error_adapter_0:error_adapter_0 ; ulight_fifo.qsys ;; Altera ; altera_avalon_st_adapter ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_004 ; ulight_fifo.qsys ;; Altera ; error_adapter ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_004|ulight_fifo_mm_interconnect_0_avalon_st_adapter_error_adapter_0:error_adapter_0 ; ulight_fifo.qsys ;; Altera ; altera_avalon_st_adapter ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_005 ; ulight_fifo.qsys ;; Altera ; error_adapter ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_005|ulight_fifo_mm_interconnect_0_avalon_st_adapter_error_adapter_0:error_adapter_0 ; ulight_fifo.qsys ;; Altera ; altera_avalon_st_adapter ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_006 ; ulight_fifo.qsys ;; Altera ; error_adapter ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_006|ulight_fifo_mm_interconnect_0_avalon_st_adapter_error_adapter_0:error_adapter_0 ; ulight_fifo.qsys ;; Altera ; altera_avalon_st_adapter ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_007 ; ulight_fifo.qsys ;; Altera ; error_adapter ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_007|ulight_fifo_mm_interconnect_0_avalon_st_adapter_error_adapter_0:error_adapter_0 ; ulight_fifo.qsys ;; Altera ; altera_avalon_st_adapter ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_008 ; ulight_fifo.qsys ;; Altera ; error_adapter ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_008|ulight_fifo_mm_interconnect_0_avalon_st_adapter_error_adapter_0:error_adapter_0 ; ulight_fifo.qsys ;; Altera ; altera_avalon_st_adapter ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_009 ; ulight_fifo.qsys ;; Altera ; error_adapter ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_009|ulight_fifo_mm_interconnect_0_avalon_st_adapter_error_adapter_0:error_adapter_0 ; ulight_fifo.qsys ;; Altera ; altera_avalon_st_adapter ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_010 ; ulight_fifo.qsys ;; Altera ; error_adapter ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_010|ulight_fifo_mm_interconnect_0_avalon_st_adapter_error_adapter_0:error_adapter_0 ; ulight_fifo.qsys ;; Altera ; altera_avalon_st_adapter ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_011 ; ulight_fifo.qsys ;; Altera ; error_adapter ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_011|ulight_fifo_mm_interconnect_0_avalon_st_adapter_error_adapter_0:error_adapter_0 ; ulight_fifo.qsys ;; Altera ; altera_avalon_st_adapter ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_012 ; ulight_fifo.qsys ;; Altera ; error_adapter ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_012|ulight_fifo_mm_interconnect_0_avalon_st_adapter_error_adapter_0:error_adapter_0 ; ulight_fifo.qsys ;; Altera ; altera_avalon_st_adapter ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_013 ; ulight_fifo.qsys ;; Altera ; error_adapter ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_013|ulight_fifo_mm_interconnect_0_avalon_st_adapter_error_adapter_0:error_adapter_0 ; ulight_fifo.qsys ;; Altera ; altera_avalon_st_adapter ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_014 ; ulight_fifo.qsys ;; Altera ; error_adapter ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_014|ulight_fifo_mm_interconnect_0_avalon_st_adapter_error_adapter_0:error_adapter_0 ; ulight_fifo.qsys ;; Altera ; altera_avalon_st_adapter ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_015 ; ulight_fifo.qsys ;; Altera ; error_adapter ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_015|ulight_fifo_mm_interconnect_0_avalon_st_adapter_error_adapter_0:error_adapter_0 ; ulight_fifo.qsys ;; Altera ; altera_avalon_st_adapter ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_016 ; ulight_fifo.qsys ;; Altera ; error_adapter ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_016|ulight_fifo_mm_interconnect_0_avalon_st_adapter_error_adapter_0:error_adapter_0 ; ulight_fifo.qsys ;; Altera ; altera_avalon_st_adapter ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_017 ; ulight_fifo.qsys ;; Altera ; error_adapter ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_017|ulight_fifo_mm_interconnect_0_avalon_st_adapter_error_adapter_0:error_adapter_0 ; ulight_fifo.qsys ;; Altera ; altera_avalon_st_adapter ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_018 ; ulight_fifo.qsys ;; Altera ; error_adapter ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_018|ulight_fifo_mm_interconnect_0_avalon_st_adapter_error_adapter_0:error_adapter_0 ; ulight_fifo.qsys ;; Altera ; altera_avalon_st_adapter ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_019 ; ulight_fifo.qsys ;; Altera ; error_adapter ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_019|ulight_fifo_mm_interconnect_0_avalon_st_adapter_error_adapter_0:error_adapter_0 ; ulight_fifo.qsys ;; Altera ; altera_avalon_st_adapter ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_020 ; ulight_fifo.qsys ;; Altera ; error_adapter ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_020|ulight_fifo_mm_interconnect_0_avalon_st_adapter_error_adapter_0:error_adapter_0 ; ulight_fifo.qsys ;; Altera ; altera_avalon_st_adapter ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_021 ; ulight_fifo.qsys ;; Altera ; error_adapter ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_021|ulight_fifo_mm_interconnect_0_avalon_st_adapter_error_adapter_0:error_adapter_0 ; ulight_fifo.qsys ;; Altera ; altera_merlin_slave_agent ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:clock_sel_s1_agent ; ulight_fifo.qsys ;; Altera ; altera_avalon_sc_fifo ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rdata_fifo ; ulight_fifo.qsys ;; Altera ; altera_avalon_sc_fifo ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rsp_fifo ; ulight_fifo.qsys ;; Altera ; altera_merlin_burst_adapter ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter ; ulight_fifo.qsys ;; Altera ; altera_merlin_slave_translator ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:clock_sel_s1_translator ; ulight_fifo.qsys ;; Altera ; altera_merlin_demultiplexer ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_demux:cmd_demux ; ulight_fifo.qsys ;; Altera ; altera_merlin_demultiplexer ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_demux:cmd_demux_001 ; ulight_fifo.qsys ;; Altera ; altera_merlin_multiplexer ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux ; ulight_fifo.qsys ;; Altera ; altera_merlin_multiplexer ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_001 ; ulight_fifo.qsys ;; Altera ; altera_merlin_multiplexer ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_002 ; ulight_fifo.qsys ;; Altera ; altera_merlin_multiplexer ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_003 ; ulight_fifo.qsys ;; Altera ; altera_merlin_multiplexer ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_004 ; ulight_fifo.qsys ;; Altera ; altera_merlin_multiplexer ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_005 ; ulight_fifo.qsys ;; Altera ; altera_merlin_multiplexer ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_006 ; ulight_fifo.qsys ;; Altera ; altera_merlin_multiplexer ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_007 ; ulight_fifo.qsys ;; Altera ; altera_merlin_multiplexer ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_008 ; ulight_fifo.qsys ;; Altera ; altera_merlin_multiplexer ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_009 ; ulight_fifo.qsys ;; Altera ; altera_merlin_multiplexer ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_010 ; ulight_fifo.qsys ;; Altera ; altera_merlin_multiplexer ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_011 ; ulight_fifo.qsys ;; Altera ; altera_merlin_multiplexer ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_012 ; ulight_fifo.qsys ;; Altera ; altera_merlin_multiplexer ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_013 ; ulight_fifo.qsys ;; Altera ; altera_merlin_multiplexer ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_014 ; ulight_fifo.qsys ;; Altera ; altera_merlin_multiplexer ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_015 ; ulight_fifo.qsys ;; Altera ; altera_merlin_multiplexer ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_016 ; ulight_fifo.qsys ;; Altera ; altera_merlin_multiplexer ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_017 ; ulight_fifo.qsys ;; Altera ; altera_merlin_multiplexer ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_018 ; ulight_fifo.qsys ;; Altera ; altera_merlin_multiplexer ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_019 ; ulight_fifo.qsys ;; Altera ; altera_merlin_multiplexer ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_020 ; ulight_fifo.qsys ;; Altera ; altera_merlin_multiplexer ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_021 ; ulight_fifo.qsys ;; Altera ; altera_merlin_slave_agent ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:counter_rx_fifo_s1_agent ; ulight_fifo.qsys ;; Altera ; altera_avalon_sc_fifo ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo ; ulight_fifo.qsys ;; Altera ; altera_avalon_sc_fifo ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rsp_fifo ; ulight_fifo.qsys ;; Altera ; altera_merlin_burst_adapter ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter ; ulight_fifo.qsys ;; Altera ; altera_merlin_slave_translator ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:counter_rx_fifo_s1_translator ; ulight_fifo.qsys ;; Altera ; altera_merlin_slave_agent ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:counter_tx_fifo_s1_agent ; ulight_fifo.qsys ;; Altera ; altera_avalon_sc_fifo ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rdata_fifo ; ulight_fifo.qsys ;; Altera ; altera_avalon_sc_fifo ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rsp_fifo ; ulight_fifo.qsys ;; Altera ; altera_merlin_burst_adapter ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter ; ulight_fifo.qsys ;; Altera ; altera_merlin_slave_translator ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:counter_tx_fifo_s1_translator ; ulight_fifo.qsys ;; Altera ; altera_merlin_slave_agent ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:data_flag_rx_s1_agent ; ulight_fifo.qsys ;; Altera ; altera_avalon_sc_fifo ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo ; ulight_fifo.qsys ;; Altera ; altera_avalon_sc_fifo ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rsp_fifo ; ulight_fifo.qsys ;; Altera ; altera_merlin_burst_adapter ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter ; ulight_fifo.qsys ;; Altera ; altera_merlin_slave_translator ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:data_flag_rx_s1_translator ; ulight_fifo.qsys ;; Altera ; altera_merlin_slave_agent ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:data_info_s1_agent ; ulight_fifo.qsys ;; Altera ; altera_avalon_sc_fifo ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo ; ulight_fifo.qsys ;; Altera ; altera_avalon_sc_fifo ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rsp_fifo ; ulight_fifo.qsys ;; Altera ; altera_merlin_burst_adapter ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter ; ulight_fifo.qsys ;; Altera ; altera_merlin_slave_translator ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:data_info_s1_translator ; ulight_fifo.qsys ;; Altera ; altera_merlin_slave_agent ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:data_read_en_rx_s1_agent ; ulight_fifo.qsys ;; Altera ; altera_avalon_sc_fifo ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo ; ulight_fifo.qsys ;; Altera ; altera_avalon_sc_fifo ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rsp_fifo ; ulight_fifo.qsys ;; Altera ; altera_merlin_burst_adapter ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter ; ulight_fifo.qsys ;; Altera ; altera_merlin_slave_translator ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:data_read_en_rx_s1_translator ; ulight_fifo.qsys ;; Altera ; altera_merlin_slave_agent ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fifo_empty_rx_status_s1_agent ; ulight_fifo.qsys ;; Altera ; altera_avalon_sc_fifo ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo ; ulight_fifo.qsys ;; Altera ; altera_avalon_sc_fifo ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rsp_fifo ; ulight_fifo.qsys ;; Altera ; altera_merlin_burst_adapter ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter ; ulight_fifo.qsys ;; Altera ; altera_merlin_slave_translator ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_empty_rx_status_s1_translator ; ulight_fifo.qsys ;; Altera ; altera_merlin_slave_agent ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fifo_empty_tx_status_s1_agent ; ulight_fifo.qsys ;; Altera ; altera_avalon_sc_fifo ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rdata_fifo ; ulight_fifo.qsys ;; Altera ; altera_avalon_sc_fifo ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rsp_fifo ; ulight_fifo.qsys ;; Altera ; altera_merlin_burst_adapter ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter ; ulight_fifo.qsys ;; Altera ; altera_merlin_slave_translator ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_empty_tx_status_s1_translator ; ulight_fifo.qsys ;; Altera ; altera_merlin_slave_agent ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fifo_full_rx_status_s1_agent ; ulight_fifo.qsys ;; Altera ; altera_avalon_sc_fifo ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo ; ulight_fifo.qsys ;; Altera ; altera_avalon_sc_fifo ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rsp_fifo ; ulight_fifo.qsys ;; Altera ; altera_merlin_burst_adapter ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter ; ulight_fifo.qsys ;; Altera ; altera_merlin_slave_translator ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_full_rx_status_s1_translator ; ulight_fifo.qsys ;; Altera ; altera_merlin_slave_agent ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fifo_full_tx_status_s1_agent ; ulight_fifo.qsys ;; Altera ; altera_avalon_sc_fifo ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo ; ulight_fifo.qsys ;; Altera ; altera_avalon_sc_fifo ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rsp_fifo ; ulight_fifo.qsys ;; Altera ; altera_merlin_burst_adapter ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter ; ulight_fifo.qsys ;; Altera ; altera_merlin_slave_translator ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_full_tx_status_s1_translator ; ulight_fifo.qsys ;; Altera ; altera_merlin_slave_agent ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fsm_info_s1_agent ; ulight_fifo.qsys ;; Altera ; altera_avalon_sc_fifo ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo ; ulight_fifo.qsys ;; Altera ; altera_avalon_sc_fifo ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rsp_fifo ; ulight_fifo.qsys ;; Altera ; altera_merlin_burst_adapter ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter ; ulight_fifo.qsys ;; Altera ; altera_merlin_slave_translator ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fsm_info_s1_translator ; ulight_fifo.qsys ;; Altera ; altera_merlin_axi_master_ni ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_axi_master_ni:hps_0_h2f_axi_master_agent ; ulight_fifo.qsys ;; Altera ; altera_merlin_traffic_limiter ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_traffic_limiter:hps_0_h2f_axi_master_rd_limiter ; ulight_fifo.qsys ;; Altera ; altera_merlin_traffic_limiter ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_traffic_limiter:hps_0_h2f_axi_master_wr_limiter ; ulight_fifo.qsys ;; Altera ; altera_merlin_slave_agent ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:led_pio_test_s1_agent ; ulight_fifo.qsys ;; Altera ; altera_avalon_sc_fifo ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo ; ulight_fifo.qsys ;; Altera ; altera_avalon_sc_fifo ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rsp_fifo ; ulight_fifo.qsys ;; Altera ; altera_merlin_burst_adapter ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter ; ulight_fifo.qsys ;; Altera ; altera_merlin_slave_translator ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:led_pio_test_s1_translator ; ulight_fifo.qsys ;; Altera ; altera_merlin_slave_agent ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:link_disable_s1_agent ; ulight_fifo.qsys ;; Altera ; altera_avalon_sc_fifo ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo ; ulight_fifo.qsys ;; Altera ; altera_avalon_sc_fifo ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rsp_fifo ; ulight_fifo.qsys ;; Altera ; altera_merlin_burst_adapter ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter ; ulight_fifo.qsys ;; Altera ; altera_merlin_slave_translator ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:link_disable_s1_translator ; ulight_fifo.qsys ;; Altera ; altera_merlin_slave_agent ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:link_start_s1_agent ; ulight_fifo.qsys ;; Altera ; altera_avalon_sc_fifo ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo ; ulight_fifo.qsys ;; Altera ; altera_avalon_sc_fifo ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rsp_fifo ; ulight_fifo.qsys ;; Altera ; altera_merlin_burst_adapter ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter ; ulight_fifo.qsys ;; Altera ; altera_merlin_slave_translator ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:link_start_s1_translator ; ulight_fifo.qsys ;; Altera ; altera_merlin_router ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_router:router ; ulight_fifo.qsys ;; Altera ; altera_merlin_router ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_router:router_001 ; ulight_fifo.qsys ;; Altera ; altera_merlin_router ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_router_002:router_002 ; ulight_fifo.qsys ;; Altera ; altera_merlin_router ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_router_002:router_003 ; ulight_fifo.qsys ;; Altera ; altera_merlin_router ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_router_002:router_004 ; ulight_fifo.qsys ;; Altera ; altera_merlin_router ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_router_002:router_005 ; ulight_fifo.qsys ;; Altera ; altera_merlin_router ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_router_002:router_006 ; ulight_fifo.qsys ;; Altera ; altera_merlin_router ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_router_002:router_007 ; ulight_fifo.qsys ;; Altera ; altera_merlin_router ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_router_002:router_008 ; ulight_fifo.qsys ;; Altera ; altera_merlin_router ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_router_002:router_009 ; ulight_fifo.qsys ;; Altera ; altera_merlin_router ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_router_002:router_010 ; ulight_fifo.qsys ;; Altera ; altera_merlin_router ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_router_002:router_011 ; ulight_fifo.qsys ;; Altera ; altera_merlin_router ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_router_002:router_012 ; ulight_fifo.qsys ;; Altera ; altera_merlin_router ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_router_002:router_013 ; ulight_fifo.qsys ;; Altera ; altera_merlin_router ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_router_002:router_014 ; ulight_fifo.qsys ;; Altera ; altera_merlin_router ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_router_002:router_015 ; ulight_fifo.qsys ;; Altera ; altera_merlin_router ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_router_002:router_016 ; ulight_fifo.qsys ;; Altera ; altera_merlin_router ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_router_002:router_017 ; ulight_fifo.qsys ;; Altera ; altera_merlin_router ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_router_002:router_018 ; ulight_fifo.qsys ;; Altera ; altera_merlin_router ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_router_002:router_019 ; ulight_fifo.qsys ;; Altera ; altera_merlin_router ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_router_002:router_020 ; ulight_fifo.qsys ;; Altera ; altera_merlin_router ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_router_002:router_021 ; ulight_fifo.qsys ;; Altera ; altera_merlin_router ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_router_002:router_022 ; ulight_fifo.qsys ;; Altera ; altera_merlin_router ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_router_002:router_023 ; ulight_fifo.qsys ;; Altera ; altera_merlin_demultiplexer ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux ; ulight_fifo.qsys ;; Altera ; altera_merlin_demultiplexer ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_001 ; ulight_fifo.qsys ;; Altera ; altera_merlin_demultiplexer ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_002 ; ulight_fifo.qsys ;; Altera ; altera_merlin_demultiplexer ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_003 ; ulight_fifo.qsys ;; Altera ; altera_merlin_demultiplexer ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_004 ; ulight_fifo.qsys ;; Altera ; altera_merlin_demultiplexer ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_005 ; ulight_fifo.qsys ;; Altera ; altera_merlin_demultiplexer ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_006 ; ulight_fifo.qsys ;; Altera ; altera_merlin_demultiplexer ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_007 ; ulight_fifo.qsys ;; Altera ; altera_merlin_demultiplexer ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_008 ; ulight_fifo.qsys ;; Altera ; altera_merlin_demultiplexer ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_009 ; ulight_fifo.qsys ;; Altera ; altera_merlin_demultiplexer ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_010 ; ulight_fifo.qsys ;; Altera ; altera_merlin_demultiplexer ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_011 ; ulight_fifo.qsys ;; Altera ; altera_merlin_demultiplexer ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_012 ; ulight_fifo.qsys ;; Altera ; altera_merlin_demultiplexer ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_013 ; ulight_fifo.qsys ;; Altera ; altera_merlin_demultiplexer ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_014 ; ulight_fifo.qsys ;; Altera ; altera_merlin_demultiplexer ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_015 ; ulight_fifo.qsys ;; Altera ; altera_merlin_demultiplexer ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_016 ; ulight_fifo.qsys ;; Altera ; altera_merlin_demultiplexer ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_017 ; ulight_fifo.qsys ;; Altera ; altera_merlin_demultiplexer ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_018 ; ulight_fifo.qsys ;; Altera ; altera_merlin_demultiplexer ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_019 ; ulight_fifo.qsys ;; Altera ; altera_merlin_demultiplexer ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_020 ; ulight_fifo.qsys ;; Altera ; altera_merlin_demultiplexer ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_021 ; ulight_fifo.qsys ;; Altera ; altera_merlin_multiplexer ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_mux:rsp_mux ; ulight_fifo.qsys ;; Altera ; altera_merlin_multiplexer ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_mux:rsp_mux_001 ; ulight_fifo.qsys ;; Altera ; altera_merlin_slave_agent ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_ready_rx_s1_agent ; ulight_fifo.qsys ;; Altera ; altera_avalon_sc_fifo ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo ; ulight_fifo.qsys ;; Altera ; altera_avalon_sc_fifo ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rsp_fifo ; ulight_fifo.qsys ;; Altera ; altera_merlin_burst_adapter ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter ; ulight_fifo.qsys ;; Altera ; altera_merlin_slave_translator ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_ready_rx_s1_translator ; ulight_fifo.qsys ;; Altera ; altera_merlin_slave_agent ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_rx_s1_agent ; ulight_fifo.qsys ;; Altera ; altera_avalon_sc_fifo ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rdata_fifo ; ulight_fifo.qsys ;; Altera ; altera_avalon_sc_fifo ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rsp_fifo ; ulight_fifo.qsys ;; Altera ; altera_merlin_burst_adapter ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter ; ulight_fifo.qsys ;; Altera ; altera_merlin_slave_translator ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_rx_s1_translator ; ulight_fifo.qsys ;; Altera ; altera_merlin_slave_agent ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_tx_data_s1_agent ; ulight_fifo.qsys ;; Altera ; altera_avalon_sc_fifo ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rdata_fifo ; ulight_fifo.qsys ;; Altera ; altera_avalon_sc_fifo ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rsp_fifo ; ulight_fifo.qsys ;; Altera ; altera_merlin_burst_adapter ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter ; ulight_fifo.qsys ;; Altera ; altera_merlin_slave_translator ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_data_s1_translator ; ulight_fifo.qsys ;; Altera ; altera_merlin_slave_agent ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_tx_enable_s1_agent ; ulight_fifo.qsys ;; Altera ; altera_avalon_sc_fifo ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rdata_fifo ; ulight_fifo.qsys ;; Altera ; altera_avalon_sc_fifo ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rsp_fifo ; ulight_fifo.qsys ;; Altera ; altera_merlin_burst_adapter ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter ; ulight_fifo.qsys ;; Altera ; altera_merlin_slave_translator ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_enable_s1_translator ; ulight_fifo.qsys ;; Altera ; altera_merlin_slave_agent ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_tx_ready_s1_agent ; ulight_fifo.qsys ;; Altera ; altera_avalon_sc_fifo ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rdata_fifo ; ulight_fifo.qsys ;; Altera ; altera_avalon_sc_fifo ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rsp_fifo ; ulight_fifo.qsys ;; Altera ; altera_merlin_burst_adapter ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter ; ulight_fifo.qsys ;; Altera ; altera_merlin_slave_translator ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_ready_s1_translator ; ulight_fifo.qsys ;; Altera ; altera_merlin_slave_agent ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:write_data_fifo_tx_s1_agent ; ulight_fifo.qsys ;; Altera ; altera_avalon_sc_fifo ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rdata_fifo ; ulight_fifo.qsys ;; Altera ; altera_avalon_sc_fifo ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rsp_fifo ; ulight_fifo.qsys ;; Altera ; altera_merlin_burst_adapter ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter ; ulight_fifo.qsys ;; Altera ; altera_merlin_slave_translator ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:write_data_fifo_tx_s1_translator ; ulight_fifo.qsys ;; Altera ; altera_merlin_slave_agent ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:write_en_tx_s1_agent ; ulight_fifo.qsys ;; Altera ; altera_avalon_sc_fifo ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo ; ulight_fifo.qsys ;; Altera ; altera_avalon_sc_fifo ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rsp_fifo ; ulight_fifo.qsys ;; Altera ; altera_merlin_burst_adapter ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter ; ulight_fifo.qsys ;; Altera ; altera_merlin_slave_translator ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:write_en_tx_s1_translator ; ulight_fifo.qsys ;; Altera ; altera_pll ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_pll_0:pll_0 ; ulight_fifo.qsys ;; Altera ; altera_reset_controller ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|altera_reset_controller:rst_controller ; ulight_fifo.qsys ;; Altera ; altera_reset_controller ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|altera_reset_controller:rst_controller_001 ; ulight_fifo.qsys ;; Altera ; altera_avalon_pio ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:timecode_ready_rx ; ulight_fifo.qsys ;; Altera ; altera_avalon_pio ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_timecode_rx:timecode_rx ; ulight_fifo.qsys ;; Altera ; altera_avalon_pio ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_timecode_tx_data:timecode_tx_data ; ulight_fifo.qsys ;; Altera ; altera_avalon_pio ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_auto_start:timecode_tx_enable ; ulight_fifo.qsys ;; Altera ; altera_avalon_pio ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:timecode_tx_ready ; ulight_fifo.qsys ;; Altera ; altera_avalon_pio ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_write_data_fifo_tx:write_data_fifo_tx ; ulight_fifo.qsys ;; Altera ; altera_avalon_pio ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_auto_start:write_en_tx ; ulight_fifo.qsys ;+--------+--------------------------------+---------+--------------+--------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------+Encoding Type: Safe One-Hot+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; State Machine - |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state ;+-----------------------------+---------------+-----------------------------+-----------------------+------------------------------------------------------------------------------------------------------------------------------------------------+; Name ; state.ST_IDLE ; state.ST_UNCOMP_WR_SUBBURST ; state.ST_UNCOMP_TRANS ; state.ST_COMP_TRANS ;+-----------------------------+---------------+-----------------------------+-----------------------+------------------------------------------------------------------------------------------------------------------------------------------------+; state.ST_IDLE ; 0 ; 0 ; 0 ; 0 ;; state.ST_COMP_TRANS ; 1 ; 0 ; 0 ; 1 ;; state.ST_UNCOMP_TRANS ; 1 ; 0 ; 1 ; 0 ;; state.ST_UNCOMP_WR_SUBBURST ; 1 ; 1 ; 0 ; 0 ;+-----------------------------+---------------+-----------------------------+-----------------------+------------------------------------------------------------------------------------------------------------------------------------------------+Encoding Type: Safe One-Hot+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; State Machine - |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state ;+-----------------------------+---------------+-----------------------------+-----------------------+------------------------------------------------------------------------------------------------------------------------------------------------+; Name ; state.ST_IDLE ; state.ST_UNCOMP_WR_SUBBURST ; state.ST_UNCOMP_TRANS ; state.ST_COMP_TRANS ;+-----------------------------+---------------+-----------------------------+-----------------------+------------------------------------------------------------------------------------------------------------------------------------------------+; state.ST_IDLE ; 0 ; 0 ; 0 ; 0 ;; state.ST_COMP_TRANS ; 1 ; 0 ; 0 ; 1 ;; state.ST_UNCOMP_TRANS ; 1 ; 0 ; 1 ; 0 ;; state.ST_UNCOMP_WR_SUBBURST ; 1 ; 1 ; 0 ; 0 ;+-----------------------------+---------------+-----------------------------+-----------------------+------------------------------------------------------------------------------------------------------------------------------------------------+Encoding Type: Safe One-Hot+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; State Machine - |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state ;+-----------------------------+---------------+-----------------------------+-----------------------+-----------------------------------------------------------------------------------------------------------------------------------------+; Name ; state.ST_IDLE ; state.ST_UNCOMP_WR_SUBBURST ; state.ST_UNCOMP_TRANS ; state.ST_COMP_TRANS ;+-----------------------------+---------------+-----------------------------+-----------------------+-----------------------------------------------------------------------------------------------------------------------------------------+; state.ST_IDLE ; 0 ; 0 ; 0 ; 0 ;; state.ST_COMP_TRANS ; 1 ; 0 ; 0 ; 1 ;; state.ST_UNCOMP_TRANS ; 1 ; 0 ; 1 ; 0 ;; state.ST_UNCOMP_WR_SUBBURST ; 1 ; 1 ; 0 ; 0 ;+-----------------------------+---------------+-----------------------------+-----------------------+-----------------------------------------------------------------------------------------------------------------------------------------+Encoding Type: Safe One-Hot+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; State Machine - |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state ;+-----------------------------+---------------+-----------------------------+-----------------------+------------------------------------------------------------------------------------------------------------------------------------------+; Name ; state.ST_IDLE ; state.ST_UNCOMP_WR_SUBBURST ; state.ST_UNCOMP_TRANS ; state.ST_COMP_TRANS ;+-----------------------------+---------------+-----------------------------+-----------------------+------------------------------------------------------------------------------------------------------------------------------------------+; state.ST_IDLE ; 0 ; 0 ; 0 ; 0 ;; state.ST_COMP_TRANS ; 1 ; 0 ; 0 ; 1 ;; state.ST_UNCOMP_TRANS ; 1 ; 0 ; 1 ; 0 ;; state.ST_UNCOMP_WR_SUBBURST ; 1 ; 1 ; 0 ; 0 ;+-----------------------------+---------------+-----------------------------+-----------------------+------------------------------------------------------------------------------------------------------------------------------------------+Encoding Type: Safe One-Hot+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; State Machine - |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state ;+-----------------------------+---------------+-----------------------------+-----------------------+------------------------------------------------------------------------------------------------------------------------------------------+; Name ; state.ST_IDLE ; state.ST_UNCOMP_WR_SUBBURST ; state.ST_UNCOMP_TRANS ; state.ST_COMP_TRANS ;+-----------------------------+---------------+-----------------------------+-----------------------+------------------------------------------------------------------------------------------------------------------------------------------+; state.ST_IDLE ; 0 ; 0 ; 0 ; 0 ;; state.ST_COMP_TRANS ; 1 ; 0 ; 0 ; 1 ;; state.ST_UNCOMP_TRANS ; 1 ; 0 ; 1 ; 0 ;; state.ST_UNCOMP_WR_SUBBURST ; 1 ; 1 ; 0 ; 0 ;+-----------------------------+---------------+-----------------------------+-----------------------+------------------------------------------------------------------------------------------------------------------------------------------+Encoding Type: Safe One-Hot+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; State Machine - |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state ;+-----------------------------+---------------+-----------------------------+-----------------------+--------------------------------------------------------------------------------------------------------------------------------------------------+; Name ; state.ST_IDLE ; state.ST_UNCOMP_WR_SUBBURST ; state.ST_UNCOMP_TRANS ; state.ST_COMP_TRANS ;+-----------------------------+---------------+-----------------------------+-----------------------+--------------------------------------------------------------------------------------------------------------------------------------------------+; state.ST_IDLE ; 0 ; 0 ; 0 ; 0 ;; state.ST_COMP_TRANS ; 1 ; 0 ; 0 ; 1 ;; state.ST_UNCOMP_TRANS ; 1 ; 0 ; 1 ; 0 ;; state.ST_UNCOMP_WR_SUBBURST ; 1 ; 1 ; 0 ; 0 ;+-----------------------------+---------------+-----------------------------+-----------------------+--------------------------------------------------------------------------------------------------------------------------------------------------+Encoding Type: Safe One-Hot+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; State Machine - |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state ;+-----------------------------+---------------+-----------------------------+-----------------------+---------------------------------------------------------------------------------------------------------------------------------------------------+; Name ; state.ST_IDLE ; state.ST_UNCOMP_WR_SUBBURST ; state.ST_UNCOMP_TRANS ; state.ST_COMP_TRANS ;+-----------------------------+---------------+-----------------------------+-----------------------+---------------------------------------------------------------------------------------------------------------------------------------------------+; state.ST_IDLE ; 0 ; 0 ; 0 ; 0 ;; state.ST_COMP_TRANS ; 1 ; 0 ; 0 ; 1 ;; state.ST_UNCOMP_TRANS ; 1 ; 0 ; 1 ; 0 ;; state.ST_UNCOMP_WR_SUBBURST ; 1 ; 1 ; 0 ; 0 ;+-----------------------------+---------------+-----------------------------+-----------------------+---------------------------------------------------------------------------------------------------------------------------------------------------+Encoding Type: Safe One-Hot+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; State Machine - |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state ;+-----------------------------+---------------+-----------------------------+-----------------------+-------------------------------------------------------------------------------------------------------------------------------------------------+; Name ; state.ST_IDLE ; state.ST_UNCOMP_WR_SUBBURST ; state.ST_UNCOMP_TRANS ; state.ST_COMP_TRANS ;+-----------------------------+---------------+-----------------------------+-----------------------+-------------------------------------------------------------------------------------------------------------------------------------------------+; state.ST_IDLE ; 0 ; 0 ; 0 ; 0 ;; state.ST_COMP_TRANS ; 1 ; 0 ; 0 ; 1 ;; state.ST_UNCOMP_TRANS ; 1 ; 0 ; 1 ; 0 ;; state.ST_UNCOMP_WR_SUBBURST ; 1 ; 1 ; 0 ; 0 ;+-----------------------------+---------------+-----------------------------+-----------------------+-------------------------------------------------------------------------------------------------------------------------------------------------+Encoding Type: Safe One-Hot+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; State Machine - |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state ;+-----------------------------+---------------+-----------------------------+-----------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+; Name ; state.ST_IDLE ; state.ST_UNCOMP_WR_SUBBURST ; state.ST_UNCOMP_TRANS ; state.ST_COMP_TRANS ;+-----------------------------+---------------+-----------------------------+-----------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+; state.ST_IDLE ; 0 ; 0 ; 0 ; 0 ;; state.ST_COMP_TRANS ; 1 ; 0 ; 0 ; 1 ;; state.ST_UNCOMP_TRANS ; 1 ; 0 ; 1 ; 0 ;; state.ST_UNCOMP_WR_SUBBURST ; 1 ; 1 ; 0 ; 0 ;+-----------------------------+---------------+-----------------------------+-----------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+Encoding Type: Safe One-Hot+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; State Machine - |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state ;+-----------------------------+---------------+-----------------------------+-----------------------+----------------------------------------------------------------------------------------------------------------------------------------------------+; Name ; state.ST_IDLE ; state.ST_UNCOMP_WR_SUBBURST ; state.ST_UNCOMP_TRANS ; state.ST_COMP_TRANS ;+-----------------------------+---------------+-----------------------------+-----------------------+----------------------------------------------------------------------------------------------------------------------------------------------------+; state.ST_IDLE ; 0 ; 0 ; 0 ; 0 ;; state.ST_COMP_TRANS ; 1 ; 0 ; 0 ; 1 ;; state.ST_UNCOMP_TRANS ; 1 ; 0 ; 1 ; 0 ;; state.ST_UNCOMP_WR_SUBBURST ; 1 ; 1 ; 0 ; 0 ;+-----------------------------+---------------+-----------------------------+-----------------------+----------------------------------------------------------------------------------------------------------------------------------------------------+Encoding Type: Safe One-Hot+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; State Machine - |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state ;+-----------------------------+---------------+-----------------------------+-----------------------+--------------------------------------------------------------------------------------------------------------------------------------------+; Name ; state.ST_IDLE ; state.ST_UNCOMP_WR_SUBBURST ; state.ST_UNCOMP_TRANS ; state.ST_COMP_TRANS ;+-----------------------------+---------------+-----------------------------+-----------------------+--------------------------------------------------------------------------------------------------------------------------------------------+; state.ST_IDLE ; 0 ; 0 ; 0 ; 0 ;; state.ST_COMP_TRANS ; 1 ; 0 ; 0 ; 1 ;; state.ST_UNCOMP_TRANS ; 1 ; 0 ; 1 ; 0 ;; state.ST_UNCOMP_WR_SUBBURST ; 1 ; 1 ; 0 ; 0 ;+-----------------------------+---------------+-----------------------------+-----------------------+--------------------------------------------------------------------------------------------------------------------------------------------+Encoding Type: Safe One-Hot+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; State Machine - |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state ;+-----------------------------+---------------+-----------------------------+-----------------------+---------------------------------------------------------------------------------------------------------------------------------------------------+; Name ; state.ST_IDLE ; state.ST_UNCOMP_WR_SUBBURST ; state.ST_UNCOMP_TRANS ; state.ST_COMP_TRANS ;+-----------------------------+---------------+-----------------------------+-----------------------+---------------------------------------------------------------------------------------------------------------------------------------------------+; state.ST_IDLE ; 0 ; 0 ; 0 ; 0 ;; state.ST_COMP_TRANS ; 1 ; 0 ; 0 ; 1 ;; state.ST_UNCOMP_TRANS ; 1 ; 0 ; 1 ; 0 ;; state.ST_UNCOMP_WR_SUBBURST ; 1 ; 1 ; 0 ; 0 ;+-----------------------------+---------------+-----------------------------+-----------------------+---------------------------------------------------------------------------------------------------------------------------------------------------+Encoding Type: Safe One-Hot+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; State Machine - |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state ;+-----------------------------+---------------+-----------------------------+-----------------------+---------------------------------------------------------------------------------------------------------------------------------------------+; Name ; state.ST_IDLE ; state.ST_UNCOMP_WR_SUBBURST ; state.ST_UNCOMP_TRANS ; state.ST_COMP_TRANS ;+-----------------------------+---------------+-----------------------------+-----------------------+---------------------------------------------------------------------------------------------------------------------------------------------+; state.ST_IDLE ; 0 ; 0 ; 0 ; 0 ;; state.ST_COMP_TRANS ; 1 ; 0 ; 0 ; 1 ;; state.ST_UNCOMP_TRANS ; 1 ; 0 ; 1 ; 0 ;; state.ST_UNCOMP_WR_SUBBURST ; 1 ; 1 ; 0 ; 0 ;+-----------------------------+---------------+-----------------------------+-----------------------+---------------------------------------------------------------------------------------------------------------------------------------------+Encoding Type: Safe One-Hot+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; State Machine - |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state ;+-----------------------------+---------------+-----------------------------+-----------------------+-------------------------------------------------------------------------------------------------------------------------------------------+; Name ; state.ST_IDLE ; state.ST_UNCOMP_WR_SUBBURST ; state.ST_UNCOMP_TRANS ; state.ST_COMP_TRANS ;+-----------------------------+---------------+-----------------------------+-----------------------+-------------------------------------------------------------------------------------------------------------------------------------------+; state.ST_IDLE ; 0 ; 0 ; 0 ; 0 ;; state.ST_COMP_TRANS ; 1 ; 0 ; 0 ; 1 ;; state.ST_UNCOMP_TRANS ; 1 ; 0 ; 1 ; 0 ;; state.ST_UNCOMP_WR_SUBBURST ; 1 ; 1 ; 0 ; 0 ;+-----------------------------+---------------+-----------------------------+-----------------------+-------------------------------------------------------------------------------------------------------------------------------------------+Encoding Type: Safe One-Hot+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; State Machine - |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state ;+-----------------------------+---------------+-----------------------------+-----------------------+-------------------------------------------------------------------------------------------------------------------------------------------+; Name ; state.ST_IDLE ; state.ST_UNCOMP_WR_SUBBURST ; state.ST_UNCOMP_TRANS ; state.ST_COMP_TRANS ;+-----------------------------+---------------+-----------------------------+-----------------------+-------------------------------------------------------------------------------------------------------------------------------------------+; state.ST_IDLE ; 0 ; 0 ; 0 ; 0 ;; state.ST_COMP_TRANS ; 1 ; 0 ; 0 ; 1 ;; state.ST_UNCOMP_TRANS ; 1 ; 0 ; 1 ; 0 ;; state.ST_UNCOMP_WR_SUBBURST ; 1 ; 1 ; 0 ; 0 ;+-----------------------------+---------------+-----------------------------+-----------------------+-------------------------------------------------------------------------------------------------------------------------------------------+Encoding Type: Safe One-Hot+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; State Machine - |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state ;+-----------------------------+---------------+-----------------------------+-----------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+; Name ; state.ST_IDLE ; state.ST_UNCOMP_WR_SUBBURST ; state.ST_UNCOMP_TRANS ; state.ST_COMP_TRANS ;+-----------------------------+---------------+-----------------------------+-----------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+; state.ST_IDLE ; 0 ; 0 ; 0 ; 0 ;; state.ST_COMP_TRANS ; 1 ; 0 ; 0 ; 1 ;; state.ST_UNCOMP_TRANS ; 1 ; 0 ; 1 ; 0 ;; state.ST_UNCOMP_WR_SUBBURST ; 1 ; 1 ; 0 ; 0 ;+-----------------------------+---------------+-----------------------------+-----------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+Encoding Type: Safe One-Hot+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; State Machine - |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state ;+-----------------------------+---------------+-----------------------------+-----------------------+----------------------------------------------------------------------------------------------------------------------------------------------------+; Name ; state.ST_IDLE ; state.ST_UNCOMP_WR_SUBBURST ; state.ST_UNCOMP_TRANS ; state.ST_COMP_TRANS ;+-----------------------------+---------------+-----------------------------+-----------------------+----------------------------------------------------------------------------------------------------------------------------------------------------+; state.ST_IDLE ; 0 ; 0 ; 0 ; 0 ;; state.ST_COMP_TRANS ; 1 ; 0 ; 0 ; 1 ;; state.ST_UNCOMP_TRANS ; 1 ; 0 ; 1 ; 0 ;; state.ST_UNCOMP_WR_SUBBURST ; 1 ; 1 ; 0 ; 0 ;+-----------------------------+---------------+-----------------------------+-----------------------+----------------------------------------------------------------------------------------------------------------------------------------------------+Encoding Type: Safe One-Hot+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; State Machine - |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state ;+-----------------------------+---------------+-----------------------------+-----------------------+------------------------------------------------------------------------------------------------------------------------------------------------+; Name ; state.ST_IDLE ; state.ST_UNCOMP_WR_SUBBURST ; state.ST_UNCOMP_TRANS ; state.ST_COMP_TRANS ;+-----------------------------+---------------+-----------------------------+-----------------------+------------------------------------------------------------------------------------------------------------------------------------------------+; state.ST_IDLE ; 0 ; 0 ; 0 ; 0 ;; state.ST_COMP_TRANS ; 1 ; 0 ; 0 ; 1 ;; state.ST_UNCOMP_TRANS ; 1 ; 0 ; 1 ; 0 ;; state.ST_UNCOMP_WR_SUBBURST ; 1 ; 1 ; 0 ; 0 ;+-----------------------------+---------------+-----------------------------+-----------------------+------------------------------------------------------------------------------------------------------------------------------------------------+Encoding Type: Safe One-Hot+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; State Machine - |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state ;+-----------------------------+---------------+-----------------------------+-----------------------+---------------------------------------------------------------------------------------------------------------------------------------------+; Name ; state.ST_IDLE ; state.ST_UNCOMP_WR_SUBBURST ; state.ST_UNCOMP_TRANS ; state.ST_COMP_TRANS ;+-----------------------------+---------------+-----------------------------+-----------------------+---------------------------------------------------------------------------------------------------------------------------------------------+; state.ST_IDLE ; 0 ; 0 ; 0 ; 0 ;; state.ST_COMP_TRANS ; 1 ; 0 ; 0 ; 1 ;; state.ST_UNCOMP_TRANS ; 1 ; 0 ; 1 ; 0 ;; state.ST_UNCOMP_WR_SUBBURST ; 1 ; 1 ; 0 ; 0 ;+-----------------------------+---------------+-----------------------------+-----------------------+---------------------------------------------------------------------------------------------------------------------------------------------+Encoding Type: Safe One-Hot+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; State Machine - |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state ;+-----------------------------+---------------+-----------------------------+-----------------------+--------------------------------------------------------------------------------------------------------------------------------------------------+; Name ; state.ST_IDLE ; state.ST_UNCOMP_WR_SUBBURST ; state.ST_UNCOMP_TRANS ; state.ST_COMP_TRANS ;+-----------------------------+---------------+-----------------------------+-----------------------+--------------------------------------------------------------------------------------------------------------------------------------------------+; state.ST_IDLE ; 0 ; 0 ; 0 ; 0 ;; state.ST_COMP_TRANS ; 1 ; 0 ; 0 ; 1 ;; state.ST_UNCOMP_TRANS ; 1 ; 0 ; 1 ; 0 ;; state.ST_UNCOMP_WR_SUBBURST ; 1 ; 1 ; 0 ; 0 ;+-----------------------------+---------------+-----------------------------+-----------------------+--------------------------------------------------------------------------------------------------------------------------------------------------+Encoding Type: Safe One-Hot+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; State Machine - |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state ;+-----------------------------+---------------+-----------------------------+-----------------------+--------------------------------------------------------------------------------------------------------------------------------------------+; Name ; state.ST_IDLE ; state.ST_UNCOMP_WR_SUBBURST ; state.ST_UNCOMP_TRANS ; state.ST_COMP_TRANS ;+-----------------------------+---------------+-----------------------------+-----------------------+--------------------------------------------------------------------------------------------------------------------------------------------+; state.ST_IDLE ; 0 ; 0 ; 0 ; 0 ;; state.ST_COMP_TRANS ; 1 ; 0 ; 0 ; 1 ;; state.ST_UNCOMP_TRANS ; 1 ; 0 ; 1 ; 0 ;; state.ST_UNCOMP_WR_SUBBURST ; 1 ; 1 ; 0 ; 0 ;+-----------------------------+---------------+-----------------------------+-----------------------+--------------------------------------------------------------------------------------------------------------------------------------------+Encoding Type: Safe One-Hot+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; State Machine - |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state ;+-----------------------------+---------------+-----------------------------+-----------------------+---------------------------------------------------------------------------------------------------------------------------------------------+; Name ; state.ST_IDLE ; state.ST_UNCOMP_WR_SUBBURST ; state.ST_UNCOMP_TRANS ; state.ST_COMP_TRANS ;+-----------------------------+---------------+-----------------------------+-----------------------+---------------------------------------------------------------------------------------------------------------------------------------------+; state.ST_IDLE ; 0 ; 0 ; 0 ; 0 ;; state.ST_COMP_TRANS ; 1 ; 0 ; 0 ; 1 ;; state.ST_UNCOMP_TRANS ; 1 ; 0 ; 1 ; 0 ;; state.ST_UNCOMP_WR_SUBBURST ; 1 ; 1 ; 0 ; 0 ;+-----------------------------+---------------+-----------------------------+-----------------------+---------------------------------------------------------------------------------------------------------------------------------------------+Encoding Type: Safe One-Hot+-------------------------------------------------------------------------+; State Machine - |SPW_ULIGHT_FIFO|detector_tokens:m_x|state_data_process ;+-----------------------+-------------------------------------------------+; Name ; state_data_process.01 ;+-----------------------+-------------------------------------------------+; state_data_process.00 ; 0 ;; state_data_process.01 ; 1 ;+-----------------------+-------------------------------------------------+Encoding Type: Safe One-Hot+-------------------------------------------------------------------------------------------------+; State Machine - |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|state_open_slot ;+--------------------+--------------------+--------------------+----------------------------------+; Name ; state_open_slot.00 ; state_open_slot.10 ; state_open_slot.01 ;+--------------------+--------------------+--------------------+----------------------------------+; state_open_slot.00 ; 0 ; 0 ; 0 ;; state_open_slot.01 ; 1 ; 0 ; 1 ;; state_open_slot.10 ; 1 ; 1 ; 0 ;+--------------------+--------------------+--------------------+----------------------------------+Encoding Type: Safe One-Hot+--------------------------------------------------------------------------------------------------+; State Machine - |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|state_data_write ;+---------------------+---------------------+---------------------+--------------------------------+; Name ; state_data_write.00 ; state_data_write.10 ; state_data_write.01 ;+---------------------+---------------------+---------------------+--------------------------------+; state_data_write.00 ; 0 ; 0 ; 0 ;; state_data_write.01 ; 1 ; 0 ; 1 ;; state_data_write.10 ; 1 ; 1 ; 0 ;+---------------------+---------------------+---------------------+--------------------------------+Encoding Type: Safe One-Hot+-------------------------------------------------------------------------------------------------+; State Machine - |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|state_data_read ;+--------------------+--------------------+--------------------+----------------------------------+; Name ; state_data_read.00 ; state_data_read.10 ; state_data_read.01 ;+--------------------+--------------------+--------------------+----------------------------------+; state_data_read.00 ; 0 ; 0 ; 0 ;; state_data_read.01 ; 1 ; 0 ; 1 ;; state_data_read.10 ; 1 ; 1 ; 0 ;+--------------------+--------------------+--------------------+----------------------------------+Encoding Type: Safe One-Hot+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; State Machine - |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i|dps_extra_kick:dps_extra_inst|dps_current_state ;+------------------------------------+------------------------------------+------------------------------------+------------------------------------+------------------------------------+------------------------------------+-----------------------------------+; Name ; dps_current_state.PHASE_DONE_LOW_0 ; dps_current_state.PHASE_DONE_LOW_4 ; dps_current_state.PHASE_DONE_LOW_3 ; dps_current_state.PHASE_DONE_LOW_2 ; dps_current_state.PHASE_DONE_LOW_1 ; dps_current_state.PHASE_DONE_HIGH ;+------------------------------------+------------------------------------+------------------------------------+------------------------------------+------------------------------------+------------------------------------+-----------------------------------+; dps_current_state.PHASE_DONE_HIGH ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;; dps_current_state.PHASE_DONE_LOW_1 ; 0 ; 0 ; 0 ; 0 ; 1 ; 1 ;; dps_current_state.PHASE_DONE_LOW_2 ; 0 ; 0 ; 0 ; 1 ; 0 ; 1 ;; dps_current_state.PHASE_DONE_LOW_3 ; 0 ; 0 ; 1 ; 0 ; 0 ; 1 ;; dps_current_state.PHASE_DONE_LOW_4 ; 0 ; 1 ; 0 ; 0 ; 0 ; 1 ;; dps_current_state.PHASE_DONE_LOW_0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 1 ;+------------------------------------+------------------------------------+------------------------------------+------------------------------------+------------------------------------+------------------------------------+-----------------------------------+Encoding Type: Safe One-Hot+--------------------------------------------------------------------------------------------------------+; State Machine - |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|state_data_read ;+--------------------+--------------------+--------------------+--------------------+--------------------+; Name ; state_data_read.11 ; state_data_read.10 ; state_data_read.01 ; state_data_read.00 ;+--------------------+--------------------+--------------------+--------------------+--------------------+; state_data_read.00 ; 0 ; 0 ; 0 ; 0 ;; state_data_read.01 ; 0 ; 0 ; 1 ; 1 ;; state_data_read.10 ; 0 ; 1 ; 0 ; 1 ;; state_data_read.11 ; 1 ; 0 ; 0 ; 1 ;+--------------------+--------------------+--------------------+--------------------+--------------------+Encoding Type: Safe One-Hot+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; State Machine - |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|state_tx ;+-----------------------------+-----------------------------+--------------------------+------------------------+-----------------------+------------------------+---------------------+----------------------+-----------------------+; Name ; state_tx.tx_spw_time_code_c ; state_tx.tx_spw_data_c_0 ; state_tx.tx_spw_data_c ; state_tx.tx_spw_fct_c ; state_tx.tx_spw_null_c ; state_tx.tx_spw_fct ; state_tx.tx_spw_null ; state_tx.tx_spw_start ;+-----------------------------+-----------------------------+--------------------------+------------------------+-----------------------+------------------------+---------------------+----------------------+-----------------------+; state_tx.tx_spw_start ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;; state_tx.tx_spw_null ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 1 ;; state_tx.tx_spw_fct ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 1 ;; state_tx.tx_spw_null_c ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 1 ;; state_tx.tx_spw_fct_c ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 1 ;; state_tx.tx_spw_data_c ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 1 ;; state_tx.tx_spw_data_c_0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ;; state_tx.tx_spw_time_code_c ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ;+-----------------------------+-----------------------------+--------------------------+------------------------+-----------------------+------------------------+---------------------+----------------------+-----------------------+Encoding Type: Safe One-Hot+---------------------------------------------------------------------------------------------------------------------------------------------------------+; State Machine - |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_send:tx_fct_snd|state_fct_send ;+--------------------+------------------------------------------------------------------------------------------------------------------------------------+; Name ; state_fct_send.001 ;+--------------------+------------------------------------------------------------------------------------------------------------------------------------+; state_fct_send.000 ; 0 ;; state_fct_send.001 ; 1 ;+--------------------+------------------------------------------------------------------------------------------------------------------------------------+Encoding Type: Safe One-Hot+-----------------------------------------------------------------------------------------------------------------------------------------------------------+; State Machine - |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_send:tx_fct_snd|state_fct_send_p ;+----------------------+----------------------+----------------------+--------------------------------------------------------------------------------------+; Name ; state_fct_send_p.000 ; state_fct_send_p.010 ; state_fct_send_p.001 ;+----------------------+----------------------+----------------------+--------------------------------------------------------------------------------------+; state_fct_send_p.001 ; 0 ; 0 ; 0 ;; state_fct_send_p.000 ; 1 ; 0 ; 1 ;; state_fct_send_p.010 ; 0 ; 1 ; 1 ;+----------------------+----------------------+----------------------+--------------------------------------------------------------------------------------+Encoding Type: Safe One-Hot+---------------------------------------------------------------------------------------------------------------------------------------------------------+; State Machine - |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_counter:tx_fct_cnt|state_fct_p ;+-----------------+-----------------+-----------------+-----------------+-----------------+---------------------------------------------------------------+; Name ; state_fct_p.011 ; state_fct_p.010 ; state_fct_p.001 ; state_fct_p.000 ; state_fct_p.100 ;+-----------------+-----------------+-----------------+-----------------+-----------------+---------------------------------------------------------------+; state_fct_p.000 ; 0 ; 0 ; 0 ; 0 ; 0 ;; state_fct_p.001 ; 0 ; 0 ; 1 ; 1 ; 0 ;; state_fct_p.010 ; 0 ; 1 ; 0 ; 1 ; 0 ;; state_fct_p.011 ; 1 ; 0 ; 0 ; 1 ; 0 ;; state_fct_p.100 ; 0 ; 0 ; 0 ; 1 ; 1 ;+-----------------+-----------------+-----------------+-----------------+-----------------+---------------------------------------------------------------+Encoding Type: Safe One-Hot+--------------------------------------------------------------------------------------------------+; State Machine - |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|state_data_write ;+---------------------+---------------------+---------------------+--------------------------------+; Name ; state_data_write.00 ; state_data_write.10 ; state_data_write.01 ;+---------------------+---------------------+---------------------+--------------------------------+; state_data_write.00 ; 0 ; 0 ; 0 ;; state_data_write.01 ; 1 ; 0 ; 1 ;; state_data_write.10 ; 1 ; 1 ; 0 ;+---------------------+---------------------+---------------------+--------------------------------+Encoding Type: Safe One-Hot+---------------------------------------------------------------------------------------------------------------------------------------------------------------+; State Machine - |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_counter:tx_fct_cnt|state_fct_receive ;+-----------------------+-----------------------+-----------------------+-----------------------+-----------------------+---------------------------------------+; Name ; state_fct_receive.011 ; state_fct_receive.010 ; state_fct_receive.001 ; state_fct_receive.000 ; state_fct_receive.100 ;+-----------------------+-----------------------+-----------------------+-----------------------+-----------------------+---------------------------------------+; state_fct_receive.000 ; 0 ; 0 ; 0 ; 0 ; 0 ;; state_fct_receive.001 ; 0 ; 0 ; 1 ; 1 ; 0 ;; state_fct_receive.010 ; 0 ; 1 ; 0 ; 1 ; 0 ;; state_fct_receive.011 ; 1 ; 0 ; 0 ; 1 ; 0 ;; state_fct_receive.100 ; 0 ; 0 ; 0 ; 1 ; 1 ;+-----------------------+-----------------------+-----------------------+-----------------------+-----------------------+---------------------------------------+Encoding Type: Safe One-Hot+---------------------------------------------------------------------------------------------------------------------------------------------------+; State Machine - |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|state_fsm ;+-----------------------+-----------------------+---------------+----------------------+-------------------+-----------------+----------------------+; Name ; state_fsm.error_reset ; state_fsm.run ; state_fsm.connecting ; state_fsm.started ; state_fsm.ready ; state_fsm.error_wait ;+-----------------------+-----------------------+---------------+----------------------+-------------------+-----------------+----------------------+; state_fsm.error_reset ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;; state_fsm.error_wait ; 1 ; 0 ; 0 ; 0 ; 0 ; 1 ;; state_fsm.ready ; 1 ; 0 ; 0 ; 0 ; 1 ; 0 ;; state_fsm.started ; 1 ; 0 ; 0 ; 1 ; 0 ; 0 ;; state_fsm.connecting ; 1 ; 0 ; 1 ; 0 ; 0 ; 0 ;; state_fsm.run ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ;+-----------------------+-----------------------+---------------+----------------------+-------------------+-----------------+----------------------++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Registers Protected by Synthesis ;+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------+--------------------------------------------+; Register Name ; Protected by Synthesis Attribute or Preserve Register Assignment ; Not to be Touched by Netlist Optimizations ;+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------+--------------------------------------------+; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|rd_ptr[5] ; yes ; yes ;; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|rd_ptr[4] ; yes ; yes ;; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|rd_ptr[3] ; yes ; yes ;; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|rd_ptr[2] ; yes ; yes ;; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|rd_ptr[1] ; yes ; yes ;; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|rd_ptr[0] ; yes ; yes ;; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|wr_ptr[5] ; yes ; yes ;; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|wr_ptr[4] ; yes ; yes ;; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|wr_ptr[3] ; yes ; yes ;; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|wr_ptr[2] ; yes ; yes ;; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|wr_ptr[1] ; yes ; yes ;; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|wr_ptr[0] ; yes ; yes ;; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|counter_writer[5] ; yes ; yes ;; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|counter_writer[4] ; yes ; yes ;; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|counter_writer[3] ; yes ; yes ;; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|counter_writer[2] ; yes ; yes ;; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|counter_writer[1] ; yes ; yes ;; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|counter_writer[0] ; yes ; yes ;; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|counter_reader[5] ; yes ; yes ;; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|counter_reader[4] ; yes ; yes ;; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|counter_reader[3] ; yes ; yes ;; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|counter_reader[2] ; yes ; yes ;; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|counter_reader[1] ; yes ; yes ;; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|counter_reader[0] ; yes ; yes ;; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|state_data_read.00 ; no ; yes ;; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|state_data_read.01 ; no ; yes ;; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|state_data_read.10 ; no ; yes ;; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|state_data_read.11 ; no ; yes ;; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|state_data_write.01 ; no ; yes ;; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|state_data_write.10 ; no ; yes ;; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|state_data_write.00 ; no ; yes ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|state_fsm.run ; no ; yes ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|state_tx.tx_spw_data_c_0 ; no ; yes ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|state_tx.tx_spw_null ; no ; yes ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|state_tx.tx_spw_null_c ; no ; yes ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|state_tx.tx_spw_fct ; no ; yes ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|state_tx.tx_spw_fct_c ; no ; yes ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|state_tx.tx_spw_data_c ; no ; yes ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|state_tx.tx_spw_time_code_c ; no ; yes ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|state_tx.tx_spw_start ; no ; yes ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|state_fsm.connecting ; no ; yes ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|state_fsm.error_wait ; no ; yes ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|state_fsm.ready ; no ; yes ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|state_fsm.started ; no ; yes ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|state_fsm.error_reset ; no ; yes ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS ; no ; yes ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS ; no ; yes ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST ; no ; yes ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS ; no ; yes ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS ; no ; yes ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST ; no ; yes ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS ; no ; yes ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS ; no ; yes ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST ; no ; yes ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS ; no ; yes ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS ; no ; yes ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST ; no ; yes ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS ; no ; yes ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS ; no ; yes ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST ; no ; yes ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS ; no ; yes ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS ; no ; yes ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST ; no ; yes ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS ; no ; yes ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS ; no ; yes ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST ; no ; yes ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS ; no ; yes ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS ; no ; yes ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST ; no ; yes ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS ; no ; yes ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS ; no ; yes ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST ; no ; yes ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS ; no ; yes ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS ; no ; yes ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST ; no ; yes ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS ; no ; yes ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS ; no ; yes ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST ; no ; yes ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS ; no ; yes ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS ; no ; yes ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST ; no ; yes ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS ; no ; yes ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS ; no ; yes ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST ; no ; yes ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS ; no ; yes ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS ; no ; yes ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST ; no ; yes ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS ; no ; yes ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS ; no ; yes ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST ; no ; yes ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS ; no ; yes ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS ; no ; yes ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST ; no ; yes ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS ; no ; yes ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS ; no ; yes ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST ; no ; yes ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS ; no ; yes ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS ; no ; yes ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST ; no ; yes ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS ; no ; yes ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS ; no ; yes ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST ; no ; yes ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS ; no ; yes ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS ; no ; yes ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST ; no ; yes ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS ; no ; yes ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS ; no ; yes ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST ; no ; yes ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS ; no ; yes ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS ; no ; yes ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST ; no ; yes ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_counter:tx_fct_cnt|state_fct_p.011 ; no ; yes ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_counter:tx_fct_cnt|state_fct_p.001 ; no ; yes ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_send:tx_fct_snd|state_fct_send_p.010 ; no ; yes ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_send:tx_fct_snd|state_fct_send_p.000 ; no ; yes ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE ; no ; yes ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE ; no ; yes ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE ; no ; yes ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE ; no ; yes ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE ; no ; yes ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE ; no ; yes ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE ; no ; yes ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE ; no ; yes ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE ; no ; yes ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE ; no ; yes ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE ; no ; yes ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE ; no ; yes ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE ; no ; yes ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE ; no ; yes ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE ; no ; yes ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE ; no ; yes ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE ; no ; yes ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE ; no ; yes ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE ; no ; yes ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE ; no ; yes ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE ; no ; yes ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE ; no ; yes ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_counter:tx_fct_cnt|state_fct_p.010 ; no ; yes ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_counter:tx_fct_cnt|state_fct_p.100 ; no ; yes ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_counter:tx_fct_cnt|state_fct_p.000 ; no ; yes ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_send:tx_fct_snd|state_fct_send_p.001 ; no ; yes ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_send:tx_fct_snd|state_fct_send.001 ; no ; yes ;; ulight_fifo:u0|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain[0] ; yes ; yes ;; ulight_fifo:u0|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain[1] ; yes ; yes ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|rx_data_receive:rx_dtarcv|last_is_data ; no ; yes ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|rx_data_receive:rx_dtarcv|last_is_timec ; no ; yes ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_counter:tx_fct_cnt|state_fct_receive.001 ; no ; yes ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_counter:tx_fct_cnt|state_fct_receive.100 ; no ; yes ;; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|state_open_slot.00 ; no ; yes ;; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|state_open_slot.01 ; no ; yes ;; ulight_fifo:u0|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain[0] ; yes ; yes ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|rx_data_receive:rx_dtarcv|timecode[0] ; no ; yes ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|rx_data_receive:rx_dtarcv|timecode[1] ; no ; yes ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|rx_data_receive:rx_dtarcv|timecode[2] ; no ; yes ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|rx_data_receive:rx_dtarcv|timecode[3] ; no ; yes ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|rx_data_receive:rx_dtarcv|timecode[4] ; no ; yes ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|rx_data_receive:rx_dtarcv|timecode[5] ; no ; yes ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|rx_data_receive:rx_dtarcv|timecode[6] ; no ; yes ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|rx_data_receive:rx_dtarcv|timecode[7] ; no ; yes ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|rx_data_receive:rx_dtarcv|rx_error_c ; no ; yes ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|rx_data_receive:rx_dtarcv|rx_error_d ; no ; yes ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|rx_data_receive:rx_dtarcv|last_is_control ; no ; yes ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|rx_data_receive:rx_dtarcv|state_data_process[0] ; no ; yes ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_counter:tx_fct_cnt|state_fct_receive.000 ; no ; yes ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_counter:tx_fct_cnt|state_fct_receive.010 ; no ; yes ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_counter:tx_fct_cnt|state_fct_receive.011 ; no ; yes ;; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|state_data_read.00 ; no ; yes ;; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|state_open_slot.10 ; no ; yes ;; ulight_fifo:u0|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain[1] ; yes ; yes ;; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|state_data_write.10 ; no ; yes ;; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|state_data_read.01 ; no ; yes ;; detector_tokens:m_x|state_data_process.01 ; no ; yes ;; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|state_data_read.10 ; no ; yes ;; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|state_data_write.01 ; no ; yes ;; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|state_data_write.00 ; no ; yes ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|rx_data_receive:rx_dtarcv|rx_data_flag[0] ; no ; yes ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|rx_data_receive:rx_dtarcv|rx_data_flag[1] ; no ; yes ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|rx_data_receive:rx_dtarcv|rx_data_flag[2] ; no ; yes ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|rx_data_receive:rx_dtarcv|rx_data_flag[3] ; no ; yes ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|rx_data_receive:rx_dtarcv|rx_data_flag[4] ; no ; yes ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|rx_data_receive:rx_dtarcv|rx_data_flag[5] ; no ; yes ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|rx_data_receive:rx_dtarcv|rx_data_flag[6] ; no ; yes ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|rx_data_receive:rx_dtarcv|rx_data_flag[7] ; no ; yes ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|rx_data_receive:rx_dtarcv|rx_data_flag[8] ; no ; yes ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|rx_data_receive:rx_dtarcv|rx_got_fct ; no ; yes ;; Total number of protected registers is 185 ; ; ;+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------+--------------------------------------------++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Registers Removed During Synthesis ;+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------+; Register name ; Reason for Removal ;+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------+; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|rx_data_receive:rx_dtarcv|state_data_process[1] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_021|locked[0,1] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_020|locked[0,1] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_019|locked[0,1] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_018|locked[0,1] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_017|locked[0,1] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_016|locked[0,1] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_015|locked[0,1] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_014|locked[0,1] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_013|locked[0,1] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_012|locked[0,1] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_011|locked[0,1] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_010|locked[0,1] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_009|locked[0,1] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_008|locked[0,1] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_007|locked[0,1] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_006|locked[0,1] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_005|locked[0,1] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_004|locked[0,1] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_003|locked[0,1] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_002|locked[0,1] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_001|locked[0,1] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux|locked[0,1] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[67,95..99] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_uncompressed_read_reg ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[67,95..99] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_uncompressed_read_reg ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[67,95..99] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_uncompressed_read_reg ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[67,95..99] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_uncompressed_read_reg ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[67,95..99] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_uncompressed_read_reg ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[67,95..99] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_uncompressed_read_reg ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[67,95..99] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_uncompressed_read_reg ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[67,95..99] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_uncompressed_read_reg ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[67,95..99] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_uncompressed_read_reg ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[67,95..99] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_uncompressed_read_reg ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[67,95..99] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_uncompressed_read_reg ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[67,95..99] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_uncompressed_read_reg ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[67,95..99] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_uncompressed_read_reg ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[67,95..99] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_uncompressed_read_reg ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[67,95..99] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_uncompressed_read_reg ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[67,95..99] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_uncompressed_read_reg ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[67,95..99] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_uncompressed_read_reg ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[67,95..99] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_uncompressed_read_reg ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[67,95..99] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_uncompressed_read_reg ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[67,95..99] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_uncompressed_read_reg ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[67,95..99] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_uncompressed_read_reg ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[67,95..99] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_uncompressed_read_reg ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:clock_sel_s1_translator|av_readdata_pre[3..31] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:clock_sel_s1_translator|av_chipselect_pre ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_enable_s1_translator|av_readdata_pre[1..31] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_enable_s1_translator|av_chipselect_pre ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_data_s1_translator|av_readdata_pre[8..31] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_data_s1_translator|av_chipselect_pre ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:write_en_tx_s1_translator|av_readdata_pre[1..31] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:write_en_tx_s1_translator|av_chipselect_pre ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:write_data_fifo_tx_s1_translator|av_readdata_pre[9..31] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:write_data_fifo_tx_s1_translator|av_chipselect_pre ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:link_disable_s1_translator|av_readdata_pre[1..31] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:link_disable_s1_translator|av_chipselect_pre ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:auto_start_s1_translator|av_readdata_pre[1..31] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:auto_start_s1_translator|av_chipselect_pre ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:link_start_s1_translator|av_readdata_pre[1..31] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:link_start_s1_translator|av_chipselect_pre ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:data_read_en_rx_s1_translator|av_readdata_pre[1..31] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:data_read_en_rx_s1_translator|av_chipselect_pre ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:led_pio_test_s1_translator|av_readdata_pre[5..31] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:led_pio_test_s1_translator|av_chipselect_pre ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:timecode_tx_ready|readdata[1..31] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_timecode_rx:timecode_rx|readdata[8..31] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:timecode_ready_rx|readdata[1..31] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_counter_rx_fifo:fsm_info|readdata[5..31] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_full_tx_status|readdata[1..31] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_full_rx_status|readdata[1..31] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_empty_tx_status|readdata[1..31] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_empty_rx_status|readdata[1..31] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_data_info:data_info|readdata[14..31] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_data_flag_rx:data_flag_rx|readdata[9..31] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_counter_rx_fifo:counter_tx_fifo|readdata[6..31] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_counter_rx_fifo:counter_rx_fifo|readdata[6..31] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_traffic_limiter:hps_0_h2f_axi_master_wr_limiter|last_channel[1..3,5,6,12,13,16,17,19..21] ; Lost fanout ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:counter_rx_fifo_s1_translator|av_readdata_pre[6..31] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:counter_tx_fifo_s1_translator|av_readdata_pre[6..31] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fsm_info_s1_translator|av_readdata_pre[5..31] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:data_info_s1_translator|av_readdata_pre[14..31] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_ready_s1_translator|av_readdata_pre[1..31] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_empty_tx_status_s1_translator|av_readdata_pre[1..31] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_full_tx_status_s1_translator|av_readdata_pre[1..31] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_empty_rx_status_s1_translator|av_readdata_pre[1..31] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_full_rx_status_s1_translator|av_readdata_pre[1..31] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:data_flag_rx_s1_translator|av_readdata_pre[9..31] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_ready_rx_s1_translator|av_readdata_pre[1..31] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_rx_s1_translator|av_readdata_pre[8..31] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[0,1,3..6] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[0,1,3..6] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[0,1,3..6] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[0,1,3..6] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[0,1,3..6] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[0,1,3..6] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[0,1,3..6] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[0,1,3..6] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[0,1,3..6] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[0,1,3..6] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[0,1,3..6] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[0,1,3..6] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[0,1,3..6] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[0,1,3..6] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[0,1,3..6] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[0,1,3..6] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[0,1,3..6] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[0,1,3..6] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[0,1,3..6] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[0,1,3..6] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[0,1,3..6] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[0,1,3..6] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_021|saved_grant[0] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_020|saved_grant[0] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_019|saved_grant[0] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_017|saved_grant[0] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_016|saved_grant[0] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_013|saved_grant[0] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_012|saved_grant[0] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_006|saved_grant[0] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_005|saved_grant[0] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_003|saved_grant[0] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_002|saved_grant[0] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_001|saved_grant[0] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[68] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[68] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[68] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[68] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[68] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[68] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[68] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[68] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[68] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[68] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[68] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[68] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_021|altera_merlin_arbitrator:arb|top_priority_reg[1] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_020|altera_merlin_arbitrator:arb|top_priority_reg[1] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_019|altera_merlin_arbitrator:arb|top_priority_reg[1] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_017|altera_merlin_arbitrator:arb|top_priority_reg[1] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_016|altera_merlin_arbitrator:arb|top_priority_reg[1] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_013|altera_merlin_arbitrator:arb|top_priority_reg[1] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_012|altera_merlin_arbitrator:arb|top_priority_reg[1] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_006|altera_merlin_arbitrator:arb|top_priority_reg[1] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_005|altera_merlin_arbitrator:arb|top_priority_reg[1] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_003|altera_merlin_arbitrator:arb|top_priority_reg[1] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_002|altera_merlin_arbitrator:arb|top_priority_reg[1] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_001|altera_merlin_arbitrator:arb|top_priority_reg[1] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[0,1] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[0,1] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[0,1] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[0,1] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[0,1] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[0,1] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[0,1] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[0,1] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[0,1] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[0,1] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[0,1] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[0,1] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[0,1] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[0,1] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[0,1] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[0,1] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[0,1] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[0,1] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[0,1] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[0,1] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[0,1] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[0,1] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[0,1] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[0,1] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[0,1] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[0,1] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[0,1] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[0,1] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[0,1] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[0,1] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[0,1] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[0,1] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[0,1] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[0,1] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rsp_fifo|mem[1][99] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rsp_fifo|mem[1][98] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rsp_fifo|mem[1][97] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rsp_fifo|mem[1][96] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rsp_fifo|mem[1][95] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rsp_fifo|mem[1][68] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rsp_fifo|mem[1][99] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rsp_fifo|mem[1][98] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rsp_fifo|mem[1][97] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rsp_fifo|mem[1][96] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rsp_fifo|mem[1][95] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rsp_fifo|mem[1][68] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rsp_fifo|mem[1][99] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rsp_fifo|mem[1][98] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rsp_fifo|mem[1][97] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rsp_fifo|mem[1][96] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rsp_fifo|mem[1][95] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rsp_fifo|mem[1][68] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rsp_fifo|mem[1][99] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rsp_fifo|mem[1][98] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rsp_fifo|mem[1][97] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rsp_fifo|mem[1][96] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rsp_fifo|mem[1][95] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rsp_fifo|mem[1][99] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rsp_fifo|mem[1][98] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rsp_fifo|mem[1][97] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rsp_fifo|mem[1][96] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rsp_fifo|mem[1][95] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rsp_fifo|mem[1][68] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rsp_fifo|mem[1][99] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rsp_fifo|mem[1][98] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rsp_fifo|mem[1][97] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rsp_fifo|mem[1][96] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rsp_fifo|mem[1][95] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rsp_fifo|mem[1][68] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rsp_fifo|mem[1][99] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rsp_fifo|mem[1][98] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rsp_fifo|mem[1][97] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rsp_fifo|mem[1][96] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rsp_fifo|mem[1][95] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rsp_fifo|mem[1][99] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rsp_fifo|mem[1][98] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rsp_fifo|mem[1][97] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rsp_fifo|mem[1][96] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rsp_fifo|mem[1][95] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][99] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][98] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][97] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][96] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][95] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][68] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][99] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][98] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][97] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][96] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][95] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][68] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rsp_fifo|mem[1][99] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rsp_fifo|mem[1][98] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rsp_fifo|mem[1][97] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rsp_fifo|mem[1][96] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rsp_fifo|mem[1][95] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][99] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][98] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][97] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][96] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][95] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rsp_fifo|mem[1][99] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rsp_fifo|mem[1][98] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rsp_fifo|mem[1][97] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rsp_fifo|mem[1][96] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rsp_fifo|mem[1][95] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rsp_fifo|mem[1][99] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rsp_fifo|mem[1][98] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rsp_fifo|mem[1][97] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rsp_fifo|mem[1][96] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rsp_fifo|mem[1][95] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rsp_fifo|mem[1][99] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rsp_fifo|mem[1][98] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rsp_fifo|mem[1][97] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rsp_fifo|mem[1][96] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rsp_fifo|mem[1][95] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][99] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][98] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][97] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][96] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][95] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][68] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][99] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][98] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][97] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][96] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][95] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][68] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rsp_fifo|mem[1][99] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rsp_fifo|mem[1][98] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rsp_fifo|mem[1][97] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rsp_fifo|mem[1][96] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rsp_fifo|mem[1][95] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rsp_fifo|mem[1][99] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rsp_fifo|mem[1][98] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rsp_fifo|mem[1][97] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rsp_fifo|mem[1][96] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rsp_fifo|mem[1][95] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rsp_fifo|mem[1][68] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rsp_fifo|mem[1][99] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rsp_fifo|mem[1][98] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rsp_fifo|mem[1][97] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rsp_fifo|mem[1][96] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rsp_fifo|mem[1][95] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rsp_fifo|mem[1][68] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rsp_fifo|mem[1][99] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rsp_fifo|mem[1][98] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rsp_fifo|mem[1][97] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rsp_fifo|mem[1][96] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rsp_fifo|mem[1][95] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rsp_fifo|mem[1][68] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rsp_fifo|mem[1][99] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rsp_fifo|mem[1][98] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rsp_fifo|mem[1][97] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rsp_fifo|mem[1][96] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rsp_fifo|mem[1][95] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rsp_fifo|mem[0][99] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rsp_fifo|mem[0][98] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rsp_fifo|mem[0][97] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rsp_fifo|mem[0][96] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rsp_fifo|mem[0][95] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rsp_fifo|mem[0][68] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rsp_fifo|mem[0][99] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rsp_fifo|mem[0][98] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rsp_fifo|mem[0][97] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rsp_fifo|mem[0][96] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rsp_fifo|mem[0][95] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rsp_fifo|mem[0][68] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rsp_fifo|mem[0][99] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rsp_fifo|mem[0][98] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rsp_fifo|mem[0][97] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rsp_fifo|mem[0][96] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rsp_fifo|mem[0][95] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rsp_fifo|mem[0][68] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rsp_fifo|mem[0][99] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rsp_fifo|mem[0][98] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rsp_fifo|mem[0][97] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rsp_fifo|mem[0][96] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rsp_fifo|mem[0][95] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rsp_fifo|mem[0][99] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rsp_fifo|mem[0][98] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rsp_fifo|mem[0][97] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rsp_fifo|mem[0][96] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rsp_fifo|mem[0][95] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rsp_fifo|mem[0][68] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rsp_fifo|mem[0][99] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rsp_fifo|mem[0][98] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rsp_fifo|mem[0][97] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rsp_fifo|mem[0][96] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rsp_fifo|mem[0][95] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rsp_fifo|mem[0][68] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rsp_fifo|mem[0][99] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rsp_fifo|mem[0][98] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rsp_fifo|mem[0][97] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rsp_fifo|mem[0][96] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rsp_fifo|mem[0][95] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rsp_fifo|mem[0][99] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rsp_fifo|mem[0][98] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rsp_fifo|mem[0][97] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rsp_fifo|mem[0][96] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rsp_fifo|mem[0][95] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][99] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][98] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][97] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][96] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][95] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][68] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][99] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][98] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][97] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][96] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][95] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][68] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rsp_fifo|mem[0][99] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rsp_fifo|mem[0][98] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rsp_fifo|mem[0][97] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rsp_fifo|mem[0][96] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rsp_fifo|mem[0][95] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][99] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][98] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][97] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][96] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][95] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rsp_fifo|mem[0][99] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rsp_fifo|mem[0][98] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rsp_fifo|mem[0][97] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rsp_fifo|mem[0][96] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rsp_fifo|mem[0][95] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rsp_fifo|mem[0][99] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rsp_fifo|mem[0][98] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rsp_fifo|mem[0][97] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rsp_fifo|mem[0][96] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rsp_fifo|mem[0][95] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rsp_fifo|mem[0][99] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rsp_fifo|mem[0][98] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rsp_fifo|mem[0][97] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rsp_fifo|mem[0][96] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rsp_fifo|mem[0][95] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][99] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][98] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][97] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][96] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][95] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][68] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][99] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][98] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][97] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][96] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][95] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][68] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rsp_fifo|mem[0][99] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rsp_fifo|mem[0][98] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rsp_fifo|mem[0][97] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rsp_fifo|mem[0][96] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rsp_fifo|mem[0][95] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rsp_fifo|mem[0][99] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rsp_fifo|mem[0][98] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rsp_fifo|mem[0][97] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rsp_fifo|mem[0][96] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rsp_fifo|mem[0][95] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rsp_fifo|mem[0][68] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rsp_fifo|mem[0][99] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rsp_fifo|mem[0][98] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rsp_fifo|mem[0][97] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rsp_fifo|mem[0][96] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rsp_fifo|mem[0][95] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rsp_fifo|mem[0][68] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rsp_fifo|mem[0][99] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rsp_fifo|mem[0][98] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rsp_fifo|mem[0][97] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rsp_fifo|mem[0][96] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rsp_fifo|mem[0][95] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rsp_fifo|mem[0][68] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rsp_fifo|mem[0][99] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rsp_fifo|mem[0][98] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rsp_fifo|mem[0][97] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rsp_fifo|mem[0][96] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rsp_fifo|mem[0][95] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rsp_fifo|mem[0][69] ; Lost fanout ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rsp_fifo|mem[0][69] ; Lost fanout ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rsp_fifo|mem[0][69] ; Lost fanout ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rsp_fifo|mem[0][69] ; Lost fanout ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rsp_fifo|mem[0][69] ; Lost fanout ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][69] ; Lost fanout ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][69] ; Lost fanout ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][69] ; Lost fanout ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][69] ; Lost fanout ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rsp_fifo|mem[0][69] ; Lost fanout ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rsp_fifo|mem[0][69] ; Lost fanout ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rsp_fifo|mem[0][69] ; Lost fanout ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rsp_fifo|mem[1][73] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rsp_fifo|mem[1][72] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rsp_fifo|mem[1][73] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rsp_fifo|mem[1][72] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rsp_fifo|mem[1][73] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rsp_fifo|mem[1][72] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rsp_fifo|mem[1][73] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rsp_fifo|mem[1][72] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rsp_fifo|mem[1][73] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rsp_fifo|mem[1][72] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rsp_fifo|mem[1][73] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rsp_fifo|mem[1][72] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rsp_fifo|mem[1][73] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rsp_fifo|mem[1][72] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rsp_fifo|mem[1][73] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rsp_fifo|mem[1][72] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][73] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][72] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][73] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][72] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rsp_fifo|mem[1][73] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rsp_fifo|mem[1][72] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][73] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][72] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rsp_fifo|mem[1][73] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rsp_fifo|mem[1][72] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rsp_fifo|mem[1][73] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rsp_fifo|mem[1][72] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rsp_fifo|mem[1][73] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rsp_fifo|mem[1][72] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][73] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][72] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][73] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][72] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rsp_fifo|mem[1][73] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rsp_fifo|mem[1][72] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rsp_fifo|mem[1][73] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rsp_fifo|mem[1][72] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rsp_fifo|mem[1][73] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rsp_fifo|mem[1][72] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rsp_fifo|mem[1][73] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rsp_fifo|mem[1][72] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rsp_fifo|mem[1][73] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rsp_fifo|mem[1][72] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rsp_fifo|mem[0][73] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rsp_fifo|mem[0][72] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rsp_fifo|mem[0][73] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rsp_fifo|mem[0][72] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rsp_fifo|mem[0][73] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rsp_fifo|mem[0][72] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rsp_fifo|mem[0][73] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rsp_fifo|mem[0][72] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rsp_fifo|mem[0][73] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rsp_fifo|mem[0][72] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rsp_fifo|mem[0][73] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rsp_fifo|mem[0][72] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rsp_fifo|mem[0][73] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rsp_fifo|mem[0][72] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rsp_fifo|mem[0][73] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rsp_fifo|mem[0][72] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][73] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][72] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][73] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][72] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rsp_fifo|mem[0][73] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rsp_fifo|mem[0][72] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][73] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][72] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rsp_fifo|mem[0][73] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rsp_fifo|mem[0][72] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rsp_fifo|mem[0][73] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rsp_fifo|mem[0][72] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rsp_fifo|mem[0][73] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rsp_fifo|mem[0][72] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][73] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][72] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][73] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][72] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rsp_fifo|mem[0][73] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rsp_fifo|mem[0][72] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rsp_fifo|mem[0][73] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rsp_fifo|mem[0][72] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rsp_fifo|mem[0][73] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rsp_fifo|mem[0][72] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rsp_fifo|mem[0][73] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rsp_fifo|mem[0][72] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rsp_fifo|mem[0][73] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rsp_fifo|mem[0][72] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rsp_fifo|mem[1][69] ; Lost fanout ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rsp_fifo|mem[1][69] ; Lost fanout ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rsp_fifo|mem[1][69] ; Lost fanout ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rsp_fifo|mem[1][69] ; Lost fanout ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rsp_fifo|mem[1][69] ; Lost fanout ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][69] ; Lost fanout ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][69] ; Lost fanout ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][69] ; Lost fanout ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][69] ; Lost fanout ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rsp_fifo|mem[1][69] ; Lost fanout ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rsp_fifo|mem[1][69] ; Lost fanout ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rsp_fifo|mem[1][69] ; Lost fanout ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_018|share_count_zero_flag ; Stuck at VCC due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_015|share_count_zero_flag ; Stuck at VCC due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_014|share_count_zero_flag ; Stuck at VCC due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_011|share_count_zero_flag ; Stuck at VCC due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_010|share_count_zero_flag ; Stuck at VCC due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_009|share_count_zero_flag ; Stuck at VCC due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_008|share_count_zero_flag ; Stuck at VCC due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_007|share_count_zero_flag ; Stuck at VCC due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_004|share_count_zero_flag ; Stuck at VCC due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux|share_count_zero_flag ; Stuck at VCC due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:counter_rx_fifo_s1_translator|wait_latency_counter[1] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:counter_tx_fifo_s1_translator|wait_latency_counter[1] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fsm_info_s1_translator|wait_latency_counter[1] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:data_info_s1_translator|wait_latency_counter[1] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_ready_s1_translator|wait_latency_counter[1] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_empty_tx_status_s1_translator|wait_latency_counter[1] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_full_tx_status_s1_translator|wait_latency_counter[1] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_empty_rx_status_s1_translator|wait_latency_counter[1] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_full_rx_status_s1_translator|wait_latency_counter[1] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:data_flag_rx_s1_translator|wait_latency_counter[1] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_ready_rx_s1_translator|wait_latency_counter[1] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_rx_s1_translator|wait_latency_counter[1] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_021|altera_merlin_arbitrator:arb|top_priority_reg[0] ; Stuck at VCC due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_021|share_count_zero_flag ; Stuck at VCC due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_020|altera_merlin_arbitrator:arb|top_priority_reg[0] ; Stuck at VCC due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_020|share_count_zero_flag ; Stuck at VCC due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_019|altera_merlin_arbitrator:arb|top_priority_reg[0] ; Stuck at VCC due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_019|share_count_zero_flag ; Stuck at VCC due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_017|altera_merlin_arbitrator:arb|top_priority_reg[0] ; Stuck at VCC due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_017|share_count_zero_flag ; Stuck at VCC due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_016|altera_merlin_arbitrator:arb|top_priority_reg[0] ; Stuck at VCC due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_016|share_count_zero_flag ; Stuck at VCC due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_013|altera_merlin_arbitrator:arb|top_priority_reg[0] ; Stuck at VCC due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_013|share_count_zero_flag ; Stuck at VCC due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_012|altera_merlin_arbitrator:arb|top_priority_reg[0] ; Stuck at VCC due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_012|share_count_zero_flag ; Stuck at VCC due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_006|altera_merlin_arbitrator:arb|top_priority_reg[0] ; Stuck at VCC due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_006|share_count_zero_flag ; Stuck at VCC due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_005|altera_merlin_arbitrator:arb|top_priority_reg[0] ; Stuck at VCC due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_005|share_count_zero_flag ; Stuck at VCC due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_003|altera_merlin_arbitrator:arb|top_priority_reg[0] ; Stuck at VCC due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_003|share_count_zero_flag ; Stuck at VCC due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_002|altera_merlin_arbitrator:arb|top_priority_reg[0] ; Stuck at VCC due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_002|share_count_zero_flag ; Stuck at VCC due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_001|altera_merlin_arbitrator:arb|top_priority_reg[0] ; Stuck at VCC due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_001|share_count_zero_flag ; Stuck at VCC due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_018|share_count[0] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_015|share_count[0] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_014|share_count[0] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_011|share_count[0] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_010|share_count[0] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_009|share_count[0] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_008|share_count[0] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_007|share_count[0] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_004|share_count[0] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux|share_count[0] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_021|share_count[0] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_020|share_count[0] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_019|share_count[0] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_017|share_count[0] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_016|share_count[0] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_013|share_count[0] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_012|share_count[0] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_006|share_count[0] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_005|share_count[0] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_003|share_count[0] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_002|share_count[0] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_001|share_count[0] ; Stuck at GND due to stuck port data_in ;; detector_tokens:m_x|control[0..3] ; Stuck at GND due to stuck port data_in ;; detector_tokens:m_x|data[0..7] ; Stuck at GND due to stuck port data_in ;; detector_tokens:m_x|info[6..9] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo|mem[1][33] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo|mem[1][32] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo|mem[1][31] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo|mem[1][30] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo|mem[1][29] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo|mem[1][28] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo|mem[1][27] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo|mem[1][26] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo|mem[1][25] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo|mem[1][24] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo|mem[1][23] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo|mem[1][22] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo|mem[1][21] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo|mem[1][20] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo|mem[1][19] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo|mem[1][18] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo|mem[1][17] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo|mem[1][16] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo|mem[1][15] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo|mem[1][14] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo|mem[1][13] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo|mem[1][12] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo|mem[1][11] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo|mem[1][10] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo|mem[1][9] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo|mem[1][8] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo|mem[1][7] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo|mem[1][6] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo|mem[1][5] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_data_info:data_info|readdata[6..9] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo|mem[0][33] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo|mem[0][32] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo|mem[0][31] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo|mem[0][30] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo|mem[0][29] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo|mem[0][28] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo|mem[0][27] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo|mem[0][26] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo|mem[0][25] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo|mem[0][24] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo|mem[0][23] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo|mem[0][22] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo|mem[0][21] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo|mem[0][20] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo|mem[0][19] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo|mem[0][18] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo|mem[0][17] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo|mem[0][16] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo|mem[0][15] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo|mem[0][14] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo|mem[0][13] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo|mem[0][12] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo|mem[0][11] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo|mem[0][10] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo|mem[0][9] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo|mem[0][8] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo|mem[0][7] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo|mem[0][6] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo|mem[0][5] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:data_info_s1_translator|av_readdata_pre[6..9] ; Stuck at GND due to stuck port data_in ;; detector_tokens:m_x|rx_got_null ; Stuck at GND due to stuck port data_in ;; detector_tokens:m_x|rx_got_time_code ; Stuck at GND due to stuck port data_in ;; detector_tokens:m_x|rx_got_fct ; Stuck at GND due to stuck port data_in ;; detector_tokens:m_x|control_l_r[0..3] ; Stuck at GND due to stuck port data_in ;; detector_tokens:m_x|info[0,1,3,10..13] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_data_info:data_info|readdata[1,3,10..13] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:data_info_s1_translator|av_readdata_pre[1,3,10..13] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_data_info:data_info|readdata[0] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:data_info_s1_translator|av_readdata_pre[0] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][33] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][32] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][31] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][30] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][29] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][28] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][27] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][26] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][25] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][24] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][23] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][22] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][21] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][20] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][19] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][18] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][17] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][16] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][15] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][14] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][13] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][12] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][11] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][10] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][9] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo|mem[1][33] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo|mem[1][32] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo|mem[1][31] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo|mem[1][30] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo|mem[1][29] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo|mem[1][28] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo|mem[1][27] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo|mem[1][26] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo|mem[1][25] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo|mem[1][24] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo|mem[1][23] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo|mem[1][22] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo|mem[1][21] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo|mem[1][20] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo|mem[1][19] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo|mem[1][18] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo|mem[1][17] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo|mem[1][16] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo|mem[1][15] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo|mem[1][14] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo|mem[1][13] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo|mem[1][12] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo|mem[1][11] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo|mem[1][10] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo|mem[1][9] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo|mem[1][8] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo|mem[1][7] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo|mem[1][6] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo|mem[1][5] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo|mem[1][4] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo|mem[1][3] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo|mem[1][2] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo|mem[1][1] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][33] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][32] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][31] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][30] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][29] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][28] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][27] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][26] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][25] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][24] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][23] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][22] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][21] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][20] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][19] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][18] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][17] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][16] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][15] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][14] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][13] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][12] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][11] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][10] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][9] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo|mem[0][33] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo|mem[0][32] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo|mem[0][31] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo|mem[0][30] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo|mem[0][29] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo|mem[0][28] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo|mem[0][27] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo|mem[0][26] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo|mem[0][25] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo|mem[0][24] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo|mem[0][23] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo|mem[0][22] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo|mem[0][21] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo|mem[0][20] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo|mem[0][19] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo|mem[0][18] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo|mem[0][17] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo|mem[0][16] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo|mem[0][15] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo|mem[0][14] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo|mem[0][13] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo|mem[0][12] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo|mem[0][11] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo|mem[0][10] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo|mem[0][9] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo|mem[0][8] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo|mem[0][7] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo|mem[0][6] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo|mem[0][5] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo|mem[0][4] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo|mem[0][3] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo|mem[0][2] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo|mem[0][1] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rdata_fifo|mem[1][33] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rdata_fifo|mem[1][32] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rdata_fifo|mem[1][31] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rdata_fifo|mem[1][30] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rdata_fifo|mem[1][29] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rdata_fifo|mem[1][28] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rdata_fifo|mem[1][27] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rdata_fifo|mem[1][26] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rdata_fifo|mem[1][25] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rdata_fifo|mem[1][24] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rdata_fifo|mem[1][23] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rdata_fifo|mem[1][22] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rdata_fifo|mem[1][21] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rdata_fifo|mem[1][20] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rdata_fifo|mem[1][19] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rdata_fifo|mem[1][18] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rdata_fifo|mem[1][17] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rdata_fifo|mem[1][16] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rdata_fifo|mem[1][15] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rdata_fifo|mem[1][14] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rdata_fifo|mem[1][13] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rdata_fifo|mem[1][12] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rdata_fifo|mem[1][11] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rdata_fifo|mem[1][10] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rdata_fifo|mem[1][9] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rdata_fifo|mem[1][8] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rdata_fifo|mem[1][7] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rdata_fifo|mem[1][6] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rdata_fifo|mem[0][33] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rdata_fifo|mem[0][32] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rdata_fifo|mem[0][31] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rdata_fifo|mem[0][30] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rdata_fifo|mem[0][29] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rdata_fifo|mem[0][28] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rdata_fifo|mem[0][27] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rdata_fifo|mem[0][26] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rdata_fifo|mem[0][25] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rdata_fifo|mem[0][24] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rdata_fifo|mem[0][23] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rdata_fifo|mem[0][22] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rdata_fifo|mem[0][21] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rdata_fifo|mem[0][20] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rdata_fifo|mem[0][19] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rdata_fifo|mem[0][18] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rdata_fifo|mem[0][17] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rdata_fifo|mem[0][16] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rdata_fifo|mem[0][15] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rdata_fifo|mem[0][14] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rdata_fifo|mem[0][13] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rdata_fifo|mem[0][12] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rdata_fifo|mem[0][11] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rdata_fifo|mem[0][10] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rdata_fifo|mem[0][9] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rdata_fifo|mem[0][8] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rdata_fifo|mem[0][7] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rdata_fifo|mem[0][6] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[1][33] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[1][32] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[1][31] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[1][30] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[1][29] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[1][28] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[1][27] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[1][26] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[1][25] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[1][24] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[1][23] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[1][22] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[1][21] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[1][20] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[1][19] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[1][18] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[1][17] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[1][16] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[1][15] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[1][14] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[1][13] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[1][12] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[1][11] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[1][10] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[1][9] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[1][8] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[1][7] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[1][6] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[1][5] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[1][4] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[1][3] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[1][2] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[1][1] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[1][33] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[1][32] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[1][31] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[1][30] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[1][29] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[1][28] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[1][27] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[1][26] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[1][25] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[1][24] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[1][23] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[1][22] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[1][21] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[1][20] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[1][19] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[1][18] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[1][17] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[1][16] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[1][15] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[1][14] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[1][13] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[1][12] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[1][11] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[1][10] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[1][9] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[1][8] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[1][7] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[1][6] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[1][5] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[1][4] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[1][3] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[1][2] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[1][1] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_axi_master_ni:hps_0_h2f_axi_master_agent|burst_bytecount[0,1] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[0][33] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[0][32] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[0][31] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[0][30] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[0][29] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[0][28] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[0][27] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[0][26] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[0][25] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[0][24] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[0][23] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[0][22] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[0][21] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[0][20] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[0][19] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[0][18] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[0][17] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[0][16] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[0][15] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[0][14] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[0][13] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[0][12] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[0][11] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[0][10] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[0][9] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[0][8] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[0][7] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[0][6] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[0][5] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[0][4] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[0][3] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[0][2] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[0][1] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[0][33] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[0][32] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[0][31] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[0][30] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[0][29] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[0][28] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[0][27] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[0][26] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[0][25] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[0][24] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[0][23] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[0][22] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[0][21] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[0][20] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[0][19] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[0][18] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[0][17] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[0][16] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[0][15] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[0][14] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[0][13] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[0][12] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[0][11] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[0][10] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[0][9] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[0][8] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[0][7] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[0][6] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[0][5] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[0][4] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[0][3] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[0][2] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[0][1] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo|mem[1][33] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo|mem[1][32] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo|mem[1][31] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo|mem[1][30] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo|mem[1][29] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo|mem[1][28] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo|mem[1][27] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo|mem[1][26] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo|mem[1][25] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo|mem[1][24] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo|mem[1][23] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo|mem[1][22] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo|mem[1][21] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo|mem[1][20] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo|mem[1][19] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo|mem[1][18] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo|mem[1][17] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo|mem[1][16] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo|mem[1][15] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo|mem[1][14] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo|mem[1][13] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo|mem[1][12] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo|mem[1][11] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo|mem[1][10] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo|mem[1][9] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo|mem[1][8] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo|mem[1][7] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo|mem[1][6] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[1][33] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[1][32] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[1][31] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[1][30] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[1][29] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[1][28] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[1][27] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[1][26] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[1][25] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[1][24] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[1][23] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[1][22] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[1][21] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[1][20] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[1][19] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[1][18] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[1][17] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[1][16] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[1][15] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[1][14] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[1][13] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[1][12] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[1][11] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[1][10] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[1][9] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[1][8] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[1][7] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[1][6] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[1][5] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rdata_fifo|mem[1][33] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rdata_fifo|mem[1][32] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rdata_fifo|mem[1][31] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rdata_fifo|mem[1][30] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rdata_fifo|mem[1][29] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rdata_fifo|mem[1][28] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rdata_fifo|mem[1][27] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rdata_fifo|mem[1][26] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rdata_fifo|mem[1][25] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rdata_fifo|mem[1][24] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rdata_fifo|mem[1][23] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rdata_fifo|mem[1][22] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rdata_fifo|mem[1][21] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rdata_fifo|mem[1][20] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rdata_fifo|mem[1][19] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rdata_fifo|mem[1][18] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rdata_fifo|mem[1][17] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rdata_fifo|mem[1][16] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rdata_fifo|mem[1][15] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rdata_fifo|mem[1][14] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rdata_fifo|mem[1][13] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rdata_fifo|mem[1][12] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rdata_fifo|mem[1][11] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rdata_fifo|mem[1][10] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rdata_fifo|mem[1][9] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rdata_fifo|mem[1][8] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rdata_fifo|mem[1][7] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rdata_fifo|mem[1][6] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rdata_fifo|mem[1][5] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rdata_fifo|mem[1][4] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rdata_fifo|mem[1][3] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[1][33] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[1][32] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[1][31] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[1][30] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[1][29] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[1][28] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[1][27] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[1][26] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[1][25] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[1][24] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[1][23] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[1][22] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[1][21] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[1][20] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[1][19] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[1][18] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[1][17] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[1][16] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[1][15] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[1][14] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rdata_fifo|mem[1][33] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rdata_fifo|mem[1][32] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rdata_fifo|mem[1][31] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rdata_fifo|mem[1][30] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rdata_fifo|mem[1][29] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rdata_fifo|mem[1][28] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rdata_fifo|mem[1][27] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rdata_fifo|mem[1][26] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rdata_fifo|mem[1][25] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rdata_fifo|mem[1][24] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rdata_fifo|mem[1][23] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rdata_fifo|mem[1][22] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rdata_fifo|mem[1][21] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rdata_fifo|mem[1][20] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rdata_fifo|mem[1][19] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rdata_fifo|mem[1][18] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rdata_fifo|mem[1][17] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rdata_fifo|mem[1][16] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rdata_fifo|mem[1][15] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rdata_fifo|mem[1][14] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rdata_fifo|mem[1][13] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rdata_fifo|mem[1][12] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rdata_fifo|mem[1][11] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rdata_fifo|mem[1][10] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rdata_fifo|mem[1][9] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rdata_fifo|mem[1][8] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rdata_fifo|mem[1][7] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rdata_fifo|mem[1][6] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rdata_fifo|mem[1][5] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rdata_fifo|mem[1][4] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rdata_fifo|mem[1][3] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rdata_fifo|mem[1][2] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rdata_fifo|mem[1][1] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rdata_fifo|mem[1][33] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rdata_fifo|mem[1][32] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rdata_fifo|mem[1][31] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rdata_fifo|mem[1][30] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rdata_fifo|mem[1][29] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rdata_fifo|mem[1][28] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rdata_fifo|mem[1][27] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rdata_fifo|mem[1][26] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rdata_fifo|mem[1][25] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rdata_fifo|mem[1][24] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rdata_fifo|mem[1][23] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rdata_fifo|mem[1][22] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rdata_fifo|mem[1][21] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rdata_fifo|mem[1][20] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rdata_fifo|mem[1][19] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rdata_fifo|mem[1][18] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rdata_fifo|mem[1][17] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rdata_fifo|mem[1][16] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rdata_fifo|mem[1][15] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rdata_fifo|mem[1][14] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rdata_fifo|mem[1][13] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rdata_fifo|mem[1][12] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rdata_fifo|mem[1][11] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rdata_fifo|mem[1][10] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rdata_fifo|mem[1][9] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rdata_fifo|mem[1][8] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rdata_fifo|mem[1][7] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rdata_fifo|mem[1][6] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rdata_fifo|mem[1][5] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rdata_fifo|mem[1][4] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rdata_fifo|mem[1][3] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rdata_fifo|mem[1][2] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rdata_fifo|mem[1][1] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rdata_fifo|mem[1][33] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rdata_fifo|mem[1][32] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rdata_fifo|mem[1][31] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rdata_fifo|mem[1][30] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rdata_fifo|mem[1][29] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rdata_fifo|mem[1][28] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rdata_fifo|mem[1][27] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rdata_fifo|mem[1][26] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rdata_fifo|mem[1][25] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rdata_fifo|mem[1][24] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rdata_fifo|mem[1][23] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rdata_fifo|mem[1][22] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rdata_fifo|mem[1][21] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rdata_fifo|mem[1][20] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rdata_fifo|mem[1][19] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rdata_fifo|mem[1][18] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rdata_fifo|mem[1][17] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rdata_fifo|mem[1][16] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rdata_fifo|mem[1][15] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rdata_fifo|mem[1][14] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rdata_fifo|mem[1][13] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rdata_fifo|mem[1][12] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rdata_fifo|mem[1][11] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rdata_fifo|mem[1][10] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rdata_fifo|mem[1][9] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rdata_fifo|mem[1][8] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rdata_fifo|mem[1][33] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rdata_fifo|mem[1][32] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rdata_fifo|mem[1][31] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rdata_fifo|mem[1][30] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rdata_fifo|mem[1][29] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rdata_fifo|mem[1][28] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rdata_fifo|mem[1][27] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rdata_fifo|mem[1][26] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rdata_fifo|mem[1][25] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rdata_fifo|mem[1][24] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rdata_fifo|mem[1][23] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rdata_fifo|mem[1][22] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rdata_fifo|mem[1][21] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rdata_fifo|mem[1][20] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rdata_fifo|mem[1][19] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rdata_fifo|mem[1][18] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rdata_fifo|mem[1][17] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rdata_fifo|mem[1][16] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rdata_fifo|mem[1][15] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rdata_fifo|mem[1][14] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rdata_fifo|mem[1][13] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rdata_fifo|mem[1][12] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rdata_fifo|mem[1][11] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rdata_fifo|mem[1][10] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rdata_fifo|mem[1][9] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rdata_fifo|mem[1][8] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rdata_fifo|mem[1][7] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rdata_fifo|mem[1][6] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rdata_fifo|mem[1][5] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rdata_fifo|mem[1][4] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rdata_fifo|mem[1][3] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rdata_fifo|mem[1][2] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rdata_fifo|mem[1][1] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo|mem[0][33] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo|mem[0][32] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo|mem[0][31] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo|mem[0][30] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo|mem[0][29] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo|mem[0][28] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo|mem[0][27] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo|mem[0][26] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo|mem[0][25] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo|mem[0][24] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo|mem[0][23] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo|mem[0][22] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo|mem[0][21] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo|mem[0][20] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo|mem[0][19] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo|mem[0][18] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo|mem[0][17] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo|mem[0][16] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo|mem[0][15] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo|mem[0][14] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo|mem[0][13] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo|mem[0][12] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo|mem[0][11] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo|mem[0][10] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo|mem[0][9] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo|mem[0][8] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo|mem[0][7] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo|mem[0][6] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[0][33] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[0][32] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[0][31] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[0][30] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[0][29] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[0][28] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[0][27] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[0][26] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[0][25] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[0][24] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[0][23] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[0][22] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[0][21] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[0][20] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[0][19] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[0][18] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[0][17] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[0][16] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[0][15] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[0][14] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[0][13] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[0][12] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[0][11] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[0][10] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[0][9] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[0][8] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[0][7] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[0][6] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[0][5] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rdata_fifo|mem[0][33] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rdata_fifo|mem[0][32] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rdata_fifo|mem[0][31] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rdata_fifo|mem[0][30] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rdata_fifo|mem[0][29] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rdata_fifo|mem[0][28] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rdata_fifo|mem[0][27] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rdata_fifo|mem[0][26] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rdata_fifo|mem[0][25] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rdata_fifo|mem[0][24] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rdata_fifo|mem[0][23] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rdata_fifo|mem[0][22] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rdata_fifo|mem[0][21] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rdata_fifo|mem[0][20] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rdata_fifo|mem[0][19] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rdata_fifo|mem[0][18] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rdata_fifo|mem[0][17] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rdata_fifo|mem[0][16] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rdata_fifo|mem[0][15] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rdata_fifo|mem[0][14] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rdata_fifo|mem[0][13] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rdata_fifo|mem[0][12] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rdata_fifo|mem[0][11] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rdata_fifo|mem[0][10] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rdata_fifo|mem[0][9] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rdata_fifo|mem[0][8] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rdata_fifo|mem[0][7] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rdata_fifo|mem[0][6] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rdata_fifo|mem[0][5] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rdata_fifo|mem[0][4] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rdata_fifo|mem[0][3] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[0][33] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[0][32] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[0][31] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[0][30] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[0][29] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[0][28] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[0][27] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[0][26] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[0][25] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[0][24] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[0][23] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[0][22] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[0][21] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[0][20] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[0][19] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[0][18] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[0][17] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[0][16] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[0][15] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[0][14] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rdata_fifo|mem[0][33] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rdata_fifo|mem[0][32] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rdata_fifo|mem[0][31] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rdata_fifo|mem[0][30] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rdata_fifo|mem[0][29] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rdata_fifo|mem[0][28] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rdata_fifo|mem[0][27] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rdata_fifo|mem[0][26] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rdata_fifo|mem[0][25] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rdata_fifo|mem[0][24] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rdata_fifo|mem[0][23] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rdata_fifo|mem[0][22] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rdata_fifo|mem[0][21] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rdata_fifo|mem[0][20] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rdata_fifo|mem[0][19] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rdata_fifo|mem[0][18] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rdata_fifo|mem[0][17] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rdata_fifo|mem[0][16] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rdata_fifo|mem[0][15] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rdata_fifo|mem[0][14] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rdata_fifo|mem[0][13] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rdata_fifo|mem[0][12] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rdata_fifo|mem[0][11] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rdata_fifo|mem[0][10] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rdata_fifo|mem[0][9] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rdata_fifo|mem[0][8] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rdata_fifo|mem[0][7] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rdata_fifo|mem[0][6] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rdata_fifo|mem[0][5] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rdata_fifo|mem[0][4] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rdata_fifo|mem[0][3] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rdata_fifo|mem[0][2] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rdata_fifo|mem[0][1] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rdata_fifo|mem[0][33] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rdata_fifo|mem[0][32] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rdata_fifo|mem[0][31] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rdata_fifo|mem[0][30] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rdata_fifo|mem[0][29] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rdata_fifo|mem[0][28] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rdata_fifo|mem[0][27] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rdata_fifo|mem[0][26] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rdata_fifo|mem[0][25] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rdata_fifo|mem[0][24] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rdata_fifo|mem[0][23] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rdata_fifo|mem[0][22] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rdata_fifo|mem[0][21] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rdata_fifo|mem[0][20] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rdata_fifo|mem[0][19] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rdata_fifo|mem[0][18] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rdata_fifo|mem[0][17] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rdata_fifo|mem[0][16] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rdata_fifo|mem[0][15] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rdata_fifo|mem[0][14] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rdata_fifo|mem[0][13] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rdata_fifo|mem[0][12] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rdata_fifo|mem[0][11] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rdata_fifo|mem[0][10] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rdata_fifo|mem[0][9] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rdata_fifo|mem[0][8] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rdata_fifo|mem[0][7] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rdata_fifo|mem[0][6] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rdata_fifo|mem[0][5] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rdata_fifo|mem[0][4] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rdata_fifo|mem[0][3] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rdata_fifo|mem[0][2] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rdata_fifo|mem[0][1] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rdata_fifo|mem[0][33] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rdata_fifo|mem[0][32] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rdata_fifo|mem[0][31] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rdata_fifo|mem[0][30] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rdata_fifo|mem[0][29] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rdata_fifo|mem[0][28] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rdata_fifo|mem[0][27] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rdata_fifo|mem[0][26] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rdata_fifo|mem[0][25] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rdata_fifo|mem[0][24] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rdata_fifo|mem[0][23] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rdata_fifo|mem[0][22] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rdata_fifo|mem[0][21] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rdata_fifo|mem[0][20] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rdata_fifo|mem[0][19] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rdata_fifo|mem[0][18] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rdata_fifo|mem[0][17] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rdata_fifo|mem[0][16] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rdata_fifo|mem[0][15] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rdata_fifo|mem[0][14] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rdata_fifo|mem[0][13] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rdata_fifo|mem[0][12] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rdata_fifo|mem[0][11] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rdata_fifo|mem[0][10] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rdata_fifo|mem[0][9] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rdata_fifo|mem[0][8] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rdata_fifo|mem[0][33] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rdata_fifo|mem[0][32] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rdata_fifo|mem[0][31] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rdata_fifo|mem[0][30] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rdata_fifo|mem[0][29] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rdata_fifo|mem[0][28] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rdata_fifo|mem[0][27] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rdata_fifo|mem[0][26] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rdata_fifo|mem[0][25] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rdata_fifo|mem[0][24] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rdata_fifo|mem[0][23] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rdata_fifo|mem[0][22] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rdata_fifo|mem[0][21] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rdata_fifo|mem[0][20] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rdata_fifo|mem[0][19] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rdata_fifo|mem[0][18] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rdata_fifo|mem[0][17] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rdata_fifo|mem[0][16] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rdata_fifo|mem[0][15] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rdata_fifo|mem[0][14] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rdata_fifo|mem[0][13] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rdata_fifo|mem[0][12] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rdata_fifo|mem[0][11] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rdata_fifo|mem[0][10] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rdata_fifo|mem[0][9] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rdata_fifo|mem[0][8] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rdata_fifo|mem[0][7] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rdata_fifo|mem[0][6] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rdata_fifo|mem[0][5] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rdata_fifo|mem[0][4] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rdata_fifo|mem[0][3] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rdata_fifo|mem[0][2] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rdata_fifo|mem[0][1] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[4..29] ; Lost fanout ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[4..6] ; Lost fanout ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[4..29] ; Lost fanout ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[4..6] ; Lost fanout ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[6] ; Lost fanout ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[6..29] ; Lost fanout ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[5] ; Lost fanout ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[5] ; Lost fanout ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[4] ; Lost fanout ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[4] ; Lost fanout ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[6] ; Lost fanout ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[6..29] ; Lost fanout ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[5] ; Lost fanout ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[5] ; Lost fanout ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[4] ; Lost fanout ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[4] ; Lost fanout ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[1][33] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[1][32] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[1][31] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[1][30] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[1][29] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[1][28] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[1][27] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[1][26] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[1][25] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[1][24] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[1][23] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[1][22] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[1][21] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[1][20] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[1][19] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[1][18] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[1][17] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[1][16] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[1][15] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[1][14] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[1][13] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[1][12] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[1][11] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[1][10] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[1][9] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[1][8] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[1][7] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[1][6] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[1][5] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[1][4] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[1][3] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[1][2] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[1][1] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rdata_fifo|mem[1][33] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rdata_fifo|mem[1][32] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rdata_fifo|mem[1][31] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rdata_fifo|mem[1][30] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rdata_fifo|mem[1][29] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rdata_fifo|mem[1][28] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rdata_fifo|mem[1][27] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rdata_fifo|mem[1][26] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rdata_fifo|mem[1][25] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rdata_fifo|mem[1][24] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rdata_fifo|mem[1][23] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rdata_fifo|mem[1][22] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rdata_fifo|mem[1][21] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rdata_fifo|mem[1][20] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rdata_fifo|mem[1][19] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rdata_fifo|mem[1][18] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rdata_fifo|mem[1][17] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rdata_fifo|mem[1][16] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rdata_fifo|mem[1][15] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rdata_fifo|mem[1][14] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rdata_fifo|mem[1][13] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rdata_fifo|mem[1][12] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rdata_fifo|mem[1][11] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rdata_fifo|mem[1][10] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rdata_fifo|mem[1][9] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rdata_fifo|mem[1][8] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[0][33] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[0][32] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[0][31] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[0][30] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[0][29] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[0][28] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[0][27] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[0][26] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[0][25] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[0][24] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[0][23] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[0][22] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[0][21] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[0][20] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[0][19] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[0][18] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[0][17] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[0][16] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[0][15] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[0][14] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[0][13] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[0][12] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[0][11] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[0][10] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[0][9] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[0][8] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[0][7] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[0][6] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[0][5] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[0][4] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[0][3] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[0][2] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[0][1] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rdata_fifo|mem[0][33] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rdata_fifo|mem[0][32] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rdata_fifo|mem[0][31] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rdata_fifo|mem[0][30] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rdata_fifo|mem[0][29] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rdata_fifo|mem[0][28] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rdata_fifo|mem[0][27] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rdata_fifo|mem[0][26] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rdata_fifo|mem[0][25] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rdata_fifo|mem[0][24] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rdata_fifo|mem[0][23] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rdata_fifo|mem[0][22] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rdata_fifo|mem[0][21] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rdata_fifo|mem[0][20] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rdata_fifo|mem[0][19] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rdata_fifo|mem[0][18] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rdata_fifo|mem[0][17] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rdata_fifo|mem[0][16] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rdata_fifo|mem[0][15] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rdata_fifo|mem[0][14] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rdata_fifo|mem[0][13] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rdata_fifo|mem[0][12] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rdata_fifo|mem[0][11] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rdata_fifo|mem[0][10] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rdata_fifo|mem[0][9] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rdata_fifo|mem[0][8] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[4..29] ; Lost fanout ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[4..6] ; Lost fanout ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[4..29] ; Lost fanout ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[4..6] ; Lost fanout ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[6] ; Lost fanout ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[6..29] ; Lost fanout ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[5] ; Lost fanout ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[5] ; Lost fanout ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[4] ; Lost fanout ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[4] ; Lost fanout ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[6] ; Lost fanout ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[6..29] ; Lost fanout ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[5] ; Lost fanout ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[5] ; Lost fanout ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[4] ; Lost fanout ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[4] ; Lost fanout ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[1][33] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[1][32] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[1][31] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[1][30] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[1][29] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[1][28] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[1][27] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[1][26] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[1][25] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[1][24] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[1][23] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[1][22] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[1][21] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[1][20] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[1][19] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[1][18] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[1][17] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[1][16] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[1][15] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[1][14] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[1][13] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[1][12] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[1][11] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[1][10] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[1][9] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[1][8] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[1][7] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[1][6] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[1][5] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[1][4] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[1][3] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[1][2] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[1][1] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo|mem[1][33] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo|mem[1][32] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo|mem[1][31] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo|mem[1][30] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo|mem[1][29] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo|mem[1][28] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo|mem[1][27] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo|mem[1][26] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo|mem[1][25] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo|mem[1][24] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo|mem[1][23] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo|mem[1][22] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo|mem[1][21] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo|mem[1][20] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo|mem[1][19] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo|mem[1][18] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo|mem[1][17] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo|mem[1][16] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo|mem[1][15] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo|mem[1][14] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo|mem[1][13] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo|mem[1][12] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo|mem[1][11] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo|mem[1][10] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo|mem[1][9] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[0][33] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[0][32] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[0][31] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[0][30] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[0][29] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[0][28] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[0][27] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[0][26] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[0][25] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[0][24] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[0][23] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[0][22] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[0][21] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[0][20] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[0][19] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[0][18] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[0][17] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[0][16] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[0][15] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[0][14] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[0][13] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[0][12] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[0][11] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[0][10] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[0][9] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[0][8] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[0][7] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[0][6] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[0][5] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[0][4] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[0][3] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[0][2] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[0][1] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo|mem[0][33] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo|mem[0][32] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo|mem[0][31] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo|mem[0][30] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo|mem[0][29] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo|mem[0][28] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo|mem[0][27] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo|mem[0][26] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo|mem[0][25] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo|mem[0][24] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo|mem[0][23] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo|mem[0][22] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo|mem[0][21] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo|mem[0][20] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo|mem[0][19] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo|mem[0][18] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo|mem[0][17] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo|mem[0][16] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo|mem[0][15] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo|mem[0][14] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo|mem[0][13] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo|mem[0][12] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo|mem[0][11] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo|mem[0][10] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo|mem[0][9] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[4..29] ; Lost fanout ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[4..6] ; Lost fanout ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[4..29] ; Lost fanout ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[4..6] ; Lost fanout ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[6] ; Lost fanout ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[6..29] ; Lost fanout ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[5] ; Lost fanout ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[5] ; Lost fanout ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[4] ; Lost fanout ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[4] ; Lost fanout ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[6] ; Lost fanout ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[6..29] ; Lost fanout ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[5] ; Lost fanout ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[5] ; Lost fanout ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[4] ; Lost fanout ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[4] ; Lost fanout ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[1][33] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[1][32] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[1][31] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[1][30] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[1][29] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[1][28] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[1][27] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[1][26] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[1][25] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[1][24] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[1][23] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[1][22] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[1][21] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[1][20] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[1][19] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[1][18] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[1][17] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[1][16] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[1][15] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[1][14] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[1][13] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[1][12] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[1][11] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[1][10] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[1][9] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[1][8] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[1][7] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[1][6] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[1][5] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[1][4] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[1][3] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[1][2] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[1][1] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[1][33] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[1][32] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[1][31] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[1][30] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[1][29] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[1][28] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[1][27] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[1][26] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[1][25] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[1][24] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[1][23] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[1][22] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[1][21] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[1][20] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[1][19] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[1][18] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[1][17] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[1][16] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[1][15] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[1][14] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[1][13] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[1][12] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[1][11] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[1][10] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[1][9] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[1][8] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[1][7] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[1][6] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[1][5] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[1][4] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[1][3] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[1][2] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[1][1] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[0][33] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[0][32] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[0][31] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[0][30] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[0][29] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[0][28] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[0][27] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[0][26] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[0][25] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[0][24] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[0][23] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[0][22] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[0][21] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[0][20] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[0][19] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[0][18] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[0][17] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[0][16] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[0][15] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[0][14] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[0][13] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[0][12] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[0][11] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[0][10] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[0][9] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[0][8] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[0][7] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[0][6] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[0][5] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[0][4] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[0][3] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[0][2] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[0][1] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[0][33] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[0][32] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[0][31] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[0][30] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[0][29] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[0][28] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[0][27] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[0][26] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[0][25] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[0][24] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[0][23] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[0][22] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[0][21] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[0][20] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[0][19] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[0][18] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[0][17] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[0][16] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[0][15] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[0][14] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[0][13] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[0][12] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[0][11] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[0][10] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[0][9] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[0][8] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[0][7] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[0][6] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[0][5] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[0][4] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[0][3] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[0][2] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[0][1] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[4..29] ; Lost fanout ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[4..6] ; Lost fanout ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[4..29] ; Lost fanout ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[4..6] ; Lost fanout ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[6] ; Lost fanout ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[6..29] ; Lost fanout ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[5] ; Lost fanout ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[5] ; Lost fanout ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[4] ; Lost fanout ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[4] ; Lost fanout ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[6] ; Lost fanout ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[6..29] ; Lost fanout ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[5] ; Lost fanout ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[5] ; Lost fanout ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[4] ; Lost fanout ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[4] ; Lost fanout ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[1][33] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[1][32] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[1][31] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[1][30] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[1][29] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[1][28] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[1][27] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[1][26] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[1][25] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[1][24] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[1][23] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[1][22] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[1][21] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[1][20] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[1][19] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[1][18] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[1][17] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[1][16] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[1][15] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[1][14] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[1][13] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[1][12] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[1][11] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[1][10] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[1][9] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[1][8] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[1][7] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[1][6] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[1][5] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[1][4] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[1][3] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[1][2] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[1][1] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[1][33] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[1][32] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[1][31] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[1][30] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[1][29] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[1][28] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[1][27] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[1][26] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[1][25] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[1][24] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[1][23] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[1][22] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[1][21] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[1][20] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[1][19] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[1][18] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[1][17] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[1][16] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[1][15] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[1][14] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[1][13] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[1][12] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[1][11] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[1][10] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[1][9] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[1][8] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[1][7] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[1][6] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[1][5] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[1][4] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[1][3] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[1][2] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[1][1] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[0][33] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[0][32] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[0][31] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[0][30] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[0][29] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[0][28] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[0][27] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[0][26] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[0][25] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[0][24] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[0][23] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[0][22] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[0][21] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[0][20] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[0][19] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[0][18] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[0][17] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[0][16] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[0][15] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[0][14] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[0][13] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[0][12] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[0][11] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[0][10] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[0][9] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[0][8] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[0][7] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[0][6] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[0][5] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[0][4] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[0][3] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[0][2] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[0][1] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[0][33] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[0][32] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[0][31] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[0][30] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[0][29] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[0][28] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[0][27] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[0][26] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[0][25] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[0][24] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[0][23] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[0][22] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[0][21] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[0][20] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[0][19] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[0][18] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[0][17] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[0][16] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[0][15] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[0][14] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[0][13] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[0][12] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[0][11] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[0][10] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[0][9] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[0][8] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[0][7] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[0][6] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[0][5] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[0][4] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[0][3] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[0][2] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[0][1] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[4..29] ; Lost fanout ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[4..6] ; Lost fanout ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[4..29] ; Lost fanout ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[4..6] ; Lost fanout ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[6] ; Lost fanout ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[6..29] ; Lost fanout ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[5] ; Lost fanout ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[5] ; Lost fanout ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[4] ; Lost fanout ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[4] ; Lost fanout ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[6] ; Lost fanout ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[6..29] ; Lost fanout ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[5] ; Lost fanout ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[5] ; Lost fanout ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[4] ; Lost fanout ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[4] ; Lost fanout ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[4..29] ; Lost fanout ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[4..6] ; Lost fanout ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[4..29] ; Lost fanout ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[4..6] ; Lost fanout ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[6] ; Lost fanout ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[6..29] ; Lost fanout ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[5] ; Lost fanout ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[5] ; Lost fanout ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[4] ; Lost fanout ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[4] ; Lost fanout ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[6] ; Lost fanout ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[6..29] ; Lost fanout ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[5] ; Lost fanout ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[5] ; Lost fanout ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[4] ; Lost fanout ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[4] ; Lost fanout ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[4..29] ; Lost fanout ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[4..6] ; Lost fanout ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[4..29] ; Lost fanout ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[4..6] ; Lost fanout ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[6] ; Lost fanout ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[6..29] ; Lost fanout ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[5] ; Lost fanout ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[5] ; Lost fanout ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[4] ; Lost fanout ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[4] ; Lost fanout ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[6] ; Lost fanout ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[6..29] ; Lost fanout ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[5] ; Lost fanout ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[5] ; Lost fanout ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[4] ; Lost fanout ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[4] ; Lost fanout ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_counter:tx_fct_cnt|fct_counter_receive[0..2] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[4..29] ; Lost fanout ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[4..6] ; Lost fanout ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[4..29] ; Lost fanout ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[4..6] ; Lost fanout ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[6] ; Lost fanout ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[6..29] ; Lost fanout ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[5] ; Lost fanout ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[5] ; Lost fanout ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[4] ; Lost fanout ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[4] ; Lost fanout ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[6] ; Lost fanout ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[6..29] ; Lost fanout ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[5] ; Lost fanout ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[5] ; Lost fanout ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[4] ; Lost fanout ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[4] ; Lost fanout ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[4..29] ; Lost fanout ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[4..6] ; Lost fanout ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[4..29] ; Lost fanout ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[4..6] ; Lost fanout ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[6] ; Lost fanout ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[6..29] ; Lost fanout ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[5] ; Lost fanout ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[5] ; Lost fanout ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[4] ; Lost fanout ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[4] ; Lost fanout ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[6] ; Lost fanout ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[6..29] ; Lost fanout ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[5] ; Lost fanout ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[5] ; Lost fanout ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[4] ; Lost fanout ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[4] ; Lost fanout ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[4..29] ; Lost fanout ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[4..6] ; Lost fanout ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[4..29] ; Lost fanout ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[4..6] ; Lost fanout ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[6] ; Lost fanout ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[6..29] ; Lost fanout ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[5] ; Lost fanout ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[5] ; Lost fanout ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[4] ; Lost fanout ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[4] ; Lost fanout ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[6] ; Lost fanout ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[6..29] ; Lost fanout ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[5] ; Lost fanout ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[5] ; Lost fanout ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[4] ; Lost fanout ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[4] ; Lost fanout ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[4..29] ; Lost fanout ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[4..6] ; Lost fanout ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[4..29] ; Lost fanout ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[4..6] ; Lost fanout ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[6] ; Lost fanout ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[6..29] ; Lost fanout ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[5] ; Lost fanout ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[5] ; Lost fanout ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[4] ; Lost fanout ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[4] ; Lost fanout ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[6] ; Lost fanout ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[6..29] ; Lost fanout ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[5] ; Lost fanout ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[5] ; Lost fanout ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[4] ; Lost fanout ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[4] ; Lost fanout ;; detector_tokens:m_x|state_data_process~5 ; Lost fanout ;; ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i|dps_extra_kick:dps_extra_inst|dps_current_state~2 ; Lost fanout ;; ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i|dps_extra_kick:dps_extra_inst|dps_current_state~3 ; Lost fanout ;; ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i|dps_extra_kick:dps_extra_inst|dps_current_state~4 ; Lost fanout ;; ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i|dps_extra_kick:dps_extra_inst|dps_current_state~5 ; Lost fanout ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|state_tx~2 ; Lost fanout ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|state_tx~3 ; Lost fanout ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|state_tx~4 ; Lost fanout ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_send:tx_fct_snd|state_fct_send~3 ; Lost fanout ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_send:tx_fct_snd|state_fct_send~4 ; Lost fanout ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_send:tx_fct_snd|state_fct_send_p~6 ; Lost fanout ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_counter:tx_fct_cnt|state_fct_p~2 ; Lost fanout ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_counter:tx_fct_cnt|state_fct_p~3 ; Lost fanout ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_counter:tx_fct_cnt|state_fct_receive~2 ; Lost fanout ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_counter:tx_fct_cnt|state_fct_receive~3 ; Lost fanout ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|state_fsm~9 ; Lost fanout ;; ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i|dps_extra_kick:dps_extra_inst|dps_current_state.PHASE_DONE_HIGH ; Stuck at GND due to stuck port clock ;; ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i|dps_extra_kick:dps_extra_inst|dps_current_state.PHASE_DONE_LOW_1 ; Stuck at GND due to stuck port clock ;; ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i|dps_extra_kick:dps_extra_inst|dps_current_state.PHASE_DONE_LOW_2 ; Stuck at GND due to stuck port clock ;; ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i|dps_extra_kick:dps_extra_inst|dps_current_state.PHASE_DONE_LOW_3 ; Stuck at GND due to stuck port clock ;; ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i|dps_extra_kick:dps_extra_inst|dps_current_state.PHASE_DONE_LOW_4 ; Stuck at GND due to stuck port clock ;; ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i|dps_extra_kick:dps_extra_inst|dps_current_state.PHASE_DONE_LOW_0 ; Stuck at GND due to stuck port clock ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[0,1] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[0,1] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[0,1] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[0,1] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[0,1] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[0,1] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[0,1] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[0,1] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[0,1] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[0,1] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:led_pio_test_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0,1] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_rx_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0,1] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_ready_rx_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0,1] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:data_flag_rx_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0,1] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:data_read_en_rx_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0,1] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fifo_full_rx_status_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0,1] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fifo_empty_rx_status_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0,1] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:link_start_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0,1] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:auto_start_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0,1] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:link_disable_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0,1] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:write_data_fifo_tx_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0,1] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:write_en_tx_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0,1] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fifo_full_tx_status_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0,1] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_tx_enable_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0,1] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_tx_ready_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0,1] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:data_info_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0,1] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:clock_sel_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0,1] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fsm_info_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0,1] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:counter_tx_fifo_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0,1] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:counter_rx_fifo_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0,1] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_axi_master_ni:hps_0_h2f_axi_master_agent|altera_merlin_address_alignment:align_address_to_size|address_burst[20..29] ; Lost fanout ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fifo_empty_tx_status_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0,1] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_tx_data_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0,1] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[1][0] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[1][1] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[1][3] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[1][6] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[1][7] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[1][8] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[1][9] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[1][10] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[1][11] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[1][12] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[1][13] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[0][0] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[0][1] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[0][3] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[0][6] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[0][7] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[0][8] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[0][9] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[0][10] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[0][11] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[0][12] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[0][13] ; Stuck at GND due to stuck port data_in ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_masked[0,1] ; Lost fanout ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_masked[0,1] ; Lost fanout ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_masked[0,1] ; Lost fanout ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_masked[0,1] ; Lost fanout ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_masked[0,1] ; Lost fanout ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_masked[0,1] ; Lost fanout ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_masked[0,1] ; Lost fanout ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_masked[0,1] ; Lost fanout ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_masked[0,1] ; Lost fanout ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_masked[0,1] ; Lost fanout ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_masked[0,1] ; Lost fanout ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_masked[0,1] ; Lost fanout ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_masked[0,1] ; Lost fanout ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_masked[0,1] ; Lost fanout ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_masked[0,1] ; Lost fanout ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_masked[0,1] ; Lost fanout ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_masked[0,1] ; Lost fanout ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_masked[0,1] ; Lost fanout ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_masked[0,1] ; Lost fanout ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_masked[0,1] ; Lost fanout ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_masked[0,1] ; Lost fanout ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_masked[0,1] ; Lost fanout ;; Total Number of Removed Registers = 4651 ; ;+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Removed Registers Triggering Further Register Optimizations ;+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Register name ; Reason for Removal ; Registers Removed due to This Register ;+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[29] ; Lost Fanouts ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[28], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[27], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[26], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[25], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[24], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[23], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[22], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[21], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[20], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[19], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[18], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[17], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[16], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[15], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[14], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[13], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[12], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[11], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[10], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[9], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[8], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[7], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[6], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[5], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[4], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[6], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[5], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[4], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[6], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[29], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[28], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[27], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[26], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[25], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[24], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[23], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[22], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[21], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[20], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[19], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[18], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[17], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[16], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[15], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[14], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[13], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[12], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[11], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[10], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[9], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[8], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[7], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[6], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[5], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[5], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[4], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[4] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[29] ; Lost Fanouts ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[28], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[27], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[26], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[25], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[24], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[23], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[22], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[21], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[20], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[19], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[18], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[17], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[16], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[15], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[14], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[13], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[12], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[11], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[10], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[9], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[8], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[7], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[6], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[5], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[4], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[6], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[5], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[4], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[6], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[29], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[28], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[27], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[26], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[25], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[24], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[23], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[22], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[21], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[20], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[19], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[18], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[17], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[16], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[15], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[14], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[13], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[12], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[11], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[10], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[9], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[8], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[7], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[6], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[5], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[5], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[4], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[4] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[29] ; Lost Fanouts ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[28], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[27], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[26], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[25], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[24], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[23], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[22], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[21], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[20], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[19], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[18], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[17], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[16], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[15], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[14], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[13], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[12], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[11], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[10], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[9], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[8], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[7], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[6], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[5], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[4], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[6], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[5], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[4], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[6], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[29], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[28], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[27], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[26], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[25], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[24], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[23], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[22], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[21], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[20], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[19], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[18], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[17], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[16], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[15], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[14], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[13], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[12], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[11], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[10], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[9], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[8], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[7], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[6], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[5], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[5], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[4], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[4] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[29] ; Lost Fanouts ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[28], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[27], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[26], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[25], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[24], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[23], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[22], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[21], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[20], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[19], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[18], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[17], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[16], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[15], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[14], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[13], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[12], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[11], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[10], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[9], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[8], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[7], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[6], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[5], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[4], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[6], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[5], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[4], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[6], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[29], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[28], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[27], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[26], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[25], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[24], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[23], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[22], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[21], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[20], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[19], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[18], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[17], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[16], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[15], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[14], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[13], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[12], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[11], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[10], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[9], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[8], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[7], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[6], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[5], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[5], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[4], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[4] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[29] ; Lost Fanouts ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[28], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[27], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[26], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[25], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[24], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[23], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[22], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[21], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[20], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[19], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[18], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[17], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[16], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[15], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[14], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[13], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[12], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[11], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[10], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[9], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[8], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[7], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[6], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[5], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[4], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[6], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[5], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[4], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[6], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[29], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[28], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[27], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[26], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[25], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[24], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[23], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[22], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[21], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[20], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[19], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[18], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[17], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[16], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[15], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[14], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[13], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[12], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[11], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[10], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[9], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[8], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[7], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[6], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[5], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[5], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[4], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[4] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[29] ; Lost Fanouts ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[28], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[27], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[26], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[25], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[24], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[23], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[22], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[21], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[20], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[19], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[18], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[17], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[16], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[15], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[14], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[13], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[12], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[11], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[10], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[9], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[8], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[7], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[6], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[5], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[4], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[6], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[5], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[4], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[6], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[29], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[28], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[27], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[26], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[25], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[24], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[23], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[22], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[21], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[20], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[19], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[18], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[17], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[16], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[15], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[14], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[13], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[12], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[11], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[10], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[9], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[8], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[7], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[6], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[5], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[5], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[4], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[4] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[29] ; Lost Fanouts ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[28], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[27], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[26], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[25], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[24], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[23], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[22], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[21], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[20], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[19], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[18], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[17], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[16], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[15], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[14], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[13], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[12], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[11], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[10], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[9], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[8], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[7], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[6], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[5], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[4], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[6], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[5], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[4], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[6], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[29], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[28], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[27], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[26], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[25], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[24], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[23], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[22], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[21], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[20], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[19], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[18], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[17], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[16], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[15], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[14], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[13], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[12], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[11], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[10], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[9], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[8], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[7], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[6], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[5], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[5], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[4], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[4] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[29] ; Lost Fanouts ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[28], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[27], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[26], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[25], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[24], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[23], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[22], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[21], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[20], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[19], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[18], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[17], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[16], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[15], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[14], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[13], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[12], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[11], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[10], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[9], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[8], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[7], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[6], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[5], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[4], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[6], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[5], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[4], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[6], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[29], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[28], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[27], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[26], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[25], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[24], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[23], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[22], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[21], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[20], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[19], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[18], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[17], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[16], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[15], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[14], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[13], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[12], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[11], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[10], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[9], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[8], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[7], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[6], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[5], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[5], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[4], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[4] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[29] ; Lost Fanouts ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[28], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[27], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[26], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[25], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[24], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[23], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[22], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[21], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[20], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[19], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[18], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[17], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[16], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[15], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[14], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[13], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[12], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[11], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[10], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[9], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[8], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[7], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[6], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[5], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[4], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[6], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[5], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[4], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[6], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[29], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[28], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[27], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[26], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[25], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[24], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[23], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[22], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[21], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[20], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[19], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[18], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[17], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[16], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[15], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[14], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[13], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[12], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[11], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[10], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[9], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[8], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[7], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[6], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[5], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[5], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[4], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[4] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[29] ; Lost Fanouts ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[28], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[27], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[26], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[25], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[24], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[23], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[22], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[21], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[20], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[19], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[18], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[17], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[16], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[15], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[14], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[13], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[12], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[11], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[10], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[9], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[8], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[7], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[6], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[5], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[4], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[6], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[5], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[4], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[6], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[29], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[28], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[27], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[26], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[25], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[24], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[23], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[22], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[21], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[20], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[19], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[18], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[17], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[16], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[15], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[14], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[13], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[12], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[11], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[10], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[9], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[8], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[7], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[6], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[5], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[5], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[4], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[4] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[29] ; Lost Fanouts ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[28], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[27], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[26], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[25], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[24], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[23], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[22], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[21], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[20], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[19], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[18], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[17], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[16], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[15], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[14], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[13], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[12], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[11], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[10], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[9], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[8], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[7], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[6], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[5], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[4], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[6], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[5], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[4], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[29], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[28], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[27], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[26], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[25], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[24], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[23], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[22], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[21], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[20], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[19], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[18], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[17], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[16], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[15], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[14], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[13], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[12], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[11], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[10], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[9], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[8], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[7], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[6], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[5], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[4] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[29] ; Lost Fanouts ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[28], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[27], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[26], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[25], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[24], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[23], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[22], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[21], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[20], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[19], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[18], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[17], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[16], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[15], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[14], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[13], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[12], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[11], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[10], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[9], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[8], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[7], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[6], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[5], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[4], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[6], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[5], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[4], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[29], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[28], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[27], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[26], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[25], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[24], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[23], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[22], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[21], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[20], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[19], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[18], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[17], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[16], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[15], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[14], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[13], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[12], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[11], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[10], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[9], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[8], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[7], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[6], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[5], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[4] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[29] ; Lost Fanouts ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[28], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[27], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[26], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[25], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[24], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[23], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[22], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[21], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[20], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[19], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[18], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[17], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[16], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[15], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[14], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[13], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[12], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[11], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[10], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[9], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[8], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[7], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[6], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[5], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[4], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[6], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[5], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[4], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[29], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[28], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[27], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[26], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[25], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[24], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[23], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[22], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[21], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[20], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[19], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[18], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[17], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[16], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[15], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[14], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[13], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[12], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[11], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[10], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[9], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[8], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[7], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[6], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[5], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[4] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[29] ; Lost Fanouts ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[28], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[27], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[26], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[25], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[24], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[23], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[22], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[21], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[20], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[19], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[18], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[17], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[16], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[15], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[14], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[13], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[12], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[11], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[10], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[9], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[8], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[7], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[6], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[5], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[4], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[6], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[5], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[4], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[29], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[28], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[27], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[26], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[25], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[24], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[23], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[22], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[21], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[20], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[19], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[18], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[17], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[16], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[15], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[14], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[13], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[12], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[11], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[10], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[9], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[8], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[7], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[6], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[5], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[4] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[29] ; Lost Fanouts ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[28], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[27], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[26], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[25], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[24], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[23], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[22], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[21], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[20], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[19], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[18], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[17], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[16], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[15], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[14], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[13], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[12], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[11], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[10], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[9], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[8], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[7], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[6], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[5], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[4], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[6], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[5], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[4], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[29], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[28], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[27], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[26], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[25], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[24], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[23], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[22], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[21], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[20], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[19], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[18], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[17], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[16], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[15], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[14], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[13], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[12], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[11], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[10], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[9], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[8], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[7], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[6], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[5], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[4] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[29] ; Lost Fanouts ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[28], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[27], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[26], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[25], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[24], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[23], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[22], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[21], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[20], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[19], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[18], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[17], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[16], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[15], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[14], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[13], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[12], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[11], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[10], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[9], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[8], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[7], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[6], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[5], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[4], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[6], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[5], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[4], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[29], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[28], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[27], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[26], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[25], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[24], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[23], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[22], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[21], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[20], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[19], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[18], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[17], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[16], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[15], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[14], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[13], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[12], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[11], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[10], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[9], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[8], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[7], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[6], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[5], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[4] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[29] ; Lost Fanouts ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[28], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[27], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[26], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[25], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[24], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[23], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[22], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[21], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[20], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[19], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[18], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[17], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[16], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[15], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[14], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[13], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[12], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[11], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[10], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[9], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[8], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[7], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[6], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[5], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[4], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[6], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[5], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[4], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[29], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[28], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[27], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[26], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[25], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[24], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[23], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[22], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[21], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[20], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[19], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[18], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[17], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[16], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[15], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[14], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[13], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[12], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[11], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[10], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[9], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[8], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[7], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[6], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[5], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[4] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[29] ; Lost Fanouts ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[28], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[27], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[26], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[25], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[24], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[23], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[22], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[21], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[20], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[19], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[18], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[17], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[16], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[15], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[14], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[13], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[12], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[11], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[10], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[9], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[8], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[7], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[6], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[5], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[4], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[6], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[5], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[4], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[29], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[28], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[27], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[26], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[25], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[24], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[23], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[22], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[21], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[20], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[19], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[18], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[17], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[16], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[15], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[14], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[13], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[12], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[11], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[10], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[9], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[8], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[7], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[6], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[5], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[4] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[29] ; Lost Fanouts ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[28], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[27], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[26], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[25], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[24], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[23], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[22], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[21], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[20], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[19], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[18], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[17], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[16], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[15], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[14], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[13], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[12], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[11], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[10], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[9], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[8], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[7], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[6], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[5], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[4], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[6], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[5], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[4], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[29], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[28], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[27], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[26], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[25], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[24], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[23], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[22], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[21], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[20], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[19], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[18], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[17], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[16], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[15], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[14], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[13], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[12], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[11], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[10], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[9], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[8], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[7], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[6], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[5], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[4] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[29] ; Lost Fanouts ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[28], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[27], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[26], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[25], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[24], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[23], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[22], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[21], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[20], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[19], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[18], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[17], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[16], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[15], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[14], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[13], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[12], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[11], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[10], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[9], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[8], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[7], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[6], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[5], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[4], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[6], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[5], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[4], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[29], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[28], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[27], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[26], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[25], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[24], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[23], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[22], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[21], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[20], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[19], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[18], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[17], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[16], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[15], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[14], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[13], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[12], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[11], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[10], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[9], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[8], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[7], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[6], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[5], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[4] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[29] ; Lost Fanouts ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[28], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[27], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[26], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[25], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[24], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[23], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[22], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[21], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[20], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[19], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[18], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[17], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[16], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[15], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[14], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[13], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[12], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[11], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[10], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[9], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[8], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[7], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[6], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[5], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[4], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[6], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[5], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[4], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[29], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[28], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[27], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[26], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[25], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[24], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[23], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[22], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[21], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[20], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[19], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[18], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[17], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[16], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[15], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[14], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[13], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[12], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[11], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[10], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[9], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[8], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[7], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[6], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[5], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[4] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[29] ; Lost Fanouts ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[28], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[27], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[26], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[25], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[24], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[23], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[22], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[21], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[20], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[19], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[18], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[17], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[16], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[15], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[14], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[13], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[12], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[11], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[10], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[9], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[8], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[7], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[6], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[5], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[4], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[6], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[5], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[4], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[29], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[28], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[27], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[26], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[25], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[24], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[23], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[22], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[21], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[20], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[19], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[18], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[17], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[16], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[15], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[14], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[13], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[12], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[11], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[10], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[9], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[8], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[7], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[6], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[5], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[4] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_021|locked[0] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_traffic_limiter:hps_0_h2f_axi_master_wr_limiter|last_channel[21], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_021|saved_grant[0], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[68], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_021|altera_merlin_arbitrator:arb|top_priority_reg[1], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[1], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rsp_fifo|mem[1][68], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rsp_fifo|mem[0][68], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:counter_rx_fifo_s1_translator|wait_latency_counter[1], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[6], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[5], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[4], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_axi_master_ni:hps_0_h2f_axi_master_agent|altera_merlin_address_alignment:align_address_to_size|address_burst[29], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_axi_master_ni:hps_0_h2f_axi_master_agent|altera_merlin_address_alignment:align_address_to_size|address_burst[28], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_axi_master_ni:hps_0_h2f_axi_master_agent|altera_merlin_address_alignment:align_address_to_size|address_burst[27], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_axi_master_ni:hps_0_h2f_axi_master_agent|altera_merlin_address_alignment:align_address_to_size|address_burst[26], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_axi_master_ni:hps_0_h2f_axi_master_agent|altera_merlin_address_alignment:align_address_to_size|address_burst[25], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_axi_master_ni:hps_0_h2f_axi_master_agent|altera_merlin_address_alignment:align_address_to_size|address_burst[24], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_axi_master_ni:hps_0_h2f_axi_master_agent|altera_merlin_address_alignment:align_address_to_size|address_burst[23], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_axi_master_ni:hps_0_h2f_axi_master_agent|altera_merlin_address_alignment:align_address_to_size|address_burst[22], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_axi_master_ni:hps_0_h2f_axi_master_agent|altera_merlin_address_alignment:align_address_to_size|address_burst[21], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_axi_master_ni:hps_0_h2f_axi_master_agent|altera_merlin_address_alignment:align_address_to_size|address_burst[20] ;; detector_tokens:m_x|control[2] ; Stuck at GND ; detector_tokens:m_x|info[8], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_data_info:data_info|readdata[8], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:data_info_s1_translator|av_readdata_pre[8], ;; ; ; detector_tokens:m_x|rx_got_null, detector_tokens:m_x|rx_got_time_code, ;; ; ; detector_tokens:m_x|rx_got_fct, detector_tokens:m_x|control_l_r[2], ;; ; ; detector_tokens:m_x|info[12], detector_tokens:m_x|info[3], ;; ; ; detector_tokens:m_x|info[1], detector_tokens:m_x|info[0], ;; ; ; ulight_fifo:u0|ulight_fifo_data_info:data_info|readdata[12], ;; ; ; ulight_fifo:u0|ulight_fifo_data_info:data_info|readdata[3], ;; ; ; ulight_fifo:u0|ulight_fifo_data_info:data_info|readdata[1], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:data_info_s1_translator|av_readdata_pre[12], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:data_info_s1_translator|av_readdata_pre[3], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:data_info_s1_translator|av_readdata_pre[1], ;; ; ; ulight_fifo:u0|ulight_fifo_data_info:data_info|readdata[0], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:data_info_s1_translator|av_readdata_pre[0] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_001|locked[0] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_traffic_limiter:hps_0_h2f_axi_master_wr_limiter|last_channel[1], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_001|saved_grant[0], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[68], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_001|altera_merlin_arbitrator:arb|top_priority_reg[1], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[1], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rsp_fifo|mem[1][68], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rsp_fifo|mem[0][68], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_rx_s1_translator|wait_latency_counter[1], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[6], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[5], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[4] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_020|locked[0] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_traffic_limiter:hps_0_h2f_axi_master_wr_limiter|last_channel[20], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_020|saved_grant[0], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[68], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_020|altera_merlin_arbitrator:arb|top_priority_reg[1], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[1], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rsp_fifo|mem[1][68], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rsp_fifo|mem[0][68], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:counter_tx_fifo_s1_translator|wait_latency_counter[1], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[6], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[5], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[4] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_019|locked[0] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_traffic_limiter:hps_0_h2f_axi_master_wr_limiter|last_channel[19], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_019|saved_grant[0], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[68], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_019|altera_merlin_arbitrator:arb|top_priority_reg[1], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[1], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rsp_fifo|mem[1][68], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rsp_fifo|mem[0][68], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fsm_info_s1_translator|wait_latency_counter[1], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[6], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[5], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[4] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_017|locked[0] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_traffic_limiter:hps_0_h2f_axi_master_wr_limiter|last_channel[17], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_017|saved_grant[0], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[68], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_017|altera_merlin_arbitrator:arb|top_priority_reg[1], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[1], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rsp_fifo|mem[1][68], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rsp_fifo|mem[0][68], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:data_info_s1_translator|wait_latency_counter[1], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[6], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[5], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[4] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_016|locked[0] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_traffic_limiter:hps_0_h2f_axi_master_wr_limiter|last_channel[16], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_016|saved_grant[0], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[68], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_016|altera_merlin_arbitrator:arb|top_priority_reg[1], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[1], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rsp_fifo|mem[1][68], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rsp_fifo|mem[0][68], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_ready_s1_translator|wait_latency_counter[1], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[6], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[5], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[4] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_013|locked[0] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_traffic_limiter:hps_0_h2f_axi_master_wr_limiter|last_channel[13], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_013|saved_grant[0], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[68], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_013|altera_merlin_arbitrator:arb|top_priority_reg[1], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[1], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][68], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][68], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_empty_tx_status_s1_translator|wait_latency_counter[1], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[6], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[5], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[4] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_012|locked[0] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_traffic_limiter:hps_0_h2f_axi_master_wr_limiter|last_channel[12], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_012|saved_grant[0], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[68], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_012|altera_merlin_arbitrator:arb|top_priority_reg[1], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[1], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][68], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][68], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_full_tx_status_s1_translator|wait_latency_counter[1], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[6], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[5], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[4] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_006|locked[0] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_traffic_limiter:hps_0_h2f_axi_master_wr_limiter|last_channel[6], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_006|saved_grant[0], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[68], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_006|altera_merlin_arbitrator:arb|top_priority_reg[1], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[1], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][68], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][68], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_empty_rx_status_s1_translator|wait_latency_counter[1], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[6], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[5], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[4] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_005|locked[0] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_traffic_limiter:hps_0_h2f_axi_master_wr_limiter|last_channel[5], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_005|saved_grant[0], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[68], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_005|altera_merlin_arbitrator:arb|top_priority_reg[1], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[1], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][68], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][68], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_full_rx_status_s1_translator|wait_latency_counter[1], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[6], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[5], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[4] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_003|locked[0] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_traffic_limiter:hps_0_h2f_axi_master_wr_limiter|last_channel[3], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_003|saved_grant[0], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[68], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_003|altera_merlin_arbitrator:arb|top_priority_reg[1], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[1], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rsp_fifo|mem[1][68], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rsp_fifo|mem[0][68], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:data_flag_rx_s1_translator|wait_latency_counter[1], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[6], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[5], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[4] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_002|locked[0] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_traffic_limiter:hps_0_h2f_axi_master_wr_limiter|last_channel[2], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_002|saved_grant[0], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[68], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_002|altera_merlin_arbitrator:arb|top_priority_reg[1], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[1], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rsp_fifo|mem[1][68], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rsp_fifo|mem[0][68], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_ready_rx_s1_translator|wait_latency_counter[1], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[6], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[5], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[4] ;; detector_tokens:m_x|control[0] ; Stuck at GND ; detector_tokens:m_x|info[6], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_data_info:data_info|readdata[6], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:data_info_s1_translator|av_readdata_pre[6], ;; ; ; detector_tokens:m_x|control_l_r[0], detector_tokens:m_x|info[10], ;; ; ; ulight_fifo:u0|ulight_fifo_data_info:data_info|readdata[10], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:data_info_s1_translator|av_readdata_pre[10] ;; detector_tokens:m_x|control[3] ; Stuck at GND ; detector_tokens:m_x|info[9], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_data_info:data_info|readdata[9], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:data_info_s1_translator|av_readdata_pre[9], ;; ; ; detector_tokens:m_x|control_l_r[3], detector_tokens:m_x|info[13], ;; ; ; ulight_fifo:u0|ulight_fifo_data_info:data_info|readdata[13], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:data_info_s1_translator|av_readdata_pre[13] ;; detector_tokens:m_x|control[1] ; Stuck at GND ; detector_tokens:m_x|info[7], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_data_info:data_info|readdata[7], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:data_info_s1_translator|av_readdata_pre[7], ;; ; ; detector_tokens:m_x|control_l_r[1], detector_tokens:m_x|info[11], ;; ; ; ulight_fifo:u0|ulight_fifo_data_info:data_info|readdata[11], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:data_info_s1_translator|av_readdata_pre[11] ;; ulight_fifo:u0|ulight_fifo_counter_rx_fifo:counter_rx_fifo|readdata[31] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:counter_rx_fifo_s1_translator|av_readdata_pre[31], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_axi_master_ni:hps_0_h2f_axi_master_agent|burst_bytecount[1], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_axi_master_ni:hps_0_h2f_axi_master_agent|burst_bytecount[0], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo|mem[1][31], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo|mem[0][31] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_uncompressed_read_reg ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rsp_fifo|mem[1][73], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rsp_fifo|mem[1][72], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rsp_fifo|mem[0][73], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rsp_fifo|mem[0][72] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_uncompressed_read_reg ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rsp_fifo|mem[1][73], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rsp_fifo|mem[1][72], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rsp_fifo|mem[0][73], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rsp_fifo|mem[0][72] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_uncompressed_read_reg ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rsp_fifo|mem[1][73], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rsp_fifo|mem[1][72], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rsp_fifo|mem[0][73], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rsp_fifo|mem[0][72] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_uncompressed_read_reg ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][73], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][72], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][73], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][72] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[99] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rsp_fifo|mem[1][99], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rsp_fifo|mem[0][99], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rsp_fifo|mem[0][69], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rsp_fifo|mem[1][69] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_uncompressed_read_reg ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rsp_fifo|mem[1][73], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rsp_fifo|mem[1][72], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rsp_fifo|mem[0][73], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rsp_fifo|mem[0][72] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[99] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][99], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][99], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][69], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][69] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_uncompressed_read_reg ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][73], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][72], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][73], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][72] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_uncompressed_read_reg ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rsp_fifo|mem[1][73], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rsp_fifo|mem[1][72], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rsp_fifo|mem[0][73], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rsp_fifo|mem[0][72] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_uncompressed_read_reg ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rsp_fifo|mem[1][73], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rsp_fifo|mem[1][72], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rsp_fifo|mem[0][73], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rsp_fifo|mem[0][72] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[99] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][99], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][99], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][69], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][69] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[99] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rsp_fifo|mem[1][99], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rsp_fifo|mem[0][99], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rsp_fifo|mem[0][69], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rsp_fifo|mem[1][69] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_uncompressed_read_reg ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rsp_fifo|mem[1][73], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rsp_fifo|mem[1][72], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rsp_fifo|mem[0][73], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rsp_fifo|mem[0][72] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_uncompressed_read_reg ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][73], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][72], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][73], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][72] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[99] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][99], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][99], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][69], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][69] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_uncompressed_read_reg ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][73], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][72], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][73], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][72] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_uncompressed_read_reg ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rsp_fifo|mem[1][73], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rsp_fifo|mem[1][72], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rsp_fifo|mem[0][73], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rsp_fifo|mem[0][72] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_uncompressed_read_reg ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][73], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][72], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][73], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][72] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[99] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rsp_fifo|mem[1][99], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rsp_fifo|mem[0][99], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rsp_fifo|mem[0][69], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rsp_fifo|mem[1][69] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[99] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rsp_fifo|mem[1][99], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rsp_fifo|mem[0][99], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rsp_fifo|mem[0][69], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rsp_fifo|mem[1][69] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_uncompressed_read_reg ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rsp_fifo|mem[1][73], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rsp_fifo|mem[1][72], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rsp_fifo|mem[0][73], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rsp_fifo|mem[0][72] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_uncompressed_read_reg ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rsp_fifo|mem[1][73], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rsp_fifo|mem[1][72], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rsp_fifo|mem[0][73], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rsp_fifo|mem[0][72] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_uncompressed_read_reg ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rsp_fifo|mem[1][73], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rsp_fifo|mem[1][72], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rsp_fifo|mem[0][73], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rsp_fifo|mem[0][72] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_uncompressed_read_reg ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rsp_fifo|mem[1][73], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rsp_fifo|mem[1][72], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rsp_fifo|mem[0][73], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rsp_fifo|mem[0][72] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[99] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rsp_fifo|mem[1][99], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rsp_fifo|mem[0][99], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rsp_fifo|mem[0][69], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rsp_fifo|mem[1][69] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_uncompressed_read_reg ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rsp_fifo|mem[1][73], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rsp_fifo|mem[1][72], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rsp_fifo|mem[0][73], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rsp_fifo|mem[0][72] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_uncompressed_read_reg ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rsp_fifo|mem[1][73], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rsp_fifo|mem[1][72], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rsp_fifo|mem[0][73], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rsp_fifo|mem[0][72] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_uncompressed_read_reg ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rsp_fifo|mem[1][73], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rsp_fifo|mem[1][72], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rsp_fifo|mem[0][73], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rsp_fifo|mem[0][72] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[99] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rsp_fifo|mem[1][99], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rsp_fifo|mem[0][99], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rsp_fifo|mem[0][69], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rsp_fifo|mem[1][69] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[99] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rsp_fifo|mem[1][99], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rsp_fifo|mem[0][99], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rsp_fifo|mem[0][69], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rsp_fifo|mem[1][69] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[99] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][99], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][99], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][69], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][69] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_uncompressed_read_reg ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rsp_fifo|mem[1][73], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rsp_fifo|mem[1][72], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rsp_fifo|mem[0][73], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rsp_fifo|mem[0][72] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[99] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rsp_fifo|mem[1][99], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rsp_fifo|mem[0][99], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rsp_fifo|mem[0][69], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rsp_fifo|mem[1][69] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_uncompressed_read_reg ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rsp_fifo|mem[1][73], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rsp_fifo|mem[1][72], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rsp_fifo|mem[0][73], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rsp_fifo|mem[0][72] ;; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_full_tx_status|readdata[27] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_full_tx_status_s1_translator|av_readdata_pre[27], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[1][27], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[0][27] ;; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_full_tx_status|readdata[30] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_full_tx_status_s1_translator|av_readdata_pre[30], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[1][30], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[0][30] ;; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_full_tx_status|readdata[29] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_full_tx_status_s1_translator|av_readdata_pre[29], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[1][29], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[0][29] ;; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_full_tx_status|readdata[31] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_full_tx_status_s1_translator|av_readdata_pre[31], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[1][31], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[0][31] ;; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_full_tx_status|readdata[20] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_full_tx_status_s1_translator|av_readdata_pre[20], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[1][20], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[0][20] ;; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_full_tx_status|readdata[19] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_full_tx_status_s1_translator|av_readdata_pre[19], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[1][19], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[0][19] ;; ulight_fifo:u0|ulight_fifo_counter_rx_fifo:fsm_info|readdata[27] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fsm_info_s1_translator|av_readdata_pre[27], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[1][27], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[0][27] ;; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_full_tx_status|readdata[28] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_full_tx_status_s1_translator|av_readdata_pre[28], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[1][28], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[0][28] ;; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_full_tx_status|readdata[26] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_full_tx_status_s1_translator|av_readdata_pre[26], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[1][26], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[0][26] ;; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_full_tx_status|readdata[25] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_full_tx_status_s1_translator|av_readdata_pre[25], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[1][25], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[0][25] ;; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_full_tx_status|readdata[21] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_full_tx_status_s1_translator|av_readdata_pre[21], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[1][21], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[0][21] ;; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_full_tx_status|readdata[24] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_full_tx_status_s1_translator|av_readdata_pre[24], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[1][24], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[0][24] ;; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_full_tx_status|readdata[22] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_full_tx_status_s1_translator|av_readdata_pre[22], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[1][22], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[0][22] ;; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_full_tx_status|readdata[23] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_full_tx_status_s1_translator|av_readdata_pre[23], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[1][23], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[0][23] ;; ulight_fifo:u0|ulight_fifo_counter_rx_fifo:fsm_info|readdata[17] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fsm_info_s1_translator|av_readdata_pre[17], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[1][17], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[0][17] ;; ulight_fifo:u0|ulight_fifo_counter_rx_fifo:fsm_info|readdata[28] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fsm_info_s1_translator|av_readdata_pre[28], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[1][28], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[0][28] ;; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_full_rx_status|readdata[1] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_full_rx_status_s1_translator|av_readdata_pre[1], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[1][1], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[0][1] ;; ulight_fifo:u0|ulight_fifo_counter_rx_fifo:fsm_info|readdata[26] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fsm_info_s1_translator|av_readdata_pre[26], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[1][26], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[0][26] ;; ulight_fifo:u0|ulight_fifo_counter_rx_fifo:fsm_info|readdata[25] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fsm_info_s1_translator|av_readdata_pre[25], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[1][25], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[0][25] ;; ulight_fifo:u0|ulight_fifo_counter_rx_fifo:fsm_info|readdata[24] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fsm_info_s1_translator|av_readdata_pre[24], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[1][24], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[0][24] ;; ulight_fifo:u0|ulight_fifo_counter_rx_fifo:fsm_info|readdata[23] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fsm_info_s1_translator|av_readdata_pre[23], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[1][23], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[0][23] ;; ulight_fifo:u0|ulight_fifo_counter_rx_fifo:fsm_info|readdata[22] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fsm_info_s1_translator|av_readdata_pre[22], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[1][22], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[0][22] ;; ulight_fifo:u0|ulight_fifo_counter_rx_fifo:fsm_info|readdata[21] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fsm_info_s1_translator|av_readdata_pre[21], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[1][21], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[0][21] ;; ulight_fifo:u0|ulight_fifo_counter_rx_fifo:fsm_info|readdata[20] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fsm_info_s1_translator|av_readdata_pre[20], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[1][20], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[0][20] ;; ulight_fifo:u0|ulight_fifo_counter_rx_fifo:fsm_info|readdata[19] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fsm_info_s1_translator|av_readdata_pre[19], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[1][19], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[0][19] ;; ulight_fifo:u0|ulight_fifo_counter_rx_fifo:fsm_info|readdata[18] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fsm_info_s1_translator|av_readdata_pre[18], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[1][18], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[0][18] ;; ulight_fifo:u0|ulight_fifo_counter_rx_fifo:fsm_info|readdata[5] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fsm_info_s1_translator|av_readdata_pre[5], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[1][5], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[0][5] ;; ulight_fifo:u0|ulight_fifo_counter_rx_fifo:fsm_info|readdata[16] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fsm_info_s1_translator|av_readdata_pre[16], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[1][16], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[0][16] ;; ulight_fifo:u0|ulight_fifo_counter_rx_fifo:fsm_info|readdata[15] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fsm_info_s1_translator|av_readdata_pre[15], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[1][15], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[0][15] ;; ulight_fifo:u0|ulight_fifo_counter_rx_fifo:fsm_info|readdata[14] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fsm_info_s1_translator|av_readdata_pre[14], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[1][14], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[0][14] ;; ulight_fifo:u0|ulight_fifo_counter_rx_fifo:fsm_info|readdata[13] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fsm_info_s1_translator|av_readdata_pre[13], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[1][13], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[0][13] ;; ulight_fifo:u0|ulight_fifo_counter_rx_fifo:fsm_info|readdata[12] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fsm_info_s1_translator|av_readdata_pre[12], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[1][12], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[0][12] ;; ulight_fifo:u0|ulight_fifo_counter_rx_fifo:fsm_info|readdata[11] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fsm_info_s1_translator|av_readdata_pre[11], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[1][11], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[0][11] ;; ulight_fifo:u0|ulight_fifo_counter_rx_fifo:fsm_info|readdata[10] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fsm_info_s1_translator|av_readdata_pre[10], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[1][10], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[0][10] ;; ulight_fifo:u0|ulight_fifo_counter_rx_fifo:fsm_info|readdata[9] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fsm_info_s1_translator|av_readdata_pre[9], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[1][9], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[0][9] ;; ulight_fifo:u0|ulight_fifo_counter_rx_fifo:fsm_info|readdata[8] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fsm_info_s1_translator|av_readdata_pre[8], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[1][8], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[0][8] ;; ulight_fifo:u0|ulight_fifo_counter_rx_fifo:fsm_info|readdata[7] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fsm_info_s1_translator|av_readdata_pre[7], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[1][7], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[0][7] ;; ulight_fifo:u0|ulight_fifo_counter_rx_fifo:fsm_info|readdata[6] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fsm_info_s1_translator|av_readdata_pre[6], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[1][6], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[0][6] ;; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_full_rx_status|readdata[11] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_full_rx_status_s1_translator|av_readdata_pre[11], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[1][11], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[0][11] ;; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_full_rx_status|readdata[23] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_full_rx_status_s1_translator|av_readdata_pre[23], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[1][23], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[0][23] ;; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_full_rx_status|readdata[22] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_full_rx_status_s1_translator|av_readdata_pre[22], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[1][22], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[0][22] ;; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_full_rx_status|readdata[21] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_full_rx_status_s1_translator|av_readdata_pre[21], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[1][21], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[0][21] ;; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_full_rx_status|readdata[20] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_full_rx_status_s1_translator|av_readdata_pre[20], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[1][20], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[0][20] ;; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_full_rx_status|readdata[19] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_full_rx_status_s1_translator|av_readdata_pre[19], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[1][19], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[0][19] ;; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_full_rx_status|readdata[18] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_full_rx_status_s1_translator|av_readdata_pre[18], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[1][18], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[0][18] ;; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_full_rx_status|readdata[17] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_full_rx_status_s1_translator|av_readdata_pre[17], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[1][17], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[0][17] ;; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_full_rx_status|readdata[16] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_full_rx_status_s1_translator|av_readdata_pre[16], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[1][16], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[0][16] ;; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_full_rx_status|readdata[15] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_full_rx_status_s1_translator|av_readdata_pre[15], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[1][15], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[0][15] ;; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_full_rx_status|readdata[14] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_full_rx_status_s1_translator|av_readdata_pre[14], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[1][14], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[0][14] ;; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_full_rx_status|readdata[13] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_full_rx_status_s1_translator|av_readdata_pre[13], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[1][13], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[0][13] ;; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_full_rx_status|readdata[12] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_full_rx_status_s1_translator|av_readdata_pre[12], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[1][12], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[0][12] ;; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_full_rx_status|readdata[24] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_full_rx_status_s1_translator|av_readdata_pre[24], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[1][24], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[0][24] ;; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_full_rx_status|readdata[10] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_full_rx_status_s1_translator|av_readdata_pre[10], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[1][10], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[0][10] ;; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_full_rx_status|readdata[9] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_full_rx_status_s1_translator|av_readdata_pre[9], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[1][9], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[0][9] ;; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_full_rx_status|readdata[8] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_full_rx_status_s1_translator|av_readdata_pre[8], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[1][8], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[0][8] ;; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_full_rx_status|readdata[7] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_full_rx_status_s1_translator|av_readdata_pre[7], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[1][7], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[0][7] ;; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_full_rx_status|readdata[6] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_full_rx_status_s1_translator|av_readdata_pre[6], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[1][6], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[0][6] ;; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_full_rx_status|readdata[5] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_full_rx_status_s1_translator|av_readdata_pre[5], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[1][5], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[0][5] ;; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_full_rx_status|readdata[4] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_full_rx_status_s1_translator|av_readdata_pre[4], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[1][4], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[0][4] ;; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_full_rx_status|readdata[3] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_full_rx_status_s1_translator|av_readdata_pre[3], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[1][3], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[0][3] ;; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_full_rx_status|readdata[2] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_full_rx_status_s1_translator|av_readdata_pre[2], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[1][2], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[0][2] ;; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:timecode_tx_ready|readdata[30] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_ready_s1_translator|av_readdata_pre[30], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rdata_fifo|mem[1][30], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rdata_fifo|mem[0][30] ;; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_empty_tx_status|readdata[31] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_empty_tx_status_s1_translator|av_readdata_pre[31], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rdata_fifo|mem[1][31], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rdata_fifo|mem[0][31] ;; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_full_tx_status|readdata[5] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_full_tx_status_s1_translator|av_readdata_pre[5], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[1][5], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[0][5] ;; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_full_tx_status|readdata[17] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_full_tx_status_s1_translator|av_readdata_pre[17], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[1][17], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[0][17] ;; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_full_tx_status|readdata[16] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_full_tx_status_s1_translator|av_readdata_pre[16], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[1][16], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[0][16] ;; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_full_tx_status|readdata[15] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_full_tx_status_s1_translator|av_readdata_pre[15], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[1][15], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[0][15] ;; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_full_tx_status|readdata[14] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_full_tx_status_s1_translator|av_readdata_pre[14], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[1][14], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[0][14] ;; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_full_tx_status|readdata[13] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_full_tx_status_s1_translator|av_readdata_pre[13], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[1][13], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[0][13] ;; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_full_tx_status|readdata[12] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_full_tx_status_s1_translator|av_readdata_pre[12], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[1][12], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[0][12] ;; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_full_tx_status|readdata[11] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_full_tx_status_s1_translator|av_readdata_pre[11], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[1][11], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[0][11] ;; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_full_tx_status|readdata[10] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_full_tx_status_s1_translator|av_readdata_pre[10], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[1][10], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[0][10] ;; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_full_tx_status|readdata[9] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_full_tx_status_s1_translator|av_readdata_pre[9], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[1][9], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[0][9] ;; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_full_tx_status|readdata[8] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_full_tx_status_s1_translator|av_readdata_pre[8], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[1][8], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[0][8] ;; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_full_tx_status|readdata[7] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_full_tx_status_s1_translator|av_readdata_pre[7], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[1][7], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[0][7] ;; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_full_tx_status|readdata[6] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_full_tx_status_s1_translator|av_readdata_pre[6], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[1][6], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[0][6] ;; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_full_tx_status|readdata[18] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_full_tx_status_s1_translator|av_readdata_pre[18], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[1][18], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[0][18] ;; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_full_tx_status|readdata[4] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_full_tx_status_s1_translator|av_readdata_pre[4], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[1][4], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[0][4] ;; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_full_tx_status|readdata[3] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_full_tx_status_s1_translator|av_readdata_pre[3], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[1][3], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[0][3] ;; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_full_tx_status|readdata[2] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_full_tx_status_s1_translator|av_readdata_pre[2], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[1][2], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[0][2] ;; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_full_tx_status|readdata[1] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_full_tx_status_s1_translator|av_readdata_pre[1], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[1][1], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[0][1] ;; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_full_rx_status|readdata[31] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_full_rx_status_s1_translator|av_readdata_pre[31], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[1][31], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[0][31] ;; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_full_rx_status|readdata[30] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_full_rx_status_s1_translator|av_readdata_pre[30], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[1][30], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[0][30] ;; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_full_rx_status|readdata[29] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_full_rx_status_s1_translator|av_readdata_pre[29], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[1][29], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[0][29] ;; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_full_rx_status|readdata[28] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_full_rx_status_s1_translator|av_readdata_pre[28], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[1][28], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[0][28] ;; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_full_rx_status|readdata[27] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_full_rx_status_s1_translator|av_readdata_pre[27], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[1][27], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[0][27] ;; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_full_rx_status|readdata[26] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_full_rx_status_s1_translator|av_readdata_pre[26], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[1][26], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[0][26] ;; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_full_rx_status|readdata[25] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_full_rx_status_s1_translator|av_readdata_pre[25], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[1][25], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[0][25] ;; ulight_fifo:u0|ulight_fifo_timecode_rx:timecode_rx|readdata[29] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_rx_s1_translator|av_readdata_pre[29], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rdata_fifo|mem[1][29], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rdata_fifo|mem[0][29] ;; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:timecode_tx_ready|readdata[8] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_ready_s1_translator|av_readdata_pre[8], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rdata_fifo|mem[1][8], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rdata_fifo|mem[0][8] ;; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:timecode_tx_ready|readdata[7] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_ready_s1_translator|av_readdata_pre[7], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rdata_fifo|mem[1][7], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rdata_fifo|mem[0][7] ;; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:timecode_tx_ready|readdata[6] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_ready_s1_translator|av_readdata_pre[6], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rdata_fifo|mem[1][6], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rdata_fifo|mem[0][6] ;; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:timecode_tx_ready|readdata[5] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_ready_s1_translator|av_readdata_pre[5], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rdata_fifo|mem[1][5], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rdata_fifo|mem[0][5] ;; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:timecode_tx_ready|readdata[4] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_ready_s1_translator|av_readdata_pre[4], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rdata_fifo|mem[1][4], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rdata_fifo|mem[0][4] ;; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:timecode_tx_ready|readdata[3] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_ready_s1_translator|av_readdata_pre[3], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rdata_fifo|mem[1][3], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rdata_fifo|mem[0][3] ;; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:timecode_tx_ready|readdata[2] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_ready_s1_translator|av_readdata_pre[2], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rdata_fifo|mem[1][2], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rdata_fifo|mem[0][2] ;; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:timecode_tx_ready|readdata[1] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_ready_s1_translator|av_readdata_pre[1], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rdata_fifo|mem[1][1], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rdata_fifo|mem[0][1] ;; ulight_fifo:u0|ulight_fifo_timecode_rx:timecode_rx|readdata[31] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_rx_s1_translator|av_readdata_pre[31], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rdata_fifo|mem[1][31], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rdata_fifo|mem[0][31] ;; ulight_fifo:u0|ulight_fifo_timecode_rx:timecode_rx|readdata[30] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_rx_s1_translator|av_readdata_pre[30], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rdata_fifo|mem[1][30], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rdata_fifo|mem[0][30] ;; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:timecode_tx_ready|readdata[9] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_ready_s1_translator|av_readdata_pre[9], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rdata_fifo|mem[1][9], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rdata_fifo|mem[0][9] ;; ulight_fifo:u0|ulight_fifo_timecode_rx:timecode_rx|readdata[28] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_rx_s1_translator|av_readdata_pre[28], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rdata_fifo|mem[1][28], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rdata_fifo|mem[0][28] ;; ulight_fifo:u0|ulight_fifo_timecode_rx:timecode_rx|readdata[27] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_rx_s1_translator|av_readdata_pre[27], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rdata_fifo|mem[1][27], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rdata_fifo|mem[0][27] ;; ulight_fifo:u0|ulight_fifo_timecode_rx:timecode_rx|readdata[26] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_rx_s1_translator|av_readdata_pre[26], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rdata_fifo|mem[1][26], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rdata_fifo|mem[0][26] ;; ulight_fifo:u0|ulight_fifo_timecode_rx:timecode_rx|readdata[25] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_rx_s1_translator|av_readdata_pre[25], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rdata_fifo|mem[1][25], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rdata_fifo|mem[0][25] ;; ulight_fifo:u0|ulight_fifo_timecode_rx:timecode_rx|readdata[24] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_rx_s1_translator|av_readdata_pre[24], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rdata_fifo|mem[1][24], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rdata_fifo|mem[0][24] ;; ulight_fifo:u0|ulight_fifo_timecode_rx:timecode_rx|readdata[23] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_rx_s1_translator|av_readdata_pre[23], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rdata_fifo|mem[1][23], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rdata_fifo|mem[0][23] ;; ulight_fifo:u0|ulight_fifo_timecode_rx:timecode_rx|readdata[22] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_rx_s1_translator|av_readdata_pre[22], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rdata_fifo|mem[1][22], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rdata_fifo|mem[0][22] ;; ulight_fifo:u0|ulight_fifo_timecode_rx:timecode_rx|readdata[21] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_rx_s1_translator|av_readdata_pre[21], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rdata_fifo|mem[1][21], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rdata_fifo|mem[0][21] ;; ulight_fifo:u0|ulight_fifo_timecode_rx:timecode_rx|readdata[20] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_rx_s1_translator|av_readdata_pre[20], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rdata_fifo|mem[1][20], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rdata_fifo|mem[0][20] ;; ulight_fifo:u0|ulight_fifo_timecode_rx:timecode_rx|readdata[19] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_rx_s1_translator|av_readdata_pre[19], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rdata_fifo|mem[1][19], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rdata_fifo|mem[0][19] ;; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:timecode_tx_ready|readdata[20] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_ready_s1_translator|av_readdata_pre[20], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rdata_fifo|mem[1][20], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rdata_fifo|mem[0][20] ;; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:timecode_tx_ready|readdata[31] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_ready_s1_translator|av_readdata_pre[31], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rdata_fifo|mem[1][31], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rdata_fifo|mem[0][31] ;; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:timecode_tx_ready|readdata[26] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_ready_s1_translator|av_readdata_pre[26], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rdata_fifo|mem[1][26], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rdata_fifo|mem[0][26] ;; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:timecode_tx_ready|readdata[29] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_ready_s1_translator|av_readdata_pre[29], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rdata_fifo|mem[1][29], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rdata_fifo|mem[0][29] ;; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:timecode_tx_ready|readdata[28] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_ready_s1_translator|av_readdata_pre[28], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rdata_fifo|mem[1][28], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rdata_fifo|mem[0][28] ;; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:timecode_tx_ready|readdata[27] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_ready_s1_translator|av_readdata_pre[27], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rdata_fifo|mem[1][27], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rdata_fifo|mem[0][27] ;; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:timecode_tx_ready|readdata[25] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_ready_s1_translator|av_readdata_pre[25], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rdata_fifo|mem[1][25], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rdata_fifo|mem[0][25] ;; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:timecode_tx_ready|readdata[24] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_ready_s1_translator|av_readdata_pre[24], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rdata_fifo|mem[1][24], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rdata_fifo|mem[0][24] ;; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:timecode_tx_ready|readdata[23] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_ready_s1_translator|av_readdata_pre[23], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rdata_fifo|mem[1][23], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rdata_fifo|mem[0][23] ;; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:timecode_tx_ready|readdata[22] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_ready_s1_translator|av_readdata_pre[22], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rdata_fifo|mem[1][22], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rdata_fifo|mem[0][22] ;; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:timecode_tx_ready|readdata[21] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_ready_s1_translator|av_readdata_pre[21], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rdata_fifo|mem[1][21], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rdata_fifo|mem[0][21] ;; ulight_fifo:u0|ulight_fifo_timecode_rx:timecode_rx|readdata[18] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_rx_s1_translator|av_readdata_pre[18], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rdata_fifo|mem[1][18], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rdata_fifo|mem[0][18] ;; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:timecode_tx_ready|readdata[19] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_ready_s1_translator|av_readdata_pre[19], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rdata_fifo|mem[1][19], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rdata_fifo|mem[0][19] ;; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:timecode_tx_ready|readdata[18] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_ready_s1_translator|av_readdata_pre[18], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rdata_fifo|mem[1][18], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rdata_fifo|mem[0][18] ;; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:timecode_tx_ready|readdata[17] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_ready_s1_translator|av_readdata_pre[17], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rdata_fifo|mem[1][17], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rdata_fifo|mem[0][17] ;; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:timecode_tx_ready|readdata[16] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_ready_s1_translator|av_readdata_pre[16], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rdata_fifo|mem[1][16], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rdata_fifo|mem[0][16] ;; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:timecode_tx_ready|readdata[15] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_ready_s1_translator|av_readdata_pre[15], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rdata_fifo|mem[1][15], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rdata_fifo|mem[0][15] ;; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:timecode_tx_ready|readdata[14] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_ready_s1_translator|av_readdata_pre[14], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rdata_fifo|mem[1][14], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rdata_fifo|mem[0][14] ;; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:timecode_tx_ready|readdata[13] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_ready_s1_translator|av_readdata_pre[13], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rdata_fifo|mem[1][13], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rdata_fifo|mem[0][13] ;; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:timecode_tx_ready|readdata[12] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_ready_s1_translator|av_readdata_pre[12], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rdata_fifo|mem[1][12], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rdata_fifo|mem[0][12] ;; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:timecode_tx_ready|readdata[11] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_ready_s1_translator|av_readdata_pre[11], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rdata_fifo|mem[1][11], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rdata_fifo|mem[0][11] ;; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:timecode_tx_ready|readdata[10] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_ready_s1_translator|av_readdata_pre[10], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rdata_fifo|mem[1][10], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rdata_fifo|mem[0][10] ;; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:timecode_ready_rx|readdata[9] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_ready_rx_s1_translator|av_readdata_pre[9], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[1][9], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[0][9] ;; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:timecode_ready_rx|readdata[19] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_ready_rx_s1_translator|av_readdata_pre[19], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[1][19], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[0][19] ;; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:timecode_ready_rx|readdata[18] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_ready_rx_s1_translator|av_readdata_pre[18], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[1][18], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[0][18] ;; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:timecode_ready_rx|readdata[17] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_ready_rx_s1_translator|av_readdata_pre[17], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[1][17], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[0][17] ;; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:timecode_ready_rx|readdata[16] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_ready_rx_s1_translator|av_readdata_pre[16], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[1][16], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[0][16] ;; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:timecode_ready_rx|readdata[15] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_ready_rx_s1_translator|av_readdata_pre[15], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[1][15], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[0][15] ;; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:timecode_ready_rx|readdata[14] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_ready_rx_s1_translator|av_readdata_pre[14], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[1][14], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[0][14] ;; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:timecode_ready_rx|readdata[13] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_ready_rx_s1_translator|av_readdata_pre[13], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[1][13], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[0][13] ;; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:timecode_ready_rx|readdata[12] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_ready_rx_s1_translator|av_readdata_pre[12], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[1][12], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[0][12] ;; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:timecode_ready_rx|readdata[11] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_ready_rx_s1_translator|av_readdata_pre[11], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[1][11], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[0][11] ;; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:timecode_ready_rx|readdata[10] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_ready_rx_s1_translator|av_readdata_pre[10], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[1][10], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[0][10] ;; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:timecode_ready_rx|readdata[20] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_ready_rx_s1_translator|av_readdata_pre[20], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[1][20], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[0][20] ;; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:timecode_ready_rx|readdata[8] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_ready_rx_s1_translator|av_readdata_pre[8], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[1][8], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[0][8] ;; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:timecode_ready_rx|readdata[7] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_ready_rx_s1_translator|av_readdata_pre[7], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[1][7], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[0][7] ;; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:timecode_ready_rx|readdata[6] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_ready_rx_s1_translator|av_readdata_pre[6], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[1][6], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[0][6] ;; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:timecode_ready_rx|readdata[5] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_ready_rx_s1_translator|av_readdata_pre[5], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[1][5], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[0][5] ;; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:timecode_ready_rx|readdata[4] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_ready_rx_s1_translator|av_readdata_pre[4], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[1][4], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[0][4] ;; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:timecode_ready_rx|readdata[3] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_ready_rx_s1_translator|av_readdata_pre[3], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[1][3], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[0][3] ;; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:timecode_ready_rx|readdata[2] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_ready_rx_s1_translator|av_readdata_pre[2], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[1][2], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[0][2] ;; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:timecode_ready_rx|readdata[1] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_ready_rx_s1_translator|av_readdata_pre[1], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[1][1], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[0][1] ;; ulight_fifo:u0|ulight_fifo_counter_rx_fifo:fsm_info|readdata[31] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fsm_info_s1_translator|av_readdata_pre[31], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[1][31], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[0][31] ;; ulight_fifo:u0|ulight_fifo_counter_rx_fifo:fsm_info|readdata[30] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fsm_info_s1_translator|av_readdata_pre[30], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[1][30], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[0][30] ;; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:timecode_ready_rx|readdata[31] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_ready_rx_s1_translator|av_readdata_pre[31], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[1][31], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[0][31] ;; ulight_fifo:u0|ulight_fifo_timecode_rx:timecode_rx|readdata[17] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_rx_s1_translator|av_readdata_pre[17], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rdata_fifo|mem[1][17], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rdata_fifo|mem[0][17] ;; ulight_fifo:u0|ulight_fifo_timecode_rx:timecode_rx|readdata[16] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_rx_s1_translator|av_readdata_pre[16], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rdata_fifo|mem[1][16], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rdata_fifo|mem[0][16] ;; ulight_fifo:u0|ulight_fifo_timecode_rx:timecode_rx|readdata[15] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_rx_s1_translator|av_readdata_pre[15], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rdata_fifo|mem[1][15], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rdata_fifo|mem[0][15] ;; ulight_fifo:u0|ulight_fifo_timecode_rx:timecode_rx|readdata[14] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_rx_s1_translator|av_readdata_pre[14], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rdata_fifo|mem[1][14], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rdata_fifo|mem[0][14] ;; ulight_fifo:u0|ulight_fifo_timecode_rx:timecode_rx|readdata[13] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_rx_s1_translator|av_readdata_pre[13], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rdata_fifo|mem[1][13], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rdata_fifo|mem[0][13] ;; ulight_fifo:u0|ulight_fifo_timecode_rx:timecode_rx|readdata[12] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_rx_s1_translator|av_readdata_pre[12], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rdata_fifo|mem[1][12], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rdata_fifo|mem[0][12] ;; ulight_fifo:u0|ulight_fifo_timecode_rx:timecode_rx|readdata[11] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_rx_s1_translator|av_readdata_pre[11], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rdata_fifo|mem[1][11], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rdata_fifo|mem[0][11] ;; ulight_fifo:u0|ulight_fifo_timecode_rx:timecode_rx|readdata[10] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_rx_s1_translator|av_readdata_pre[10], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rdata_fifo|mem[1][10], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rdata_fifo|mem[0][10] ;; ulight_fifo:u0|ulight_fifo_timecode_rx:timecode_rx|readdata[9] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_rx_s1_translator|av_readdata_pre[9], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rdata_fifo|mem[1][9], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rdata_fifo|mem[0][9] ;; ulight_fifo:u0|ulight_fifo_timecode_rx:timecode_rx|readdata[8] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_rx_s1_translator|av_readdata_pre[8], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rdata_fifo|mem[1][8], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rdata_fifo|mem[0][8] ;; ulight_fifo:u0|ulight_fifo_counter_rx_fifo:fsm_info|readdata[29] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fsm_info_s1_translator|av_readdata_pre[29], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[1][29], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[0][29] ;; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:timecode_ready_rx|readdata[30] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_ready_rx_s1_translator|av_readdata_pre[30], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[1][30], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[0][30] ;; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:timecode_ready_rx|readdata[29] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_ready_rx_s1_translator|av_readdata_pre[29], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[1][29], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[0][29] ;; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:timecode_ready_rx|readdata[28] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_ready_rx_s1_translator|av_readdata_pre[28], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[1][28], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[0][28] ;; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:timecode_ready_rx|readdata[27] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_ready_rx_s1_translator|av_readdata_pre[27], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[1][27], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[0][27] ;; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:timecode_ready_rx|readdata[26] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_ready_rx_s1_translator|av_readdata_pre[26], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[1][26], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[0][26] ;; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:timecode_ready_rx|readdata[25] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_ready_rx_s1_translator|av_readdata_pre[25], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[1][25], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[0][25] ;; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:timecode_ready_rx|readdata[24] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_ready_rx_s1_translator|av_readdata_pre[24], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[1][24], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[0][24] ;; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:timecode_ready_rx|readdata[23] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_ready_rx_s1_translator|av_readdata_pre[23], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[1][23], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[0][23] ;; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:timecode_ready_rx|readdata[22] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_ready_rx_s1_translator|av_readdata_pre[22], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[1][22], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[0][22] ;; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:timecode_ready_rx|readdata[21] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_ready_rx_s1_translator|av_readdata_pre[21], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[1][21], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[0][21] ;; ulight_fifo:u0|ulight_fifo_counter_rx_fifo:counter_tx_fifo|readdata[13] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:counter_tx_fifo_s1_translator|av_readdata_pre[13], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rdata_fifo|mem[1][13], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rdata_fifo|mem[0][13] ;; ulight_fifo:u0|ulight_fifo_counter_rx_fifo:counter_tx_fifo|readdata[23] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:counter_tx_fifo_s1_translator|av_readdata_pre[23], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rdata_fifo|mem[1][23], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rdata_fifo|mem[0][23] ;; ulight_fifo:u0|ulight_fifo_counter_rx_fifo:counter_tx_fifo|readdata[22] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:counter_tx_fifo_s1_translator|av_readdata_pre[22], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rdata_fifo|mem[1][22], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rdata_fifo|mem[0][22] ;; ulight_fifo:u0|ulight_fifo_counter_rx_fifo:counter_tx_fifo|readdata[21] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:counter_tx_fifo_s1_translator|av_readdata_pre[21], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rdata_fifo|mem[1][21], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rdata_fifo|mem[0][21] ;; ulight_fifo:u0|ulight_fifo_counter_rx_fifo:counter_tx_fifo|readdata[20] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:counter_tx_fifo_s1_translator|av_readdata_pre[20], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rdata_fifo|mem[1][20], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rdata_fifo|mem[0][20] ;; ulight_fifo:u0|ulight_fifo_counter_rx_fifo:counter_tx_fifo|readdata[19] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:counter_tx_fifo_s1_translator|av_readdata_pre[19], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rdata_fifo|mem[1][19], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rdata_fifo|mem[0][19] ;; ulight_fifo:u0|ulight_fifo_counter_rx_fifo:counter_tx_fifo|readdata[18] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:counter_tx_fifo_s1_translator|av_readdata_pre[18], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rdata_fifo|mem[1][18], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rdata_fifo|mem[0][18] ;; ulight_fifo:u0|ulight_fifo_counter_rx_fifo:counter_tx_fifo|readdata[17] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:counter_tx_fifo_s1_translator|av_readdata_pre[17], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rdata_fifo|mem[1][17], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rdata_fifo|mem[0][17] ;; ulight_fifo:u0|ulight_fifo_counter_rx_fifo:counter_tx_fifo|readdata[16] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:counter_tx_fifo_s1_translator|av_readdata_pre[16], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rdata_fifo|mem[1][16], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rdata_fifo|mem[0][16] ;; ulight_fifo:u0|ulight_fifo_counter_rx_fifo:counter_tx_fifo|readdata[15] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:counter_tx_fifo_s1_translator|av_readdata_pre[15], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rdata_fifo|mem[1][15], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rdata_fifo|mem[0][15] ;; ulight_fifo:u0|ulight_fifo_counter_rx_fifo:counter_tx_fifo|readdata[14] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:counter_tx_fifo_s1_translator|av_readdata_pre[14], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rdata_fifo|mem[1][14], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rdata_fifo|mem[0][14] ;; ulight_fifo:u0|ulight_fifo_counter_rx_fifo:counter_tx_fifo|readdata[24] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:counter_tx_fifo_s1_translator|av_readdata_pre[24], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rdata_fifo|mem[1][24], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rdata_fifo|mem[0][24] ;; ulight_fifo:u0|ulight_fifo_counter_rx_fifo:counter_tx_fifo|readdata[12] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:counter_tx_fifo_s1_translator|av_readdata_pre[12], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rdata_fifo|mem[1][12], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rdata_fifo|mem[0][12] ;; ulight_fifo:u0|ulight_fifo_counter_rx_fifo:counter_tx_fifo|readdata[11] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:counter_tx_fifo_s1_translator|av_readdata_pre[11], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rdata_fifo|mem[1][11], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rdata_fifo|mem[0][11] ;; ulight_fifo:u0|ulight_fifo_counter_rx_fifo:counter_tx_fifo|readdata[10] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:counter_tx_fifo_s1_translator|av_readdata_pre[10], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rdata_fifo|mem[1][10], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rdata_fifo|mem[0][10] ;; ulight_fifo:u0|ulight_fifo_counter_rx_fifo:counter_tx_fifo|readdata[9] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:counter_tx_fifo_s1_translator|av_readdata_pre[9], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rdata_fifo|mem[1][9], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rdata_fifo|mem[0][9] ;; ulight_fifo:u0|ulight_fifo_counter_rx_fifo:counter_tx_fifo|readdata[8] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:counter_tx_fifo_s1_translator|av_readdata_pre[8], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rdata_fifo|mem[1][8], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rdata_fifo|mem[0][8] ;; ulight_fifo:u0|ulight_fifo_counter_rx_fifo:counter_tx_fifo|readdata[7] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:counter_tx_fifo_s1_translator|av_readdata_pre[7], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rdata_fifo|mem[1][7], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rdata_fifo|mem[0][7] ;; ulight_fifo:u0|ulight_fifo_counter_rx_fifo:counter_tx_fifo|readdata[6] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:counter_tx_fifo_s1_translator|av_readdata_pre[6], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rdata_fifo|mem[1][6], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rdata_fifo|mem[0][6] ;; ulight_fifo:u0|ulight_fifo_counter_rx_fifo:counter_rx_fifo|readdata[30] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:counter_rx_fifo_s1_translator|av_readdata_pre[30], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo|mem[1][30], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo|mem[0][30] ;; ulight_fifo:u0|ulight_fifo_counter_rx_fifo:counter_rx_fifo|readdata[29] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:counter_rx_fifo_s1_translator|av_readdata_pre[29], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo|mem[1][29], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo|mem[0][29] ;; ulight_fifo:u0|ulight_fifo_counter_rx_fifo:counter_rx_fifo|readdata[28] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:counter_rx_fifo_s1_translator|av_readdata_pre[28], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo|mem[1][28], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo|mem[0][28] ;; ulight_fifo:u0|ulight_fifo_data_flag_rx:data_flag_rx|readdata[12] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:data_flag_rx_s1_translator|av_readdata_pre[12], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo|mem[1][12], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo|mem[0][12] ;; ulight_fifo:u0|ulight_fifo_data_flag_rx:data_flag_rx|readdata[22] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:data_flag_rx_s1_translator|av_readdata_pre[22], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo|mem[1][22], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo|mem[0][22] ;; ulight_fifo:u0|ulight_fifo_data_flag_rx:data_flag_rx|readdata[21] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:data_flag_rx_s1_translator|av_readdata_pre[21], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo|mem[1][21], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo|mem[0][21] ;; ulight_fifo:u0|ulight_fifo_data_flag_rx:data_flag_rx|readdata[20] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:data_flag_rx_s1_translator|av_readdata_pre[20], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo|mem[1][20], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo|mem[0][20] ;; ulight_fifo:u0|ulight_fifo_data_flag_rx:data_flag_rx|readdata[19] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:data_flag_rx_s1_translator|av_readdata_pre[19], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo|mem[1][19], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo|mem[0][19] ;; ulight_fifo:u0|ulight_fifo_data_flag_rx:data_flag_rx|readdata[18] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:data_flag_rx_s1_translator|av_readdata_pre[18], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo|mem[1][18], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo|mem[0][18] ;; ulight_fifo:u0|ulight_fifo_data_flag_rx:data_flag_rx|readdata[17] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:data_flag_rx_s1_translator|av_readdata_pre[17], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo|mem[1][17], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo|mem[0][17] ;; ulight_fifo:u0|ulight_fifo_data_flag_rx:data_flag_rx|readdata[16] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:data_flag_rx_s1_translator|av_readdata_pre[16], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo|mem[1][16], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo|mem[0][16] ;; ulight_fifo:u0|ulight_fifo_data_flag_rx:data_flag_rx|readdata[15] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:data_flag_rx_s1_translator|av_readdata_pre[15], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo|mem[1][15], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo|mem[0][15] ;; ulight_fifo:u0|ulight_fifo_data_flag_rx:data_flag_rx|readdata[14] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:data_flag_rx_s1_translator|av_readdata_pre[14], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo|mem[1][14], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo|mem[0][14] ;; ulight_fifo:u0|ulight_fifo_data_flag_rx:data_flag_rx|readdata[13] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:data_flag_rx_s1_translator|av_readdata_pre[13], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo|mem[1][13], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo|mem[0][13] ;; ulight_fifo:u0|ulight_fifo_counter_rx_fifo:counter_rx_fifo|readdata[27] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:counter_rx_fifo_s1_translator|av_readdata_pre[27], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo|mem[1][27], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo|mem[0][27] ;; ulight_fifo:u0|ulight_fifo_data_flag_rx:data_flag_rx|readdata[11] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:data_flag_rx_s1_translator|av_readdata_pre[11], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo|mem[1][11], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo|mem[0][11] ;; ulight_fifo:u0|ulight_fifo_data_flag_rx:data_flag_rx|readdata[10] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:data_flag_rx_s1_translator|av_readdata_pre[10], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo|mem[1][10], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo|mem[0][10] ;; ulight_fifo:u0|ulight_fifo_data_flag_rx:data_flag_rx|readdata[9] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:data_flag_rx_s1_translator|av_readdata_pre[9], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo|mem[1][9], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo|mem[0][9] ;; ulight_fifo:u0|ulight_fifo_counter_rx_fifo:counter_tx_fifo|readdata[31] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:counter_tx_fifo_s1_translator|av_readdata_pre[31], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rdata_fifo|mem[1][31], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rdata_fifo|mem[0][31] ;; ulight_fifo:u0|ulight_fifo_counter_rx_fifo:counter_tx_fifo|readdata[30] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:counter_tx_fifo_s1_translator|av_readdata_pre[30], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rdata_fifo|mem[1][30], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rdata_fifo|mem[0][30] ;; ulight_fifo:u0|ulight_fifo_counter_rx_fifo:counter_tx_fifo|readdata[29] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:counter_tx_fifo_s1_translator|av_readdata_pre[29], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rdata_fifo|mem[1][29], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rdata_fifo|mem[0][29] ;; ulight_fifo:u0|ulight_fifo_counter_rx_fifo:counter_tx_fifo|readdata[28] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:counter_tx_fifo_s1_translator|av_readdata_pre[28], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rdata_fifo|mem[1][28], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rdata_fifo|mem[0][28] ;; ulight_fifo:u0|ulight_fifo_counter_rx_fifo:counter_tx_fifo|readdata[27] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:counter_tx_fifo_s1_translator|av_readdata_pre[27], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rdata_fifo|mem[1][27], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rdata_fifo|mem[0][27] ;; ulight_fifo:u0|ulight_fifo_counter_rx_fifo:counter_tx_fifo|readdata[26] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:counter_tx_fifo_s1_translator|av_readdata_pre[26], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rdata_fifo|mem[1][26], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rdata_fifo|mem[0][26] ;; ulight_fifo:u0|ulight_fifo_counter_rx_fifo:counter_tx_fifo|readdata[25] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:counter_tx_fifo_s1_translator|av_readdata_pre[25], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rdata_fifo|mem[1][25], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rdata_fifo|mem[0][25] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[6] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[0], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[1], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[0] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[6] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[1], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[0], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[0] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[6] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[1], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[0], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[0] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[6] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[0], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[1], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[0] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[6] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[1], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[0], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[0] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[6] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[1], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[0], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[0] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[6] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[0], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[1], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[0] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[6] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[0], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[1], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[0] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[6] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[1], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[0], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[0] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[6] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[1], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[0], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[0] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[6] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[0], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[1], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[0] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[6] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[1], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[0], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[0] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[6] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[0], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[1], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[0] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[6] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[0], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[1], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[0] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[6] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[0], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[1], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[0] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[6] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[1], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[0], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[0] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[6] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[1], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[0], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[0] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[6] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[0], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[1], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[0] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[6] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[1], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[0], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[0] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[6] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[1], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[0], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[0] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[6] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[1], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[0], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[0] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[6] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[0], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[1], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[0] ;; ulight_fifo:u0|ulight_fifo_counter_rx_fifo:counter_rx_fifo|readdata[16] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:counter_rx_fifo_s1_translator|av_readdata_pre[16], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo|mem[1][16], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo|mem[0][16] ;; ulight_fifo:u0|ulight_fifo_counter_rx_fifo:counter_rx_fifo|readdata[26] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:counter_rx_fifo_s1_translator|av_readdata_pre[26], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo|mem[1][26], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo|mem[0][26] ;; ulight_fifo:u0|ulight_fifo_counter_rx_fifo:counter_rx_fifo|readdata[25] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:counter_rx_fifo_s1_translator|av_readdata_pre[25], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo|mem[1][25], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo|mem[0][25] ;; ulight_fifo:u0|ulight_fifo_counter_rx_fifo:counter_rx_fifo|readdata[24] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:counter_rx_fifo_s1_translator|av_readdata_pre[24], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo|mem[1][24], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo|mem[0][24] ;; ulight_fifo:u0|ulight_fifo_counter_rx_fifo:counter_rx_fifo|readdata[23] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:counter_rx_fifo_s1_translator|av_readdata_pre[23], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo|mem[1][23], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo|mem[0][23] ;; ulight_fifo:u0|ulight_fifo_counter_rx_fifo:counter_rx_fifo|readdata[22] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:counter_rx_fifo_s1_translator|av_readdata_pre[22], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo|mem[1][22], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo|mem[0][22] ;; ulight_fifo:u0|ulight_fifo_counter_rx_fifo:counter_rx_fifo|readdata[21] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:counter_rx_fifo_s1_translator|av_readdata_pre[21], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo|mem[1][21], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo|mem[0][21] ;; ulight_fifo:u0|ulight_fifo_counter_rx_fifo:counter_rx_fifo|readdata[20] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:counter_rx_fifo_s1_translator|av_readdata_pre[20], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo|mem[1][20], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo|mem[0][20] ;; ulight_fifo:u0|ulight_fifo_counter_rx_fifo:counter_rx_fifo|readdata[19] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:counter_rx_fifo_s1_translator|av_readdata_pre[19], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo|mem[1][19], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo|mem[0][19] ;; ulight_fifo:u0|ulight_fifo_counter_rx_fifo:counter_rx_fifo|readdata[18] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:counter_rx_fifo_s1_translator|av_readdata_pre[18], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo|mem[1][18], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo|mem[0][18] ;; ulight_fifo:u0|ulight_fifo_counter_rx_fifo:counter_rx_fifo|readdata[17] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:counter_rx_fifo_s1_translator|av_readdata_pre[17], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo|mem[1][17], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo|mem[0][17] ;; ulight_fifo:u0|ulight_fifo_data_flag_rx:data_flag_rx|readdata[23] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:data_flag_rx_s1_translator|av_readdata_pre[23], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo|mem[1][23], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo|mem[0][23] ;; ulight_fifo:u0|ulight_fifo_counter_rx_fifo:counter_rx_fifo|readdata[15] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:counter_rx_fifo_s1_translator|av_readdata_pre[15], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo|mem[1][15], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo|mem[0][15] ;; ulight_fifo:u0|ulight_fifo_counter_rx_fifo:counter_rx_fifo|readdata[14] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:counter_rx_fifo_s1_translator|av_readdata_pre[14], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo|mem[1][14], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo|mem[0][14] ;; ulight_fifo:u0|ulight_fifo_counter_rx_fifo:counter_rx_fifo|readdata[13] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:counter_rx_fifo_s1_translator|av_readdata_pre[13], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo|mem[1][13], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo|mem[0][13] ;; ulight_fifo:u0|ulight_fifo_counter_rx_fifo:counter_rx_fifo|readdata[12] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:counter_rx_fifo_s1_translator|av_readdata_pre[12], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo|mem[1][12], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo|mem[0][12] ;; ulight_fifo:u0|ulight_fifo_counter_rx_fifo:counter_rx_fifo|readdata[11] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:counter_rx_fifo_s1_translator|av_readdata_pre[11], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo|mem[1][11], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo|mem[0][11] ;; ulight_fifo:u0|ulight_fifo_counter_rx_fifo:counter_rx_fifo|readdata[10] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:counter_rx_fifo_s1_translator|av_readdata_pre[10], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo|mem[1][10], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo|mem[0][10] ;; ulight_fifo:u0|ulight_fifo_counter_rx_fifo:counter_rx_fifo|readdata[9] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:counter_rx_fifo_s1_translator|av_readdata_pre[9], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo|mem[1][9], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo|mem[0][9] ;; ulight_fifo:u0|ulight_fifo_counter_rx_fifo:counter_rx_fifo|readdata[8] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:counter_rx_fifo_s1_translator|av_readdata_pre[8], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo|mem[1][8], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo|mem[0][8] ;; ulight_fifo:u0|ulight_fifo_counter_rx_fifo:counter_rx_fifo|readdata[7] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:counter_rx_fifo_s1_translator|av_readdata_pre[7], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo|mem[1][7], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo|mem[0][7] ;; ulight_fifo:u0|ulight_fifo_counter_rx_fifo:counter_rx_fifo|readdata[6] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:counter_rx_fifo_s1_translator|av_readdata_pre[6], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo|mem[1][6], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo|mem[0][6] ;; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_empty_rx_status|readdata[28] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_empty_rx_status_s1_translator|av_readdata_pre[28], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[1][28], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[0][28] ;; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_empty_tx_status|readdata[7] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_empty_tx_status_s1_translator|av_readdata_pre[7], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rdata_fifo|mem[1][7], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rdata_fifo|mem[0][7] ;; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_empty_tx_status|readdata[6] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_empty_tx_status_s1_translator|av_readdata_pre[6], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rdata_fifo|mem[1][6], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rdata_fifo|mem[0][6] ;; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_empty_tx_status|readdata[5] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_empty_tx_status_s1_translator|av_readdata_pre[5], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rdata_fifo|mem[1][5], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rdata_fifo|mem[0][5] ;; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_empty_tx_status|readdata[4] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_empty_tx_status_s1_translator|av_readdata_pre[4], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rdata_fifo|mem[1][4], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rdata_fifo|mem[0][4] ;; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_empty_tx_status|readdata[3] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_empty_tx_status_s1_translator|av_readdata_pre[3], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rdata_fifo|mem[1][3], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rdata_fifo|mem[0][3] ;; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_empty_tx_status|readdata[2] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_empty_tx_status_s1_translator|av_readdata_pre[2], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rdata_fifo|mem[1][2], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rdata_fifo|mem[0][2] ;; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_empty_tx_status|readdata[1] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_empty_tx_status_s1_translator|av_readdata_pre[1], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rdata_fifo|mem[1][1], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rdata_fifo|mem[0][1] ;; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_empty_rx_status|readdata[31] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_empty_rx_status_s1_translator|av_readdata_pre[31], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[1][31], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[0][31] ;; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_empty_rx_status|readdata[30] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_empty_rx_status_s1_translator|av_readdata_pre[30], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[1][30], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[0][30] ;; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_empty_rx_status|readdata[29] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_empty_rx_status_s1_translator|av_readdata_pre[29], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[1][29], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[0][29] ;; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_empty_tx_status|readdata[8] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_empty_tx_status_s1_translator|av_readdata_pre[8], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rdata_fifo|mem[1][8], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rdata_fifo|mem[0][8] ;; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_empty_rx_status|readdata[27] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_empty_rx_status_s1_translator|av_readdata_pre[27], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[1][27], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[0][27] ;; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_empty_rx_status|readdata[26] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_empty_rx_status_s1_translator|av_readdata_pre[26], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[1][26], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[0][26] ;; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_empty_rx_status|readdata[25] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_empty_rx_status_s1_translator|av_readdata_pre[25], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[1][25], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[0][25] ;; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_empty_rx_status|readdata[24] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_empty_rx_status_s1_translator|av_readdata_pre[24], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[1][24], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[0][24] ;; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_empty_rx_status|readdata[23] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_empty_rx_status_s1_translator|av_readdata_pre[23], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[1][23], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[0][23] ;; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_empty_rx_status|readdata[22] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_empty_rx_status_s1_translator|av_readdata_pre[22], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[1][22], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[0][22] ;; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_empty_rx_status|readdata[21] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_empty_rx_status_s1_translator|av_readdata_pre[21], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[1][21], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[0][21] ;; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_empty_rx_status|readdata[20] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_empty_rx_status_s1_translator|av_readdata_pre[20], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[1][20], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[0][20] ;; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_empty_rx_status|readdata[19] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_empty_rx_status_s1_translator|av_readdata_pre[19], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[1][19], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[0][19] ;; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_empty_rx_status|readdata[18] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_empty_rx_status_s1_translator|av_readdata_pre[18], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[1][18], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[0][18] ;; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_empty_tx_status|readdata[19] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_empty_tx_status_s1_translator|av_readdata_pre[19], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rdata_fifo|mem[1][19], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rdata_fifo|mem[0][19] ;; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_empty_tx_status|readdata[29] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_empty_tx_status_s1_translator|av_readdata_pre[29], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rdata_fifo|mem[1][29], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rdata_fifo|mem[0][29] ;; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_empty_tx_status|readdata[28] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_empty_tx_status_s1_translator|av_readdata_pre[28], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rdata_fifo|mem[1][28], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rdata_fifo|mem[0][28] ;; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_empty_tx_status|readdata[27] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_empty_tx_status_s1_translator|av_readdata_pre[27], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rdata_fifo|mem[1][27], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rdata_fifo|mem[0][27] ;; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_empty_tx_status|readdata[26] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_empty_tx_status_s1_translator|av_readdata_pre[26], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rdata_fifo|mem[1][26], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rdata_fifo|mem[0][26] ;; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_empty_tx_status|readdata[25] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_empty_tx_status_s1_translator|av_readdata_pre[25], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rdata_fifo|mem[1][25], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rdata_fifo|mem[0][25] ;; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_empty_tx_status|readdata[24] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_empty_tx_status_s1_translator|av_readdata_pre[24], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rdata_fifo|mem[1][24], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rdata_fifo|mem[0][24] ;; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_empty_tx_status|readdata[23] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_empty_tx_status_s1_translator|av_readdata_pre[23], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rdata_fifo|mem[1][23], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rdata_fifo|mem[0][23] ;; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_empty_tx_status|readdata[22] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_empty_tx_status_s1_translator|av_readdata_pre[22], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rdata_fifo|mem[1][22], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rdata_fifo|mem[0][22] ;; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_empty_tx_status|readdata[21] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_empty_tx_status_s1_translator|av_readdata_pre[21], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rdata_fifo|mem[1][21], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rdata_fifo|mem[0][21] ;; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_empty_tx_status|readdata[20] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_empty_tx_status_s1_translator|av_readdata_pre[20], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rdata_fifo|mem[1][20], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rdata_fifo|mem[0][20] ;; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_empty_rx_status|readdata[17] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_empty_rx_status_s1_translator|av_readdata_pre[17], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[1][17], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[0][17] ;; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_empty_tx_status|readdata[18] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_empty_tx_status_s1_translator|av_readdata_pre[18], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rdata_fifo|mem[1][18], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rdata_fifo|mem[0][18] ;; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_empty_tx_status|readdata[17] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_empty_tx_status_s1_translator|av_readdata_pre[17], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rdata_fifo|mem[1][17], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rdata_fifo|mem[0][17] ;; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_empty_tx_status|readdata[16] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_empty_tx_status_s1_translator|av_readdata_pre[16], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rdata_fifo|mem[1][16], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rdata_fifo|mem[0][16] ;; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_empty_tx_status|readdata[15] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_empty_tx_status_s1_translator|av_readdata_pre[15], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rdata_fifo|mem[1][15], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rdata_fifo|mem[0][15] ;; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_empty_tx_status|readdata[14] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_empty_tx_status_s1_translator|av_readdata_pre[14], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rdata_fifo|mem[1][14], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rdata_fifo|mem[0][14] ;; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_empty_tx_status|readdata[13] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_empty_tx_status_s1_translator|av_readdata_pre[13], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rdata_fifo|mem[1][13], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rdata_fifo|mem[0][13] ;; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_empty_tx_status|readdata[12] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_empty_tx_status_s1_translator|av_readdata_pre[12], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rdata_fifo|mem[1][12], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rdata_fifo|mem[0][12] ;; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_empty_tx_status|readdata[11] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_empty_tx_status_s1_translator|av_readdata_pre[11], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rdata_fifo|mem[1][11], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rdata_fifo|mem[0][11] ;; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_empty_tx_status|readdata[10] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_empty_tx_status_s1_translator|av_readdata_pre[10], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rdata_fifo|mem[1][10], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rdata_fifo|mem[0][10] ;; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_empty_tx_status|readdata[9] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_empty_tx_status_s1_translator|av_readdata_pre[9], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rdata_fifo|mem[1][9], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rdata_fifo|mem[0][9] ;; ulight_fifo:u0|ulight_fifo_data_info:data_info|readdata[16] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:data_info_s1_translator|av_readdata_pre[16], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[1][16], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[0][16] ;; ulight_fifo:u0|ulight_fifo_data_info:data_info|readdata[26] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:data_info_s1_translator|av_readdata_pre[26], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[1][26], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[0][26] ;; ulight_fifo:u0|ulight_fifo_data_info:data_info|readdata[25] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:data_info_s1_translator|av_readdata_pre[25], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[1][25], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[0][25] ;; ulight_fifo:u0|ulight_fifo_data_info:data_info|readdata[24] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:data_info_s1_translator|av_readdata_pre[24], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[1][24], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[0][24] ;; ulight_fifo:u0|ulight_fifo_data_info:data_info|readdata[23] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:data_info_s1_translator|av_readdata_pre[23], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[1][23], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[0][23] ;; ulight_fifo:u0|ulight_fifo_data_info:data_info|readdata[22] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:data_info_s1_translator|av_readdata_pre[22], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[1][22], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[0][22] ;; ulight_fifo:u0|ulight_fifo_data_info:data_info|readdata[21] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:data_info_s1_translator|av_readdata_pre[21], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[1][21], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[0][21] ;; ulight_fifo:u0|ulight_fifo_data_info:data_info|readdata[20] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:data_info_s1_translator|av_readdata_pre[20], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[1][20], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[0][20] ;; ulight_fifo:u0|ulight_fifo_data_info:data_info|readdata[19] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:data_info_s1_translator|av_readdata_pre[19], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[1][19], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[0][19] ;; ulight_fifo:u0|ulight_fifo_data_info:data_info|readdata[18] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:data_info_s1_translator|av_readdata_pre[18], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[1][18], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[0][18] ;; ulight_fifo:u0|ulight_fifo_data_info:data_info|readdata[17] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:data_info_s1_translator|av_readdata_pre[17], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[1][17], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[0][17] ;; ulight_fifo:u0|ulight_fifo_data_info:data_info|readdata[27] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:data_info_s1_translator|av_readdata_pre[27], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[1][27], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[0][27] ;; ulight_fifo:u0|ulight_fifo_data_info:data_info|readdata[15] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:data_info_s1_translator|av_readdata_pre[15], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[1][15], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[0][15] ;; ulight_fifo:u0|ulight_fifo_data_info:data_info|readdata[14] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:data_info_s1_translator|av_readdata_pre[14], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[1][14], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[0][14] ;; ulight_fifo:u0|ulight_fifo_data_flag_rx:data_flag_rx|readdata[31] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:data_flag_rx_s1_translator|av_readdata_pre[31], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo|mem[1][31], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo|mem[0][31] ;; ulight_fifo:u0|ulight_fifo_data_flag_rx:data_flag_rx|readdata[30] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:data_flag_rx_s1_translator|av_readdata_pre[30], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo|mem[1][30], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo|mem[0][30] ;; ulight_fifo:u0|ulight_fifo_data_flag_rx:data_flag_rx|readdata[29] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:data_flag_rx_s1_translator|av_readdata_pre[29], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo|mem[1][29], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo|mem[0][29] ;; ulight_fifo:u0|ulight_fifo_data_flag_rx:data_flag_rx|readdata[28] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:data_flag_rx_s1_translator|av_readdata_pre[28], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo|mem[1][28], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo|mem[0][28] ;; ulight_fifo:u0|ulight_fifo_data_flag_rx:data_flag_rx|readdata[27] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:data_flag_rx_s1_translator|av_readdata_pre[27], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo|mem[1][27], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo|mem[0][27] ;; ulight_fifo:u0|ulight_fifo_data_flag_rx:data_flag_rx|readdata[26] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:data_flag_rx_s1_translator|av_readdata_pre[26], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo|mem[1][26], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo|mem[0][26] ;; ulight_fifo:u0|ulight_fifo_data_flag_rx:data_flag_rx|readdata[25] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:data_flag_rx_s1_translator|av_readdata_pre[25], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo|mem[1][25], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo|mem[0][25] ;; ulight_fifo:u0|ulight_fifo_data_flag_rx:data_flag_rx|readdata[24] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:data_flag_rx_s1_translator|av_readdata_pre[24], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo|mem[1][24], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo|mem[0][24] ;; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_empty_rx_status|readdata[6] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_empty_rx_status_s1_translator|av_readdata_pre[6], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[1][6], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[0][6] ;; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_empty_rx_status|readdata[16] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_empty_rx_status_s1_translator|av_readdata_pre[16], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[1][16], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[0][16] ;; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_empty_rx_status|readdata[15] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_empty_rx_status_s1_translator|av_readdata_pre[15], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[1][15], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[0][15] ;; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_empty_rx_status|readdata[14] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_empty_rx_status_s1_translator|av_readdata_pre[14], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[1][14], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[0][14] ;; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_empty_rx_status|readdata[13] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_empty_rx_status_s1_translator|av_readdata_pre[13], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[1][13], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[0][13] ;; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_empty_rx_status|readdata[12] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_empty_rx_status_s1_translator|av_readdata_pre[12], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[1][12], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[0][12] ;; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_empty_rx_status|readdata[11] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_empty_rx_status_s1_translator|av_readdata_pre[11], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[1][11], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[0][11] ;; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_empty_rx_status|readdata[10] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_empty_rx_status_s1_translator|av_readdata_pre[10], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[1][10], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[0][10] ;; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_empty_rx_status|readdata[9] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_empty_rx_status_s1_translator|av_readdata_pre[9], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[1][9], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[0][9] ;; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_empty_rx_status|readdata[8] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_empty_rx_status_s1_translator|av_readdata_pre[8], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[1][8], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[0][8] ;; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_empty_rx_status|readdata[7] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_empty_rx_status_s1_translator|av_readdata_pre[7], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[1][7], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[0][7] ;; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_empty_tx_status|readdata[30] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_empty_tx_status_s1_translator|av_readdata_pre[30], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rdata_fifo|mem[1][30], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rdata_fifo|mem[0][30] ;; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_empty_rx_status|readdata[5] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_empty_rx_status_s1_translator|av_readdata_pre[5], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[1][5], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[0][5] ;; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_empty_rx_status|readdata[4] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_empty_rx_status_s1_translator|av_readdata_pre[4], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[1][4], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[0][4] ;; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_empty_rx_status|readdata[3] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_empty_rx_status_s1_translator|av_readdata_pre[3], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[1][3], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[0][3] ;; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_empty_rx_status|readdata[2] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_empty_rx_status_s1_translator|av_readdata_pre[2], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[1][2], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[0][2] ;; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_empty_rx_status|readdata[1] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_empty_rx_status_s1_translator|av_readdata_pre[1], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[1][1], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[0][1] ;; ulight_fifo:u0|ulight_fifo_data_info:data_info|readdata[31] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:data_info_s1_translator|av_readdata_pre[31], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[1][31], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[0][31] ;; ulight_fifo:u0|ulight_fifo_data_info:data_info|readdata[30] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:data_info_s1_translator|av_readdata_pre[30], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[1][30], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[0][30] ;; ulight_fifo:u0|ulight_fifo_data_info:data_info|readdata[29] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:data_info_s1_translator|av_readdata_pre[29], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[1][29], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[0][29] ;; ulight_fifo:u0|ulight_fifo_data_info:data_info|readdata[28] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:data_info_s1_translator|av_readdata_pre[28], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[1][28], ;; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[0][28] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_enable_s1_translator|av_readdata_pre[25] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rdata_fifo|mem[1][25], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rdata_fifo|mem[0][25] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:clock_sel_s1_translator|av_readdata_pre[8] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rdata_fifo|mem[1][8], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rdata_fifo|mem[0][8] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:clock_sel_s1_translator|av_readdata_pre[7] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rdata_fifo|mem[1][7], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rdata_fifo|mem[0][7] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:clock_sel_s1_translator|av_readdata_pre[6] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rdata_fifo|mem[1][6], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rdata_fifo|mem[0][6] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:clock_sel_s1_translator|av_readdata_pre[5] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rdata_fifo|mem[1][5], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rdata_fifo|mem[0][5] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:clock_sel_s1_translator|av_readdata_pre[4] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rdata_fifo|mem[1][4], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rdata_fifo|mem[0][4] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:clock_sel_s1_translator|av_readdata_pre[3] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rdata_fifo|mem[1][3], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rdata_fifo|mem[0][3] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_enable_s1_translator|av_readdata_pre[31] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rdata_fifo|mem[1][31], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rdata_fifo|mem[0][31] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_enable_s1_translator|av_readdata_pre[30] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rdata_fifo|mem[1][30], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rdata_fifo|mem[0][30] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_enable_s1_translator|av_readdata_pre[29] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rdata_fifo|mem[1][29], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rdata_fifo|mem[0][29] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_enable_s1_translator|av_readdata_pre[28] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rdata_fifo|mem[1][28], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rdata_fifo|mem[0][28] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_enable_s1_translator|av_readdata_pre[27] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rdata_fifo|mem[1][27], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rdata_fifo|mem[0][27] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_enable_s1_translator|av_readdata_pre[26] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rdata_fifo|mem[1][26], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rdata_fifo|mem[0][26] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:clock_sel_s1_translator|av_readdata_pre[9] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rdata_fifo|mem[1][9], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rdata_fifo|mem[0][9] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_enable_s1_translator|av_readdata_pre[24] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rdata_fifo|mem[1][24], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rdata_fifo|mem[0][24] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_enable_s1_translator|av_readdata_pre[23] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rdata_fifo|mem[1][23], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rdata_fifo|mem[0][23] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_enable_s1_translator|av_readdata_pre[22] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rdata_fifo|mem[1][22], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rdata_fifo|mem[0][22] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_enable_s1_translator|av_readdata_pre[21] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rdata_fifo|mem[1][21], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rdata_fifo|mem[0][21] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_enable_s1_translator|av_readdata_pre[20] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rdata_fifo|mem[1][20], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rdata_fifo|mem[0][20] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_enable_s1_translator|av_readdata_pre[19] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rdata_fifo|mem[1][19], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rdata_fifo|mem[0][19] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_enable_s1_translator|av_readdata_pre[18] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rdata_fifo|mem[1][18], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rdata_fifo|mem[0][18] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_enable_s1_translator|av_readdata_pre[17] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rdata_fifo|mem[1][17], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rdata_fifo|mem[0][17] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_enable_s1_translator|av_readdata_pre[16] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rdata_fifo|mem[1][16], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rdata_fifo|mem[0][16] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_enable_s1_translator|av_readdata_pre[15] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rdata_fifo|mem[1][15], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rdata_fifo|mem[0][15] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_enable_s1_translator|av_readdata_pre[14] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rdata_fifo|mem[1][14], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rdata_fifo|mem[0][14] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:clock_sel_s1_translator|av_readdata_pre[21] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rdata_fifo|mem[1][21], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rdata_fifo|mem[0][21] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[95] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rsp_fifo|mem[1][95], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rsp_fifo|mem[0][95] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:clock_sel_s1_translator|av_readdata_pre[31] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rdata_fifo|mem[1][31], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rdata_fifo|mem[0][31] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:clock_sel_s1_translator|av_readdata_pre[30] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rdata_fifo|mem[1][30], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rdata_fifo|mem[0][30] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:clock_sel_s1_translator|av_readdata_pre[29] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rdata_fifo|mem[1][29], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rdata_fifo|mem[0][29] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:clock_sel_s1_translator|av_readdata_pre[28] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rdata_fifo|mem[1][28], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rdata_fifo|mem[0][28] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:clock_sel_s1_translator|av_readdata_pre[27] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rdata_fifo|mem[1][27], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rdata_fifo|mem[0][27] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:clock_sel_s1_translator|av_readdata_pre[26] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rdata_fifo|mem[1][26], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rdata_fifo|mem[0][26] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:clock_sel_s1_translator|av_readdata_pre[25] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rdata_fifo|mem[1][25], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rdata_fifo|mem[0][25] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:clock_sel_s1_translator|av_readdata_pre[24] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rdata_fifo|mem[1][24], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rdata_fifo|mem[0][24] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:clock_sel_s1_translator|av_readdata_pre[23] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rdata_fifo|mem[1][23], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rdata_fifo|mem[0][23] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:clock_sel_s1_translator|av_readdata_pre[22] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rdata_fifo|mem[1][22], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rdata_fifo|mem[0][22] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_enable_s1_translator|av_readdata_pre[13] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rdata_fifo|mem[1][13], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rdata_fifo|mem[0][13] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:clock_sel_s1_translator|av_readdata_pre[20] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rdata_fifo|mem[1][20], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rdata_fifo|mem[0][20] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:clock_sel_s1_translator|av_readdata_pre[19] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rdata_fifo|mem[1][19], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rdata_fifo|mem[0][19] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:clock_sel_s1_translator|av_readdata_pre[18] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rdata_fifo|mem[1][18], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rdata_fifo|mem[0][18] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:clock_sel_s1_translator|av_readdata_pre[17] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rdata_fifo|mem[1][17], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rdata_fifo|mem[0][17] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:clock_sel_s1_translator|av_readdata_pre[16] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rdata_fifo|mem[1][16], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rdata_fifo|mem[0][16] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:clock_sel_s1_translator|av_readdata_pre[15] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rdata_fifo|mem[1][15], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rdata_fifo|mem[0][15] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:clock_sel_s1_translator|av_readdata_pre[14] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rdata_fifo|mem[1][14], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rdata_fifo|mem[0][14] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:clock_sel_s1_translator|av_readdata_pre[13] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rdata_fifo|mem[1][13], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rdata_fifo|mem[0][13] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:clock_sel_s1_translator|av_readdata_pre[12] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rdata_fifo|mem[1][12], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rdata_fifo|mem[0][12] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:clock_sel_s1_translator|av_readdata_pre[11] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rdata_fifo|mem[1][11], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rdata_fifo|mem[0][11] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:clock_sel_s1_translator|av_readdata_pre[10] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rdata_fifo|mem[1][10], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rdata_fifo|mem[0][10] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_data_s1_translator|av_readdata_pre[8] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rdata_fifo|mem[1][8], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rdata_fifo|mem[0][8] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_data_s1_translator|av_readdata_pre[19] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rdata_fifo|mem[1][19], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rdata_fifo|mem[0][19] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_data_s1_translator|av_readdata_pre[18] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rdata_fifo|mem[1][18], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rdata_fifo|mem[0][18] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_data_s1_translator|av_readdata_pre[17] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rdata_fifo|mem[1][17], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rdata_fifo|mem[0][17] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_data_s1_translator|av_readdata_pre[16] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rdata_fifo|mem[1][16], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rdata_fifo|mem[0][16] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_data_s1_translator|av_readdata_pre[15] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rdata_fifo|mem[1][15], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rdata_fifo|mem[0][15] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_data_s1_translator|av_readdata_pre[14] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rdata_fifo|mem[1][14], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rdata_fifo|mem[0][14] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_data_s1_translator|av_readdata_pre[13] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rdata_fifo|mem[1][13], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rdata_fifo|mem[0][13] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_data_s1_translator|av_readdata_pre[12] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rdata_fifo|mem[1][12], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rdata_fifo|mem[0][12] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_data_s1_translator|av_readdata_pre[11] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rdata_fifo|mem[1][11], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rdata_fifo|mem[0][11] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_data_s1_translator|av_readdata_pre[10] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rdata_fifo|mem[1][10], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rdata_fifo|mem[0][10] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_data_s1_translator|av_readdata_pre[9] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rdata_fifo|mem[1][9], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rdata_fifo|mem[0][9] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_data_s1_translator|av_readdata_pre[20] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rdata_fifo|mem[1][20], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rdata_fifo|mem[0][20] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:write_en_tx_s1_translator|av_readdata_pre[31] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[1][31], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[0][31] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:write_en_tx_s1_translator|av_readdata_pre[30] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[1][30], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[0][30] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:write_en_tx_s1_translator|av_readdata_pre[29] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[1][29], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[0][29] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:write_en_tx_s1_translator|av_readdata_pre[28] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[1][28], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[0][28] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:write_en_tx_s1_translator|av_readdata_pre[27] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[1][27], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[0][27] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:write_en_tx_s1_translator|av_readdata_pre[26] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[1][26], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[0][26] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:write_en_tx_s1_translator|av_readdata_pre[25] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[1][25], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[0][25] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:write_en_tx_s1_translator|av_readdata_pre[24] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[1][24], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[0][24] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:write_en_tx_s1_translator|av_readdata_pre[23] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[1][23], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[0][23] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:write_en_tx_s1_translator|av_readdata_pre[22] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[1][22], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[0][22] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:write_en_tx_s1_translator|av_readdata_pre[21] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[1][21], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[0][21] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_enable_s1_translator|av_readdata_pre[1] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rdata_fifo|mem[1][1], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rdata_fifo|mem[0][1] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_enable_s1_translator|av_readdata_pre[12] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rdata_fifo|mem[1][12], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rdata_fifo|mem[0][12] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_enable_s1_translator|av_readdata_pre[11] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rdata_fifo|mem[1][11], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rdata_fifo|mem[0][11] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_enable_s1_translator|av_readdata_pre[10] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rdata_fifo|mem[1][10], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rdata_fifo|mem[0][10] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_enable_s1_translator|av_readdata_pre[9] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rdata_fifo|mem[1][9], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rdata_fifo|mem[0][9] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_enable_s1_translator|av_readdata_pre[8] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rdata_fifo|mem[1][8], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rdata_fifo|mem[0][8] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_enable_s1_translator|av_readdata_pre[7] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rdata_fifo|mem[1][7], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rdata_fifo|mem[0][7] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_enable_s1_translator|av_readdata_pre[6] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rdata_fifo|mem[1][6], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rdata_fifo|mem[0][6] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_enable_s1_translator|av_readdata_pre[5] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rdata_fifo|mem[1][5], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rdata_fifo|mem[0][5] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_enable_s1_translator|av_readdata_pre[4] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rdata_fifo|mem[1][4], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rdata_fifo|mem[0][4] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_enable_s1_translator|av_readdata_pre[3] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rdata_fifo|mem[1][3], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rdata_fifo|mem[0][3] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_enable_s1_translator|av_readdata_pre[2] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rdata_fifo|mem[1][2], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rdata_fifo|mem[0][2] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[96] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rsp_fifo|mem[1][96], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rsp_fifo|mem[0][96] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_data_s1_translator|av_readdata_pre[31] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rdata_fifo|mem[1][31], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rdata_fifo|mem[0][31] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_data_s1_translator|av_readdata_pre[30] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rdata_fifo|mem[1][30], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rdata_fifo|mem[0][30] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_data_s1_translator|av_readdata_pre[29] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rdata_fifo|mem[1][29], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rdata_fifo|mem[0][29] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_data_s1_translator|av_readdata_pre[28] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rdata_fifo|mem[1][28], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rdata_fifo|mem[0][28] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_data_s1_translator|av_readdata_pre[27] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rdata_fifo|mem[1][27], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rdata_fifo|mem[0][27] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_data_s1_translator|av_readdata_pre[26] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rdata_fifo|mem[1][26], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rdata_fifo|mem[0][26] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_data_s1_translator|av_readdata_pre[25] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rdata_fifo|mem[1][25], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rdata_fifo|mem[0][25] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_data_s1_translator|av_readdata_pre[24] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rdata_fifo|mem[1][24], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rdata_fifo|mem[0][24] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_data_s1_translator|av_readdata_pre[23] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rdata_fifo|mem[1][23], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rdata_fifo|mem[0][23] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_data_s1_translator|av_readdata_pre[22] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rdata_fifo|mem[1][22], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rdata_fifo|mem[0][22] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_data_s1_translator|av_readdata_pre[21] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rdata_fifo|mem[1][21], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rdata_fifo|mem[0][21] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[97] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][97], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][97] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[95] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rsp_fifo|mem[1][95], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rsp_fifo|mem[0][95] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[99] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rsp_fifo|mem[1][99], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rsp_fifo|mem[0][99] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[98] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rsp_fifo|mem[1][98], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rsp_fifo|mem[0][98] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[97] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rsp_fifo|mem[1][97], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rsp_fifo|mem[0][97] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[96] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rsp_fifo|mem[1][96], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rsp_fifo|mem[0][96] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[95] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rsp_fifo|mem[1][95], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rsp_fifo|mem[0][95] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[99] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rsp_fifo|mem[1][99], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rsp_fifo|mem[0][99] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[98] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rsp_fifo|mem[1][98], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rsp_fifo|mem[0][98] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[97] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rsp_fifo|mem[1][97], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rsp_fifo|mem[0][97] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[96] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rsp_fifo|mem[1][96], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rsp_fifo|mem[0][96] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[95] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rsp_fifo|mem[1][95], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rsp_fifo|mem[0][95] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[98] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][98], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][98] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[96] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rsp_fifo|mem[1][96], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rsp_fifo|mem[0][96] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[96] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][96], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][96] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[95] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][95], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][95] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[98] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][98], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][98] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[97] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][97], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][97] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[96] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][96], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][96] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[95] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][95], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][95] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[99] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rsp_fifo|mem[1][99], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rsp_fifo|mem[0][99] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[98] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rsp_fifo|mem[1][98], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rsp_fifo|mem[0][98] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[97] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rsp_fifo|mem[1][97], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rsp_fifo|mem[0][97] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[96] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rsp_fifo|mem[1][96], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rsp_fifo|mem[0][96] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[95] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rsp_fifo|mem[1][95], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rsp_fifo|mem[0][95] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[95] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rsp_fifo|mem[1][95], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rsp_fifo|mem[0][95] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[98] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rsp_fifo|mem[1][98], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rsp_fifo|mem[0][98] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[97] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rsp_fifo|mem[1][97], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rsp_fifo|mem[0][97] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[96] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rsp_fifo|mem[1][96], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rsp_fifo|mem[0][96] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[95] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rsp_fifo|mem[1][95], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rsp_fifo|mem[0][95] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[98] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rsp_fifo|mem[1][98], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rsp_fifo|mem[0][98] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[97] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rsp_fifo|mem[1][97], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rsp_fifo|mem[0][97] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[96] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rsp_fifo|mem[1][96], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rsp_fifo|mem[0][96] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[95] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rsp_fifo|mem[1][95], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rsp_fifo|mem[0][95] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[98] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rsp_fifo|mem[1][98], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rsp_fifo|mem[0][98] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[97] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rsp_fifo|mem[1][97], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rsp_fifo|mem[0][97] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[96] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rsp_fifo|mem[1][96], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rsp_fifo|mem[0][96] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[99] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][99], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][99] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[99] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rsp_fifo|mem[1][99], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rsp_fifo|mem[0][99] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[98] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rsp_fifo|mem[1][98], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rsp_fifo|mem[0][98] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[97] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rsp_fifo|mem[1][97], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rsp_fifo|mem[0][97] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[96] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rsp_fifo|mem[1][96], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rsp_fifo|mem[0][96] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[95] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rsp_fifo|mem[1][95], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rsp_fifo|mem[0][95] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[98] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rsp_fifo|mem[1][98], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rsp_fifo|mem[0][98] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[97] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rsp_fifo|mem[1][97], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rsp_fifo|mem[0][97] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[96] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rsp_fifo|mem[1][96], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rsp_fifo|mem[0][96] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[95] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rsp_fifo|mem[1][95], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rsp_fifo|mem[0][95] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[98] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rsp_fifo|mem[1][98], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rsp_fifo|mem[0][98] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[97] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rsp_fifo|mem[1][97], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rsp_fifo|mem[0][97] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[95] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rsp_fifo|mem[1][95], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rsp_fifo|mem[0][95] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[97] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][97], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][97] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[96] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][96], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][96] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[95] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][95], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][95] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[99] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rsp_fifo|mem[1][99], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rsp_fifo|mem[0][99] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[98] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rsp_fifo|mem[1][98], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rsp_fifo|mem[0][98] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[97] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rsp_fifo|mem[1][97], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rsp_fifo|mem[0][97] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[96] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rsp_fifo|mem[1][96], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rsp_fifo|mem[0][96] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[95] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rsp_fifo|mem[1][95], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rsp_fifo|mem[0][95] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[98] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rsp_fifo|mem[1][98], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rsp_fifo|mem[0][98] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[97] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rsp_fifo|mem[1][97], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rsp_fifo|mem[0][97] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[96] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rsp_fifo|mem[1][96], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rsp_fifo|mem[0][96] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[98] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][98], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][98] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[98] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rsp_fifo|mem[1][98], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rsp_fifo|mem[0][98] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[97] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rsp_fifo|mem[1][97], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rsp_fifo|mem[0][97] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[96] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rsp_fifo|mem[1][96], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rsp_fifo|mem[0][96] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[95] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rsp_fifo|mem[1][95], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rsp_fifo|mem[0][95] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[98] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rsp_fifo|mem[1][98], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rsp_fifo|mem[0][98] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[97] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rsp_fifo|mem[1][97], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rsp_fifo|mem[0][97] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[96] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rsp_fifo|mem[1][96], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rsp_fifo|mem[0][96] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[95] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rsp_fifo|mem[1][95], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rsp_fifo|mem[0][95] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[99] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rsp_fifo|mem[1][99], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rsp_fifo|mem[0][99] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[98] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rsp_fifo|mem[1][98], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rsp_fifo|mem[0][98] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[97] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rsp_fifo|mem[1][97], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rsp_fifo|mem[0][97] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[97] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rsp_fifo|mem[1][97], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rsp_fifo|mem[0][97] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[98] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][98], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][98] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[97] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][97], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][97] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[96] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][96], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][96] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[95] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][95], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][95] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[99] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rsp_fifo|mem[1][99], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rsp_fifo|mem[0][99] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[98] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rsp_fifo|mem[1][98], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rsp_fifo|mem[0][98] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[97] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rsp_fifo|mem[1][97], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rsp_fifo|mem[0][97] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[96] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rsp_fifo|mem[1][96], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rsp_fifo|mem[0][96] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[95] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rsp_fifo|mem[1][95], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rsp_fifo|mem[0][95] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[99] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rsp_fifo|mem[1][99], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rsp_fifo|mem[0][99] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[98] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rsp_fifo|mem[1][98], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rsp_fifo|mem[0][98] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:led_pio_test_s1_translator|av_readdata_pre[24] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo|mem[1][24], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo|mem[0][24] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[96] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rsp_fifo|mem[1][96], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rsp_fifo|mem[0][96] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[95] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rsp_fifo|mem[1][95], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rsp_fifo|mem[0][95] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[99] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rsp_fifo|mem[1][99], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rsp_fifo|mem[0][99] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[98] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rsp_fifo|mem[1][98], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rsp_fifo|mem[0][98] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[97] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rsp_fifo|mem[1][97], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rsp_fifo|mem[0][97] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[96] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rsp_fifo|mem[1][96], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rsp_fifo|mem[0][96] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[95] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rsp_fifo|mem[1][95], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rsp_fifo|mem[0][95] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[98] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][98], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][98] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[97] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][97], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][97] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[96] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][96], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][96] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[95] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][95], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][95] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:link_start_s1_translator|av_readdata_pre[3] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[1][3], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[0][3] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:link_start_s1_translator|av_readdata_pre[15] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[1][15], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[0][15] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:link_start_s1_translator|av_readdata_pre[14] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[1][14], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[0][14] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:link_start_s1_translator|av_readdata_pre[13] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[1][13], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[0][13] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:link_start_s1_translator|av_readdata_pre[12] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[1][12], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[0][12] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:link_start_s1_translator|av_readdata_pre[11] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[1][11], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[0][11] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:link_start_s1_translator|av_readdata_pre[10] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[1][10], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[0][10] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:link_start_s1_translator|av_readdata_pre[9] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[1][9], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[0][9] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:link_start_s1_translator|av_readdata_pre[8] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[1][8], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[0][8] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:link_start_s1_translator|av_readdata_pre[7] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[1][7], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[0][7] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:link_start_s1_translator|av_readdata_pre[6] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[1][6], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[0][6] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:link_start_s1_translator|av_readdata_pre[5] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[1][5], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[0][5] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:link_start_s1_translator|av_readdata_pre[4] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[1][4], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[0][4] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:link_start_s1_translator|av_readdata_pre[16] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[1][16], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[0][16] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:link_start_s1_translator|av_readdata_pre[2] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[1][2], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[0][2] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:link_start_s1_translator|av_readdata_pre[1] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[1][1], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[0][1] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:data_read_en_rx_s1_translator|av_readdata_pre[31] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[1][31], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[0][31] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:data_read_en_rx_s1_translator|av_readdata_pre[30] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[1][30], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[0][30] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:data_read_en_rx_s1_translator|av_readdata_pre[29] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[1][29], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[0][29] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:data_read_en_rx_s1_translator|av_readdata_pre[28] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[1][28], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[0][28] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:data_read_en_rx_s1_translator|av_readdata_pre[27] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[1][27], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[0][27] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:data_read_en_rx_s1_translator|av_readdata_pre[26] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[1][26], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[0][26] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:data_read_en_rx_s1_translator|av_readdata_pre[25] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[1][25], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[0][25] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:data_read_en_rx_s1_translator|av_readdata_pre[24] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[1][24], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[0][24] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:data_read_en_rx_s1_translator|av_readdata_pre[23] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[1][23], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[0][23] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:link_start_s1_translator|av_readdata_pre[28] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[1][28], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[0][28] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:auto_start_s1_translator|av_readdata_pre[8] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[1][8], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[0][8] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:auto_start_s1_translator|av_readdata_pre[7] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[1][7], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[0][7] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:auto_start_s1_translator|av_readdata_pre[6] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[1][6], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[0][6] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:auto_start_s1_translator|av_readdata_pre[5] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[1][5], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[0][5] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:auto_start_s1_translator|av_readdata_pre[4] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[1][4], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[0][4] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:auto_start_s1_translator|av_readdata_pre[3] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[1][3], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[0][3] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:auto_start_s1_translator|av_readdata_pre[2] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[1][2], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[0][2] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:auto_start_s1_translator|av_readdata_pre[1] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[1][1], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[0][1] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:link_start_s1_translator|av_readdata_pre[31] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[1][31], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[0][31] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:link_start_s1_translator|av_readdata_pre[30] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[1][30], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[0][30] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:link_start_s1_translator|av_readdata_pre[29] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[1][29], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[0][29] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:data_read_en_rx_s1_translator|av_readdata_pre[22] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[1][22], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[0][22] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:link_start_s1_translator|av_readdata_pre[27] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[1][27], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[0][27] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:link_start_s1_translator|av_readdata_pre[26] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[1][26], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[0][26] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:link_start_s1_translator|av_readdata_pre[25] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[1][25], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[0][25] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:link_start_s1_translator|av_readdata_pre[24] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[1][24], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[0][24] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:link_start_s1_translator|av_readdata_pre[23] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[1][23], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[0][23] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:link_start_s1_translator|av_readdata_pre[22] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[1][22], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[0][22] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:link_start_s1_translator|av_readdata_pre[21] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[1][21], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[0][21] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:link_start_s1_translator|av_readdata_pre[20] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[1][20], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[0][20] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:link_start_s1_translator|av_readdata_pre[19] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[1][19], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[0][19] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:link_start_s1_translator|av_readdata_pre[18] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[1][18], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[0][18] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:link_start_s1_translator|av_readdata_pre[17] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[1][17], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[0][17] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:led_pio_test_s1_translator|av_readdata_pre[13] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo|mem[1][13], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo|mem[0][13] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:led_pio_test_s1_translator|av_readdata_pre[28] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo|mem[1][28], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo|mem[0][28] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:led_pio_test_s1_translator|av_readdata_pre[27] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo|mem[1][27], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo|mem[0][27] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:led_pio_test_s1_translator|av_readdata_pre[26] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo|mem[1][26], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo|mem[0][26] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:led_pio_test_s1_translator|av_readdata_pre[5] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo|mem[1][5], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo|mem[0][5] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:led_pio_test_s1_translator|av_readdata_pre[6] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo|mem[1][6], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo|mem[0][6] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:led_pio_test_s1_translator|av_readdata_pre[7] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo|mem[1][7], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo|mem[0][7] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:led_pio_test_s1_translator|av_readdata_pre[8] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo|mem[1][8], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo|mem[0][8] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:led_pio_test_s1_translator|av_readdata_pre[9] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo|mem[1][9], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo|mem[0][9] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:led_pio_test_s1_translator|av_readdata_pre[10] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo|mem[1][10], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo|mem[0][10] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:led_pio_test_s1_translator|av_readdata_pre[11] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo|mem[1][11], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo|mem[0][11] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:led_pio_test_s1_translator|av_readdata_pre[12] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo|mem[1][12], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo|mem[0][12] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:led_pio_test_s1_translator|av_readdata_pre[29] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo|mem[1][29], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo|mem[0][29] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:led_pio_test_s1_translator|av_readdata_pre[14] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo|mem[1][14], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo|mem[0][14] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:led_pio_test_s1_translator|av_readdata_pre[15] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo|mem[1][15], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo|mem[0][15] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:led_pio_test_s1_translator|av_readdata_pre[16] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo|mem[1][16], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo|mem[0][16] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:led_pio_test_s1_translator|av_readdata_pre[17] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo|mem[1][17], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo|mem[0][17] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:led_pio_test_s1_translator|av_readdata_pre[18] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo|mem[1][18], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo|mem[0][18] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:led_pio_test_s1_translator|av_readdata_pre[19] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo|mem[1][19], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo|mem[0][19] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:led_pio_test_s1_translator|av_readdata_pre[20] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo|mem[1][20], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo|mem[0][20] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:led_pio_test_s1_translator|av_readdata_pre[21] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo|mem[1][21], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo|mem[0][21] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:led_pio_test_s1_translator|av_readdata_pre[22] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo|mem[1][22], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo|mem[0][22] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:led_pio_test_s1_translator|av_readdata_pre[23] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo|mem[1][23], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo|mem[0][23] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:led_pio_test_s1_translator|av_readdata_pre[25] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo|mem[1][25], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo|mem[0][25] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:data_read_en_rx_s1_translator|av_readdata_pre[10] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[1][10], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[0][10] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:data_read_en_rx_s1_translator|av_readdata_pre[21] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[1][21], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[0][21] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:data_read_en_rx_s1_translator|av_readdata_pre[20] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[1][20], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[0][20] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:data_read_en_rx_s1_translator|av_readdata_pre[19] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[1][19], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[0][19] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:data_read_en_rx_s1_translator|av_readdata_pre[18] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[1][18], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[0][18] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:data_read_en_rx_s1_translator|av_readdata_pre[17] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[1][17], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[0][17] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:data_read_en_rx_s1_translator|av_readdata_pre[16] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[1][16], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[0][16] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:data_read_en_rx_s1_translator|av_readdata_pre[15] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[1][15], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[0][15] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:data_read_en_rx_s1_translator|av_readdata_pre[14] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[1][14], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[0][14] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:data_read_en_rx_s1_translator|av_readdata_pre[13] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[1][13], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[0][13] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:data_read_en_rx_s1_translator|av_readdata_pre[12] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[1][12], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[0][12] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:data_read_en_rx_s1_translator|av_readdata_pre[11] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[1][11], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[0][11] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:write_en_tx_s1_translator|av_readdata_pre[19] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[1][19], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[0][19] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:data_read_en_rx_s1_translator|av_readdata_pre[9] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[1][9], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[0][9] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:data_read_en_rx_s1_translator|av_readdata_pre[8] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[1][8], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[0][8] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:data_read_en_rx_s1_translator|av_readdata_pre[7] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[1][7], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[0][7] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:data_read_en_rx_s1_translator|av_readdata_pre[6] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[1][6], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[0][6] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:data_read_en_rx_s1_translator|av_readdata_pre[5] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[1][5], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[0][5] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:data_read_en_rx_s1_translator|av_readdata_pre[4] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[1][4], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[0][4] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:data_read_en_rx_s1_translator|av_readdata_pre[3] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[1][3], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[0][3] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:data_read_en_rx_s1_translator|av_readdata_pre[2] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[1][2], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[0][2] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:data_read_en_rx_s1_translator|av_readdata_pre[1] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[1][1], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[0][1] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:led_pio_test_s1_translator|av_readdata_pre[31] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo|mem[1][31], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo|mem[0][31] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:led_pio_test_s1_translator|av_readdata_pre[30] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo|mem[1][30], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo|mem[0][30] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:write_data_fifo_tx_s1_translator|av_readdata_pre[15] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][15], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][15] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:write_data_fifo_tx_s1_translator|av_readdata_pre[27] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][27], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][27] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:write_data_fifo_tx_s1_translator|av_readdata_pre[26] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][26], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][26] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:write_data_fifo_tx_s1_translator|av_readdata_pre[25] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][25], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][25] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:write_data_fifo_tx_s1_translator|av_readdata_pre[24] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][24], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][24] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:write_data_fifo_tx_s1_translator|av_readdata_pre[23] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][23], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][23] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:write_data_fifo_tx_s1_translator|av_readdata_pre[21] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][21], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][21] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:write_data_fifo_tx_s1_translator|av_readdata_pre[20] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][20], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][20] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:write_data_fifo_tx_s1_translator|av_readdata_pre[19] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][19], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][19] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:write_data_fifo_tx_s1_translator|av_readdata_pre[18] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][18], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][18] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:write_data_fifo_tx_s1_translator|av_readdata_pre[17] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][17], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][17] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:write_data_fifo_tx_s1_translator|av_readdata_pre[16] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][16], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][16] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:write_data_fifo_tx_s1_translator|av_readdata_pre[28] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][28], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][28] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:write_data_fifo_tx_s1_translator|av_readdata_pre[14] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][14], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][14] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:write_data_fifo_tx_s1_translator|av_readdata_pre[13] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][13], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][13] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:write_data_fifo_tx_s1_translator|av_readdata_pre[12] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][12], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][12] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:write_data_fifo_tx_s1_translator|av_readdata_pre[11] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][11], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][11] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:write_data_fifo_tx_s1_translator|av_readdata_pre[10] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][10], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][10] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:write_data_fifo_tx_s1_translator|av_readdata_pre[9] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][9], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][9] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:link_disable_s1_translator|av_readdata_pre[31] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo|mem[1][31], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo|mem[0][31] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:link_disable_s1_translator|av_readdata_pre[30] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo|mem[1][30], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo|mem[0][30] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:link_disable_s1_translator|av_readdata_pre[29] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo|mem[1][29], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo|mem[0][29] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:link_disable_s1_translator|av_readdata_pre[28] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo|mem[1][28], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo|mem[0][28] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:link_disable_s1_translator|av_readdata_pre[27] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo|mem[1][27], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo|mem[0][27] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:write_en_tx_s1_translator|av_readdata_pre[8] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[1][8], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[0][8] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:write_en_tx_s1_translator|av_readdata_pre[9] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[1][9], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[0][9] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:write_en_tx_s1_translator|av_readdata_pre[10] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[1][10], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[0][10] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:write_en_tx_s1_translator|av_readdata_pre[11] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[1][11], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[0][11] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:write_en_tx_s1_translator|av_readdata_pre[12] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[1][12], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[0][12] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:write_en_tx_s1_translator|av_readdata_pre[13] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[1][13], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[0][13] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:write_en_tx_s1_translator|av_readdata_pre[14] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[1][14], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[0][14] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:write_en_tx_s1_translator|av_readdata_pre[15] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[1][15], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[0][15] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:write_en_tx_s1_translator|av_readdata_pre[16] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[1][16], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[0][16] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:write_en_tx_s1_translator|av_readdata_pre[17] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[1][17], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[0][17] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:write_en_tx_s1_translator|av_readdata_pre[18] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[1][18], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[0][18] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:write_en_tx_s1_translator|av_readdata_pre[20] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[1][20], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[0][20] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:write_data_fifo_tx_s1_translator|av_readdata_pre[22] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][22], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][22] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:write_en_tx_s1_translator|av_readdata_pre[7] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[1][7], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[0][7] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:write_en_tx_s1_translator|av_readdata_pre[6] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[1][6], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[0][6] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:write_en_tx_s1_translator|av_readdata_pre[5] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[1][5], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[0][5] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:auto_start_s1_translator|av_readdata_pre[9] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[1][9], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[0][9] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:write_en_tx_s1_translator|av_readdata_pre[4] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[1][4], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[0][4] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:write_en_tx_s1_translator|av_readdata_pre[3] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[1][3], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[0][3] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:write_en_tx_s1_translator|av_readdata_pre[2] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[1][2], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[0][2] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:write_en_tx_s1_translator|av_readdata_pre[1] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[1][1], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[0][1] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:write_data_fifo_tx_s1_translator|av_readdata_pre[31] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][31], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][31] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:write_data_fifo_tx_s1_translator|av_readdata_pre[30] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][30], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][30] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:write_data_fifo_tx_s1_translator|av_readdata_pre[29] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][29], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][29] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:auto_start_s1_translator|av_readdata_pre[21] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[1][21], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[0][21] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:link_disable_s1_translator|av_readdata_pre[2] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo|mem[1][2], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo|mem[0][2] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:link_disable_s1_translator|av_readdata_pre[1] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo|mem[1][1], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo|mem[0][1] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:auto_start_s1_translator|av_readdata_pre[31] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[1][31], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[0][31] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:auto_start_s1_translator|av_readdata_pre[30] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[1][30], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[0][30] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:auto_start_s1_translator|av_readdata_pre[29] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[1][29], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[0][29] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:auto_start_s1_translator|av_readdata_pre[28] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[1][28], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[0][28] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:auto_start_s1_translator|av_readdata_pre[27] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[1][27], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[0][27] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:auto_start_s1_translator|av_readdata_pre[26] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[1][26], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[0][26] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:auto_start_s1_translator|av_readdata_pre[25] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[1][25], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[0][25] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:auto_start_s1_translator|av_readdata_pre[24] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[1][24], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[0][24] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:auto_start_s1_translator|av_readdata_pre[23] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[1][23], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[0][23] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:auto_start_s1_translator|av_readdata_pre[22] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[1][22], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[0][22] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:link_disable_s1_translator|av_readdata_pre[25] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo|mem[1][25], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo|mem[0][25] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:auto_start_s1_translator|av_readdata_pre[20] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[1][20], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[0][20] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:auto_start_s1_translator|av_readdata_pre[19] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[1][19], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[0][19] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:auto_start_s1_translator|av_readdata_pre[18] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[1][18], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[0][18] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:auto_start_s1_translator|av_readdata_pre[17] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[1][17], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[0][17] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:auto_start_s1_translator|av_readdata_pre[16] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[1][16], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[0][16] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:auto_start_s1_translator|av_readdata_pre[15] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[1][15], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[0][15] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:auto_start_s1_translator|av_readdata_pre[14] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[1][14], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[0][14] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:auto_start_s1_translator|av_readdata_pre[13] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[1][13], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[0][13] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:auto_start_s1_translator|av_readdata_pre[12] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[1][12], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[0][12] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:auto_start_s1_translator|av_readdata_pre[11] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[1][11], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[0][11] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:auto_start_s1_translator|av_readdata_pre[10] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[1][10], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[0][10] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:link_disable_s1_translator|av_readdata_pre[11] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo|mem[1][11], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo|mem[0][11] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:link_disable_s1_translator|av_readdata_pre[26] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo|mem[1][26], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo|mem[0][26] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:link_disable_s1_translator|av_readdata_pre[24] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo|mem[1][24], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo|mem[0][24] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:link_disable_s1_translator|av_readdata_pre[23] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo|mem[1][23], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo|mem[0][23] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:link_disable_s1_translator|av_readdata_pre[22] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo|mem[1][22], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo|mem[0][22] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:link_disable_s1_translator|av_readdata_pre[21] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo|mem[1][21], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo|mem[0][21] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:link_disable_s1_translator|av_readdata_pre[20] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo|mem[1][20], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo|mem[0][20] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:link_disable_s1_translator|av_readdata_pre[19] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo|mem[1][19], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo|mem[0][19] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:link_disable_s1_translator|av_readdata_pre[18] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo|mem[1][18], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo|mem[0][18] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:link_disable_s1_translator|av_readdata_pre[17] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo|mem[1][17], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo|mem[0][17] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:link_disable_s1_translator|av_readdata_pre[16] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo|mem[1][16], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo|mem[0][16] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:link_disable_s1_translator|av_readdata_pre[15] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo|mem[1][15], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo|mem[0][15] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:link_disable_s1_translator|av_readdata_pre[14] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo|mem[1][14], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo|mem[0][14] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:link_disable_s1_translator|av_readdata_pre[13] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo|mem[1][13], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo|mem[0][13] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:link_disable_s1_translator|av_readdata_pre[12] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo|mem[1][12], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo|mem[0][12] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:link_disable_s1_translator|av_readdata_pre[3] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo|mem[1][3], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo|mem[0][3] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:link_disable_s1_translator|av_readdata_pre[4] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo|mem[1][4], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo|mem[0][4] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:link_disable_s1_translator|av_readdata_pre[10] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo|mem[1][10], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo|mem[0][10] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:link_disable_s1_translator|av_readdata_pre[9] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo|mem[1][9], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo|mem[0][9] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:link_disable_s1_translator|av_readdata_pre[8] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo|mem[1][8], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo|mem[0][8] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:link_disable_s1_translator|av_readdata_pre[5] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo|mem[1][5], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo|mem[0][5] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:link_disable_s1_translator|av_readdata_pre[6] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo|mem[1][6], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo|mem[0][6] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:link_disable_s1_translator|av_readdata_pre[7] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo|mem[1][7], ;; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo|mem[0][7] ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[1][33] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[0][33] ;; ; due to stuck port data_in ; ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[1][32] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[0][32] ;; ; due to stuck port data_in ; ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[1][33] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[0][33] ;; ; due to stuck port data_in ; ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[1][32] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[0][32] ;; ; due to stuck port data_in ; ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[1][33] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[0][33] ;; ; due to stuck port data_in ; ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[1][32] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[0][32] ;; ; due to stuck port data_in ; ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[1][33] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[0][33] ;; ; due to stuck port data_in ; ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[1][12] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[0][12] ;; ; due to stuck port data_in ; ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo|mem[1][32] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo|mem[0][32] ;; ; due to stuck port data_in ; ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo|mem[1][33] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo|mem[0][33] ;; ; due to stuck port data_in ; ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[1][32] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[0][32] ;; ; due to stuck port data_in ; ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[1][33] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[0][33] ;; ; due to stuck port data_in ; ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rdata_fifo|mem[1][32] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rdata_fifo|mem[0][32] ;; ; due to stuck port data_in ; ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rdata_fifo|mem[1][33] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rdata_fifo|mem[0][33] ;; ; due to stuck port data_in ; ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[1][32] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[0][32] ;; ; due to stuck port data_in ; ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[1][33] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[0][33] ;; ; due to stuck port data_in ; ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[1][13] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[0][13] ;; ; due to stuck port data_in ; ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_005|locked[1] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_005|altera_merlin_arbitrator:arb|top_priority_reg[0] ;; ; due to stuck port data_in ; ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[1][1] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[0][1] ;; ; due to stuck port data_in ; ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[1][0] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[0][0] ;; ; due to stuck port data_in ; ;; ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i|dps_extra_kick:dps_extra_inst|dps_current_state.PHASE_DONE_HIGH ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i|dps_extra_kick:dps_extra_inst|dps_current_state.PHASE_DONE_LOW_0 ;; ; due to stuck port clock ; ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_020|locked[1] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_020|altera_merlin_arbitrator:arb|top_priority_reg[0] ;; ; due to stuck port data_in ; ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_019|locked[1] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_019|altera_merlin_arbitrator:arb|top_priority_reg[0] ;; ; due to stuck port data_in ; ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_017|locked[1] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_017|altera_merlin_arbitrator:arb|top_priority_reg[0] ;; ; due to stuck port data_in ; ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_016|locked[1] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_016|altera_merlin_arbitrator:arb|top_priority_reg[0] ;; ; due to stuck port data_in ; ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_013|locked[1] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_013|altera_merlin_arbitrator:arb|top_priority_reg[0] ;; ; due to stuck port data_in ; ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_012|locked[1] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_012|altera_merlin_arbitrator:arb|top_priority_reg[0] ;; ; due to stuck port data_in ; ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_006|locked[1] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_006|altera_merlin_arbitrator:arb|top_priority_reg[0] ;; ; due to stuck port data_in ; ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[1][3] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[0][3] ;; ; due to stuck port data_in ; ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_003|locked[1] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_003|altera_merlin_arbitrator:arb|top_priority_reg[0] ;; ; due to stuck port data_in ; ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_002|locked[1] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_002|altera_merlin_arbitrator:arb|top_priority_reg[0] ;; ; due to stuck port data_in ; ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_001|locked[1] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_001|altera_merlin_arbitrator:arb|top_priority_reg[0] ;; ; due to stuck port data_in ; ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[1][6] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[0][6] ;; ; due to stuck port data_in ; ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[1][7] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[0][7] ;; ; due to stuck port data_in ; ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[1][8] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[0][8] ;; ; due to stuck port data_in ; ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[1][9] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[0][9] ;; ; due to stuck port data_in ; ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[1][10] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[0][10] ;; ; due to stuck port data_in ; ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[1][11] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[0][11] ;; ; due to stuck port data_in ; ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[1][32] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[0][32] ;; ; due to stuck port data_in ; ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_020|share_count_zero_flag ; Stuck at VCC ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_020|share_count[0] ;; ; due to stuck port data_in ; ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo|mem[1][32] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo|mem[0][32] ;; ; due to stuck port data_in ; ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo|mem[1][33] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo|mem[0][33] ;; ; due to stuck port data_in ; ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_001|share_count_zero_flag ; Stuck at VCC ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_001|share_count[0] ;; ; due to stuck port data_in ; ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_002|share_count_zero_flag ; Stuck at VCC ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_002|share_count[0] ;; ; due to stuck port data_in ; ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_003|share_count_zero_flag ; Stuck at VCC ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_003|share_count[0] ;; ; due to stuck port data_in ; ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_005|share_count_zero_flag ; Stuck at VCC ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_005|share_count[0] ;; ; due to stuck port data_in ; ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_006|share_count_zero_flag ; Stuck at VCC ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_006|share_count[0] ;; ; due to stuck port data_in ; ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_012|share_count_zero_flag ; Stuck at VCC ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_012|share_count[0] ;; ; due to stuck port data_in ; ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_013|share_count_zero_flag ; Stuck at VCC ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_013|share_count[0] ;; ; due to stuck port data_in ; ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_016|share_count_zero_flag ; Stuck at VCC ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_016|share_count[0] ;; ; due to stuck port data_in ; ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_017|share_count_zero_flag ; Stuck at VCC ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_017|share_count[0] ;; ; due to stuck port data_in ; ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_019|share_count_zero_flag ; Stuck at VCC ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_019|share_count[0] ;; ; due to stuck port data_in ; ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][33] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][33] ;; ; due to stuck port data_in ; ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_021|share_count_zero_flag ; Stuck at VCC ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_021|share_count[0] ;; ; due to stuck port data_in ; ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux|share_count_zero_flag ; Stuck at VCC ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux|share_count[0] ;; ; due to stuck port data_in ; ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_004|share_count_zero_flag ; Stuck at VCC ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_004|share_count[0] ;; ; due to stuck port data_in ; ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_007|share_count_zero_flag ; Stuck at VCC ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_007|share_count[0] ;; ; due to stuck port data_in ; ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_008|share_count_zero_flag ; Stuck at VCC ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_008|share_count[0] ;; ; due to stuck port data_in ; ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_009|share_count_zero_flag ; Stuck at VCC ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_009|share_count[0] ;; ; due to stuck port data_in ; ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_010|share_count_zero_flag ; Stuck at VCC ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_010|share_count[0] ;; ; due to stuck port data_in ; ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_011|share_count_zero_flag ; Stuck at VCC ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_011|share_count[0] ;; ; due to stuck port data_in ; ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_014|share_count_zero_flag ; Stuck at VCC ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_014|share_count[0] ;; ; due to stuck port data_in ; ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_015|share_count_zero_flag ; Stuck at VCC ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_015|share_count[0] ;; ; due to stuck port data_in ; ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_018|share_count_zero_flag ; Stuck at VCC ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_018|share_count[0] ;; ; due to stuck port data_in ; ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_021|locked[1] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_021|altera_merlin_arbitrator:arb|top_priority_reg[0] ;; ; due to stuck port data_in ; ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[1][33] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[0][33] ;; ; due to stuck port data_in ; ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rdata_fifo|mem[1][33] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rdata_fifo|mem[0][33] ;; ; due to stuck port data_in ; ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rdata_fifo|mem[1][32] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rdata_fifo|mem[0][32] ;; ; due to stuck port data_in ; ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rdata_fifo|mem[1][33] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rdata_fifo|mem[0][33] ;; ; due to stuck port data_in ; ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rdata_fifo|mem[1][32] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rdata_fifo|mem[0][32] ;; ; due to stuck port data_in ; ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rdata_fifo|mem[1][33] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rdata_fifo|mem[0][33] ;; ; due to stuck port data_in ; ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rdata_fifo|mem[1][32] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rdata_fifo|mem[0][32] ;; ; due to stuck port data_in ; ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rdata_fifo|mem[1][33] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rdata_fifo|mem[0][33] ;; ; due to stuck port data_in ; ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[1][32] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[0][32] ;; ; due to stuck port data_in ; ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[1][33] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[0][33] ;; ; due to stuck port data_in ; ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rdata_fifo|mem[1][32] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rdata_fifo|mem[0][32] ;; ; due to stuck port data_in ; ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rdata_fifo|mem[1][33] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rdata_fifo|mem[0][33] ;; ; due to stuck port data_in ; ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[1][32] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[0][32] ;; ; due to stuck port data_in ; ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rdata_fifo|mem[1][32] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rdata_fifo|mem[0][32] ;; ; due to stuck port data_in ; ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo|mem[1][32] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo|mem[0][32] ;; ; due to stuck port data_in ; ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo|mem[1][33] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo|mem[0][33] ;; ; due to stuck port data_in ; ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[1][32] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[0][32] ;; ; due to stuck port data_in ; ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[1][33] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[0][33] ;; ; due to stuck port data_in ; ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[1][32] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[0][32] ;; ; due to stuck port data_in ; ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[1][33] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[0][33] ;; ; due to stuck port data_in ; ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rdata_fifo|mem[1][32] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rdata_fifo|mem[0][32] ;; ; due to stuck port data_in ; ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rdata_fifo|mem[1][33] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rdata_fifo|mem[0][33] ;; ; due to stuck port data_in ; ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo|mem[1][32] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo|mem[0][32] ;; ; due to stuck port data_in ; ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo|mem[1][33] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo|mem[0][33] ;; ; due to stuck port data_in ; ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][32] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][32] ;; ; due to stuck port data_in ; ;+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------++------------------------------------------------------+; General Register Statistics ;+----------------------------------------------+-------+; Statistic ; Value ;+----------------------------------------------+-------+; Total registers ; 4628 ;; Number of registers using Synchronous Clear ; 0 ;; Number of registers using Synchronous Load ; 0 ;; Number of registers using Asynchronous Clear ; 4451 ;; Number of registers using Asynchronous Load ; 0 ;; Number of registers using Clock Enable ; 3301 ;; Number of registers using Preset ; 0 ;+----------------------------------------------+-------++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Inverted Register Statistics ;+-------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------+; Inverted Register ; Fan out ;+-------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------+; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_empty_tx_status_s1_translator|waitrequest_reset_override ; 3 ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:data_read_en_rx_s1_translator|waitrequest_reset_override ; 2 ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_data_s1_translator|waitrequest_reset_override ; 2 ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_enable_s1_translator|waitrequest_reset_override ; 2 ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:write_en_tx_s1_translator|waitrequest_reset_override ; 2 ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:clock_sel_s1_translator|waitrequest_reset_override ; 2 ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_ready_rx_s1_translator|waitrequest_reset_override ; 3 ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_empty_rx_status_s1_translator|waitrequest_reset_override ; 3 ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_full_tx_status_s1_translator|waitrequest_reset_override ; 3 ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fsm_info_s1_translator|waitrequest_reset_override ; 3 ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:led_pio_test_s1_translator|waitrequest_reset_override ; 2 ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_rx_s1_translator|waitrequest_reset_override ; 3 ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:data_flag_rx_s1_translator|waitrequest_reset_override ; 3 ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_full_rx_status_s1_translator|waitrequest_reset_override ; 3 ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_ready_s1_translator|waitrequest_reset_override ; 3 ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:counter_tx_fifo_s1_translator|waitrequest_reset_override ; 3 ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:write_data_fifo_tx_s1_translator|waitrequest_reset_override ; 2 ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:link_disable_s1_translator|waitrequest_reset_override ; 2 ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:data_info_s1_translator|waitrequest_reset_override ; 3 ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:link_start_s1_translator|waitrequest_reset_override ; 2 ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:counter_rx_fifo_s1_translator|waitrequest_reset_override ; 3 ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:auto_start_s1_translator|waitrequest_reset_override ; 2 ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_axi_master_ni:hps_0_h2f_axi_master_agent|sop_enable ; 61 ;; ulight_fifo:u0|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; 2969 ;; ulight_fifo:u0|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; 74 ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_004|altera_merlin_arbitrator:arb|top_priority_reg[0] ; 4 ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_014|altera_merlin_arbitrator:arb|top_priority_reg[0] ; 3 ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_015|altera_merlin_arbitrator:arb|top_priority_reg[0] ; 3 ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_011|altera_merlin_arbitrator:arb|top_priority_reg[0] ; 3 ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_018|altera_merlin_arbitrator:arb|top_priority_reg[0] ; 4 ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux|altera_merlin_arbitrator:arb|top_priority_reg[0] ; 3 ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_010|altera_merlin_arbitrator:arb|top_priority_reg[0] ; 3 ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_009|altera_merlin_arbitrator:arb|top_priority_reg[0] ; 3 ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_007|altera_merlin_arbitrator:arb|top_priority_reg[0] ; 3 ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_008|altera_merlin_arbitrator:arb|top_priority_reg[0] ; 4 ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_send:tx_fct_snd|fct_flag_p[2] ; 6 ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_send:tx_fct_snd|fct_flag_p[1] ; 6 ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_send:tx_fct_snd|fct_flag_p[0] ; 6 ;; ulight_fifo:u0|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain[0] ; 1 ;; ulight_fifo:u0|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain[0] ; 1 ;; ulight_fifo:u0|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain[1] ; 1 ;; ulight_fifo:u0|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain[1] ; 1 ;; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|credit_counter[3] ; 6 ;; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|credit_counter[5] ; 5 ;; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|credit_counter[4] ; 5 ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|counter_neg:cnt_neg|counter_neg[0] ; 10 ;; detector_tokens:m_x|counter_neg:cnt_neg|counter_neg[0] ; 10 ;; Total number of inverted registers = 47 ; ;+-------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Multiplexer Restructuring Statistics (No Restructuring Performed) ;+--------------------+-----------+---------------+----------------------+------------------------+------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;+--------------------+-----------+---------------+----------------------+------------------------+------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; 3:1 ; 2 bits ; 4 LEs ; 4 LEs ; 0 LEs ; Yes ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:clock_sel_s1_translator|wait_latency_counter[1] ;; 3:1 ; 2 bits ; 4 LEs ; 4 LEs ; 0 LEs ; Yes ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_enable_s1_translator|wait_latency_counter[0] ;; 3:1 ; 2 bits ; 4 LEs ; 4 LEs ; 0 LEs ; Yes ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_data_s1_translator|wait_latency_counter[0] ;; 3:1 ; 2 bits ; 4 LEs ; 4 LEs ; 0 LEs ; Yes ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:write_en_tx_s1_translator|wait_latency_counter[1] ;; 3:1 ; 2 bits ; 4 LEs ; 4 LEs ; 0 LEs ; Yes ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:write_data_fifo_tx_s1_translator|wait_latency_counter[0] ;; 3:1 ; 2 bits ; 4 LEs ; 4 LEs ; 0 LEs ; Yes ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:link_disable_s1_translator|wait_latency_counter[1] ;; 3:1 ; 2 bits ; 4 LEs ; 4 LEs ; 0 LEs ; Yes ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:auto_start_s1_translator|wait_latency_counter[1] ;; 3:1 ; 2 bits ; 4 LEs ; 4 LEs ; 0 LEs ; Yes ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:link_start_s1_translator|wait_latency_counter[1] ;; 3:1 ; 2 bits ; 4 LEs ; 4 LEs ; 0 LEs ; Yes ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:data_read_en_rx_s1_translator|wait_latency_counter[0] ;; 3:1 ; 2 bits ; 4 LEs ; 4 LEs ; 0 LEs ; Yes ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:led_pio_test_s1_translator|wait_latency_counter[1] ;; 3:1 ; 2 bits ; 4 LEs ; 4 LEs ; 0 LEs ; Yes ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:counter_rx_fifo_s1_translator|wait_latency_counter[1] ;; 3:1 ; 2 bits ; 4 LEs ; 4 LEs ; 0 LEs ; Yes ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:counter_tx_fifo_s1_translator|wait_latency_counter[1] ;; 3:1 ; 2 bits ; 4 LEs ; 4 LEs ; 0 LEs ; Yes ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fsm_info_s1_translator|wait_latency_counter[0] ;; 3:1 ; 2 bits ; 4 LEs ; 4 LEs ; 0 LEs ; Yes ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:data_info_s1_translator|wait_latency_counter[1] ;; 3:1 ; 2 bits ; 4 LEs ; 4 LEs ; 0 LEs ; Yes ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_ready_s1_translator|wait_latency_counter[1] ;; 3:1 ; 2 bits ; 4 LEs ; 4 LEs ; 0 LEs ; Yes ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_empty_tx_status_s1_translator|wait_latency_counter[1] ;; 3:1 ; 2 bits ; 4 LEs ; 4 LEs ; 0 LEs ; Yes ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_full_tx_status_s1_translator|wait_latency_counter[1] ;; 3:1 ; 2 bits ; 4 LEs ; 4 LEs ; 0 LEs ; Yes ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_empty_rx_status_s1_translator|wait_latency_counter[1] ;; 3:1 ; 2 bits ; 4 LEs ; 4 LEs ; 0 LEs ; Yes ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_full_rx_status_s1_translator|wait_latency_counter[0] ;; 3:1 ; 2 bits ; 4 LEs ; 4 LEs ; 0 LEs ; Yes ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:data_flag_rx_s1_translator|wait_latency_counter[0] ;; 3:1 ; 2 bits ; 4 LEs ; 4 LEs ; 0 LEs ; Yes ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_ready_rx_s1_translator|wait_latency_counter[1] ;; 3:1 ; 2 bits ; 4 LEs ; 4 LEs ; 0 LEs ; Yes ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_rx_s1_translator|wait_latency_counter[1] ;; 3:1 ; 4 bits ; 8 LEs ; 8 LEs ; 0 LEs ; No ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rsp_fifo|mem ;; 3:1 ; 4 bits ; 8 LEs ; 8 LEs ; 0 LEs ; No ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rsp_fifo|mem ;; 3:1 ; 4 bits ; 8 LEs ; 8 LEs ; 0 LEs ; No ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rsp_fifo|mem ;; 3:1 ; 4 bits ; 8 LEs ; 8 LEs ; 0 LEs ; No ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rsp_fifo|mem ;; 3:1 ; 4 bits ; 8 LEs ; 8 LEs ; 0 LEs ; No ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rsp_fifo|mem ;; 3:1 ; 4 bits ; 8 LEs ; 8 LEs ; 0 LEs ; No ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rsp_fifo|mem ;; 3:1 ; 4 bits ; 8 LEs ; 8 LEs ; 0 LEs ; No ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rsp_fifo|mem ;; 3:1 ; 4 bits ; 8 LEs ; 8 LEs ; 0 LEs ; No ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rsp_fifo|mem ;; 3:1 ; 4 bits ; 8 LEs ; 8 LEs ; 0 LEs ; No ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rsp_fifo|mem ;; 3:1 ; 4 bits ; 8 LEs ; 8 LEs ; 0 LEs ; No ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rsp_fifo|mem ;; 3:1 ; 4 bits ; 8 LEs ; 8 LEs ; 0 LEs ; No ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rsp_fifo|mem ;; 3:1 ; 4 bits ; 8 LEs ; 8 LEs ; 0 LEs ; No ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rsp_fifo|mem ;; 3:1 ; 4 bits ; 8 LEs ; 8 LEs ; 0 LEs ; No ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rsp_fifo|mem ;; 3:1 ; 4 bits ; 8 LEs ; 8 LEs ; 0 LEs ; No ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rsp_fifo|mem ;; 3:1 ; 4 bits ; 8 LEs ; 8 LEs ; 0 LEs ; No ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rsp_fifo|mem ;; 3:1 ; 4 bits ; 8 LEs ; 8 LEs ; 0 LEs ; No ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rsp_fifo|mem ;; 3:1 ; 4 bits ; 8 LEs ; 8 LEs ; 0 LEs ; No ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rsp_fifo|mem ;; 3:1 ; 4 bits ; 8 LEs ; 8 LEs ; 0 LEs ; No ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rsp_fifo|mem ;; 3:1 ; 4 bits ; 8 LEs ; 8 LEs ; 0 LEs ; No ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rsp_fifo|mem ;; 3:1 ; 4 bits ; 8 LEs ; 8 LEs ; 0 LEs ; No ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rsp_fifo|mem ;; 3:1 ; 4 bits ; 8 LEs ; 8 LEs ; 0 LEs ; No ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rsp_fifo|mem ;; 3:1 ; 4 bits ; 8 LEs ; 8 LEs ; 0 LEs ; No ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rsp_fifo|mem ;; 3:1 ; 5 bits ; 10 LEs ; 10 LEs ; 0 LEs ; No ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6] ;; 3:1 ; 5 bits ; 10 LEs ; 10 LEs ; 0 LEs ; No ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6] ;; 3:1 ; 5 bits ; 10 LEs ; 10 LEs ; 0 LEs ; No ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3] ;; 3:1 ; 5 bits ; 10 LEs ; 10 LEs ; 0 LEs ; No ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6] ;; 3:1 ; 5 bits ; 10 LEs ; 10 LEs ; 0 LEs ; No ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6] ;; 3:1 ; 5 bits ; 10 LEs ; 10 LEs ; 0 LEs ; No ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6] ;; 3:1 ; 5 bits ; 10 LEs ; 10 LEs ; 0 LEs ; No ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6] ;; 3:1 ; 5 bits ; 10 LEs ; 10 LEs ; 0 LEs ; No ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2] ;; 3:1 ; 5 bits ; 10 LEs ; 10 LEs ; 0 LEs ; No ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6] ;; 3:1 ; 5 bits ; 10 LEs ; 10 LEs ; 0 LEs ; No ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6] ;; 3:1 ; 5 bits ; 10 LEs ; 10 LEs ; 0 LEs ; No ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3] ;; 3:1 ; 5 bits ; 10 LEs ; 10 LEs ; 0 LEs ; No ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6] ;; 3:1 ; 5 bits ; 10 LEs ; 10 LEs ; 0 LEs ; No ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3] ;; 3:1 ; 5 bits ; 10 LEs ; 10 LEs ; 0 LEs ; No ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2] ;; 3:1 ; 5 bits ; 10 LEs ; 10 LEs ; 0 LEs ; No ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5] ;; 3:1 ; 5 bits ; 10 LEs ; 10 LEs ; 0 LEs ; No ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3] ;; 3:1 ; 5 bits ; 10 LEs ; 10 LEs ; 0 LEs ; No ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3] ;; 3:1 ; 5 bits ; 10 LEs ; 10 LEs ; 0 LEs ; No ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4] ;; 3:1 ; 5 bits ; 10 LEs ; 10 LEs ; 0 LEs ; No ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3] ;; 3:1 ; 5 bits ; 10 LEs ; 10 LEs ; 0 LEs ; No ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6] ;; 3:1 ; 5 bits ; 10 LEs ; 10 LEs ; 0 LEs ; No ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2] ;; 3:1 ; 5 bits ; 10 LEs ; 10 LEs ; 0 LEs ; No ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6] ;; 6:1 ; 3 bits ; 12 LEs ; 12 LEs ; 0 LEs ; No ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_router:router|src_channel[18] ;; 8:1 ; 3 bits ; 15 LEs ; 15 LEs ; 0 LEs ; No ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_router:router|src_data[103] ;; 19:1 ; 4 bits ; 48 LEs ; 48 LEs ; 0 LEs ; No ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_router:router_001|src_data[103] ;; 20:1 ; 2 bits ; 26 LEs ; 26 LEs ; 0 LEs ; No ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_router:router_001|src_channel[0] ;; 3:1 ; 6 bits ; 12 LEs ; 6 LEs ; 6 LEs ; Yes ; |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|counter[0] ;; 3:1 ; 3 bits ; 6 LEs ; 3 LEs ; 3 LEs ; Yes ; |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|credit_counter[2] ;; 3:1 ; 2 bits ; 4 LEs ; 2 LEs ; 2 LEs ; Yes ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:led_pio_test_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[1] ;; 3:1 ; 6 bits ; 12 LEs ; 12 LEs ; 0 LEs ; Yes ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:led_pio_test_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[6] ;; 3:1 ; 2 bits ; 4 LEs ; 0 LEs ; 4 LEs ; Yes ; |SPW_ULIGHT_FIFO|detector_tokens:m_x|parity_rec_d_gen ;; 3:1 ; 2 bits ; 4 LEs ; 2 LEs ; 2 LEs ; Yes ; |SPW_ULIGHT_FIFO|debounce_db:db_system_spwulight_b|aux_pb ;; 3:1 ; 16 bits ; 32 LEs ; 16 LEs ; 16 LEs ; Yes ; |SPW_ULIGHT_FIFO|debounce_db:db_system_spwulight_b|counter[15] ;; 4:1 ; 3 bits ; 6 LEs ; 6 LEs ; 0 LEs ; Yes ; |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|credit_counter[5] ;; 64:1 ; 9 bits ; 378 LEs ; 378 LEs ; 0 LEs ; Yes ; |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|data_out[7] ;; 64:1 ; 2 bits ; 84 LEs ; 26 LEs ; 58 LEs ; Yes ; |SPW_ULIGHT_FIFO|detector_tokens:m_x|counter_neg:cnt_neg|counter_neg[1] ;; 3:1 ; 2 bits ; 4 LEs ; 2 LEs ; 2 LEs ; Yes ; |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|rx_data_receive:rx_dtarcv|last_is_data ;; 3:1 ; 2 bits ; 4 LEs ; 2 LEs ; 2 LEs ; Yes ; |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|rx_data_control_p:data_control|parity_rec_c_gen ;; 5:1 ; 9 bits ; 27 LEs ; 18 LEs ; 9 LEs ; Yes ; |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|rx_data_receive:rx_dtarcv|rx_data_flag[0] ;; 3:1 ; 8 bits ; 16 LEs ; 8 LEs ; 8 LEs ; Yes ; |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|last_timein_control_flag_tx[1] ;; 3:1 ; 4 bits ; 8 LEs ; 4 LEs ; 4 LEs ; Yes ; |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_sout_e ;; 3:1 ; 2 bits ; 4 LEs ; 4 LEs ; 0 LEs ; Yes ; |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|eop_eep_last ;; 3:1 ; 4 bits ; 8 LEs ; 8 LEs ; 0 LEs ; Yes ; |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|global_counter_transfer[3] ;; 3:1 ; 8 bits ; 16 LEs ; 8 LEs ; 8 LEs ; Yes ; |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_data_send:tx_data_snd|tx_tcode_in[6] ;; 3:1 ; 9 bits ; 18 LEs ; 9 LEs ; 9 LEs ; Yes ; |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_data_send:tx_data_snd|tx_data_in[8] ;; 3:1 ; 9 bits ; 18 LEs ; 9 LEs ; 9 LEs ; Yes ; |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_data_send:tx_data_snd|tx_data_in_0[6] ;; 5:1 ; 3 bits ; 9 LEs ; 6 LEs ; 3 LEs ; Yes ; |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_send:tx_fct_snd|fct_flag[0] ;; 5:1 ; 6 bits ; 18 LEs ; 12 LEs ; 6 LEs ; Yes ; |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_counter:tx_fct_cnt|fct_counter_p[0] ;; 64:1 ; 9 bits ; 378 LEs ; 378 LEs ; 0 LEs ; Yes ; |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|data_out[1] ;; 6:1 ; 3 bits ; 12 LEs ; 6 LEs ; 6 LEs ; Yes ; |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_send:tx_fct_snd|fct_flag_p[1] ;; 6:1 ; 8 bits ; 32 LEs ; 16 LEs ; 16 LEs ; Yes ; |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|txdata_flagctrl_tx_last[3] ;; 5:1 ; 2 bits ; 6 LEs ; 6 LEs ; 0 LEs ; No ; |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|counter_aux[1] ;; 3:1 ; 2 bits ; 4 LEs ; 4 LEs ; 0 LEs ; No ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:led_pio_test_s1_agent|rp_data[124] ;; 3:1 ; 2 bits ; 4 LEs ; 4 LEs ; 0 LEs ; No ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_rx_s1_agent|rp_data[124] ;; 3:1 ; 2 bits ; 4 LEs ; 4 LEs ; 0 LEs ; No ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_ready_rx_s1_agent|rp_data[125] ;; 3:1 ; 2 bits ; 4 LEs ; 4 LEs ; 0 LEs ; No ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:data_flag_rx_s1_agent|rp_data[125] ;; 3:1 ; 2 bits ; 4 LEs ; 4 LEs ; 0 LEs ; No ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:data_read_en_rx_s1_agent|rp_data[124] ;; 3:1 ; 2 bits ; 4 LEs ; 4 LEs ; 0 LEs ; No ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fifo_full_rx_status_s1_agent|rp_data[124] ;; 3:1 ; 2 bits ; 4 LEs ; 4 LEs ; 0 LEs ; No ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fifo_empty_rx_status_s1_agent|rp_data[125] ;; 3:1 ; 2 bits ; 4 LEs ; 4 LEs ; 0 LEs ; No ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:link_start_s1_agent|rp_data[125] ;; 3:1 ; 2 bits ; 4 LEs ; 4 LEs ; 0 LEs ; No ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:auto_start_s1_agent|rp_data[125] ;; 3:1 ; 2 bits ; 4 LEs ; 4 LEs ; 0 LEs ; No ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:link_disable_s1_agent|rp_data[125] ;; 3:1 ; 2 bits ; 4 LEs ; 4 LEs ; 0 LEs ; No ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:write_data_fifo_tx_s1_agent|rp_data[125] ;; 3:1 ; 2 bits ; 4 LEs ; 4 LEs ; 0 LEs ; No ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:write_en_tx_s1_agent|rp_data[125] ;; 3:1 ; 2 bits ; 4 LEs ; 4 LEs ; 0 LEs ; No ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fifo_full_tx_status_s1_agent|rp_data[124] ;; 3:1 ; 2 bits ; 4 LEs ; 4 LEs ; 0 LEs ; No ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fifo_empty_tx_status_s1_agent|rp_data[124] ;; 3:1 ; 2 bits ; 4 LEs ; 4 LEs ; 0 LEs ; No ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_tx_data_s1_agent|rp_data[124] ;; 3:1 ; 2 bits ; 4 LEs ; 4 LEs ; 0 LEs ; No ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_tx_enable_s1_agent|rp_data[124] ;; 3:1 ; 2 bits ; 4 LEs ; 4 LEs ; 0 LEs ; No ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_tx_ready_s1_agent|rp_data[124] ;; 3:1 ; 2 bits ; 4 LEs ; 4 LEs ; 0 LEs ; No ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:data_info_s1_agent|rp_data[124] ;; 3:1 ; 2 bits ; 4 LEs ; 4 LEs ; 0 LEs ; No ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:clock_sel_s1_agent|rp_data[124] ;; 3:1 ; 2 bits ; 4 LEs ; 4 LEs ; 0 LEs ; No ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fsm_info_s1_agent|rp_data[124] ;; 3:1 ; 2 bits ; 4 LEs ; 4 LEs ; 0 LEs ; No ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:counter_tx_fifo_s1_agent|rp_data[124] ;; 3:1 ; 2 bits ; 4 LEs ; 4 LEs ; 0 LEs ; No ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:counter_rx_fifo_s1_agent|rp_data[124] ;; 3:1 ; 2 bits ; 4 LEs ; 2 LEs ; 2 LEs ; Yes ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_tx_data_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[1] ;; 3:1 ; 6 bits ; 12 LEs ; 12 LEs ; 0 LEs ; Yes ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_tx_data_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[5] ;; 3:1 ; 2 bits ; 4 LEs ; 2 LEs ; 2 LEs ; Yes ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fifo_empty_tx_status_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[1] ;; 3:1 ; 6 bits ; 12 LEs ; 12 LEs ; 0 LEs ; Yes ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fifo_empty_tx_status_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[4] ;; 4:1 ; 24 bits ; 48 LEs ; 24 LEs ; 24 LEs ; Yes ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_axi_master_ni:hps_0_h2f_axi_master_agent|altera_merlin_address_alignment:align_address_to_size|address_burst[29] ;; 3:1 ; 6 bits ; 12 LEs ; 12 LEs ; 0 LEs ; No ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_axi_master_ni:hps_0_h2f_axi_master_agent|Selector1 ;; 3:1 ; 2 bits ; 4 LEs ; 2 LEs ; 2 LEs ; Yes ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:counter_rx_fifo_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0] ;; 3:1 ; 6 bits ; 12 LEs ; 12 LEs ; 0 LEs ; Yes ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:counter_rx_fifo_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[2] ;; 3:1 ; 2 bits ; 4 LEs ; 2 LEs ; 2 LEs ; Yes ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:counter_tx_fifo_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0] ;; 3:1 ; 6 bits ; 12 LEs ; 12 LEs ; 0 LEs ; Yes ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:counter_tx_fifo_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[2] ;; 3:1 ; 2 bits ; 4 LEs ; 2 LEs ; 2 LEs ; Yes ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fsm_info_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0] ;; 3:1 ; 6 bits ; 12 LEs ; 12 LEs ; 0 LEs ; Yes ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fsm_info_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[7] ;; 3:1 ; 2 bits ; 4 LEs ; 2 LEs ; 2 LEs ; Yes ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:clock_sel_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0] ;; 3:1 ; 6 bits ; 12 LEs ; 12 LEs ; 0 LEs ; Yes ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:clock_sel_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[2] ;; 3:1 ; 2 bits ; 4 LEs ; 2 LEs ; 2 LEs ; Yes ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:data_info_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0] ;; 3:1 ; 6 bits ; 12 LEs ; 12 LEs ; 0 LEs ; Yes ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:data_info_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[3] ;; 3:1 ; 2 bits ; 4 LEs ; 2 LEs ; 2 LEs ; Yes ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_tx_ready_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0] ;; 3:1 ; 6 bits ; 12 LEs ; 12 LEs ; 0 LEs ; Yes ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_tx_ready_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[7] ;; 3:1 ; 2 bits ; 4 LEs ; 2 LEs ; 2 LEs ; Yes ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_tx_enable_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[1] ;; 3:1 ; 6 bits ; 12 LEs ; 12 LEs ; 0 LEs ; Yes ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_tx_enable_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[7] ;; 3:1 ; 2 bits ; 4 LEs ; 2 LEs ; 2 LEs ; Yes ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fifo_full_tx_status_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0] ;; 3:1 ; 6 bits ; 12 LEs ; 12 LEs ; 0 LEs ; Yes ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fifo_full_tx_status_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[7] ;; 3:1 ; 2 bits ; 4 LEs ; 2 LEs ; 2 LEs ; Yes ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:write_en_tx_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0] ;; 3:1 ; 6 bits ; 12 LEs ; 12 LEs ; 0 LEs ; Yes ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:write_en_tx_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[2] ;; 3:1 ; 2 bits ; 4 LEs ; 2 LEs ; 2 LEs ; Yes ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:write_data_fifo_tx_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[1] ;; 3:1 ; 6 bits ; 12 LEs ; 12 LEs ; 0 LEs ; Yes ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:write_data_fifo_tx_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[7] ;; 3:1 ; 2 bits ; 4 LEs ; 2 LEs ; 2 LEs ; Yes ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:link_disable_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0] ;; 3:1 ; 6 bits ; 12 LEs ; 12 LEs ; 0 LEs ; Yes ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:link_disable_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[2] ;; 3:1 ; 2 bits ; 4 LEs ; 2 LEs ; 2 LEs ; Yes ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:auto_start_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0] ;; 3:1 ; 6 bits ; 12 LEs ; 12 LEs ; 0 LEs ; Yes ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:auto_start_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[2] ;; 3:1 ; 2 bits ; 4 LEs ; 2 LEs ; 2 LEs ; Yes ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:link_start_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0] ;; 3:1 ; 6 bits ; 12 LEs ; 12 LEs ; 0 LEs ; Yes ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:link_start_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[7] ;; 3:1 ; 2 bits ; 4 LEs ; 2 LEs ; 2 LEs ; Yes ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fifo_empty_rx_status_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0] ;; 3:1 ; 6 bits ; 12 LEs ; 12 LEs ; 0 LEs ; Yes ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fifo_empty_rx_status_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[3] ;; 3:1 ; 2 bits ; 4 LEs ; 2 LEs ; 2 LEs ; Yes ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fifo_full_rx_status_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[1] ;; 3:1 ; 6 bits ; 12 LEs ; 12 LEs ; 0 LEs ; Yes ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fifo_full_rx_status_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[7] ;; 3:1 ; 2 bits ; 4 LEs ; 2 LEs ; 2 LEs ; Yes ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:data_read_en_rx_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0] ;; 3:1 ; 6 bits ; 12 LEs ; 12 LEs ; 0 LEs ; Yes ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:data_read_en_rx_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[7] ;; 3:1 ; 2 bits ; 4 LEs ; 2 LEs ; 2 LEs ; Yes ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:data_flag_rx_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0] ;; 3:1 ; 6 bits ; 12 LEs ; 12 LEs ; 0 LEs ; Yes ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:data_flag_rx_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[7] ;; 3:1 ; 2 bits ; 4 LEs ; 2 LEs ; 2 LEs ; Yes ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_ready_rx_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0] ;; 3:1 ; 6 bits ; 12 LEs ; 12 LEs ; 0 LEs ; Yes ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_ready_rx_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[7] ;; 3:1 ; 2 bits ; 4 LEs ; 2 LEs ; 2 LEs ; Yes ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_rx_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[1] ;; 3:1 ; 6 bits ; 12 LEs ; 12 LEs ; 0 LEs ; Yes ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_rx_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[6] ;; 3:1 ; 11 bits ; 22 LEs ; 22 LEs ; 0 LEs ; Yes ; |SPW_ULIGHT_FIFO|clock_reduce:R_400_to_2_5_10_100_200_300MHZ|counter_100[3] ;; 4:1 ; 12 bits ; 24 LEs ; 24 LEs ; 0 LEs ; Yes ; |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after64us[7] ;; 4:1 ; 12 bits ; 24 LEs ; 24 LEs ; 0 LEs ; Yes ; |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after850ns[9] ;; 5:1 ; 12 bits ; 36 LEs ; 36 LEs ; 0 LEs ; Yes ; |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us[7] ;; 64:1 ; 2 bits ; 84 LEs ; 26 LEs ; 58 LEs ; Yes ; |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|counter_neg:cnt_neg|counter_neg[1] ;; 17:1 ; 11 bits ; 121 LEs ; 22 LEs ; 99 LEs ; Yes ; |SPW_ULIGHT_FIFO|clock_reduce:R_400_to_2_5_10_100_200_300MHZ|counter[10] ;; 13:1 ; 3 bits ; 24 LEs ; 18 LEs ; 6 LEs ; No ; |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|Selector2 ;; 3:1 ; 6 bits ; 12 LEs ; 12 LEs ; 0 LEs ; No ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_axi_master_ni:hps_0_h2f_axi_master_agent|Selector8 ;+--------------------+-----------+---------------+----------------------+------------------------+------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Source assignments for ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll ;+---------------------------------------+-----------------------+------+----------------------------------------------------------------------------------------------------------+; Assignment ; Value ; From ; To ;+---------------------------------------+-----------------------+------+----------------------------------------------------------------------------------------------------------+; IP_TOOL_NAME ; altera_mem_if_hps_pll ; - ; - ;; IP_TOOL_VERSION ; 17.1 ; - ; - ;; FITTER_ADJUST_HC_SHORT_PATH_GUARDBAND ; 100 ; - ; - ;; ALLOW_SYNCH_CTRL_USAGE ; OFF ; - ; - ;; AUTO_CLOCK_ENABLE_RECOGNITION ; OFF ; - ; - ;; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF ; - ; - ;+---------------------------------------+-----------------------+------+----------------------------------------------------------------------------------------------------------++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Source assignments for ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0 ;+---------------------------------------+----------------------------------+------+---------------------------------------------------------------------------------------------+; Assignment ; Value ; From ; To ;+---------------------------------------+----------------------------------+------+---------------------------------------------------------------------------------------------+; IP_TOOL_NAME ; altera_mem_if_ddr3_hard_phy_core ; - ; - ;; IP_TOOL_VERSION ; 17.1 ; - ; - ;; FITTER_ADJUST_HC_SHORT_PATH_GUARDBAND ; 100 ; - ; - ;+---------------------------------------+----------------------------------+------+---------------------------------------------------------------------------------------------++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Source assignments for ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|altddio_out:clock_gen[0].umem_ck_pad ;+-------------------------+-------------+------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Assignment ; Value ; From ; To ;+-------------------------+-------------+------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; - ; - ;; PRESERVE_REGISTER ; ON ; - ; output_cell_L ;; DDIO_OUTPUT_REGISTER ; LOW ; - ; output_cell_L ;; DDIO_OUTPUT_REGISTER ; HIGH ; - ; mux ;+-------------------------+-------------+------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Source assignments for ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|altddio_out:clock_gen[0].umem_ck_pad|ddio_out_uqe:auto_generated ;+-----------------------------+---------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Assignment ; Value ; From ; To ;+-----------------------------+---------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; SYNCHRONIZER_IDENTIFICATION ; OFF ; - ; - ;; ADV_NETLIST_OPT_ALLOWED ; DEFAULT ; - ; - ;+-----------------------------+---------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Source assignments for ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_altdqdqs:dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_acv_connect_to_hard_phy_cyclonev:altdq_dqs2_inst ;+-----------------------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Assignment ; Value ; From ; To ;+-----------------------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; MESSAGE_DISABLE ; 12010 ; - ; - ;; MESSAGE_DISABLE ; 12161 ; - ; - ;; DONT_MERGE_REGISTER ; on ; - ; output_path_gen[0].oe_reg ;; FAST_OUTPUT_ENABLE_REGISTER ; on ; - ; output_path_gen[0].oe_reg ;; DONT_MERGE_REGISTER ; on ; - ; output_path_gen[1].oe_reg ;; FAST_OUTPUT_ENABLE_REGISTER ; on ; - ; output_path_gen[1].oe_reg ;; DONT_MERGE_REGISTER ; on ; - ; output_path_gen[2].oe_reg ;; FAST_OUTPUT_ENABLE_REGISTER ; on ; - ; output_path_gen[2].oe_reg ;; DONT_MERGE_REGISTER ; on ; - ; output_path_gen[3].oe_reg ;; FAST_OUTPUT_ENABLE_REGISTER ; on ; - ; output_path_gen[3].oe_reg ;; DONT_MERGE_REGISTER ; on ; - ; output_path_gen[4].oe_reg ;; FAST_OUTPUT_ENABLE_REGISTER ; on ; - ; output_path_gen[4].oe_reg ;; DONT_MERGE_REGISTER ; on ; - ; output_path_gen[5].oe_reg ;; FAST_OUTPUT_ENABLE_REGISTER ; on ; - ; output_path_gen[5].oe_reg ;; DONT_MERGE_REGISTER ; on ; - ; output_path_gen[6].oe_reg ;; FAST_OUTPUT_ENABLE_REGISTER ; on ; - ; output_path_gen[6].oe_reg ;; DONT_MERGE_REGISTER ; on ; - ; output_path_gen[7].oe_reg ;; FAST_OUTPUT_ENABLE_REGISTER ; on ; - ; output_path_gen[7].oe_reg ;+-----------------------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Source assignments for ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|altera_mem_if_hard_memory_controller_top_cyclonev:c0 ;+---------------------------------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------+; Assignment ; Value ; From ; To ;+---------------------------------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------+; FITTER_ADJUST_HC_SHORT_PATH_GUARDBAND ; 100 ; - ; - ;+---------------------------------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Source assignments for ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|altera_mem_if_oct_cyclonev:oct ;+---------------------------------------+-------------------+------+---------------------------------------------------------------------------------------------------------------------------+; Assignment ; Value ; From ; To ;+---------------------------------------+-------------------+------+---------------------------------------------------------------------------------------------------------------------------+; IP_TOOL_NAME ; altera_mem_if_oct ; - ; - ;; IP_TOOL_VERSION ; 17.1 ; - ; - ;; FITTER_ADJUST_HC_SHORT_PATH_GUARDBAND ; 100 ; - ; - ;; ALLOW_SYNCH_CTRL_USAGE ; OFF ; - ; - ;; AUTO_CLOCK_ENABLE_RECOGNITION ; OFF ; - ; - ;; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF ; - ; - ;+---------------------------------------+-------------------+------+---------------------------------------------------------------------------------------------------------------------------++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Source assignments for ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|altera_mem_if_dll_cyclonev:dll ;+---------------------------------------+-------------------+------+---------------------------------------------------------------------------------------------------------------------------+; Assignment ; Value ; From ; To ;+---------------------------------------+-------------------+------+---------------------------------------------------------------------------------------------------------------------------+; IP_TOOL_NAME ; altera_mem_if_dll ; - ; - ;; IP_TOOL_VERSION ; 17.1 ; - ; - ;; FITTER_ADJUST_HC_SHORT_PATH_GUARDBAND ; 100 ; - ; - ;; ALLOW_SYNCH_CTRL_USAGE ; OFF ; - ; - ;; AUTO_CLOCK_ENABLE_RECOGNITION ; OFF ; - ; - ;; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF ; - ; - ;+---------------------------------------+-------------------+------+---------------------------------------------------------------------------------------------------------------------------++---------------------------------------------------------------------------------------+; Source assignments for ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i ;+------------------------------+-------+------+-----------------------------------------+; Assignment ; Value ; From ; To ;+------------------------------+-------+------+-----------------------------------------+; IGNORE_LCELL_BUFFERS ; off ; - ; cntsel_temp[4] ;; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; cntsel_temp[4] ;; IGNORE_LCELL_BUFFERS ; off ; - ; cntsel_temp[3] ;; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; cntsel_temp[3] ;; IGNORE_LCELL_BUFFERS ; off ; - ; cntsel_temp[2] ;; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; cntsel_temp[2] ;; IGNORE_LCELL_BUFFERS ; off ; - ; cntsel_temp[1] ;; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; cntsel_temp[1] ;; IGNORE_LCELL_BUFFERS ; off ; - ; cntsel_temp[0] ;; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; cntsel_temp[0] ;; IGNORE_LCELL_BUFFERS ; off ; - ; gnd ;; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gnd ;+------------------------------+-------+------+-----------------------------------------++------------------------------------------------------------------------------------------------------------------------------------+; Source assignments for ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i|altera_pll_dps_lcell_comb:lcell_cntsel_int_0 ;+--------------------------------------+-------+------+------------------------------------------------------------------------------+; Assignment ; Value ; From ; To ;+--------------------------------------+-------+------+------------------------------------------------------------------------------+; PHYSICAL_SYNTHESIS_COMBO_LOGIC ; OFF ; - ; - ;; PHYSICAL_SYNTHESIS_REGISTER_RETIMING ; OFF ; - ; - ;; ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP ; OFF ; - ; - ;; REMOVE_REDUNDANT_LOGIC_CELLS ; OFF ; - ; - ;+--------------------------------------+-------+------+------------------------------------------------------------------------------++------------------------------------------------------------------------------------------------------------------------------------+; Source assignments for ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i|altera_pll_dps_lcell_comb:lcell_cntsel_int_1 ;+--------------------------------------+-------+------+------------------------------------------------------------------------------+; Assignment ; Value ; From ; To ;+--------------------------------------+-------+------+------------------------------------------------------------------------------+; PHYSICAL_SYNTHESIS_COMBO_LOGIC ; OFF ; - ; - ;; PHYSICAL_SYNTHESIS_REGISTER_RETIMING ; OFF ; - ; - ;; ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP ; OFF ; - ; - ;; REMOVE_REDUNDANT_LOGIC_CELLS ; OFF ; - ; - ;+--------------------------------------+-------+------+------------------------------------------------------------------------------++------------------------------------------------------------------------------------------------------------------------------------+; Source assignments for ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i|altera_pll_dps_lcell_comb:lcell_cntsel_int_2 ;+--------------------------------------+-------+------+------------------------------------------------------------------------------+; Assignment ; Value ; From ; To ;+--------------------------------------+-------+------+------------------------------------------------------------------------------+; PHYSICAL_SYNTHESIS_COMBO_LOGIC ; OFF ; - ; - ;; PHYSICAL_SYNTHESIS_REGISTER_RETIMING ; OFF ; - ; - ;; ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP ; OFF ; - ; - ;; REMOVE_REDUNDANT_LOGIC_CELLS ; OFF ; - ; - ;+--------------------------------------+-------+------+------------------------------------------------------------------------------++------------------------------------------------------------------------------------------------------------------------------------+; Source assignments for ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i|altera_pll_dps_lcell_comb:lcell_cntsel_int_3 ;+--------------------------------------+-------+------+------------------------------------------------------------------------------+; Assignment ; Value ; From ; To ;+--------------------------------------+-------+------+------------------------------------------------------------------------------+; PHYSICAL_SYNTHESIS_COMBO_LOGIC ; OFF ; - ; - ;; PHYSICAL_SYNTHESIS_REGISTER_RETIMING ; OFF ; - ; - ;; ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP ; OFF ; - ; - ;; REMOVE_REDUNDANT_LOGIC_CELLS ; OFF ; - ; - ;+--------------------------------------+-------+------+------------------------------------------------------------------------------++------------------------------------------------------------------------------------------------------------------------------------+; Source assignments for ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i|altera_pll_dps_lcell_comb:lcell_cntsel_int_4 ;+--------------------------------------+-------+------+------------------------------------------------------------------------------+; Assignment ; Value ; From ; To ;+--------------------------------------+-------+------+------------------------------------------------------------------------------+; PHYSICAL_SYNTHESIS_COMBO_LOGIC ; OFF ; - ; - ;; PHYSICAL_SYNTHESIS_REGISTER_RETIMING ; OFF ; - ; - ;; ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP ; OFF ; - ; - ;; REMOVE_REDUNDANT_LOGIC_CELLS ; OFF ; - ; - ;+--------------------------------------+-------+------+------------------------------------------------------------------------------++-----------------------------------------------------------------------------------------------------------------------------------------+; Source assignments for ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_demux:cmd_demux ;+-----------------+-------+------+--------------------------------------------------------------------------------------------------------+; Assignment ; Value ; From ; To ;+-----------------+-------+------+--------------------------------------------------------------------------------------------------------+; MESSAGE_DISABLE ; 15610 ; - ; clk ;; MESSAGE_DISABLE ; 15610 ; - ; reset ;+-----------------+-------+------+--------------------------------------------------------------------------------------------------------++---------------------------------------------------------------------------------------------------------------------------------------------+; Source assignments for ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_demux:cmd_demux_001 ;+-----------------+-------+------+------------------------------------------------------------------------------------------------------------+; Assignment ; Value ; From ; To ;+-----------------+-------+------+------------------------------------------------------------------------------------------------------------+; MESSAGE_DISABLE ; 15610 ; - ; clk ;; MESSAGE_DISABLE ; 15610 ; - ; reset ;+-----------------+-------+------+------------------------------------------------------------------------------------------------------------++-----------------------------------------------------------------------------------------------------------------------------------------+; Source assignments for ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux ;+-----------------+-------+------+--------------------------------------------------------------------------------------------------------+; Assignment ; Value ; From ; To ;+-----------------+-------+------+--------------------------------------------------------------------------------------------------------+; MESSAGE_DISABLE ; 15610 ; - ; clk ;; MESSAGE_DISABLE ; 15610 ; - ; reset ;+-----------------+-------+------+--------------------------------------------------------------------------------------------------------++---------------------------------------------------------------------------------------------------------------------------------------------+; Source assignments for ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_001 ;+-----------------+-------+------+------------------------------------------------------------------------------------------------------------+; Assignment ; Value ; From ; To ;+-----------------+-------+------+------------------------------------------------------------------------------------------------------------+; MESSAGE_DISABLE ; 15610 ; - ; clk ;; MESSAGE_DISABLE ; 15610 ; - ; reset ;+-----------------+-------+------+------------------------------------------------------------------------------------------------------------++---------------------------------------------------------------------------------------------------------------------------------------------+; Source assignments for ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_002 ;+-----------------+-------+------+------------------------------------------------------------------------------------------------------------+; Assignment ; Value ; From ; To ;+-----------------+-------+------+------------------------------------------------------------------------------------------------------------+; MESSAGE_DISABLE ; 15610 ; - ; clk ;; MESSAGE_DISABLE ; 15610 ; - ; reset ;+-----------------+-------+------+------------------------------------------------------------------------------------------------------------++---------------------------------------------------------------------------------------------------------------------------------------------+; Source assignments for ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_003 ;+-----------------+-------+------+------------------------------------------------------------------------------------------------------------+; Assignment ; Value ; From ; To ;+-----------------+-------+------+------------------------------------------------------------------------------------------------------------+; MESSAGE_DISABLE ; 15610 ; - ; clk ;; MESSAGE_DISABLE ; 15610 ; - ; reset ;+-----------------+-------+------+------------------------------------------------------------------------------------------------------------++---------------------------------------------------------------------------------------------------------------------------------------------+; Source assignments for ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_004 ;+-----------------+-------+------+------------------------------------------------------------------------------------------------------------+; Assignment ; Value ; From ; To ;+-----------------+-------+------+------------------------------------------------------------------------------------------------------------+; MESSAGE_DISABLE ; 15610 ; - ; clk ;; MESSAGE_DISABLE ; 15610 ; - ; reset ;+-----------------+-------+------+------------------------------------------------------------------------------------------------------------++---------------------------------------------------------------------------------------------------------------------------------------------+; Source assignments for ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_005 ;+-----------------+-------+------+------------------------------------------------------------------------------------------------------------+; Assignment ; Value ; From ; To ;+-----------------+-------+------+------------------------------------------------------------------------------------------------------------+; MESSAGE_DISABLE ; 15610 ; - ; clk ;; MESSAGE_DISABLE ; 15610 ; - ; reset ;+-----------------+-------+------+------------------------------------------------------------------------------------------------------------++---------------------------------------------------------------------------------------------------------------------------------------------+; Source assignments for ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_006 ;+-----------------+-------+------+------------------------------------------------------------------------------------------------------------+; Assignment ; Value ; From ; To ;+-----------------+-------+------+------------------------------------------------------------------------------------------------------------+; MESSAGE_DISABLE ; 15610 ; - ; clk ;; MESSAGE_DISABLE ; 15610 ; - ; reset ;+-----------------+-------+------+------------------------------------------------------------------------------------------------------------++---------------------------------------------------------------------------------------------------------------------------------------------+; Source assignments for ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_007 ;+-----------------+-------+------+------------------------------------------------------------------------------------------------------------+; Assignment ; Value ; From ; To ;+-----------------+-------+------+------------------------------------------------------------------------------------------------------------+; MESSAGE_DISABLE ; 15610 ; - ; clk ;; MESSAGE_DISABLE ; 15610 ; - ; reset ;+-----------------+-------+------+------------------------------------------------------------------------------------------------------------++---------------------------------------------------------------------------------------------------------------------------------------------+; Source assignments for ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_008 ;+-----------------+-------+------+------------------------------------------------------------------------------------------------------------+; Assignment ; Value ; From ; To ;+-----------------+-------+------+------------------------------------------------------------------------------------------------------------+; MESSAGE_DISABLE ; 15610 ; - ; clk ;; MESSAGE_DISABLE ; 15610 ; - ; reset ;+-----------------+-------+------+------------------------------------------------------------------------------------------------------------++---------------------------------------------------------------------------------------------------------------------------------------------+; Source assignments for ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_009 ;+-----------------+-------+------+------------------------------------------------------------------------------------------------------------+; Assignment ; Value ; From ; To ;+-----------------+-------+------+------------------------------------------------------------------------------------------------------------+; MESSAGE_DISABLE ; 15610 ; - ; clk ;; MESSAGE_DISABLE ; 15610 ; - ; reset ;+-----------------+-------+------+------------------------------------------------------------------------------------------------------------++---------------------------------------------------------------------------------------------------------------------------------------------+; Source assignments for ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_010 ;+-----------------+-------+------+------------------------------------------------------------------------------------------------------------+; Assignment ; Value ; From ; To ;+-----------------+-------+------+------------------------------------------------------------------------------------------------------------+; MESSAGE_DISABLE ; 15610 ; - ; clk ;; MESSAGE_DISABLE ; 15610 ; - ; reset ;+-----------------+-------+------+------------------------------------------------------------------------------------------------------------++---------------------------------------------------------------------------------------------------------------------------------------------+; Source assignments for ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_011 ;+-----------------+-------+------+------------------------------------------------------------------------------------------------------------+; Assignment ; Value ; From ; To ;+-----------------+-------+------+------------------------------------------------------------------------------------------------------------+; MESSAGE_DISABLE ; 15610 ; - ; clk ;; MESSAGE_DISABLE ; 15610 ; - ; reset ;+-----------------+-------+------+------------------------------------------------------------------------------------------------------------++---------------------------------------------------------------------------------------------------------------------------------------------+; Source assignments for ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_012 ;+-----------------+-------+------+------------------------------------------------------------------------------------------------------------+; Assignment ; Value ; From ; To ;+-----------------+-------+------+------------------------------------------------------------------------------------------------------------+; MESSAGE_DISABLE ; 15610 ; - ; clk ;; MESSAGE_DISABLE ; 15610 ; - ; reset ;+-----------------+-------+------+------------------------------------------------------------------------------------------------------------++---------------------------------------------------------------------------------------------------------------------------------------------+; Source assignments for ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_013 ;+-----------------+-------+------+------------------------------------------------------------------------------------------------------------+; Assignment ; Value ; From ; To ;+-----------------+-------+------+------------------------------------------------------------------------------------------------------------+; MESSAGE_DISABLE ; 15610 ; - ; clk ;; MESSAGE_DISABLE ; 15610 ; - ; reset ;+-----------------+-------+------+------------------------------------------------------------------------------------------------------------++---------------------------------------------------------------------------------------------------------------------------------------------+; Source assignments for ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_014 ;+-----------------+-------+------+------------------------------------------------------------------------------------------------------------+; Assignment ; Value ; From ; To ;+-----------------+-------+------+------------------------------------------------------------------------------------------------------------+; MESSAGE_DISABLE ; 15610 ; - ; clk ;; MESSAGE_DISABLE ; 15610 ; - ; reset ;+-----------------+-------+------+------------------------------------------------------------------------------------------------------------++---------------------------------------------------------------------------------------------------------------------------------------------+; Source assignments for ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_015 ;+-----------------+-------+------+------------------------------------------------------------------------------------------------------------+; Assignment ; Value ; From ; To ;+-----------------+-------+------+------------------------------------------------------------------------------------------------------------+; MESSAGE_DISABLE ; 15610 ; - ; clk ;; MESSAGE_DISABLE ; 15610 ; - ; reset ;+-----------------+-------+------+------------------------------------------------------------------------------------------------------------++---------------------------------------------------------------------------------------------------------------------------------------------+; Source assignments for ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_016 ;+-----------------+-------+------+------------------------------------------------------------------------------------------------------------+; Assignment ; Value ; From ; To ;+-----------------+-------+------+------------------------------------------------------------------------------------------------------------+; MESSAGE_DISABLE ; 15610 ; - ; clk ;; MESSAGE_DISABLE ; 15610 ; - ; reset ;+-----------------+-------+------+------------------------------------------------------------------------------------------------------------++---------------------------------------------------------------------------------------------------------------------------------------------+; Source assignments for ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_017 ;+-----------------+-------+------+------------------------------------------------------------------------------------------------------------+; Assignment ; Value ; From ; To ;+-----------------+-------+------+------------------------------------------------------------------------------------------------------------+; MESSAGE_DISABLE ; 15610 ; - ; clk ;; MESSAGE_DISABLE ; 15610 ; - ; reset ;+-----------------+-------+------+------------------------------------------------------------------------------------------------------------++---------------------------------------------------------------------------------------------------------------------------------------------+; Source assignments for ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_018 ;+-----------------+-------+------+------------------------------------------------------------------------------------------------------------+; Assignment ; Value ; From ; To ;+-----------------+-------+------+------------------------------------------------------------------------------------------------------------+; MESSAGE_DISABLE ; 15610 ; - ; clk ;; MESSAGE_DISABLE ; 15610 ; - ; reset ;+-----------------+-------+------+------------------------------------------------------------------------------------------------------------++---------------------------------------------------------------------------------------------------------------------------------------------+; Source assignments for ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_019 ;+-----------------+-------+------+------------------------------------------------------------------------------------------------------------+; Assignment ; Value ; From ; To ;+-----------------+-------+------+------------------------------------------------------------------------------------------------------------+; MESSAGE_DISABLE ; 15610 ; - ; clk ;; MESSAGE_DISABLE ; 15610 ; - ; reset ;+-----------------+-------+------+------------------------------------------------------------------------------------------------------------++---------------------------------------------------------------------------------------------------------------------------------------------+; Source assignments for ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_020 ;+-----------------+-------+------+------------------------------------------------------------------------------------------------------------+; Assignment ; Value ; From ; To ;+-----------------+-------+------+------------------------------------------------------------------------------------------------------------+; MESSAGE_DISABLE ; 15610 ; - ; clk ;; MESSAGE_DISABLE ; 15610 ; - ; reset ;+-----------------+-------+------+------------------------------------------------------------------------------------------------------------++---------------------------------------------------------------------------------------------------------------------------------------------+; Source assignments for ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_021 ;+-----------------+-------+------+------------------------------------------------------------------------------------------------------------+; Assignment ; Value ; From ; To ;+-----------------+-------+------+------------------------------------------------------------------------------------------------------------+; MESSAGE_DISABLE ; 15610 ; - ; clk ;; MESSAGE_DISABLE ; 15610 ; - ; reset ;+-----------------+-------+------+------------------------------------------------------------------------------------------------------------++-------------------------------------------------------------------------------------------------------------------------+; Source assignments for ulight_fifo:u0|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1 ;+-------------------+-------+------+--------------------------------------------------------------------------------------+; Assignment ; Value ; From ; To ;+-------------------+-------+------+--------------------------------------------------------------------------------------+; PRESERVE_REGISTER ; on ; - ; altera_reset_synchronizer_int_chain[1] ;; PRESERVE_REGISTER ; on ; - ; altera_reset_synchronizer_int_chain[0] ;+-------------------+-------+------+--------------------------------------------------------------------------------------++-----------------------------------------------------------------------------------------------------------------------------+; Source assignments for ulight_fifo:u0|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_req_sync_uq1 ;+-------------------+-------+------+------------------------------------------------------------------------------------------+; Assignment ; Value ; From ; To ;+-------------------+-------+------+------------------------------------------------------------------------------------------+; PRESERVE_REGISTER ; on ; - ; altera_reset_synchronizer_int_chain[0] ;; PRESERVE_REGISTER ; on ; - ; altera_reset_synchronizer_int_chain[1] ;+-------------------+-------+------+------------------------------------------------------------------------------------------++-----------------------------------------------------------------------------------------------------------------------------+; Source assignments for ulight_fifo:u0|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1 ;+-------------------+-------+------+------------------------------------------------------------------------------------------+; Assignment ; Value ; From ; To ;+-------------------+-------+------+------------------------------------------------------------------------------------------+; PRESERVE_REGISTER ; on ; - ; altera_reset_synchronizer_int_chain[1] ;; PRESERVE_REGISTER ; on ; - ; altera_reset_synchronizer_int_chain[0] ;+-------------------+-------+------+------------------------------------------------------------------------------------------++---------------------------------------------------------------------------------------------------------------------------------+; Source assignments for ulight_fifo:u0|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_req_sync_uq1 ;+-------------------+-------+------+----------------------------------------------------------------------------------------------+; Assignment ; Value ; From ; To ;+-------------------+-------+------+----------------------------------------------------------------------------------------------+; PRESERVE_REGISTER ; on ; - ; altera_reset_synchronizer_int_chain[0] ;; PRESERVE_REGISTER ; on ; - ; altera_reset_synchronizer_int_chain[1] ;+-------------------+-------+------+----------------------------------------------------------------------------------------------++-------------------------------------------------------------------------------------------------------------------+; Source assignments for spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|rx_data_receive:rx_dtarcv ;+-------------------------+-------------+------+--------------------------------------------------------------------+; Assignment ; Value ; From ; To ;+-------------------------+-------------+------+--------------------------------------------------------------------+; ADV_NETLIST_OPT_ALLOWED ; Never Allow ; - ; - ;+-------------------------+-------------+------+--------------------------------------------------------------------++-----------------------------------------------------------------------------------------------------------------------------------+; Source assignments for spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_counter:tx_fct_cnt ;+-------------------------+-------------+------+------------------------------------------------------------------------------------+; Assignment ; Value ; From ; To ;+-------------------------+-------------+------+------------------------------------------------------------------------------------+; ADV_NETLIST_OPT_ALLOWED ; Never Allow ; - ; state_fct_p.000 ;; ADV_NETLIST_OPT_ALLOWED ; Never Allow ; - ; state_fct_p.001 ;; ADV_NETLIST_OPT_ALLOWED ; Never Allow ; - ; state_fct_p.010 ;; ADV_NETLIST_OPT_ALLOWED ; Never Allow ; - ; state_fct_p.011 ;; ADV_NETLIST_OPT_ALLOWED ; Never Allow ; - ; state_fct_p.100 ;; ADV_NETLIST_OPT_ALLOWED ; Never Allow ; - ; state_fct_receive.100 ;; ADV_NETLIST_OPT_ALLOWED ; Never Allow ; - ; state_fct_receive.011 ;; ADV_NETLIST_OPT_ALLOWED ; Never Allow ; - ; state_fct_receive.010 ;; ADV_NETLIST_OPT_ALLOWED ; Never Allow ; - ; state_fct_receive.001 ;; ADV_NETLIST_OPT_ALLOWED ; Never Allow ; - ; state_fct_receive.000 ;+-------------------------+-------------+------+------------------------------------------------------------------------------------++--------------------------------------------------------------------------------------------------------------------------------+; Source assignments for spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_send:tx_fct_snd ;+-------------------------+-------------+------+---------------------------------------------------------------------------------+; Assignment ; Value ; From ; To ;+-------------------------+-------------+------+---------------------------------------------------------------------------------+; ADV_NETLIST_OPT_ALLOWED ; Never Allow ; - ; state_fct_send.000 ;; ADV_NETLIST_OPT_ALLOWED ; Never Allow ; - ; state_fct_send.001 ;; ADV_NETLIST_OPT_ALLOWED ; Never Allow ; - ; state_fct_send_p.000 ;; ADV_NETLIST_OPT_ALLOWED ; Never Allow ; - ; state_fct_send_p.001 ;; ADV_NETLIST_OPT_ALLOWED ; Never Allow ; - ; state_fct_send_p.010 ;+-------------------------+-------------+------+---------------------------------------------------------------------------------++-----------------------------------------------------------------------+; Source assignments for spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data ;+---------------------------+-------+------+----------------------------+; Assignment ; Value ; From ; To ;+---------------------------+-------+------+----------------------------+; PRESERVE_FANOUT_FREE_NODE ; on ; - ; - ;; PRESERVE_REGISTER ; on ; - ; wr_ptr[5] ;; PRESERVE_FANOUT_FREE_NODE ; on ; - ; wr_ptr[5] ;; PRESERVE_REGISTER ; on ; - ; wr_ptr[4] ;; PRESERVE_FANOUT_FREE_NODE ; on ; - ; wr_ptr[4] ;; PRESERVE_REGISTER ; on ; - ; wr_ptr[3] ;; PRESERVE_FANOUT_FREE_NODE ; on ; - ; wr_ptr[3] ;; PRESERVE_REGISTER ; on ; - ; wr_ptr[2] ;; PRESERVE_FANOUT_FREE_NODE ; on ; - ; wr_ptr[2] ;; PRESERVE_REGISTER ; on ; - ; wr_ptr[1] ;; PRESERVE_FANOUT_FREE_NODE ; on ; - ; wr_ptr[1] ;; PRESERVE_REGISTER ; on ; - ; wr_ptr[0] ;; PRESERVE_FANOUT_FREE_NODE ; on ; - ; wr_ptr[0] ;; PRESERVE_REGISTER ; on ; - ; counter_writer[5] ;; PRESERVE_FANOUT_FREE_NODE ; on ; - ; counter_writer[5] ;; PRESERVE_REGISTER ; on ; - ; counter_writer[4] ;; PRESERVE_FANOUT_FREE_NODE ; on ; - ; counter_writer[4] ;; PRESERVE_REGISTER ; on ; - ; counter_writer[3] ;; PRESERVE_FANOUT_FREE_NODE ; on ; - ; counter_writer[3] ;; PRESERVE_REGISTER ; on ; - ; counter_writer[2] ;; PRESERVE_FANOUT_FREE_NODE ; on ; - ; counter_writer[2] ;; PRESERVE_REGISTER ; on ; - ; counter_writer[1] ;; PRESERVE_FANOUT_FREE_NODE ; on ; - ; counter_writer[1] ;; PRESERVE_REGISTER ; on ; - ; counter_writer[0] ;; PRESERVE_FANOUT_FREE_NODE ; on ; - ; counter_writer[0] ;; PRESERVE_REGISTER ; on ; - ; counter_reader[5] ;; PRESERVE_FANOUT_FREE_NODE ; on ; - ; counter_reader[5] ;; PRESERVE_REGISTER ; on ; - ; counter_reader[4] ;; PRESERVE_FANOUT_FREE_NODE ; on ; - ; counter_reader[4] ;; PRESERVE_REGISTER ; on ; - ; counter_reader[3] ;; PRESERVE_FANOUT_FREE_NODE ; on ; - ; counter_reader[3] ;; PRESERVE_REGISTER ; on ; - ; counter_reader[2] ;; PRESERVE_FANOUT_FREE_NODE ; on ; - ; counter_reader[2] ;; PRESERVE_REGISTER ; on ; - ; counter_reader[1] ;; PRESERVE_FANOUT_FREE_NODE ; on ; - ; counter_reader[1] ;; PRESERVE_REGISTER ; on ; - ; counter_reader[0] ;; PRESERVE_FANOUT_FREE_NODE ; on ; - ; counter_reader[0] ;; PRESERVE_REGISTER ; on ; - ; rd_ptr[5] ;; PRESERVE_FANOUT_FREE_NODE ; on ; - ; rd_ptr[5] ;; PRESERVE_REGISTER ; on ; - ; rd_ptr[4] ;; PRESERVE_FANOUT_FREE_NODE ; on ; - ; rd_ptr[4] ;; PRESERVE_REGISTER ; on ; - ; rd_ptr[3] ;; PRESERVE_FANOUT_FREE_NODE ; on ; - ; rd_ptr[3] ;; PRESERVE_REGISTER ; on ; - ; rd_ptr[2] ;; PRESERVE_FANOUT_FREE_NODE ; on ; - ; rd_ptr[2] ;; PRESERVE_REGISTER ; on ; - ; rd_ptr[1] ;; PRESERVE_FANOUT_FREE_NODE ; on ; - ; rd_ptr[1] ;; PRESERVE_REGISTER ; on ; - ; rd_ptr[0] ;; PRESERVE_FANOUT_FREE_NODE ; on ; - ; rd_ptr[0] ;+---------------------------+-------+------+----------------------------++-------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_hps_0:hps_0 ;+----------------+-------+------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+------------------------------------------------------------+; F2S_Width ; 0 ; Signed Integer ;; S2F_Width ; 1 ; Signed Integer ;+----------------+-------+------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll ;+----------------------------+-----------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------------------+-----------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+; DEVICE_FAMILY ; Cyclone V ; String ;; IS_HHP_HPS ; true ; String ;; GENERIC_PLL ; true ; String ;; REF_CLK_FREQ ; 125.0 MHz ; String ;; REF_CLK_PERIOD_PS ; 8000 ; Signed Integer ;; PLL_MEM_CLK_FREQ_STR ; 300.0 MHz ; String ;; PLL_WRITE_CLK_FREQ_STR ; 300.0 MHz ; String ;; PLL_DR_CLK_FREQ_STR ; ; String ;; PLL_MEM_CLK_FREQ_SIM_STR ; 3334 ps ; String ;; PLL_WRITE_CLK_FREQ_SIM_STR ; 3334 ps ; String ;; PLL_DR_CLK_FREQ_SIM_STR ; 0 ps ; String ;; MEM_CLK_PHASE ; 0 ps ; String ;; WRITE_CLK_PHASE ; 2500 ps ; String ;; DR_CLK_PHASE ; ; String ;+----------------------------+-----------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0 ;+--------------------------------------+------------------+-------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+--------------------------------------+------------------+-------------------------------------------------------------------------------------------------------------------------------------------+; DEVICE_FAMILY ; Cyclone V ; String ;; IS_HHP_HPS ; true ; String ;; ALTERA_ALT_MEM_IF_PHY_FAST_SIM_MODEL ; 0 ; Signed Integer ;; OCT_TERM_CONTROL_WIDTH ; 16 ; Signed Integer ;; MEM_IF_ADDR_WIDTH ; 13 ; Signed Integer ;; MEM_IF_BANKADDR_WIDTH ; 3 ; Signed Integer ;; MEM_IF_CK_WIDTH ; 1 ; Signed Integer ;; MEM_IF_CLK_EN_WIDTH ; 1 ; Signed Integer ;; MEM_IF_CS_WIDTH ; 1 ; Signed Integer ;; MEM_IF_DM_WIDTH ; 1 ; Signed Integer ;; MEM_IF_CONTROL_WIDTH ; 1 ; Signed Integer ;; MEM_IF_DQ_WIDTH ; 8 ; Signed Integer ;; MEM_IF_DQS_WIDTH ; 1 ; Signed Integer ;; MEM_IF_READ_DQS_WIDTH ; 1 ; Signed Integer ;; MEM_IF_WRITE_DQS_WIDTH ; 1 ; Signed Integer ;; MEM_IF_ODT_WIDTH ; 1 ; Signed Integer ;; DLL_DELAY_CTRL_WIDTH ; 7 ; Signed Integer ;; SCC_DATA_WIDTH ; 1 ; Signed Integer ;; READ_VALID_FIFO_SIZE ; 16 ; Signed Integer ;; READ_FIFO_SIZE ; 8 ; Signed Integer ;; MR1_ODS ; 0 ; Signed Integer ;; MR1_RTT ; 0 ; Signed Integer ;; MR2_RTT_WR ; 0 ; Signed Integer ;; DLL_OFFSET_CTRL_WIDTH ; 6 ; Signed Integer ;; CALIB_REG_WIDTH ; 8 ; Signed Integer ;; TB_PROTOCOL ; DDR3 ; String ;; TB_MEM_CLK_FREQ ; 300.0 ; String ;; TB_RATE ; FULL ; String ;; TB_MEM_DQ_WIDTH ; 8 ; String ;; TB_MEM_DQS_WIDTH ; 1 ; String ;; TB_PLL_DLL_MASTER ; true ; String ;; FAST_SIM_CALIBRATION ; false ; String ;; AC_ROM_INIT_FILE_NAME ; hps_AC_ROM.hex ; String ;; INST_ROM_INIT_FILE_NAME ; hps_inst_ROM.hex ; String ;+--------------------------------------+------------------+-------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy ;+---------------------------------+------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+---------------------------------+------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; DEVICE_FAMILY ; Cyclone V ; String ;; IS_HHP_HPS ; true ; String ;; OCT_SERIES_TERM_CONTROL_WIDTH ; 16 ; Signed Integer ;; OCT_PARALLEL_TERM_CONTROL_WIDTH ; 16 ; Signed Integer ;; MEM_ADDRESS_WIDTH ; 13 ; Signed Integer ;; MEM_BANK_WIDTH ; 3 ; Signed Integer ;; MEM_IF_CS_WIDTH ; 1 ; Signed Integer ;; MEM_CLK_EN_WIDTH ; 1 ; Signed Integer ;; MEM_CK_WIDTH ; 1 ; Signed Integer ;; MEM_ODT_WIDTH ; 1 ; Signed Integer ;; MEM_DQS_WIDTH ; 1 ; Signed Integer ;; MEM_DM_WIDTH ; 1 ; Signed Integer ;; MEM_CONTROL_WIDTH ; 1 ; Signed Integer ;; MEM_DQ_WIDTH ; 8 ; Signed Integer ;; MEM_READ_DQS_WIDTH ; 1 ; Signed Integer ;; MEM_WRITE_DQS_WIDTH ; 1 ; Signed Integer ;; DLL_DELAY_CTRL_WIDTH ; 7 ; Signed Integer ;; MR1_ODS ; 0 ; Signed Integer ;; MR1_RTT ; 0 ; Signed Integer ;; MR2_RTT_WR ; 0 ; Signed Integer ;; TB_PROTOCOL ; DDR3 ; String ;; TB_MEM_CLK_FREQ ; 300.0 ; String ;; TB_RATE ; FULL ; String ;; TB_MEM_DQ_WIDTH ; 8 ; String ;; TB_MEM_DQS_WIDTH ; 1 ; String ;; TB_PLL_DLL_MASTER ; true ; String ;; FAST_SIM_MODEL ; 0 ; Signed Integer ;; FAST_SIM_CALIBRATION ; false ; String ;; CALIB_REG_WIDTH ; 8 ; Signed Integer ;; AC_ROM_INIT_FILE_NAME ; hps_AC_ROM.hex ; String ;; INST_ROM_INIT_FILE_NAME ; hps_inst_ROM.hex ; String ;+---------------------------------+------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_ldc:memphy_ldc ;+----------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; DLL_DELAY_CTRL_WIDTH ; 7 ; Signed Integer ;; ADC_PHASE_SETTING ; 0 ; Signed Integer ;; ADC_INVERT_PHASE ; true ; String ;; IS_HHP_HPS ; true ; String ;+----------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads ;+---------------------------------+-----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+---------------------------------+-----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; DEVICE_FAMILY ; Cyclone V ; String ;; FAST_SIM_MODEL ; 0 ; Signed Integer ;; OCT_SERIES_TERM_CONTROL_WIDTH ; 16 ; Signed Integer ;; OCT_PARALLEL_TERM_CONTROL_WIDTH ; 16 ; Signed Integer ;; MEM_ADDRESS_WIDTH ; 13 ; Signed Integer ;; MEM_BANK_WIDTH ; 3 ; Signed Integer ;; MEM_CHIP_SELECT_WIDTH ; 1 ; Signed Integer ;; MEM_CLK_EN_WIDTH ; 1 ; Signed Integer ;; MEM_CK_WIDTH ; 1 ; Signed Integer ;; MEM_ODT_WIDTH ; 1 ; Signed Integer ;; MEM_DQS_WIDTH ; 1 ; Signed Integer ;; MEM_DM_WIDTH ; 1 ; Signed Integer ;; MEM_CONTROL_WIDTH ; 1 ; Signed Integer ;; MEM_DQ_WIDTH ; 8 ; Signed Integer ;; MEM_READ_DQS_WIDTH ; 1 ; Signed Integer ;; MEM_WRITE_DQS_WIDTH ; 1 ; Signed Integer ;; DLL_DELAY_CTRL_WIDTH ; 7 ; Signed Integer ;; ADC_PHASE_SETTING ; 0 ; Signed Integer ;; ADC_INVERT_PHASE ; true ; String ;; IS_HHP_HPS ; true ; String ;+---------------------------------+-----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads ;+-----------------------+-----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+-----------------------+-----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; DEVICE_FAMILY ; Cyclone V ; String ;; MEM_ADDRESS_WIDTH ; 13 ; Signed Integer ;; MEM_BANK_WIDTH ; 3 ; Signed Integer ;; MEM_CHIP_SELECT_WIDTH ; 1 ; Signed Integer ;; MEM_CLK_EN_WIDTH ; 1 ; Signed Integer ;; MEM_CK_WIDTH ; 1 ; Signed Integer ;; MEM_ODT_WIDTH ; 1 ; Signed Integer ;; MEM_CONTROL_WIDTH ; 1 ; Signed Integer ;; AFI_ADDRESS_WIDTH ; 52 ; Signed Integer ;; AFI_BANK_WIDTH ; 12 ; Signed Integer ;; AFI_CHIP_SELECT_WIDTH ; 4 ; Signed Integer ;; AFI_CLK_EN_WIDTH ; 4 ; Signed Integer ;; AFI_ODT_WIDTH ; 4 ; Signed Integer ;; AFI_CONTROL_WIDTH ; 4 ; Signed Integer ;; DLL_WIDTH ; 7 ; Signed Integer ;; ADC_PHASE_SETTING ; 0 ; Signed Integer ;; ADC_INVERT_PHASE ; true ; String ;; IS_HHP_HPS ; true ; String ;+-----------------------+-----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|hps_sdram_p0_acv_ldc:address_gen[0].acv_ac_ldc ;+----------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; DLL_DELAY_CTRL_WIDTH ; 7 ; Signed Integer ;; ADC_PHASE_SETTING ; 0 ; Signed Integer ;; ADC_INVERT_PHASE ; true ; String ;; IS_HHP_HPS ; true ; String ;+----------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|hps_sdram_p0_acv_ldc:address_gen[1].acv_ac_ldc ;+----------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; DLL_DELAY_CTRL_WIDTH ; 7 ; Signed Integer ;; ADC_PHASE_SETTING ; 0 ; Signed Integer ;; ADC_INVERT_PHASE ; true ; String ;; IS_HHP_HPS ; true ; String ;+----------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|hps_sdram_p0_acv_ldc:address_gen[2].acv_ac_ldc ;+----------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; DLL_DELAY_CTRL_WIDTH ; 7 ; Signed Integer ;; ADC_PHASE_SETTING ; 0 ; Signed Integer ;; ADC_INVERT_PHASE ; true ; String ;; IS_HHP_HPS ; true ; String ;+----------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|hps_sdram_p0_acv_ldc:address_gen[3].acv_ac_ldc ;+----------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; DLL_DELAY_CTRL_WIDTH ; 7 ; Signed Integer ;; ADC_PHASE_SETTING ; 0 ; Signed Integer ;; ADC_INVERT_PHASE ; true ; String ;; IS_HHP_HPS ; true ; String ;+----------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|hps_sdram_p0_acv_ldc:address_gen[4].acv_ac_ldc ;+----------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; DLL_DELAY_CTRL_WIDTH ; 7 ; Signed Integer ;; ADC_PHASE_SETTING ; 0 ; Signed Integer ;; ADC_INVERT_PHASE ; true ; String ;; IS_HHP_HPS ; true ; String ;+----------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|hps_sdram_p0_acv_ldc:address_gen[5].acv_ac_ldc ;+----------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; DLL_DELAY_CTRL_WIDTH ; 7 ; Signed Integer ;; ADC_PHASE_SETTING ; 0 ; Signed Integer ;; ADC_INVERT_PHASE ; true ; String ;; IS_HHP_HPS ; true ; String ;+----------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|hps_sdram_p0_acv_ldc:address_gen[6].acv_ac_ldc ;+----------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; DLL_DELAY_CTRL_WIDTH ; 7 ; Signed Integer ;; ADC_PHASE_SETTING ; 0 ; Signed Integer ;; ADC_INVERT_PHASE ; true ; String ;; IS_HHP_HPS ; true ; String ;+----------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|hps_sdram_p0_acv_ldc:address_gen[7].acv_ac_ldc ;+----------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; DLL_DELAY_CTRL_WIDTH ; 7 ; Signed Integer ;; ADC_PHASE_SETTING ; 0 ; Signed Integer ;; ADC_INVERT_PHASE ; true ; String ;; IS_HHP_HPS ; true ; String ;+----------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|hps_sdram_p0_acv_ldc:address_gen[8].acv_ac_ldc ;+----------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; DLL_DELAY_CTRL_WIDTH ; 7 ; Signed Integer ;; ADC_PHASE_SETTING ; 0 ; Signed Integer ;; ADC_INVERT_PHASE ; true ; String ;; IS_HHP_HPS ; true ; String ;+----------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|hps_sdram_p0_acv_ldc:address_gen[9].acv_ac_ldc ;+----------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; DLL_DELAY_CTRL_WIDTH ; 7 ; Signed Integer ;; ADC_PHASE_SETTING ; 0 ; Signed Integer ;; ADC_INVERT_PHASE ; true ; String ;; IS_HHP_HPS ; true ; String ;+----------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|hps_sdram_p0_acv_ldc:address_gen[10].acv_ac_ldc ;+----------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; DLL_DELAY_CTRL_WIDTH ; 7 ; Signed Integer ;; ADC_PHASE_SETTING ; 0 ; Signed Integer ;; ADC_INVERT_PHASE ; true ; String ;; IS_HHP_HPS ; true ; String ;+----------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|hps_sdram_p0_acv_ldc:address_gen[11].acv_ac_ldc ;+----------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; DLL_DELAY_CTRL_WIDTH ; 7 ; Signed Integer ;; ADC_PHASE_SETTING ; 0 ; Signed Integer ;; ADC_INVERT_PHASE ; true ; String ;; IS_HHP_HPS ; true ; String ;+----------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|hps_sdram_p0_acv_ldc:address_gen[12].acv_ac_ldc ;+----------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; DLL_DELAY_CTRL_WIDTH ; 7 ; Signed Integer ;; ADC_PHASE_SETTING ; 0 ; Signed Integer ;; ADC_INVERT_PHASE ; true ; String ;; IS_HHP_HPS ; true ; String ;+----------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|hps_sdram_p0_acv_ldc:address_gen[13].acv_ac_ldc ;+----------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; DLL_DELAY_CTRL_WIDTH ; 7 ; Signed Integer ;; ADC_PHASE_SETTING ; 0 ; Signed Integer ;; ADC_INVERT_PHASE ; true ; String ;; IS_HHP_HPS ; true ; String ;+----------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|hps_sdram_p0_acv_ldc:address_gen[14].acv_ac_ldc ;+----------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; DLL_DELAY_CTRL_WIDTH ; 7 ; Signed Integer ;; ADC_PHASE_SETTING ; 0 ; Signed Integer ;; ADC_INVERT_PHASE ; true ; String ;; IS_HHP_HPS ; true ; String ;+----------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|hps_sdram_p0_acv_ldc:address_gen[15].acv_ac_ldc ;+----------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; DLL_DELAY_CTRL_WIDTH ; 7 ; Signed Integer ;; ADC_PHASE_SETTING ; 0 ; Signed Integer ;; ADC_INVERT_PHASE ; true ; String ;; IS_HHP_HPS ; true ; String ;+----------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|hps_sdram_p0_acv_ldc:address_gen[16].acv_ac_ldc ;+----------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; DLL_DELAY_CTRL_WIDTH ; 7 ; Signed Integer ;; ADC_PHASE_SETTING ; 0 ; Signed Integer ;; ADC_INVERT_PHASE ; true ; String ;; IS_HHP_HPS ; true ; String ;+----------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|hps_sdram_p0_acv_ldc:address_gen[17].acv_ac_ldc ;+----------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; DLL_DELAY_CTRL_WIDTH ; 7 ; Signed Integer ;; ADC_PHASE_SETTING ; 0 ; Signed Integer ;; ADC_INVERT_PHASE ; true ; String ;; IS_HHP_HPS ; true ; String ;+----------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|hps_sdram_p0_acv_ldc:address_gen[18].acv_ac_ldc ;+----------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; DLL_DELAY_CTRL_WIDTH ; 7 ; Signed Integer ;; ADC_PHASE_SETTING ; 0 ; Signed Integer ;; ADC_INVERT_PHASE ; true ; String ;; IS_HHP_HPS ; true ; String ;+----------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|hps_sdram_p0_acv_ldc:address_gen[19].acv_ac_ldc ;+----------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; DLL_DELAY_CTRL_WIDTH ; 7 ; Signed Integer ;; ADC_PHASE_SETTING ; 0 ; Signed Integer ;; ADC_INVERT_PHASE ; true ; String ;; IS_HHP_HPS ; true ; String ;+----------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|hps_sdram_p0_acv_ldc:address_gen[20].acv_ac_ldc ;+----------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; DLL_DELAY_CTRL_WIDTH ; 7 ; Signed Integer ;; ADC_PHASE_SETTING ; 0 ; Signed Integer ;; ADC_INVERT_PHASE ; true ; String ;; IS_HHP_HPS ; true ; String ;+----------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|hps_sdram_p0_acv_ldc:address_gen[21].acv_ac_ldc ;+----------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; DLL_DELAY_CTRL_WIDTH ; 7 ; Signed Integer ;; ADC_PHASE_SETTING ; 0 ; Signed Integer ;; ADC_INVERT_PHASE ; true ; String ;; IS_HHP_HPS ; true ; String ;+----------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|hps_sdram_p0_acv_ldc:address_gen[22].acv_ac_ldc ;+----------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; DLL_DELAY_CTRL_WIDTH ; 7 ; Signed Integer ;; ADC_PHASE_SETTING ; 0 ; Signed Integer ;; ADC_INVERT_PHASE ; true ; String ;; IS_HHP_HPS ; true ; String ;+----------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|hps_sdram_p0_generic_ddio:uaddress_pad ;+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 13 ; Signed Integer ;+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|hps_sdram_p0_generic_ddio:ubank_pad ;+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 3 ; Signed Integer ;+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|hps_sdram_p0_generic_ddio:ucmd_pad ;+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 6 ; Signed Integer ;+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|hps_sdram_p0_generic_ddio:ureset_n_pad ;+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 1 ; Signed Integer ;+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|altddio_out:clock_gen[0].umem_ck_pad ;+------------------------+--------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+------------------------+--------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ;; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;; WIDTH ; 1 ; Signed Integer ;; POWER_UP_HIGH ; OFF ; Untyped ;; OE_REG ; UNUSED ; Untyped ;; extend_oe_disable ; UNUSED ; Untyped ;; INTENDED_DEVICE_FAMILY ; Cyclone V ; Untyped ;; DEVICE_FAMILY ; Cyclone V ; Untyped ;; CBXI_PARAMETER ; ddio_out_uqe ; Untyped ;+------------------------+--------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_altdqdqs:dq_ddio[0].ubidir_dq_dqs ;+----------------------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; ALTERA_ALTDQ_DQS2_FAST_SIM_MODEL ; ; String ;+----------------------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_altdqdqs:dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_acv_connect_to_hard_phy_cyclonev:altdq_dqs2_inst ;+----------------------------------+---------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------------------------+---------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; PIN_WIDTH ; 8 ; Signed Integer ;; PIN_TYPE ; bidir ; String ;; USE_INPUT_PHASE_ALIGNMENT ; false ; String ;; USE_OUTPUT_PHASE_ALIGNMENT ; false ; String ;; USE_HALF_RATE_INPUT ; false ; String ;; USE_HALF_RATE_OUTPUT ; true ; String ;; DIFFERENTIAL_CAPTURE_STROBE ; true ; String ;; SEPARATE_CAPTURE_STROBE ; false ; String ;; INPUT_FREQ ; 300.0 ; Signed Float ;; INPUT_FREQ_PS ; 3333 ps ; String ;; DELAY_CHAIN_BUFFER_MODE ; high ; String ;; DQS_PHASE_SETTING ; 0 ; Signed Integer ;; DQS_PHASE_SHIFT ; 0 ; Signed Integer ;; DQS_ENABLE_PHASE_SETTING ; 3 ; Signed Integer ;; USE_DYNAMIC_CONFIG ; true ; String ;; INVERT_CAPTURE_STROBE ; true ; String ;; SWAP_CAPTURE_STROBE_POLARITY ; false ; String ;; USE_TERMINATION_CONTROL ; true ; String ;; USE_OCT_ENA_IN_FOR_OCT ; true ; String ;; USE_DQS_ENABLE ; true ; String ;; USE_IO_CONFIG ; false ; String ;; USE_DQS_CONFIG ; false ; String ;; USE_OFFSET_CTRL ; false ; String ;; HR_DDIO_OUT_HAS_THREE_REGS ; false ; String ;; USE_OUTPUT_STROBE ; true ; String ;; DIFFERENTIAL_OUTPUT_STROBE ; true ; String ;; USE_OUTPUT_STROBE_RESET ; false ; String ;; USE_BIDIR_STROBE ; true ; String ;; REVERSE_READ_WORDS ; false ; String ;; NATURAL_ALIGNMENT ; true ; String ;; EXTRA_OUTPUT_WIDTH ; 1 ; Signed Integer ;; PREAMBLE_TYPE ; high ; String ;; USE_DATA_OE_FOR_OCT ; false ; String ;; DQS_ENABLE_WIDTH ; 1 ; Signed Integer ;; EMIF_UNALIGNED_PREAMBLE_SUPPORT ; false ; String ;; EMIF_BYPASS_OCT_DDIO ; false ; String ;; USE_2X_FF ; false ; String ;; USE_DQS_TRACKING ; true ; String ;; SEPERATE_LDC_FOR_WRITE_STROBE ; false ; String ;; DQS_ENABLE_PHASECTRL ; true ; String ;; DYNAMIC_MODE ; dynamic ; String ;; OCT_SERIES_TERM_CONTROL_WIDTH ; 16 ; Signed Integer ;; OCT_PARALLEL_TERM_CONTROL_WIDTH ; 16 ; Signed Integer ;; DLL_WIDTH ; 7 ; Signed Integer ;; REGULAR_WRITE_BUS_ORDERING ; true ; String ;; ALTERA_ALTDQ_DQS2_FAST_SIM_MODEL ; 0 ; Signed Integer ;; USE_HARD_FIFOS ; true ; String ;; CALIBRATION_SUPPORT ; false ; String ;; USE_DQSIN_FOR_VFIFO_READ ; false ; String ;; HHP_HPS ; true ; String ;; USE_LDC_AS_LOW_SKEW_CLOCK ; false ; String ;; DLL_USE_2X_CLK ; false ; String ;; DQS_ENABLE_AFTER_T7 ; true ; String ;; LFIFO_OCT_EN_MASK ; -1 ; Signed Integer ;+----------------------------------+---------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|altera_mem_if_hhp_qseq_synth_top:seq ;+--------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+--------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; APB_DATA_WIDTH ; 32 ; Signed Integer ;; APB_ADDR_WIDTH ; 32 ; Signed Integer ;; AVL_DATA_WIDTH ; 32 ; Signed Integer ;; AVL_ADDR_WIDTH ; 16 ; Signed Integer ;; AVL_MMR_DATA_WIDTH ; 32 ; Signed Integer ;; AVL_MMR_ADDR_WIDTH ; 8 ; Signed Integer ;; MEM_IF_DQS_WIDTH ; 1 ; Signed Integer ;; MEM_IF_DQ_WIDTH ; 8 ; Signed Integer ;; MEM_IF_DM_WIDTH ; 1 ; Signed Integer ;; MEM_IF_CS_WIDTH ; 1 ; Signed Integer ;+--------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|altera_mem_if_hard_memory_controller_top_cyclonev:c0 ;+-----------------------------------------+------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+-----------------------------------------+------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------+; AVL_SIZE_WIDTH ; 3 ; Signed Integer ;; AVL_ADDR_WIDTH ; 22 ; Signed Integer ;; AVL_DATA_WIDTH ; 16 ; Signed Integer ;; MEM_IF_CLK_PAIR_COUNT ; 1 ; Signed Integer ;; MEM_IF_CS_WIDTH ; 1 ; Signed Integer ;; MEM_IF_DQS_WIDTH ; 1 ; Signed Integer ;; MEM_IF_CHIP_BITS ; 1 ; Signed Integer ;; AFI_ADDR_WIDTH ; 13 ; Signed Integer ;; AFI_BANKADDR_WIDTH ; 3 ; Signed Integer ;; AFI_CONTROL_WIDTH ; 1 ; Signed Integer ;; AFI_CS_WIDTH ; 1 ; Signed Integer ;; AFI_ODT_WIDTH ; 1 ; Signed Integer ;; AFI_DM_WIDTH ; 2 ; Signed Integer ;; AFI_DQ_WIDTH ; 16 ; Signed Integer ;; AFI_WRITE_DQS_WIDTH ; 1 ; Signed Integer ;; AFI_RATE_RATIO ; 1 ; Signed Integer ;; AFI_WLAT_WIDTH ; 6 ; Signed Integer ;; AFI_RLAT_WIDTH ; 6 ; Signed Integer ;; CSR_BE_WIDTH ; 1 ; Signed Integer ;; CSR_ADDR_WIDTH ; 10 ; Signed Integer ;; CSR_DATA_WIDTH ; 8 ; Signed Integer ;; AVL_DATA_WIDTH_PORT_0 ; 1 ; Signed Integer ;; AVL_DATA_WIDTH_PORT_1 ; 1 ; Signed Integer ;; AVL_DATA_WIDTH_PORT_2 ; 1 ; Signed Integer ;; AVL_DATA_WIDTH_PORT_3 ; 1 ; Signed Integer ;; AVL_DATA_WIDTH_PORT_4 ; 1 ; Signed Integer ;; AVL_DATA_WIDTH_PORT_5 ; 1 ; Signed Integer ;; AVL_ADDR_WIDTH_PORT_0 ; 1 ; Signed Integer ;; AVL_ADDR_WIDTH_PORT_1 ; 1 ; Signed Integer ;; AVL_ADDR_WIDTH_PORT_2 ; 1 ; Signed Integer ;; AVL_ADDR_WIDTH_PORT_3 ; 1 ; Signed Integer ;; AVL_ADDR_WIDTH_PORT_4 ; 1 ; Signed Integer ;; AVL_ADDR_WIDTH_PORT_5 ; 1 ; Signed Integer ;; AVL_NUM_SYMBOLS_PORT_0 ; 1 ; Signed Integer ;; AVL_NUM_SYMBOLS_PORT_1 ; 1 ; Signed Integer ;; AVL_NUM_SYMBOLS_PORT_2 ; 1 ; Signed Integer ;; AVL_NUM_SYMBOLS_PORT_3 ; 1 ; Signed Integer ;; AVL_NUM_SYMBOLS_PORT_4 ; 1 ; Signed Integer ;; AVL_NUM_SYMBOLS_PORT_5 ; 1 ; Signed Integer ;; LSB_WFIFO_PORT_0 ; 5 ; Signed Integer ;; MSB_WFIFO_PORT_0 ; 5 ; Signed Integer ;; LSB_RFIFO_PORT_0 ; 5 ; Signed Integer ;; MSB_RFIFO_PORT_0 ; 5 ; Signed Integer ;; LSB_WFIFO_PORT_1 ; 5 ; Signed Integer ;; MSB_WFIFO_PORT_1 ; 5 ; Signed Integer ;; LSB_RFIFO_PORT_1 ; 5 ; Signed Integer ;; MSB_RFIFO_PORT_1 ; 5 ; Signed Integer ;; LSB_WFIFO_PORT_2 ; 5 ; Signed Integer ;; MSB_WFIFO_PORT_2 ; 5 ; Signed Integer ;; LSB_RFIFO_PORT_2 ; 5 ; Signed Integer ;; MSB_RFIFO_PORT_2 ; 5 ; Signed Integer ;; LSB_WFIFO_PORT_3 ; 5 ; Signed Integer ;; MSB_WFIFO_PORT_3 ; 5 ; Signed Integer ;; LSB_RFIFO_PORT_3 ; 5 ; Signed Integer ;; MSB_RFIFO_PORT_3 ; 5 ; Signed Integer ;; LSB_WFIFO_PORT_4 ; 5 ; Signed Integer ;; MSB_WFIFO_PORT_4 ; 5 ; Signed Integer ;; LSB_RFIFO_PORT_4 ; 5 ; Signed Integer ;; MSB_RFIFO_PORT_4 ; 5 ; Signed Integer ;; LSB_WFIFO_PORT_5 ; 5 ; Signed Integer ;; MSB_WFIFO_PORT_5 ; 5 ; Signed Integer ;; LSB_RFIFO_PORT_5 ; 5 ; Signed Integer ;; MSB_RFIFO_PORT_5 ; 5 ; Signed Integer ;; HARD_PHY ; 1 ; Signed Integer ;; ENUM_ATTR_COUNTER_ONE_RESET ; DISABLED ; String ;; ENUM_ATTR_COUNTER_ZERO_RESET ; DISABLED ; String ;; ENUM_ATTR_STATIC_CONFIG_VALID ; DISABLED ; String ;; ENUM_AUTO_PCH_ENABLE_0 ; DISABLED ; String ;; ENUM_AUTO_PCH_ENABLE_1 ; DISABLED ; String ;; ENUM_AUTO_PCH_ENABLE_2 ; DISABLED ; String ;; ENUM_AUTO_PCH_ENABLE_3 ; DISABLED ; String ;; ENUM_AUTO_PCH_ENABLE_4 ; DISABLED ; String ;; ENUM_AUTO_PCH_ENABLE_5 ; DISABLED ; String ;; ENUM_CAL_REQ ; DISABLED ; String ;; ENUM_CFG_BURST_LENGTH ; BL_8 ; String ;; ENUM_CFG_INTERFACE_WIDTH ; DWIDTH_8 ; String ;; ENUM_CFG_SELF_RFSH_EXIT_CYCLES ; SELF_RFSH_EXIT_CYCLES_512 ; String ;; ENUM_CFG_STARVE_LIMIT ; STARVE_LIMIT_10 ; String ;; ENUM_CFG_TYPE ; DDR3 ; String ;; ENUM_CLOCK_OFF_0 ; DISABLED ; String ;; ENUM_CLOCK_OFF_1 ; DISABLED ; String ;; ENUM_CLOCK_OFF_2 ; DISABLED ; String ;; ENUM_CLOCK_OFF_3 ; DISABLED ; String ;; ENUM_CLOCK_OFF_4 ; DISABLED ; String ;; ENUM_CLOCK_OFF_5 ; DISABLED ; String ;; ENUM_CLR_INTR ; NO_CLR_INTR ; String ;; ENUM_CMD_PORT_IN_USE_0 ; FALSE ; String ;; ENUM_CMD_PORT_IN_USE_1 ; FALSE ; String ;; ENUM_CMD_PORT_IN_USE_2 ; FALSE ; String ;; ENUM_CMD_PORT_IN_USE_3 ; FALSE ; String ;; ENUM_CMD_PORT_IN_USE_4 ; FALSE ; String ;; ENUM_CMD_PORT_IN_USE_5 ; FALSE ; String ;; ENUM_CPORT0_RDY_ALMOST_FULL ; NOT_FULL ; String ;; ENUM_CPORT0_RFIFO_MAP ; FIFO_0 ; String ;; ENUM_CPORT0_TYPE ; DISABLE ; String ;; ENUM_CPORT0_WFIFO_MAP ; FIFO_0 ; String ;; ENUM_CPORT1_RDY_ALMOST_FULL ; NOT_FULL ; String ;; ENUM_CPORT1_RFIFO_MAP ; FIFO_0 ; String ;; ENUM_CPORT1_TYPE ; DISABLE ; String ;; ENUM_CPORT1_WFIFO_MAP ; FIFO_0 ; String ;; ENUM_CPORT2_RDY_ALMOST_FULL ; NOT_FULL ; String ;; ENUM_CPORT2_RFIFO_MAP ; FIFO_0 ; String ;; ENUM_CPORT2_TYPE ; DISABLE ; String ;; ENUM_CPORT2_WFIFO_MAP ; FIFO_0 ; String ;; ENUM_CPORT3_RDY_ALMOST_FULL ; NOT_FULL ; String ;; ENUM_CPORT3_RFIFO_MAP ; FIFO_0 ; String ;; ENUM_CPORT3_TYPE ; DISABLE ; String ;; ENUM_CPORT3_WFIFO_MAP ; FIFO_0 ; String ;; ENUM_CPORT4_RDY_ALMOST_FULL ; NOT_FULL ; String ;; ENUM_CPORT4_RFIFO_MAP ; FIFO_0 ; String ;; ENUM_CPORT4_TYPE ; DISABLE ; String ;; ENUM_CPORT4_WFIFO_MAP ; FIFO_0 ; String ;; ENUM_CPORT5_RDY_ALMOST_FULL ; NOT_FULL ; String ;; ENUM_CPORT5_RFIFO_MAP ; FIFO_0 ; String ;; ENUM_CPORT5_TYPE ; DISABLE ; String ;; ENUM_CPORT5_WFIFO_MAP ; FIFO_0 ; String ;; ENUM_CTL_ADDR_ORDER ; CHIP_ROW_BANK_COL ; String ;; ENUM_CTL_ECC_ENABLED ; CTL_ECC_DISABLED ; String ;; ENUM_CTL_ECC_RMW_ENABLED ; CTL_ECC_RMW_DISABLED ; String ;; ENUM_CTL_REGDIMM_ENABLED ; REGDIMM_DISABLED ; String ;; ENUM_CTL_USR_REFRESH ; CTL_USR_REFRESH_DISABLED ; String ;; ENUM_CTRL_WIDTH ; DATA_WIDTH_16_BIT ; String ;; ENUM_DELAY_BONDING ; BONDING_LATENCY_0 ; String ;; ENUM_DFX_BYPASS_ENABLE ; DFX_BYPASS_DISABLED ; String ;; ENUM_DISABLE_MERGING ; MERGING_ENABLED ; String ;; ENUM_ECC_DQ_WIDTH ; ECC_DQ_WIDTH_0 ; String ;; ENUM_ENABLE_ATPG ; DISABLED ; String ;; ENUM_ENABLE_BONDING_0 ; DISABLED ; String ;; ENUM_ENABLE_BONDING_1 ; DISABLED ; String ;; ENUM_ENABLE_BONDING_2 ; DISABLED ; String ;; ENUM_ENABLE_BONDING_3 ; DISABLED ; String ;; ENUM_ENABLE_BONDING_4 ; DISABLED ; String ;; ENUM_ENABLE_BONDING_5 ; DISABLED ; String ;; ENUM_ENABLE_BONDING_WRAPBACK ; DISABLED ; String ;; ENUM_ENABLE_DQS_TRACKING ; ENABLED ; String ;; ENUM_ENABLE_ECC_CODE_OVERWRITES ; DISABLED ; String ;; ENUM_ENABLE_FAST_EXIT_PPD ; DISABLED ; String ;; ENUM_ENABLE_INTR ; DISABLED ; String ;; ENUM_ENABLE_NO_DM ; DISABLED ; String ;; ENUM_ENABLE_PIPELINEGLOBAL ; DISABLED ; String ;; ENUM_GANGED_ARF ; DISABLED ; String ;; ENUM_GEN_DBE ; GEN_DBE_DISABLED ; String ;; ENUM_GEN_SBE ; GEN_SBE_DISABLED ; String ;; ENUM_INC_SYNC ; FIFO_SET_2 ; String ;; ENUM_LOCAL_IF_CS_WIDTH ; ADDR_WIDTH_0 ; String ;; ENUM_MASK_CORR_DROPPED_INTR ; DISABLED ; String ;; ENUM_MASK_DBE_INTR ; DISABLED ; String ;; ENUM_MASK_SBE_INTR ; DISABLED ; String ;; ENUM_MEM_IF_AL ; AL_0 ; String ;; ENUM_MEM_IF_BANKADDR_WIDTH ; ADDR_WIDTH_3 ; String ;; ENUM_MEM_IF_BURSTLENGTH ; MEM_IF_BURSTLENGTH_8 ; String ;; ENUM_MEM_IF_COLADDR_WIDTH ; ADDR_WIDTH_8 ; String ;; ENUM_MEM_IF_CS_PER_RANK ; MEM_IF_CS_PER_RANK_1 ; String ;; ENUM_MEM_IF_CS_WIDTH ; MEM_IF_CS_WIDTH_1 ; String ;; ENUM_MEM_IF_DQ_PER_CHIP ; MEM_IF_DQ_PER_CHIP_8 ; String ;; ENUM_MEM_IF_DQS_WIDTH ; DQS_WIDTH_1 ; String ;; ENUM_MEM_IF_DWIDTH ; MEM_IF_DWIDTH_8 ; String ;; ENUM_MEM_IF_MEMTYPE ; DDR3_SDRAM ; String ;; ENUM_MEM_IF_ROWADDR_WIDTH ; ADDR_WIDTH_12 ; String ;; ENUM_MEM_IF_SPEEDBIN ; DDR3_800_5_5_5 ; String ;; ENUM_MEM_IF_TCCD ; TCCD_4 ; String ;; ENUM_MEM_IF_TCL ; TCL_7 ; String ;; ENUM_MEM_IF_TCWL ; TCWL_6 ; String ;; ENUM_MEM_IF_TFAW ; TFAW_12 ; String ;; ENUM_MEM_IF_TMRD ; TMRD_4 ; String ;; ENUM_MEM_IF_TRAS ; TRAS_13 ; String ;; ENUM_MEM_IF_TRC ; TRC_17 ; String ;; ENUM_MEM_IF_TRCD ; TRCD_5 ; String ;; ENUM_MEM_IF_TRP ; TRP_5 ; String ;; ENUM_MEM_IF_TRRD ; TRRD_3 ; String ;; ENUM_MEM_IF_TRTP ; TRTP_3 ; String ;; ENUM_MEM_IF_TWR ; TWR_5 ; String ;; ENUM_MEM_IF_TWTR ; TWTR_2 ; String ;; ENUM_MMR_CFG_MEM_BL ; MP_BL_8 ; String ;; ENUM_OUTPUT_REGD ; DISABLED ; String ;; ENUM_PDN_EXIT_CYCLES ; SLOW_EXIT ; String ;; ENUM_PORT0_WIDTH ; PORT_32_BIT ; String ;; ENUM_PORT1_WIDTH ; PORT_32_BIT ; String ;; ENUM_PORT2_WIDTH ; PORT_32_BIT ; String ;; ENUM_PORT3_WIDTH ; PORT_32_BIT ; String ;; ENUM_PORT4_WIDTH ; PORT_32_BIT ; String ;; ENUM_PORT5_WIDTH ; PORT_32_BIT ; String ;; ENUM_PRIORITY_0_0 ; WEIGHT_0 ; String ;; ENUM_PRIORITY_0_1 ; WEIGHT_0 ; String ;; ENUM_PRIORITY_0_2 ; WEIGHT_0 ; String ;; ENUM_PRIORITY_0_3 ; WEIGHT_0 ; String ;; ENUM_PRIORITY_0_4 ; WEIGHT_0 ; String ;; ENUM_PRIORITY_0_5 ; WEIGHT_0 ; String ;; ENUM_PRIORITY_1_0 ; WEIGHT_0 ; String ;; ENUM_PRIORITY_1_1 ; WEIGHT_0 ; String ;; ENUM_PRIORITY_1_2 ; WEIGHT_0 ; String ;; ENUM_PRIORITY_1_3 ; WEIGHT_0 ; String ;; ENUM_PRIORITY_1_4 ; WEIGHT_0 ; String ;; ENUM_PRIORITY_1_5 ; WEIGHT_0 ; String ;; ENUM_PRIORITY_2_0 ; WEIGHT_0 ; String ;; ENUM_PRIORITY_2_1 ; WEIGHT_0 ; String ;; ENUM_PRIORITY_2_2 ; WEIGHT_0 ; String ;; ENUM_PRIORITY_2_3 ; WEIGHT_0 ; String ;; ENUM_PRIORITY_2_4 ; WEIGHT_0 ; String ;; ENUM_PRIORITY_2_5 ; WEIGHT_0 ; String ;; ENUM_PRIORITY_3_0 ; WEIGHT_0 ; String ;; ENUM_PRIORITY_3_1 ; WEIGHT_0 ; String ;; ENUM_PRIORITY_3_2 ; WEIGHT_0 ; String ;; ENUM_PRIORITY_3_3 ; WEIGHT_0 ; String ;; ENUM_PRIORITY_3_4 ; WEIGHT_0 ; String ;; ENUM_PRIORITY_3_5 ; WEIGHT_0 ; String ;; ENUM_PRIORITY_4_0 ; WEIGHT_0 ; String ;; ENUM_PRIORITY_4_1 ; WEIGHT_0 ; String ;; ENUM_PRIORITY_4_2 ; WEIGHT_0 ; String ;; ENUM_PRIORITY_4_3 ; WEIGHT_0 ; String ;; ENUM_PRIORITY_4_4 ; WEIGHT_0 ; String ;; ENUM_PRIORITY_4_5 ; WEIGHT_0 ; String ;; ENUM_PRIORITY_5_0 ; WEIGHT_0 ; String ;; ENUM_PRIORITY_5_1 ; WEIGHT_0 ; String ;; ENUM_PRIORITY_5_2 ; WEIGHT_0 ; String ;; ENUM_PRIORITY_5_3 ; WEIGHT_0 ; String ;; ENUM_PRIORITY_5_4 ; WEIGHT_0 ; String ;; ENUM_PRIORITY_5_5 ; WEIGHT_0 ; String ;; ENUM_PRIORITY_6_0 ; WEIGHT_0 ; String ;; ENUM_PRIORITY_6_1 ; WEIGHT_0 ; String ;; ENUM_PRIORITY_6_2 ; WEIGHT_0 ; String ;; ENUM_PRIORITY_6_3 ; WEIGHT_0 ; String ;; ENUM_PRIORITY_6_4 ; WEIGHT_0 ; String ;; ENUM_PRIORITY_6_5 ; WEIGHT_0 ; String ;; ENUM_PRIORITY_7_0 ; WEIGHT_0 ; String ;; ENUM_PRIORITY_7_1 ; WEIGHT_0 ; String ;; ENUM_PRIORITY_7_2 ; WEIGHT_0 ; String ;; ENUM_PRIORITY_7_3 ; WEIGHT_0 ; String ;; ENUM_PRIORITY_7_4 ; WEIGHT_0 ; String ;; ENUM_PRIORITY_7_5 ; WEIGHT_0 ; String ;; ENUM_RCFG_STATIC_WEIGHT_0 ; WEIGHT_0 ; String ;; ENUM_RCFG_STATIC_WEIGHT_1 ; WEIGHT_0 ; String ;; ENUM_RCFG_STATIC_WEIGHT_2 ; WEIGHT_0 ; String ;; ENUM_RCFG_STATIC_WEIGHT_3 ; WEIGHT_0 ; String ;; ENUM_RCFG_STATIC_WEIGHT_4 ; WEIGHT_0 ; String ;; ENUM_RCFG_STATIC_WEIGHT_5 ; WEIGHT_0 ; String ;; ENUM_RCFG_USER_PRIORITY_0 ; PRIORITY_1 ; String ;; ENUM_RCFG_USER_PRIORITY_1 ; PRIORITY_1 ; String ;; ENUM_RCFG_USER_PRIORITY_2 ; PRIORITY_1 ; String ;; ENUM_RCFG_USER_PRIORITY_3 ; PRIORITY_1 ; String ;; ENUM_RCFG_USER_PRIORITY_4 ; PRIORITY_1 ; String ;; ENUM_RCFG_USER_PRIORITY_5 ; PRIORITY_1 ; String ;; ENUM_RD_DWIDTH_0 ; DWIDTH_0 ; String ;; ENUM_RD_DWIDTH_1 ; DWIDTH_0 ; String ;; ENUM_RD_DWIDTH_2 ; DWIDTH_0 ; String ;; ENUM_RD_DWIDTH_3 ; DWIDTH_0 ; String ;; ENUM_RD_DWIDTH_4 ; DWIDTH_0 ; String ;; ENUM_RD_DWIDTH_5 ; DWIDTH_0 ; String ;; ENUM_RD_FIFO_IN_USE_0 ; FALSE ; String ;; ENUM_RD_FIFO_IN_USE_1 ; FALSE ; String ;; ENUM_RD_FIFO_IN_USE_2 ; FALSE ; String ;; ENUM_RD_FIFO_IN_USE_3 ; FALSE ; String ;; ENUM_RD_PORT_INFO_0 ; USE_NO ; String ;; ENUM_RD_PORT_INFO_1 ; USE_NO ; String ;; ENUM_RD_PORT_INFO_2 ; USE_NO ; String ;; ENUM_RD_PORT_INFO_3 ; USE_NO ; String ;; ENUM_RD_PORT_INFO_4 ; USE_NO ; String ;; ENUM_RD_PORT_INFO_5 ; USE_NO ; String ;; ENUM_READ_ODT_CHIP ; ODT_DISABLED ; String ;; ENUM_REORDER_DATA ; DATA_REORDERING ; String ;; ENUM_RFIFO0_CPORT_MAP ; CMD_PORT_0 ; String ;; ENUM_RFIFO1_CPORT_MAP ; CMD_PORT_0 ; String ;; ENUM_RFIFO2_CPORT_MAP ; CMD_PORT_0 ; String ;; ENUM_RFIFO3_CPORT_MAP ; CMD_PORT_0 ; String ;; ENUM_SINGLE_READY_0 ; CONCATENATE_RDY ; String ;; ENUM_SINGLE_READY_1 ; CONCATENATE_RDY ; String ;; ENUM_SINGLE_READY_2 ; CONCATENATE_RDY ; String ;; ENUM_SINGLE_READY_3 ; CONCATENATE_RDY ; String ;; ENUM_STATIC_WEIGHT_0 ; WEIGHT_0 ; String ;; ENUM_STATIC_WEIGHT_1 ; WEIGHT_0 ; String ;; ENUM_STATIC_WEIGHT_2 ; WEIGHT_0 ; String ;; ENUM_STATIC_WEIGHT_3 ; WEIGHT_0 ; String ;; ENUM_STATIC_WEIGHT_4 ; WEIGHT_0 ; String ;; ENUM_STATIC_WEIGHT_5 ; WEIGHT_0 ; String ;; ENUM_SYNC_MODE_0 ; ASYNCHRONOUS ; String ;; ENUM_SYNC_MODE_1 ; ASYNCHRONOUS ; String ;; ENUM_SYNC_MODE_2 ; ASYNCHRONOUS ; String ;; ENUM_SYNC_MODE_3 ; ASYNCHRONOUS ; String ;; ENUM_SYNC_MODE_4 ; ASYNCHRONOUS ; String ;; ENUM_SYNC_MODE_5 ; ASYNCHRONOUS ; String ;; ENUM_TEST_MODE ; NORMAL_MODE ; String ;; ENUM_THLD_JAR1_0 ; THRESHOLD_32 ; String ;; ENUM_THLD_JAR1_1 ; THRESHOLD_32 ; String ;; ENUM_THLD_JAR1_2 ; THRESHOLD_32 ; String ;; ENUM_THLD_JAR1_3 ; THRESHOLD_32 ; String ;; ENUM_THLD_JAR1_4 ; THRESHOLD_32 ; String ;; ENUM_THLD_JAR1_5 ; THRESHOLD_32 ; String ;; ENUM_THLD_JAR2_0 ; THRESHOLD_16 ; String ;; ENUM_THLD_JAR2_1 ; THRESHOLD_16 ; String ;; ENUM_THLD_JAR2_2 ; THRESHOLD_16 ; String ;; ENUM_THLD_JAR2_3 ; THRESHOLD_16 ; String ;; ENUM_THLD_JAR2_4 ; THRESHOLD_16 ; String ;; ENUM_THLD_JAR2_5 ; THRESHOLD_16 ; String ;; ENUM_USE_ALMOST_EMPTY_0 ; EMPTY ; String ;; ENUM_USE_ALMOST_EMPTY_1 ; EMPTY ; String ;; ENUM_USE_ALMOST_EMPTY_2 ; EMPTY ; String ;; ENUM_USE_ALMOST_EMPTY_3 ; EMPTY ; String ;; ENUM_USER_ECC_EN ; DISABLE ; String ;; ENUM_USER_PRIORITY_0 ; PRIORITY_1 ; String ;; ENUM_USER_PRIORITY_1 ; PRIORITY_1 ; String ;; ENUM_USER_PRIORITY_2 ; PRIORITY_1 ; String ;; ENUM_USER_PRIORITY_3 ; PRIORITY_1 ; String ;; ENUM_USER_PRIORITY_4 ; PRIORITY_1 ; String ;; ENUM_USER_PRIORITY_5 ; PRIORITY_1 ; String ;; ENUM_WFIFO0_CPORT_MAP ; CMD_PORT_0 ; String ;; ENUM_WFIFO0_RDY_ALMOST_FULL ; NOT_FULL ; String ;; ENUM_WFIFO1_CPORT_MAP ; CMD_PORT_0 ; String ;; ENUM_WFIFO1_RDY_ALMOST_FULL ; NOT_FULL ; String ;; ENUM_WFIFO2_CPORT_MAP ; CMD_PORT_0 ; String ;; ENUM_WFIFO2_RDY_ALMOST_FULL ; NOT_FULL ; String ;; ENUM_WFIFO3_CPORT_MAP ; CMD_PORT_0 ; String ;; ENUM_WFIFO3_RDY_ALMOST_FULL ; NOT_FULL ; String ;; ENUM_WR_DWIDTH_0 ; DWIDTH_0 ; String ;; ENUM_WR_DWIDTH_1 ; DWIDTH_0 ; String ;; ENUM_WR_DWIDTH_2 ; DWIDTH_0 ; String ;; ENUM_WR_DWIDTH_3 ; DWIDTH_0 ; String ;; ENUM_WR_DWIDTH_4 ; DWIDTH_0 ; String ;; ENUM_WR_DWIDTH_5 ; DWIDTH_0 ; String ;; ENUM_WR_FIFO_IN_USE_0 ; FALSE ; String ;; ENUM_WR_FIFO_IN_USE_1 ; FALSE ; String ;; ENUM_WR_FIFO_IN_USE_2 ; FALSE ; String ;; ENUM_WR_FIFO_IN_USE_3 ; FALSE ; String ;; ENUM_WR_PORT_INFO_0 ; USE_NO ; String ;; ENUM_WR_PORT_INFO_1 ; USE_NO ; String ;; ENUM_WR_PORT_INFO_2 ; USE_NO ; String ;; ENUM_WR_PORT_INFO_3 ; USE_NO ; String ;; ENUM_WR_PORT_INFO_4 ; USE_NO ; String ;; ENUM_WR_PORT_INFO_5 ; USE_NO ; String ;; ENUM_WRITE_ODT_CHIP ; ODT_DISABLED ; String ;; ENUM_ENABLE_BURST_INTERRUPT ; DISABLED ; String ;; ENUM_ENABLE_BURST_TERMINATE ; DISABLED ; String ;; INTG_POWER_SAVING_EXIT_CYCLES ; 5 ; Signed Integer ;; INTG_MEM_CLK_ENTRY_CYCLES ; 10 ; Signed Integer ;; INTG_PRIORITY_REMAP ; 0 ; Signed Integer ;; INTG_MEM_AUTO_PD_CYCLES ; 0 ; Signed Integer ;; INTG_CYC_TO_RLD_JARS_0 ; 1 ; Signed Integer ;; INTG_CYC_TO_RLD_JARS_1 ; 1 ; Signed Integer ;; INTG_CYC_TO_RLD_JARS_2 ; 1 ; Signed Integer ;; INTG_CYC_TO_RLD_JARS_3 ; 1 ; Signed Integer ;; INTG_CYC_TO_RLD_JARS_4 ; 1 ; Signed Integer ;; INTG_CYC_TO_RLD_JARS_5 ; 1 ; Signed Integer ;; INTG_EXTRA_CTL_CLK_ACT_TO_ACT ; 0 ; Signed Integer ;; INTG_EXTRA_CTL_CLK_ACT_TO_ACT_DIFF_BANK ; 0 ; Signed Integer ;; INTG_EXTRA_CTL_CLK_ACT_TO_PCH ; 0 ; Signed Integer ;; INTG_EXTRA_CTL_CLK_ACT_TO_RDWR ; 0 ; Signed Integer ;; INTG_EXTRA_CTL_CLK_ARF_PERIOD ; 0 ; Signed Integer ;; INTG_EXTRA_CTL_CLK_ARF_TO_VALID ; 0 ; Signed Integer ;; INTG_EXTRA_CTL_CLK_FOUR_ACT_TO_ACT ; 0 ; Signed Integer ;; INTG_EXTRA_CTL_CLK_PCH_ALL_TO_VALID ; 0 ; Signed Integer ;; INTG_EXTRA_CTL_CLK_PCH_TO_VALID ; 0 ; Signed Integer ;; INTG_EXTRA_CTL_CLK_PDN_PERIOD ; 0 ; Signed Integer ;; INTG_EXTRA_CTL_CLK_PDN_TO_VALID ; 0 ; Signed Integer ;; INTG_EXTRA_CTL_CLK_RD_AP_TO_VALID ; 0 ; Signed Integer ;; INTG_EXTRA_CTL_CLK_RD_TO_PCH ; 0 ; Signed Integer ;; INTG_EXTRA_CTL_CLK_RD_TO_RD ; 0 ; Signed Integer ;; INTG_EXTRA_CTL_CLK_RD_TO_RD_DIFF_CHIP ; 0 ; Signed Integer ;; INTG_EXTRA_CTL_CLK_RD_TO_WR ; 2 ; Signed Integer ;; INTG_EXTRA_CTL_CLK_RD_TO_WR_BC ; 2 ; Signed Integer ;; INTG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP ; 2 ; Signed Integer ;; INTG_EXTRA_CTL_CLK_SRF_TO_VALID ; 0 ; Signed Integer ;; INTG_EXTRA_CTL_CLK_SRF_TO_ZQ_CAL ; 0 ; Signed Integer ;; INTG_EXTRA_CTL_CLK_WR_AP_TO_VALID ; 0 ; Signed Integer ;; INTG_EXTRA_CTL_CLK_WR_TO_PCH ; 0 ; Signed Integer ;; INTG_EXTRA_CTL_CLK_WR_TO_RD ; 3 ; Signed Integer ;; INTG_EXTRA_CTL_CLK_WR_TO_RD_BC ; 3 ; Signed Integer ;; INTG_EXTRA_CTL_CLK_WR_TO_RD_DIFF_CHIP ; 3 ; Signed Integer ;; INTG_EXTRA_CTL_CLK_WR_TO_WR ; 0 ; Signed Integer ;; INTG_EXTRA_CTL_CLK_WR_TO_WR_DIFF_CHIP ; 0 ; Signed Integer ;; INTG_MEM_IF_TREFI ; 2101 ; Signed Integer ;; INTG_MEM_IF_TRFC ; 23 ; Signed Integer ;; INTG_RCFG_SUM_WT_PRIORITY_0 ; 0 ; Signed Integer ;; INTG_RCFG_SUM_WT_PRIORITY_1 ; 0 ; Signed Integer ;; INTG_RCFG_SUM_WT_PRIORITY_2 ; 0 ; Signed Integer ;; INTG_RCFG_SUM_WT_PRIORITY_3 ; 0 ; Signed Integer ;; INTG_RCFG_SUM_WT_PRIORITY_4 ; 0 ; Signed Integer ;; INTG_RCFG_SUM_WT_PRIORITY_5 ; 0 ; Signed Integer ;; INTG_RCFG_SUM_WT_PRIORITY_6 ; 0 ; Signed Integer ;; INTG_RCFG_SUM_WT_PRIORITY_7 ; 0 ; Signed Integer ;; INTG_SUM_WT_PRIORITY_0 ; 0 ; Signed Integer ;; INTG_SUM_WT_PRIORITY_1 ; 0 ; Signed Integer ;; INTG_SUM_WT_PRIORITY_2 ; 0 ; Signed Integer ;; INTG_SUM_WT_PRIORITY_3 ; 0 ; Signed Integer ;; INTG_SUM_WT_PRIORITY_4 ; 0 ; Signed Integer ;; INTG_SUM_WT_PRIORITY_5 ; 0 ; Signed Integer ;; INTG_SUM_WT_PRIORITY_6 ; 0 ; Signed Integer ;; INTG_SUM_WT_PRIORITY_7 ; 0 ; Signed Integer ;; VECT_ATTR_COUNTER_ONE_MASK ; 0000000000000000000000000000000000000000000000000000000000000000 ; Unsigned Binary ;; VECT_ATTR_COUNTER_ONE_MATCH ; 0000000000000000000000000000000000000000000000000000000000000000 ; Unsigned Binary ;; VECT_ATTR_COUNTER_ZERO_MASK ; 0000000000000000000000000000000000000000000000000000000000000000 ; Unsigned Binary ;; VECT_ATTR_COUNTER_ZERO_MATCH ; 0000000000000000000000000000000000000000000000000000000000000000 ; Unsigned Binary ;; VECT_ATTR_DEBUG_SELECT_BYTE ; 00000000000000000000000000000000 ; Unsigned Binary ;+-----------------------------------------+------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|altera_mem_if_oct_cyclonev:oct ;+------------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+------------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; OCT_TERM_CONTROL_WIDTH ; 16 ; Signed Integer ;+------------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|altera_mem_if_dll_cyclonev:dll ;+----------------------------+---------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------------------+---------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; DLL_DELAY_CTRL_WIDTH ; 7 ; Signed Integer ;; DELAY_BUFFER_MODE ; HIGH ; String ;; DELAY_CHAIN_LENGTH ; 8 ; Signed Integer ;; DLL_INPUT_FREQUENCY_PS_STR ; 3333 ps ; String ;; DLL_OFFSET_CTRL_WIDTH ; 6 ; Signed Integer ;+----------------------------+---------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+-------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i ;+--------------------------------------+------------------------+---------------------------------------------+; Parameter Name ; Value ; Type ;+--------------------------------------+------------------------+---------------------------------------------+; reference_clock_frequency ; 50.0 MHz ; String ;; fractional_vco_multiplier ; false ; String ;; pll_type ; Cyclone V ; String ;; pll_subtype ; General ; String ;; number_of_clocks ; 1 ; Signed Integer ;; operation_mode ; normal ; String ;; deserialization_factor ; 4 ; Signed Integer ;; data_rate ; 0 ; Signed Integer ;; sim_additional_refclk_cycles_to_lock ; 0 ; Signed Integer ;; output_clock_frequency0 ; 400.000000 MHz ; String ;; phase_shift0 ; 0 ps ; String ;; duty_cycle0 ; 50 ; Signed Integer ;; output_clock_frequency1 ; 0 MHz ; String ;; phase_shift1 ; 0 ps ; String ;; duty_cycle1 ; 50 ; Signed Integer ;; output_clock_frequency2 ; 0 MHz ; String ;; phase_shift2 ; 0 ps ; String ;; duty_cycle2 ; 50 ; Signed Integer ;; output_clock_frequency3 ; 0 MHz ; String ;; phase_shift3 ; 0 ps ; String ;; duty_cycle3 ; 50 ; Signed Integer ;; output_clock_frequency4 ; 0 MHz ; String ;; phase_shift4 ; 0 ps ; String ;; duty_cycle4 ; 50 ; Signed Integer ;; output_clock_frequency5 ; 0 MHz ; String ;; phase_shift5 ; 0 ps ; String ;; duty_cycle5 ; 50 ; Signed Integer ;; output_clock_frequency6 ; 0 MHz ; String ;; phase_shift6 ; 0 ps ; String ;; duty_cycle6 ; 50 ; Signed Integer ;; output_clock_frequency7 ; 0 MHz ; String ;; phase_shift7 ; 0 ps ; String ;; duty_cycle7 ; 50 ; Signed Integer ;; output_clock_frequency8 ; 0 MHz ; String ;; phase_shift8 ; 0 ps ; String ;; duty_cycle8 ; 50 ; Signed Integer ;; output_clock_frequency9 ; 0 MHz ; String ;; phase_shift9 ; 0 ps ; String ;; duty_cycle9 ; 50 ; Signed Integer ;; output_clock_frequency10 ; 0 MHz ; String ;; phase_shift10 ; 0 ps ; String ;; duty_cycle10 ; 50 ; Signed Integer ;; output_clock_frequency11 ; 0 MHz ; String ;; phase_shift11 ; 0 ps ; String ;; duty_cycle11 ; 50 ; Signed Integer ;; output_clock_frequency12 ; 0 MHz ; String ;; phase_shift12 ; 0 ps ; String ;; duty_cycle12 ; 50 ; Signed Integer ;; output_clock_frequency13 ; 0 MHz ; String ;; phase_shift13 ; 0 ps ; String ;; duty_cycle13 ; 50 ; Signed Integer ;; output_clock_frequency14 ; 0 MHz ; String ;; phase_shift14 ; 0 ps ; String ;; duty_cycle14 ; 50 ; Signed Integer ;; output_clock_frequency15 ; 0 MHz ; String ;; phase_shift15 ; 0 ps ; String ;; duty_cycle15 ; 50 ; Signed Integer ;; output_clock_frequency16 ; 0 MHz ; String ;; phase_shift16 ; 0 ps ; String ;; duty_cycle16 ; 50 ; Signed Integer ;; output_clock_frequency17 ; 0 MHz ; String ;; phase_shift17 ; 0 ps ; String ;; duty_cycle17 ; 50 ; Signed Integer ;; clock_name_0 ; ; String ;; clock_name_1 ; ; String ;; clock_name_2 ; ; String ;; clock_name_3 ; ; String ;; clock_name_4 ; ; String ;; clock_name_5 ; ; String ;; clock_name_6 ; ; String ;; clock_name_7 ; ; String ;; clock_name_8 ; ; String ;; clock_name_global_0 ; false ; String ;; clock_name_global_1 ; false ; String ;; clock_name_global_2 ; false ; String ;; clock_name_global_3 ; false ; String ;; clock_name_global_4 ; false ; String ;; clock_name_global_5 ; false ; String ;; clock_name_global_6 ; false ; String ;; clock_name_global_7 ; false ; String ;; clock_name_global_8 ; false ; String ;; m_cnt_hi_div ; 4 ; Signed Integer ;; m_cnt_lo_div ; 4 ; Signed Integer ;; m_cnt_bypass_en ; false ; String ;; m_cnt_odd_div_duty_en ; false ; String ;; n_cnt_hi_div ; 256 ; Signed Integer ;; n_cnt_lo_div ; 256 ; Signed Integer ;; n_cnt_bypass_en ; true ; String ;; n_cnt_odd_div_duty_en ; false ; String ;; c_cnt_hi_div0 ; 256 ; Signed Integer ;; c_cnt_lo_div0 ; 256 ; Signed Integer ;; c_cnt_bypass_en0 ; true ; String ;; c_cnt_in_src0 ; ph_mux_clk ; String ;; c_cnt_odd_div_duty_en0 ; false ; String ;; c_cnt_prst0 ; 1 ; Signed Integer ;; c_cnt_ph_mux_prst0 ; 0 ; Signed Integer ;; c_cnt_hi_div1 ; 1 ; Signed Integer ;; c_cnt_lo_div1 ; 1 ; Signed Integer ;; c_cnt_bypass_en1 ; true ; String ;; c_cnt_in_src1 ; ph_mux_clk ; String ;; c_cnt_odd_div_duty_en1 ; false ; String ;; c_cnt_prst1 ; 1 ; Signed Integer ;; c_cnt_ph_mux_prst1 ; 0 ; Signed Integer ;; c_cnt_hi_div2 ; 1 ; Signed Integer ;; c_cnt_lo_div2 ; 1 ; Signed Integer ;; c_cnt_bypass_en2 ; true ; String ;; c_cnt_in_src2 ; ph_mux_clk ; String ;; c_cnt_odd_div_duty_en2 ; false ; String ;; c_cnt_prst2 ; 1 ; Signed Integer ;; c_cnt_ph_mux_prst2 ; 0 ; Signed Integer ;; c_cnt_hi_div3 ; 1 ; Signed Integer ;; c_cnt_lo_div3 ; 1 ; Signed Integer ;; c_cnt_bypass_en3 ; true ; String ;; c_cnt_in_src3 ; ph_mux_clk ; String ;; c_cnt_odd_div_duty_en3 ; false ; String ;; c_cnt_prst3 ; 1 ; Signed Integer ;; c_cnt_ph_mux_prst3 ; 0 ; Signed Integer ;; c_cnt_hi_div4 ; 1 ; Signed Integer ;; c_cnt_lo_div4 ; 1 ; Signed Integer ;; c_cnt_bypass_en4 ; true ; String ;; c_cnt_in_src4 ; ph_mux_clk ; String ;; c_cnt_odd_div_duty_en4 ; false ; String ;; c_cnt_prst4 ; 1 ; Signed Integer ;; c_cnt_ph_mux_prst4 ; 0 ; Signed Integer ;; c_cnt_hi_div5 ; 1 ; Signed Integer ;; c_cnt_lo_div5 ; 1 ; Signed Integer ;; c_cnt_bypass_en5 ; true ; String ;; c_cnt_in_src5 ; ph_mux_clk ; String ;; c_cnt_odd_div_duty_en5 ; false ; String ;; c_cnt_prst5 ; 1 ; Signed Integer ;; c_cnt_ph_mux_prst5 ; 0 ; Signed Integer ;; c_cnt_hi_div6 ; 1 ; Signed Integer ;; c_cnt_lo_div6 ; 1 ; Signed Integer ;; c_cnt_bypass_en6 ; true ; String ;; c_cnt_in_src6 ; ph_mux_clk ; String ;; c_cnt_odd_div_duty_en6 ; false ; String ;; c_cnt_prst6 ; 1 ; Signed Integer ;; c_cnt_ph_mux_prst6 ; 0 ; Signed Integer ;; c_cnt_hi_div7 ; 1 ; Signed Integer ;; c_cnt_lo_div7 ; 1 ; Signed Integer ;; c_cnt_bypass_en7 ; true ; String ;; c_cnt_in_src7 ; ph_mux_clk ; String ;; c_cnt_odd_div_duty_en7 ; false ; String ;; c_cnt_prst7 ; 1 ; Signed Integer ;; c_cnt_ph_mux_prst7 ; 0 ; Signed Integer ;; c_cnt_hi_div8 ; 1 ; Signed Integer ;; c_cnt_lo_div8 ; 1 ; Signed Integer ;; c_cnt_bypass_en8 ; true ; String ;; c_cnt_in_src8 ; ph_mux_clk ; String ;; c_cnt_odd_div_duty_en8 ; false ; String ;; c_cnt_prst8 ; 1 ; Signed Integer ;; c_cnt_ph_mux_prst8 ; 0 ; Signed Integer ;; c_cnt_hi_div9 ; 1 ; Signed Integer ;; c_cnt_lo_div9 ; 1 ; Signed Integer ;; c_cnt_bypass_en9 ; true ; String ;; c_cnt_in_src9 ; ph_mux_clk ; String ;; c_cnt_odd_div_duty_en9 ; false ; String ;; c_cnt_prst9 ; 1 ; Signed Integer ;; c_cnt_ph_mux_prst9 ; 0 ; Signed Integer ;; c_cnt_hi_div10 ; 1 ; Signed Integer ;; c_cnt_lo_div10 ; 1 ; Signed Integer ;; c_cnt_bypass_en10 ; true ; String ;; c_cnt_in_src10 ; ph_mux_clk ; String ;; c_cnt_odd_div_duty_en10 ; false ; String ;; c_cnt_prst10 ; 1 ; Signed Integer ;; c_cnt_ph_mux_prst10 ; 0 ; Signed Integer ;; c_cnt_hi_div11 ; 1 ; Signed Integer ;; c_cnt_lo_div11 ; 1 ; Signed Integer ;; c_cnt_bypass_en11 ; true ; String ;; c_cnt_in_src11 ; ph_mux_clk ; String ;; c_cnt_odd_div_duty_en11 ; false ; String ;; c_cnt_prst11 ; 1 ; Signed Integer ;; c_cnt_ph_mux_prst11 ; 0 ; Signed Integer ;; c_cnt_hi_div12 ; 1 ; Signed Integer ;; c_cnt_lo_div12 ; 1 ; Signed Integer ;; c_cnt_bypass_en12 ; true ; String ;; c_cnt_in_src12 ; ph_mux_clk ; String ;; c_cnt_odd_div_duty_en12 ; false ; String ;; c_cnt_prst12 ; 1 ; Signed Integer ;; c_cnt_ph_mux_prst12 ; 0 ; Signed Integer ;; c_cnt_hi_div13 ; 1 ; Signed Integer ;; c_cnt_lo_div13 ; 1 ; Signed Integer ;; c_cnt_bypass_en13 ; true ; String ;; c_cnt_in_src13 ; ph_mux_clk ; String ;; c_cnt_odd_div_duty_en13 ; false ; String ;; c_cnt_prst13 ; 1 ; Signed Integer ;; c_cnt_ph_mux_prst13 ; 0 ; Signed Integer ;; c_cnt_hi_div14 ; 1 ; Signed Integer ;; c_cnt_lo_div14 ; 1 ; Signed Integer ;; c_cnt_bypass_en14 ; true ; String ;; c_cnt_in_src14 ; ph_mux_clk ; String ;; c_cnt_odd_div_duty_en14 ; false ; String ;; c_cnt_prst14 ; 1 ; Signed Integer ;; c_cnt_ph_mux_prst14 ; 0 ; Signed Integer ;; c_cnt_hi_div15 ; 1 ; Signed Integer ;; c_cnt_lo_div15 ; 1 ; Signed Integer ;; c_cnt_bypass_en15 ; true ; String ;; c_cnt_in_src15 ; ph_mux_clk ; String ;; c_cnt_odd_div_duty_en15 ; false ; String ;; c_cnt_prst15 ; 1 ; Signed Integer ;; c_cnt_ph_mux_prst15 ; 0 ; Signed Integer ;; c_cnt_hi_div16 ; 1 ; Signed Integer ;; c_cnt_lo_div16 ; 1 ; Signed Integer ;; c_cnt_bypass_en16 ; true ; String ;; c_cnt_in_src16 ; ph_mux_clk ; String ;; c_cnt_odd_div_duty_en16 ; false ; String ;; c_cnt_prst16 ; 1 ; Signed Integer ;; c_cnt_ph_mux_prst16 ; 0 ; Signed Integer ;; c_cnt_hi_div17 ; 1 ; Signed Integer ;; c_cnt_lo_div17 ; 1 ; Signed Integer ;; c_cnt_bypass_en17 ; true ; String ;; c_cnt_in_src17 ; ph_mux_clk ; String ;; c_cnt_odd_div_duty_en17 ; false ; String ;; c_cnt_prst17 ; 1 ; Signed Integer ;; c_cnt_ph_mux_prst17 ; 0 ; Signed Integer ;; pll_vco_div ; 2 ; Signed Integer ;; pll_slf_rst ; false ; String ;; pll_bw_sel ; low ; String ;; pll_output_clk_frequency ; 400.0 MHz ; String ;; pll_cp_current ; 20 ; Signed Integer ;; pll_bwctrl ; 4000 ; Signed Integer ;; pll_fractional_division ; 1 ; String ;; pll_fractional_cout ; 32 ; Signed Integer ;; pll_dsm_out_sel ; 1st_order ; String ;; mimic_fbclk_type ; gclk ; String ;; pll_fbclk_mux_1 ; glb ; String ;; pll_fbclk_mux_2 ; fb_1 ; String ;; pll_m_cnt_in_src ; ph_mux_clk ; String ;; pll_vcoph_div ; 1 ; Signed Integer ;; refclk1_frequency ; 100.0 MHz ; String ;; pll_clkin_0_src ; clk_0 ; String ;; pll_clkin_1_src ; clk_1 ; String ;; pll_clk_loss_sw_en ; true ; String ;; pll_auto_clk_sw_en ; true ; String ;; pll_manu_clk_sw_en ; false ; String ;; pll_clk_sw_dly ; 0 ; Signed Integer ;; pll_extclk_0_cnt_src ; pll_extclk_cnt_src_vss ; String ;; pll_extclk_1_cnt_src ; pll_extclk_cnt_src_vss ; String ;+--------------------------------------+------------------------+---------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:led_pio_test_s1_translator ;+--------------------------------+-------+------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+--------------------------------+-------+------------------------------------------------------------------------------------------------------------------------------+; AV_ADDRESS_W ; 2 ; Signed Integer ;; AV_DATA_W ; 32 ; Signed Integer ;; AV_BURSTCOUNT_W ; 1 ; Signed Integer ;; AV_BYTEENABLE_W ; 1 ; Signed Integer ;; UAV_BYTEENABLE_W ; 4 ; Signed Integer ;; AV_READLATENCY ; 0 ; Signed Integer ;; AV_READ_WAIT_CYCLES ; 1 ; Signed Integer ;; AV_WRITE_WAIT_CYCLES ; 0 ; Signed Integer ;; AV_SETUP_WAIT_CYCLES ; 0 ; Signed Integer ;; AV_DATA_HOLD_CYCLES ; 0 ; Signed Integer ;; USE_READDATAVALID ; 0 ; Signed Integer ;; USE_WAITREQUEST ; 0 ; Signed Integer ;; USE_READRESPONSE ; 0 ; Signed Integer ;; USE_WRITERESPONSE ; 0 ; Signed Integer ;; AV_SYMBOLS_PER_WORD ; 4 ; Signed Integer ;; AV_ADDRESS_SYMBOLS ; 0 ; Signed Integer ;; AV_BURSTCOUNT_SYMBOLS ; 0 ; Signed Integer ;; BITS_PER_WORD ; 2 ; Signed Integer ;; UAV_ADDRESS_W ; 30 ; Signed Integer ;; UAV_BURSTCOUNT_W ; 3 ; Signed Integer ;; UAV_DATA_W ; 32 ; Signed Integer ;; AV_CONSTANT_BURST_BEHAVIOR ; 0 ; Signed Integer ;; UAV_CONSTANT_BURST_BEHAVIOR ; 0 ; Signed Integer ;; CHIPSELECT_THROUGH_READLATENCY ; 0 ; Signed Integer ;; USE_UAV_CLKEN ; 0 ; Signed Integer ;; AV_REQUIRE_UNALIGNED_ADDRESSES ; 0 ; Signed Integer ;+--------------------------------+-------+------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+----------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_rx_s1_translator ;+--------------------------------+-------+-----------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+--------------------------------+-------+-----------------------------------------------------------------------------------------------------------------------------+; AV_ADDRESS_W ; 2 ; Signed Integer ;; AV_DATA_W ; 32 ; Signed Integer ;; AV_BURSTCOUNT_W ; 1 ; Signed Integer ;; AV_BYTEENABLE_W ; 1 ; Signed Integer ;; UAV_BYTEENABLE_W ; 4 ; Signed Integer ;; AV_READLATENCY ; 0 ; Signed Integer ;; AV_READ_WAIT_CYCLES ; 1 ; Signed Integer ;; AV_WRITE_WAIT_CYCLES ; 0 ; Signed Integer ;; AV_SETUP_WAIT_CYCLES ; 0 ; Signed Integer ;; AV_DATA_HOLD_CYCLES ; 0 ; Signed Integer ;; USE_READDATAVALID ; 0 ; Signed Integer ;; USE_WAITREQUEST ; 0 ; Signed Integer ;; USE_READRESPONSE ; 0 ; Signed Integer ;; USE_WRITERESPONSE ; 0 ; Signed Integer ;; AV_SYMBOLS_PER_WORD ; 4 ; Signed Integer ;; AV_ADDRESS_SYMBOLS ; 0 ; Signed Integer ;; AV_BURSTCOUNT_SYMBOLS ; 0 ; Signed Integer ;; BITS_PER_WORD ; 2 ; Signed Integer ;; UAV_ADDRESS_W ; 30 ; Signed Integer ;; UAV_BURSTCOUNT_W ; 3 ; Signed Integer ;; UAV_DATA_W ; 32 ; Signed Integer ;; AV_CONSTANT_BURST_BEHAVIOR ; 0 ; Signed Integer ;; UAV_CONSTANT_BURST_BEHAVIOR ; 0 ; Signed Integer ;; CHIPSELECT_THROUGH_READLATENCY ; 0 ; Signed Integer ;; USE_UAV_CLKEN ; 0 ; Signed Integer ;; AV_REQUIRE_UNALIGNED_ADDRESSES ; 0 ; Signed Integer ;+--------------------------------+-------+-----------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_ready_rx_s1_translator ;+--------------------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+--------------------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------+; AV_ADDRESS_W ; 2 ; Signed Integer ;; AV_DATA_W ; 32 ; Signed Integer ;; AV_BURSTCOUNT_W ; 1 ; Signed Integer ;; AV_BYTEENABLE_W ; 1 ; Signed Integer ;; UAV_BYTEENABLE_W ; 4 ; Signed Integer ;; AV_READLATENCY ; 0 ; Signed Integer ;; AV_READ_WAIT_CYCLES ; 1 ; Signed Integer ;; AV_WRITE_WAIT_CYCLES ; 0 ; Signed Integer ;; AV_SETUP_WAIT_CYCLES ; 0 ; Signed Integer ;; AV_DATA_HOLD_CYCLES ; 0 ; Signed Integer ;; USE_READDATAVALID ; 0 ; Signed Integer ;; USE_WAITREQUEST ; 0 ; Signed Integer ;; USE_READRESPONSE ; 0 ; Signed Integer ;; USE_WRITERESPONSE ; 0 ; Signed Integer ;; AV_SYMBOLS_PER_WORD ; 4 ; Signed Integer ;; AV_ADDRESS_SYMBOLS ; 0 ; Signed Integer ;; AV_BURSTCOUNT_SYMBOLS ; 0 ; Signed Integer ;; BITS_PER_WORD ; 2 ; Signed Integer ;; UAV_ADDRESS_W ; 30 ; Signed Integer ;; UAV_BURSTCOUNT_W ; 3 ; Signed Integer ;; UAV_DATA_W ; 32 ; Signed Integer ;; AV_CONSTANT_BURST_BEHAVIOR ; 0 ; Signed Integer ;; UAV_CONSTANT_BURST_BEHAVIOR ; 0 ; Signed Integer ;; CHIPSELECT_THROUGH_READLATENCY ; 0 ; Signed Integer ;; USE_UAV_CLKEN ; 0 ; Signed Integer ;; AV_REQUIRE_UNALIGNED_ADDRESSES ; 0 ; Signed Integer ;+--------------------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:data_flag_rx_s1_translator ;+--------------------------------+-------+------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+--------------------------------+-------+------------------------------------------------------------------------------------------------------------------------------+; AV_ADDRESS_W ; 2 ; Signed Integer ;; AV_DATA_W ; 32 ; Signed Integer ;; AV_BURSTCOUNT_W ; 1 ; Signed Integer ;; AV_BYTEENABLE_W ; 1 ; Signed Integer ;; UAV_BYTEENABLE_W ; 4 ; Signed Integer ;; AV_READLATENCY ; 0 ; Signed Integer ;; AV_READ_WAIT_CYCLES ; 1 ; Signed Integer ;; AV_WRITE_WAIT_CYCLES ; 0 ; Signed Integer ;; AV_SETUP_WAIT_CYCLES ; 0 ; Signed Integer ;; AV_DATA_HOLD_CYCLES ; 0 ; Signed Integer ;; USE_READDATAVALID ; 0 ; Signed Integer ;; USE_WAITREQUEST ; 0 ; Signed Integer ;; USE_READRESPONSE ; 0 ; Signed Integer ;; USE_WRITERESPONSE ; 0 ; Signed Integer ;; AV_SYMBOLS_PER_WORD ; 4 ; Signed Integer ;; AV_ADDRESS_SYMBOLS ; 0 ; Signed Integer ;; AV_BURSTCOUNT_SYMBOLS ; 0 ; Signed Integer ;; BITS_PER_WORD ; 2 ; Signed Integer ;; UAV_ADDRESS_W ; 30 ; Signed Integer ;; UAV_BURSTCOUNT_W ; 3 ; Signed Integer ;; UAV_DATA_W ; 32 ; Signed Integer ;; AV_CONSTANT_BURST_BEHAVIOR ; 0 ; Signed Integer ;; UAV_CONSTANT_BURST_BEHAVIOR ; 0 ; Signed Integer ;; CHIPSELECT_THROUGH_READLATENCY ; 0 ; Signed Integer ;; USE_UAV_CLKEN ; 0 ; Signed Integer ;; AV_REQUIRE_UNALIGNED_ADDRESSES ; 0 ; Signed Integer ;+--------------------------------+-------+------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:data_read_en_rx_s1_translator ;+--------------------------------+-------+---------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+--------------------------------+-------+---------------------------------------------------------------------------------------------------------------------------------+; AV_ADDRESS_W ; 2 ; Signed Integer ;; AV_DATA_W ; 32 ; Signed Integer ;; AV_BURSTCOUNT_W ; 1 ; Signed Integer ;; AV_BYTEENABLE_W ; 1 ; Signed Integer ;; UAV_BYTEENABLE_W ; 4 ; Signed Integer ;; AV_READLATENCY ; 0 ; Signed Integer ;; AV_READ_WAIT_CYCLES ; 1 ; Signed Integer ;; AV_WRITE_WAIT_CYCLES ; 0 ; Signed Integer ;; AV_SETUP_WAIT_CYCLES ; 0 ; Signed Integer ;; AV_DATA_HOLD_CYCLES ; 0 ; Signed Integer ;; USE_READDATAVALID ; 0 ; Signed Integer ;; USE_WAITREQUEST ; 0 ; Signed Integer ;; USE_READRESPONSE ; 0 ; Signed Integer ;; USE_WRITERESPONSE ; 0 ; Signed Integer ;; AV_SYMBOLS_PER_WORD ; 4 ; Signed Integer ;; AV_ADDRESS_SYMBOLS ; 0 ; Signed Integer ;; AV_BURSTCOUNT_SYMBOLS ; 0 ; Signed Integer ;; BITS_PER_WORD ; 2 ; Signed Integer ;; UAV_ADDRESS_W ; 30 ; Signed Integer ;; UAV_BURSTCOUNT_W ; 3 ; Signed Integer ;; UAV_DATA_W ; 32 ; Signed Integer ;; AV_CONSTANT_BURST_BEHAVIOR ; 0 ; Signed Integer ;; UAV_CONSTANT_BURST_BEHAVIOR ; 0 ; Signed Integer ;; CHIPSELECT_THROUGH_READLATENCY ; 0 ; Signed Integer ;; USE_UAV_CLKEN ; 0 ; Signed Integer ;; AV_REQUIRE_UNALIGNED_ADDRESSES ; 0 ; Signed Integer ;+--------------------------------+-------+---------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_full_rx_status_s1_translator ;+--------------------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+--------------------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------+; AV_ADDRESS_W ; 2 ; Signed Integer ;; AV_DATA_W ; 32 ; Signed Integer ;; AV_BURSTCOUNT_W ; 1 ; Signed Integer ;; AV_BYTEENABLE_W ; 1 ; Signed Integer ;; UAV_BYTEENABLE_W ; 4 ; Signed Integer ;; AV_READLATENCY ; 0 ; Signed Integer ;; AV_READ_WAIT_CYCLES ; 1 ; Signed Integer ;; AV_WRITE_WAIT_CYCLES ; 0 ; Signed Integer ;; AV_SETUP_WAIT_CYCLES ; 0 ; Signed Integer ;; AV_DATA_HOLD_CYCLES ; 0 ; Signed Integer ;; USE_READDATAVALID ; 0 ; Signed Integer ;; USE_WAITREQUEST ; 0 ; Signed Integer ;; USE_READRESPONSE ; 0 ; Signed Integer ;; USE_WRITERESPONSE ; 0 ; Signed Integer ;; AV_SYMBOLS_PER_WORD ; 4 ; Signed Integer ;; AV_ADDRESS_SYMBOLS ; 0 ; Signed Integer ;; AV_BURSTCOUNT_SYMBOLS ; 0 ; Signed Integer ;; BITS_PER_WORD ; 2 ; Signed Integer ;; UAV_ADDRESS_W ; 30 ; Signed Integer ;; UAV_BURSTCOUNT_W ; 3 ; Signed Integer ;; UAV_DATA_W ; 32 ; Signed Integer ;; AV_CONSTANT_BURST_BEHAVIOR ; 0 ; Signed Integer ;; UAV_CONSTANT_BURST_BEHAVIOR ; 0 ; Signed Integer ;; CHIPSELECT_THROUGH_READLATENCY ; 0 ; Signed Integer ;; USE_UAV_CLKEN ; 0 ; Signed Integer ;; AV_REQUIRE_UNALIGNED_ADDRESSES ; 0 ; Signed Integer ;+--------------------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_empty_rx_status_s1_translator ;+--------------------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+--------------------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------+; AV_ADDRESS_W ; 2 ; Signed Integer ;; AV_DATA_W ; 32 ; Signed Integer ;; AV_BURSTCOUNT_W ; 1 ; Signed Integer ;; AV_BYTEENABLE_W ; 1 ; Signed Integer ;; UAV_BYTEENABLE_W ; 4 ; Signed Integer ;; AV_READLATENCY ; 0 ; Signed Integer ;; AV_READ_WAIT_CYCLES ; 1 ; Signed Integer ;; AV_WRITE_WAIT_CYCLES ; 0 ; Signed Integer ;; AV_SETUP_WAIT_CYCLES ; 0 ; Signed Integer ;; AV_DATA_HOLD_CYCLES ; 0 ; Signed Integer ;; USE_READDATAVALID ; 0 ; Signed Integer ;; USE_WAITREQUEST ; 0 ; Signed Integer ;; USE_READRESPONSE ; 0 ; Signed Integer ;; USE_WRITERESPONSE ; 0 ; Signed Integer ;; AV_SYMBOLS_PER_WORD ; 4 ; Signed Integer ;; AV_ADDRESS_SYMBOLS ; 0 ; Signed Integer ;; AV_BURSTCOUNT_SYMBOLS ; 0 ; Signed Integer ;; BITS_PER_WORD ; 2 ; Signed Integer ;; UAV_ADDRESS_W ; 30 ; Signed Integer ;; UAV_BURSTCOUNT_W ; 3 ; Signed Integer ;; UAV_DATA_W ; 32 ; Signed Integer ;; AV_CONSTANT_BURST_BEHAVIOR ; 0 ; Signed Integer ;; UAV_CONSTANT_BURST_BEHAVIOR ; 0 ; Signed Integer ;; CHIPSELECT_THROUGH_READLATENCY ; 0 ; Signed Integer ;; USE_UAV_CLKEN ; 0 ; Signed Integer ;; AV_REQUIRE_UNALIGNED_ADDRESSES ; 0 ; Signed Integer ;+--------------------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+---------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:link_start_s1_translator ;+--------------------------------+-------+----------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+--------------------------------+-------+----------------------------------------------------------------------------------------------------------------------------+; AV_ADDRESS_W ; 2 ; Signed Integer ;; AV_DATA_W ; 32 ; Signed Integer ;; AV_BURSTCOUNT_W ; 1 ; Signed Integer ;; AV_BYTEENABLE_W ; 1 ; Signed Integer ;; UAV_BYTEENABLE_W ; 4 ; Signed Integer ;; AV_READLATENCY ; 0 ; Signed Integer ;; AV_READ_WAIT_CYCLES ; 1 ; Signed Integer ;; AV_WRITE_WAIT_CYCLES ; 0 ; Signed Integer ;; AV_SETUP_WAIT_CYCLES ; 0 ; Signed Integer ;; AV_DATA_HOLD_CYCLES ; 0 ; Signed Integer ;; USE_READDATAVALID ; 0 ; Signed Integer ;; USE_WAITREQUEST ; 0 ; Signed Integer ;; USE_READRESPONSE ; 0 ; Signed Integer ;; USE_WRITERESPONSE ; 0 ; Signed Integer ;; AV_SYMBOLS_PER_WORD ; 4 ; Signed Integer ;; AV_ADDRESS_SYMBOLS ; 0 ; Signed Integer ;; AV_BURSTCOUNT_SYMBOLS ; 0 ; Signed Integer ;; BITS_PER_WORD ; 2 ; Signed Integer ;; UAV_ADDRESS_W ; 30 ; Signed Integer ;; UAV_BURSTCOUNT_W ; 3 ; Signed Integer ;; UAV_DATA_W ; 32 ; Signed Integer ;; AV_CONSTANT_BURST_BEHAVIOR ; 0 ; Signed Integer ;; UAV_CONSTANT_BURST_BEHAVIOR ; 0 ; Signed Integer ;; CHIPSELECT_THROUGH_READLATENCY ; 0 ; Signed Integer ;; USE_UAV_CLKEN ; 0 ; Signed Integer ;; AV_REQUIRE_UNALIGNED_ADDRESSES ; 0 ; Signed Integer ;+--------------------------------+-------+----------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+---------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:auto_start_s1_translator ;+--------------------------------+-------+----------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+--------------------------------+-------+----------------------------------------------------------------------------------------------------------------------------+; AV_ADDRESS_W ; 2 ; Signed Integer ;; AV_DATA_W ; 32 ; Signed Integer ;; AV_BURSTCOUNT_W ; 1 ; Signed Integer ;; AV_BYTEENABLE_W ; 1 ; Signed Integer ;; UAV_BYTEENABLE_W ; 4 ; Signed Integer ;; AV_READLATENCY ; 0 ; Signed Integer ;; AV_READ_WAIT_CYCLES ; 1 ; Signed Integer ;; AV_WRITE_WAIT_CYCLES ; 0 ; Signed Integer ;; AV_SETUP_WAIT_CYCLES ; 0 ; Signed Integer ;; AV_DATA_HOLD_CYCLES ; 0 ; Signed Integer ;; USE_READDATAVALID ; 0 ; Signed Integer ;; USE_WAITREQUEST ; 0 ; Signed Integer ;; USE_READRESPONSE ; 0 ; Signed Integer ;; USE_WRITERESPONSE ; 0 ; Signed Integer ;; AV_SYMBOLS_PER_WORD ; 4 ; Signed Integer ;; AV_ADDRESS_SYMBOLS ; 0 ; Signed Integer ;; AV_BURSTCOUNT_SYMBOLS ; 0 ; Signed Integer ;; BITS_PER_WORD ; 2 ; Signed Integer ;; UAV_ADDRESS_W ; 30 ; Signed Integer ;; UAV_BURSTCOUNT_W ; 3 ; Signed Integer ;; UAV_DATA_W ; 32 ; Signed Integer ;; AV_CONSTANT_BURST_BEHAVIOR ; 0 ; Signed Integer ;; UAV_CONSTANT_BURST_BEHAVIOR ; 0 ; Signed Integer ;; CHIPSELECT_THROUGH_READLATENCY ; 0 ; Signed Integer ;; USE_UAV_CLKEN ; 0 ; Signed Integer ;; AV_REQUIRE_UNALIGNED_ADDRESSES ; 0 ; Signed Integer ;+--------------------------------+-------+----------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:link_disable_s1_translator ;+--------------------------------+-------+------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+--------------------------------+-------+------------------------------------------------------------------------------------------------------------------------------+; AV_ADDRESS_W ; 2 ; Signed Integer ;; AV_DATA_W ; 32 ; Signed Integer ;; AV_BURSTCOUNT_W ; 1 ; Signed Integer ;; AV_BYTEENABLE_W ; 1 ; Signed Integer ;; UAV_BYTEENABLE_W ; 4 ; Signed Integer ;; AV_READLATENCY ; 0 ; Signed Integer ;; AV_READ_WAIT_CYCLES ; 1 ; Signed Integer ;; AV_WRITE_WAIT_CYCLES ; 0 ; Signed Integer ;; AV_SETUP_WAIT_CYCLES ; 0 ; Signed Integer ;; AV_DATA_HOLD_CYCLES ; 0 ; Signed Integer ;; USE_READDATAVALID ; 0 ; Signed Integer ;; USE_WAITREQUEST ; 0 ; Signed Integer ;; USE_READRESPONSE ; 0 ; Signed Integer ;; USE_WRITERESPONSE ; 0 ; Signed Integer ;; AV_SYMBOLS_PER_WORD ; 4 ; Signed Integer ;; AV_ADDRESS_SYMBOLS ; 0 ; Signed Integer ;; AV_BURSTCOUNT_SYMBOLS ; 0 ; Signed Integer ;; BITS_PER_WORD ; 2 ; Signed Integer ;; UAV_ADDRESS_W ; 30 ; Signed Integer ;; UAV_BURSTCOUNT_W ; 3 ; Signed Integer ;; UAV_DATA_W ; 32 ; Signed Integer ;; AV_CONSTANT_BURST_BEHAVIOR ; 0 ; Signed Integer ;; UAV_CONSTANT_BURST_BEHAVIOR ; 0 ; Signed Integer ;; CHIPSELECT_THROUGH_READLATENCY ; 0 ; Signed Integer ;; USE_UAV_CLKEN ; 0 ; Signed Integer ;; AV_REQUIRE_UNALIGNED_ADDRESSES ; 0 ; Signed Integer ;+--------------------------------+-------+------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:write_data_fifo_tx_s1_translator ;+--------------------------------+-------+------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+--------------------------------+-------+------------------------------------------------------------------------------------------------------------------------------------+; AV_ADDRESS_W ; 2 ; Signed Integer ;; AV_DATA_W ; 32 ; Signed Integer ;; AV_BURSTCOUNT_W ; 1 ; Signed Integer ;; AV_BYTEENABLE_W ; 1 ; Signed Integer ;; UAV_BYTEENABLE_W ; 4 ; Signed Integer ;; AV_READLATENCY ; 0 ; Signed Integer ;; AV_READ_WAIT_CYCLES ; 1 ; Signed Integer ;; AV_WRITE_WAIT_CYCLES ; 0 ; Signed Integer ;; AV_SETUP_WAIT_CYCLES ; 0 ; Signed Integer ;; AV_DATA_HOLD_CYCLES ; 0 ; Signed Integer ;; USE_READDATAVALID ; 0 ; Signed Integer ;; USE_WAITREQUEST ; 0 ; Signed Integer ;; USE_READRESPONSE ; 0 ; Signed Integer ;; USE_WRITERESPONSE ; 0 ; Signed Integer ;; AV_SYMBOLS_PER_WORD ; 4 ; Signed Integer ;; AV_ADDRESS_SYMBOLS ; 0 ; Signed Integer ;; AV_BURSTCOUNT_SYMBOLS ; 0 ; Signed Integer ;; BITS_PER_WORD ; 2 ; Signed Integer ;; UAV_ADDRESS_W ; 30 ; Signed Integer ;; UAV_BURSTCOUNT_W ; 3 ; Signed Integer ;; UAV_DATA_W ; 32 ; Signed Integer ;; AV_CONSTANT_BURST_BEHAVIOR ; 0 ; Signed Integer ;; UAV_CONSTANT_BURST_BEHAVIOR ; 0 ; Signed Integer ;; CHIPSELECT_THROUGH_READLATENCY ; 0 ; Signed Integer ;; USE_UAV_CLKEN ; 0 ; Signed Integer ;; AV_REQUIRE_UNALIGNED_ADDRESSES ; 0 ; Signed Integer ;+--------------------------------+-------+------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+----------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:write_en_tx_s1_translator ;+--------------------------------+-------+-----------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+--------------------------------+-------+-----------------------------------------------------------------------------------------------------------------------------+; AV_ADDRESS_W ; 2 ; Signed Integer ;; AV_DATA_W ; 32 ; Signed Integer ;; AV_BURSTCOUNT_W ; 1 ; Signed Integer ;; AV_BYTEENABLE_W ; 1 ; Signed Integer ;; UAV_BYTEENABLE_W ; 4 ; Signed Integer ;; AV_READLATENCY ; 0 ; Signed Integer ;; AV_READ_WAIT_CYCLES ; 1 ; Signed Integer ;; AV_WRITE_WAIT_CYCLES ; 0 ; Signed Integer ;; AV_SETUP_WAIT_CYCLES ; 0 ; Signed Integer ;; AV_DATA_HOLD_CYCLES ; 0 ; Signed Integer ;; USE_READDATAVALID ; 0 ; Signed Integer ;; USE_WAITREQUEST ; 0 ; Signed Integer ;; USE_READRESPONSE ; 0 ; Signed Integer ;; USE_WRITERESPONSE ; 0 ; Signed Integer ;; AV_SYMBOLS_PER_WORD ; 4 ; Signed Integer ;; AV_ADDRESS_SYMBOLS ; 0 ; Signed Integer ;; AV_BURSTCOUNT_SYMBOLS ; 0 ; Signed Integer ;; BITS_PER_WORD ; 2 ; Signed Integer ;; UAV_ADDRESS_W ; 30 ; Signed Integer ;; UAV_BURSTCOUNT_W ; 3 ; Signed Integer ;; UAV_DATA_W ; 32 ; Signed Integer ;; AV_CONSTANT_BURST_BEHAVIOR ; 0 ; Signed Integer ;; UAV_CONSTANT_BURST_BEHAVIOR ; 0 ; Signed Integer ;; CHIPSELECT_THROUGH_READLATENCY ; 0 ; Signed Integer ;; USE_UAV_CLKEN ; 0 ; Signed Integer ;; AV_REQUIRE_UNALIGNED_ADDRESSES ; 0 ; Signed Integer ;+--------------------------------+-------+-----------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_full_tx_status_s1_translator ;+--------------------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+--------------------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------+; AV_ADDRESS_W ; 2 ; Signed Integer ;; AV_DATA_W ; 32 ; Signed Integer ;; AV_BURSTCOUNT_W ; 1 ; Signed Integer ;; AV_BYTEENABLE_W ; 1 ; Signed Integer ;; UAV_BYTEENABLE_W ; 4 ; Signed Integer ;; AV_READLATENCY ; 0 ; Signed Integer ;; AV_READ_WAIT_CYCLES ; 1 ; Signed Integer ;; AV_WRITE_WAIT_CYCLES ; 0 ; Signed Integer ;; AV_SETUP_WAIT_CYCLES ; 0 ; Signed Integer ;; AV_DATA_HOLD_CYCLES ; 0 ; Signed Integer ;; USE_READDATAVALID ; 0 ; Signed Integer ;; USE_WAITREQUEST ; 0 ; Signed Integer ;; USE_READRESPONSE ; 0 ; Signed Integer ;; USE_WRITERESPONSE ; 0 ; Signed Integer ;; AV_SYMBOLS_PER_WORD ; 4 ; Signed Integer ;; AV_ADDRESS_SYMBOLS ; 0 ; Signed Integer ;; AV_BURSTCOUNT_SYMBOLS ; 0 ; Signed Integer ;; BITS_PER_WORD ; 2 ; Signed Integer ;; UAV_ADDRESS_W ; 30 ; Signed Integer ;; UAV_BURSTCOUNT_W ; 3 ; Signed Integer ;; UAV_DATA_W ; 32 ; Signed Integer ;; AV_CONSTANT_BURST_BEHAVIOR ; 0 ; Signed Integer ;; UAV_CONSTANT_BURST_BEHAVIOR ; 0 ; Signed Integer ;; CHIPSELECT_THROUGH_READLATENCY ; 0 ; Signed Integer ;; USE_UAV_CLKEN ; 0 ; Signed Integer ;; AV_REQUIRE_UNALIGNED_ADDRESSES ; 0 ; Signed Integer ;+--------------------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_empty_tx_status_s1_translator ;+--------------------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+--------------------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------+; AV_ADDRESS_W ; 2 ; Signed Integer ;; AV_DATA_W ; 32 ; Signed Integer ;; AV_BURSTCOUNT_W ; 1 ; Signed Integer ;; AV_BYTEENABLE_W ; 1 ; Signed Integer ;; UAV_BYTEENABLE_W ; 4 ; Signed Integer ;; AV_READLATENCY ; 0 ; Signed Integer ;; AV_READ_WAIT_CYCLES ; 1 ; Signed Integer ;; AV_WRITE_WAIT_CYCLES ; 0 ; Signed Integer ;; AV_SETUP_WAIT_CYCLES ; 0 ; Signed Integer ;; AV_DATA_HOLD_CYCLES ; 0 ; Signed Integer ;; USE_READDATAVALID ; 0 ; Signed Integer ;; USE_WAITREQUEST ; 0 ; Signed Integer ;; USE_READRESPONSE ; 0 ; Signed Integer ;; USE_WRITERESPONSE ; 0 ; Signed Integer ;; AV_SYMBOLS_PER_WORD ; 4 ; Signed Integer ;; AV_ADDRESS_SYMBOLS ; 0 ; Signed Integer ;; AV_BURSTCOUNT_SYMBOLS ; 0 ; Signed Integer ;; BITS_PER_WORD ; 2 ; Signed Integer ;; UAV_ADDRESS_W ; 30 ; Signed Integer ;; UAV_BURSTCOUNT_W ; 3 ; Signed Integer ;; UAV_DATA_W ; 32 ; Signed Integer ;; AV_CONSTANT_BURST_BEHAVIOR ; 0 ; Signed Integer ;; UAV_CONSTANT_BURST_BEHAVIOR ; 0 ; Signed Integer ;; CHIPSELECT_THROUGH_READLATENCY ; 0 ; Signed Integer ;; USE_UAV_CLKEN ; 0 ; Signed Integer ;; AV_REQUIRE_UNALIGNED_ADDRESSES ; 0 ; Signed Integer ;+--------------------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_data_s1_translator ;+--------------------------------+-------+----------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+--------------------------------+-------+----------------------------------------------------------------------------------------------------------------------------------+; AV_ADDRESS_W ; 2 ; Signed Integer ;; AV_DATA_W ; 32 ; Signed Integer ;; AV_BURSTCOUNT_W ; 1 ; Signed Integer ;; AV_BYTEENABLE_W ; 1 ; Signed Integer ;; UAV_BYTEENABLE_W ; 4 ; Signed Integer ;; AV_READLATENCY ; 0 ; Signed Integer ;; AV_READ_WAIT_CYCLES ; 1 ; Signed Integer ;; AV_WRITE_WAIT_CYCLES ; 0 ; Signed Integer ;; AV_SETUP_WAIT_CYCLES ; 0 ; Signed Integer ;; AV_DATA_HOLD_CYCLES ; 0 ; Signed Integer ;; USE_READDATAVALID ; 0 ; Signed Integer ;; USE_WAITREQUEST ; 0 ; Signed Integer ;; USE_READRESPONSE ; 0 ; Signed Integer ;; USE_WRITERESPONSE ; 0 ; Signed Integer ;; AV_SYMBOLS_PER_WORD ; 4 ; Signed Integer ;; AV_ADDRESS_SYMBOLS ; 0 ; Signed Integer ;; AV_BURSTCOUNT_SYMBOLS ; 0 ; Signed Integer ;; BITS_PER_WORD ; 2 ; Signed Integer ;; UAV_ADDRESS_W ; 30 ; Signed Integer ;; UAV_BURSTCOUNT_W ; 3 ; Signed Integer ;; UAV_DATA_W ; 32 ; Signed Integer ;; AV_CONSTANT_BURST_BEHAVIOR ; 0 ; Signed Integer ;; UAV_CONSTANT_BURST_BEHAVIOR ; 0 ; Signed Integer ;; CHIPSELECT_THROUGH_READLATENCY ; 0 ; Signed Integer ;; USE_UAV_CLKEN ; 0 ; Signed Integer ;; AV_REQUIRE_UNALIGNED_ADDRESSES ; 0 ; Signed Integer ;+--------------------------------+-------+----------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_enable_s1_translator ;+--------------------------------+-------+------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+--------------------------------+-------+------------------------------------------------------------------------------------------------------------------------------------+; AV_ADDRESS_W ; 2 ; Signed Integer ;; AV_DATA_W ; 32 ; Signed Integer ;; AV_BURSTCOUNT_W ; 1 ; Signed Integer ;; AV_BYTEENABLE_W ; 1 ; Signed Integer ;; UAV_BYTEENABLE_W ; 4 ; Signed Integer ;; AV_READLATENCY ; 0 ; Signed Integer ;; AV_READ_WAIT_CYCLES ; 1 ; Signed Integer ;; AV_WRITE_WAIT_CYCLES ; 0 ; Signed Integer ;; AV_SETUP_WAIT_CYCLES ; 0 ; Signed Integer ;; AV_DATA_HOLD_CYCLES ; 0 ; Signed Integer ;; USE_READDATAVALID ; 0 ; Signed Integer ;; USE_WAITREQUEST ; 0 ; Signed Integer ;; USE_READRESPONSE ; 0 ; Signed Integer ;; USE_WRITERESPONSE ; 0 ; Signed Integer ;; AV_SYMBOLS_PER_WORD ; 4 ; Signed Integer ;; AV_ADDRESS_SYMBOLS ; 0 ; Signed Integer ;; AV_BURSTCOUNT_SYMBOLS ; 0 ; Signed Integer ;; BITS_PER_WORD ; 2 ; Signed Integer ;; UAV_ADDRESS_W ; 30 ; Signed Integer ;; UAV_BURSTCOUNT_W ; 3 ; Signed Integer ;; UAV_DATA_W ; 32 ; Signed Integer ;; AV_CONSTANT_BURST_BEHAVIOR ; 0 ; Signed Integer ;; UAV_CONSTANT_BURST_BEHAVIOR ; 0 ; Signed Integer ;; CHIPSELECT_THROUGH_READLATENCY ; 0 ; Signed Integer ;; USE_UAV_CLKEN ; 0 ; Signed Integer ;; AV_REQUIRE_UNALIGNED_ADDRESSES ; 0 ; Signed Integer ;+--------------------------------+-------+------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_ready_s1_translator ;+--------------------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+--------------------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------+; AV_ADDRESS_W ; 2 ; Signed Integer ;; AV_DATA_W ; 32 ; Signed Integer ;; AV_BURSTCOUNT_W ; 1 ; Signed Integer ;; AV_BYTEENABLE_W ; 1 ; Signed Integer ;; UAV_BYTEENABLE_W ; 4 ; Signed Integer ;; AV_READLATENCY ; 0 ; Signed Integer ;; AV_READ_WAIT_CYCLES ; 1 ; Signed Integer ;; AV_WRITE_WAIT_CYCLES ; 0 ; Signed Integer ;; AV_SETUP_WAIT_CYCLES ; 0 ; Signed Integer ;; AV_DATA_HOLD_CYCLES ; 0 ; Signed Integer ;; USE_READDATAVALID ; 0 ; Signed Integer ;; USE_WAITREQUEST ; 0 ; Signed Integer ;; USE_READRESPONSE ; 0 ; Signed Integer ;; USE_WRITERESPONSE ; 0 ; Signed Integer ;; AV_SYMBOLS_PER_WORD ; 4 ; Signed Integer ;; AV_ADDRESS_SYMBOLS ; 0 ; Signed Integer ;; AV_BURSTCOUNT_SYMBOLS ; 0 ; Signed Integer ;; BITS_PER_WORD ; 2 ; Signed Integer ;; UAV_ADDRESS_W ; 30 ; Signed Integer ;; UAV_BURSTCOUNT_W ; 3 ; Signed Integer ;; UAV_DATA_W ; 32 ; Signed Integer ;; AV_CONSTANT_BURST_BEHAVIOR ; 0 ; Signed Integer ;; UAV_CONSTANT_BURST_BEHAVIOR ; 0 ; Signed Integer ;; CHIPSELECT_THROUGH_READLATENCY ; 0 ; Signed Integer ;; USE_UAV_CLKEN ; 0 ; Signed Integer ;; AV_REQUIRE_UNALIGNED_ADDRESSES ; 0 ; Signed Integer ;+--------------------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+--------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:data_info_s1_translator ;+--------------------------------+-------+---------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+--------------------------------+-------+---------------------------------------------------------------------------------------------------------------------------+; AV_ADDRESS_W ; 2 ; Signed Integer ;; AV_DATA_W ; 32 ; Signed Integer ;; AV_BURSTCOUNT_W ; 1 ; Signed Integer ;; AV_BYTEENABLE_W ; 1 ; Signed Integer ;; UAV_BYTEENABLE_W ; 4 ; Signed Integer ;; AV_READLATENCY ; 0 ; Signed Integer ;; AV_READ_WAIT_CYCLES ; 1 ; Signed Integer ;; AV_WRITE_WAIT_CYCLES ; 0 ; Signed Integer ;; AV_SETUP_WAIT_CYCLES ; 0 ; Signed Integer ;; AV_DATA_HOLD_CYCLES ; 0 ; Signed Integer ;; USE_READDATAVALID ; 0 ; Signed Integer ;; USE_WAITREQUEST ; 0 ; Signed Integer ;; USE_READRESPONSE ; 0 ; Signed Integer ;; USE_WRITERESPONSE ; 0 ; Signed Integer ;; AV_SYMBOLS_PER_WORD ; 4 ; Signed Integer ;; AV_ADDRESS_SYMBOLS ; 0 ; Signed Integer ;; AV_BURSTCOUNT_SYMBOLS ; 0 ; Signed Integer ;; BITS_PER_WORD ; 2 ; Signed Integer ;; UAV_ADDRESS_W ; 30 ; Signed Integer ;; UAV_BURSTCOUNT_W ; 3 ; Signed Integer ;; UAV_DATA_W ; 32 ; Signed Integer ;; AV_CONSTANT_BURST_BEHAVIOR ; 0 ; Signed Integer ;; UAV_CONSTANT_BURST_BEHAVIOR ; 0 ; Signed Integer ;; CHIPSELECT_THROUGH_READLATENCY ; 0 ; Signed Integer ;; USE_UAV_CLKEN ; 0 ; Signed Integer ;; AV_REQUIRE_UNALIGNED_ADDRESSES ; 0 ; Signed Integer ;+--------------------------------+-------+---------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+--------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:clock_sel_s1_translator ;+--------------------------------+-------+---------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+--------------------------------+-------+---------------------------------------------------------------------------------------------------------------------------+; AV_ADDRESS_W ; 2 ; Signed Integer ;; AV_DATA_W ; 32 ; Signed Integer ;; AV_BURSTCOUNT_W ; 1 ; Signed Integer ;; AV_BYTEENABLE_W ; 1 ; Signed Integer ;; UAV_BYTEENABLE_W ; 4 ; Signed Integer ;; AV_READLATENCY ; 0 ; Signed Integer ;; AV_READ_WAIT_CYCLES ; 1 ; Signed Integer ;; AV_WRITE_WAIT_CYCLES ; 0 ; Signed Integer ;; AV_SETUP_WAIT_CYCLES ; 0 ; Signed Integer ;; AV_DATA_HOLD_CYCLES ; 0 ; Signed Integer ;; USE_READDATAVALID ; 0 ; Signed Integer ;; USE_WAITREQUEST ; 0 ; Signed Integer ;; USE_READRESPONSE ; 0 ; Signed Integer ;; USE_WRITERESPONSE ; 0 ; Signed Integer ;; AV_SYMBOLS_PER_WORD ; 4 ; Signed Integer ;; AV_ADDRESS_SYMBOLS ; 0 ; Signed Integer ;; AV_BURSTCOUNT_SYMBOLS ; 0 ; Signed Integer ;; BITS_PER_WORD ; 2 ; Signed Integer ;; UAV_ADDRESS_W ; 30 ; Signed Integer ;; UAV_BURSTCOUNT_W ; 3 ; Signed Integer ;; UAV_DATA_W ; 32 ; Signed Integer ;; AV_CONSTANT_BURST_BEHAVIOR ; 0 ; Signed Integer ;; UAV_CONSTANT_BURST_BEHAVIOR ; 0 ; Signed Integer ;; CHIPSELECT_THROUGH_READLATENCY ; 0 ; Signed Integer ;; USE_UAV_CLKEN ; 0 ; Signed Integer ;; AV_REQUIRE_UNALIGNED_ADDRESSES ; 0 ; Signed Integer ;+--------------------------------+-------+---------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+-------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fsm_info_s1_translator ;+--------------------------------+-------+--------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+--------------------------------+-------+--------------------------------------------------------------------------------------------------------------------------+; AV_ADDRESS_W ; 2 ; Signed Integer ;; AV_DATA_W ; 32 ; Signed Integer ;; AV_BURSTCOUNT_W ; 1 ; Signed Integer ;; AV_BYTEENABLE_W ; 1 ; Signed Integer ;; UAV_BYTEENABLE_W ; 4 ; Signed Integer ;; AV_READLATENCY ; 0 ; Signed Integer ;; AV_READ_WAIT_CYCLES ; 1 ; Signed Integer ;; AV_WRITE_WAIT_CYCLES ; 0 ; Signed Integer ;; AV_SETUP_WAIT_CYCLES ; 0 ; Signed Integer ;; AV_DATA_HOLD_CYCLES ; 0 ; Signed Integer ;; USE_READDATAVALID ; 0 ; Signed Integer ;; USE_WAITREQUEST ; 0 ; Signed Integer ;; USE_READRESPONSE ; 0 ; Signed Integer ;; USE_WRITERESPONSE ; 0 ; Signed Integer ;; AV_SYMBOLS_PER_WORD ; 4 ; Signed Integer ;; AV_ADDRESS_SYMBOLS ; 0 ; Signed Integer ;; AV_BURSTCOUNT_SYMBOLS ; 0 ; Signed Integer ;; BITS_PER_WORD ; 2 ; Signed Integer ;; UAV_ADDRESS_W ; 30 ; Signed Integer ;; UAV_BURSTCOUNT_W ; 3 ; Signed Integer ;; UAV_DATA_W ; 32 ; Signed Integer ;; AV_CONSTANT_BURST_BEHAVIOR ; 0 ; Signed Integer ;; UAV_CONSTANT_BURST_BEHAVIOR ; 0 ; Signed Integer ;; CHIPSELECT_THROUGH_READLATENCY ; 0 ; Signed Integer ;; USE_UAV_CLKEN ; 0 ; Signed Integer ;; AV_REQUIRE_UNALIGNED_ADDRESSES ; 0 ; Signed Integer ;+--------------------------------+-------+--------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:counter_tx_fifo_s1_translator ;+--------------------------------+-------+---------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+--------------------------------+-------+---------------------------------------------------------------------------------------------------------------------------------+; AV_ADDRESS_W ; 2 ; Signed Integer ;; AV_DATA_W ; 32 ; Signed Integer ;; AV_BURSTCOUNT_W ; 1 ; Signed Integer ;; AV_BYTEENABLE_W ; 1 ; Signed Integer ;; UAV_BYTEENABLE_W ; 4 ; Signed Integer ;; AV_READLATENCY ; 0 ; Signed Integer ;; AV_READ_WAIT_CYCLES ; 1 ; Signed Integer ;; AV_WRITE_WAIT_CYCLES ; 0 ; Signed Integer ;; AV_SETUP_WAIT_CYCLES ; 0 ; Signed Integer ;; AV_DATA_HOLD_CYCLES ; 0 ; Signed Integer ;; USE_READDATAVALID ; 0 ; Signed Integer ;; USE_WAITREQUEST ; 0 ; Signed Integer ;; USE_READRESPONSE ; 0 ; Signed Integer ;; USE_WRITERESPONSE ; 0 ; Signed Integer ;; AV_SYMBOLS_PER_WORD ; 4 ; Signed Integer ;; AV_ADDRESS_SYMBOLS ; 0 ; Signed Integer ;; AV_BURSTCOUNT_SYMBOLS ; 0 ; Signed Integer ;; BITS_PER_WORD ; 2 ; Signed Integer ;; UAV_ADDRESS_W ; 30 ; Signed Integer ;; UAV_BURSTCOUNT_W ; 3 ; Signed Integer ;; UAV_DATA_W ; 32 ; Signed Integer ;; AV_CONSTANT_BURST_BEHAVIOR ; 0 ; Signed Integer ;; UAV_CONSTANT_BURST_BEHAVIOR ; 0 ; Signed Integer ;; CHIPSELECT_THROUGH_READLATENCY ; 0 ; Signed Integer ;; USE_UAV_CLKEN ; 0 ; Signed Integer ;; AV_REQUIRE_UNALIGNED_ADDRESSES ; 0 ; Signed Integer ;+--------------------------------+-------+---------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:counter_rx_fifo_s1_translator ;+--------------------------------+-------+---------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+--------------------------------+-------+---------------------------------------------------------------------------------------------------------------------------------+; AV_ADDRESS_W ; 2 ; Signed Integer ;; AV_DATA_W ; 32 ; Signed Integer ;; AV_BURSTCOUNT_W ; 1 ; Signed Integer ;; AV_BYTEENABLE_W ; 1 ; Signed Integer ;; UAV_BYTEENABLE_W ; 4 ; Signed Integer ;; AV_READLATENCY ; 0 ; Signed Integer ;; AV_READ_WAIT_CYCLES ; 1 ; Signed Integer ;; AV_WRITE_WAIT_CYCLES ; 0 ; Signed Integer ;; AV_SETUP_WAIT_CYCLES ; 0 ; Signed Integer ;; AV_DATA_HOLD_CYCLES ; 0 ; Signed Integer ;; USE_READDATAVALID ; 0 ; Signed Integer ;; USE_WAITREQUEST ; 0 ; Signed Integer ;; USE_READRESPONSE ; 0 ; Signed Integer ;; USE_WRITERESPONSE ; 0 ; Signed Integer ;; AV_SYMBOLS_PER_WORD ; 4 ; Signed Integer ;; AV_ADDRESS_SYMBOLS ; 0 ; Signed Integer ;; AV_BURSTCOUNT_SYMBOLS ; 0 ; Signed Integer ;; BITS_PER_WORD ; 2 ; Signed Integer ;; UAV_ADDRESS_W ; 30 ; Signed Integer ;; UAV_BURSTCOUNT_W ; 3 ; Signed Integer ;; UAV_DATA_W ; 32 ; Signed Integer ;; AV_CONSTANT_BURST_BEHAVIOR ; 0 ; Signed Integer ;; UAV_CONSTANT_BURST_BEHAVIOR ; 0 ; Signed Integer ;; CHIPSELECT_THROUGH_READLATENCY ; 0 ; Signed Integer ;; USE_UAV_CLKEN ; 0 ; Signed Integer ;; AV_REQUIRE_UNALIGNED_ADDRESSES ; 0 ; Signed Integer ;+--------------------------------+-------+---------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+--------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_axi_master_ni:hps_0_h2f_axi_master_agent ;+---------------------------+-------+--------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+---------------------------+-------+--------------------------------------------------------------------------------------------------------------------------------+; ID_WIDTH ; 12 ; Signed Integer ;; ADDR_WIDTH ; 30 ; Signed Integer ;; RDATA_WIDTH ; 32 ; Signed Integer ;; WDATA_WIDTH ; 32 ; Signed Integer ;; ADDR_USER_WIDTH ; 1 ; Signed Integer ;; DATA_USER_WIDTH ; 1 ; Signed Integer ;; AXI_LOCK_WIDTH ; 2 ; Signed Integer ;; AXI_BURST_LENGTH_WIDTH ; 4 ; Signed Integer ;; WRITE_ISSUING_CAPABILITY ; 8 ; Signed Integer ;; READ_ISSUING_CAPABILITY ; 8 ; Signed Integer ;; AXI_VERSION ; AXI3 ; String ;; PKT_THREAD_ID_H ; 116 ; Signed Integer ;; PKT_THREAD_ID_L ; 105 ; Signed Integer ;; PKT_QOS_H ; 94 ; Signed Integer ;; PKT_QOS_L ; 94 ; Signed Integer ;; PKT_BEGIN_BURST ; 93 ; Signed Integer ;; PKT_CACHE_H ; 123 ; Signed Integer ;; PKT_CACHE_L ; 120 ; Signed Integer ;; PKT_ADDR_SIDEBAND_H ; 91 ; Signed Integer ;; PKT_ADDR_SIDEBAND_L ; 91 ; Signed Integer ;; PKT_DATA_SIDEBAND_H ; 92 ; Signed Integer ;; PKT_DATA_SIDEBAND_L ; 92 ; Signed Integer ;; PKT_PROTECTION_H ; 119 ; Signed Integer ;; PKT_PROTECTION_L ; 117 ; Signed Integer ;; PKT_BURST_SIZE_H ; 88 ; Signed Integer ;; PKT_BURST_SIZE_L ; 86 ; Signed Integer ;; PKT_BURST_TYPE_H ; 90 ; Signed Integer ;; PKT_BURST_TYPE_L ; 89 ; Signed Integer ;; PKT_RESPONSE_STATUS_L ; 124 ; Signed Integer ;; PKT_RESPONSE_STATUS_H ; 125 ; Signed Integer ;; PKT_BURSTWRAP_H ; 85 ; Signed Integer ;; PKT_BURSTWRAP_L ; 79 ; Signed Integer ;; PKT_BYTE_CNT_H ; 78 ; Signed Integer ;; PKT_BYTE_CNT_L ; 72 ; Signed Integer ;; PKT_ADDR_H ; 65 ; Signed Integer ;; PKT_ADDR_L ; 36 ; Signed Integer ;; PKT_TRANS_EXCLUSIVE ; 71 ; Signed Integer ;; PKT_TRANS_LOCK ; 70 ; Signed Integer ;; PKT_TRANS_COMPRESSED_READ ; 66 ; Signed Integer ;; PKT_TRANS_POSTED ; 67 ; Signed Integer ;; PKT_TRANS_WRITE ; 68 ; Signed Integer ;; PKT_TRANS_READ ; 69 ; Signed Integer ;; PKT_DATA_H ; 31 ; Signed Integer ;; PKT_DATA_L ; 0 ; Signed Integer ;; PKT_BYTEEN_H ; 35 ; Signed Integer ;; PKT_BYTEEN_L ; 32 ; Signed Integer ;; PKT_SRC_ID_H ; 99 ; Signed Integer ;; PKT_SRC_ID_L ; 95 ; Signed Integer ;; PKT_DEST_ID_H ; 104 ; Signed Integer ;; PKT_DEST_ID_L ; 100 ; Signed Integer ;; PKT_ORI_BURST_SIZE_H ; 128 ; Signed Integer ;; PKT_ORI_BURST_SIZE_L ; 126 ; Signed Integer ;; ST_DATA_W ; 129 ; Signed Integer ;; ST_CHANNEL_W ; 22 ; Signed Integer ;; ID ; 0 ; Signed Integer ;; PKT_BURSTWRAP_W ; 7 ; Signed Integer ;; PKT_BYTE_CNT_W ; 7 ; Signed Integer ;; PKT_ADDR_W ; 30 ; Signed Integer ;; PKT_DATA_W ; 32 ; Signed Integer ;; PKT_BYTEEN_W ; 4 ; Signed Integer ;; PKT_SRC_ID_W ; 5 ; Signed Integer ;; PKT_DEST_ID_W ; 5 ; Signed Integer ;+---------------------------+-------+--------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_axi_master_ni:hps_0_h2f_axi_master_agent|altera_merlin_address_alignment:align_address_to_size ;+-------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+-------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; ADDR_W ; 30 ; Signed Integer ;; BURSTWRAP_W ; 7 ; Signed Integer ;; TYPE_W ; 2 ; Signed Integer ;; SIZE_W ; 3 ; Signed Integer ;; INCREMENT_ADDRESS ; 1 ; Signed Integer ;; NUMSYMBOLS ; 4 ; Signed Integer ;; SELECT_BITS ; 2 ; Signed Integer ;; IN_DATA_W ; 41 ; Signed Integer ;; OUT_DATA_W ; 32 ; Signed Integer ;+-------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+-------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:led_pio_test_s1_agent ;+---------------------------+-------+-------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+---------------------------+-------+-------------------------------------------------------------------------------------------------------------------------+; PKT_BEGIN_BURST ; 93 ; Signed Integer ;; PKT_DATA_H ; 31 ; Signed Integer ;; PKT_DATA_L ; 0 ; Signed Integer ;; PKT_SYMBOL_W ; 8 ; Signed Integer ;; PKT_BYTEEN_H ; 35 ; Signed Integer ;; PKT_BYTEEN_L ; 32 ; Signed Integer ;; PKT_ADDR_H ; 65 ; Signed Integer ;; PKT_ADDR_L ; 36 ; Signed Integer ;; PKT_TRANS_LOCK ; 70 ; Signed Integer ;; PKT_TRANS_COMPRESSED_READ ; 66 ; Signed Integer ;; PKT_TRANS_POSTED ; 67 ; Signed Integer ;; PKT_TRANS_WRITE ; 68 ; Signed Integer ;; PKT_TRANS_READ ; 69 ; Signed Integer ;; PKT_SRC_ID_H ; 99 ; Signed Integer ;; PKT_SRC_ID_L ; 95 ; Signed Integer ;; PKT_DEST_ID_H ; 104 ; Signed Integer ;; PKT_DEST_ID_L ; 100 ; Signed Integer ;; PKT_BURSTWRAP_H ; 85 ; Signed Integer ;; PKT_BURSTWRAP_L ; 79 ; Signed Integer ;; PKT_BYTE_CNT_H ; 78 ; Signed Integer ;; PKT_BYTE_CNT_L ; 72 ; Signed Integer ;; PKT_PROTECTION_H ; 119 ; Signed Integer ;; PKT_PROTECTION_L ; 117 ; Signed Integer ;; PKT_RESPONSE_STATUS_H ; 125 ; Signed Integer ;; PKT_RESPONSE_STATUS_L ; 124 ; Signed Integer ;; PKT_BURST_SIZE_H ; 88 ; Signed Integer ;; PKT_BURST_SIZE_L ; 86 ; Signed Integer ;; PKT_ORI_BURST_SIZE_L ; 126 ; Signed Integer ;; PKT_ORI_BURST_SIZE_H ; 128 ; Signed Integer ;; ST_DATA_W ; 129 ; Signed Integer ;; ST_CHANNEL_W ; 22 ; Signed Integer ;; ADDR_W ; 30 ; Signed Integer ;; AVS_DATA_W ; 32 ; Signed Integer ;; AVS_BURSTCOUNT_W ; 3 ; Signed Integer ;; PKT_SYMBOLS ; 4 ; Signed Integer ;; PREVENT_FIFO_OVERFLOW ; 1 ; Signed Integer ;; SUPPRESS_0_BYTEEN_CMD ; 1 ; Signed Integer ;; USE_READRESPONSE ; 0 ; Signed Integer ;; USE_WRITERESPONSE ; 0 ; Signed Integer ;; AVS_BE_W ; 4 ; Signed Integer ;; BURST_SIZE_W ; 3 ; Signed Integer ;; FIFO_DATA_W ; 130 ; Signed Integer ;; ECC_ENABLE ; 0 ; Signed Integer ;+---------------------------+-------+-------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:led_pio_test_s1_agent|altera_merlin_burst_uncompressor:uncompressor ;+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; ADDR_W ; 30 ; Signed Integer ;; BURSTWRAP_W ; 7 ; Signed Integer ;; BYTE_CNT_W ; 7 ; Signed Integer ;; PKT_SYMBOLS ; 4 ; Signed Integer ;; BURST_SIZE_W ; 3 ; Signed Integer ;+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rsp_fifo ;+---------------------+-------+------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+---------------------+-------+------------------------------------------------------------------------------------------------------------------------------------+; SYMBOLS_PER_BEAT ; 1 ; Signed Integer ;; BITS_PER_SYMBOL ; 130 ; Signed Integer ;; FIFO_DEPTH ; 2 ; Signed Integer ;; CHANNEL_WIDTH ; 0 ; Signed Integer ;; ERROR_WIDTH ; 0 ; Signed Integer ;; USE_PACKETS ; 1 ; Signed Integer ;; USE_FILL_LEVEL ; 0 ; Signed Integer ;; USE_STORE_FORWARD ; 0 ; Signed Integer ;; USE_ALMOST_FULL_IF ; 0 ; Signed Integer ;; USE_ALMOST_EMPTY_IF ; 0 ; Signed Integer ;; EMPTY_LATENCY ; 1 ; Signed Integer ;; USE_MEMORY_BLOCKS ; 0 ; Signed Integer ;; DATA_WIDTH ; 130 ; Signed Integer ;; EMPTY_WIDTH ; 0 ; Signed Integer ;+---------------------+-------+------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+--------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo ;+---------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+---------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------+; SYMBOLS_PER_BEAT ; 1 ; Signed Integer ;; BITS_PER_SYMBOL ; 34 ; Signed Integer ;; FIFO_DEPTH ; 2 ; Signed Integer ;; CHANNEL_WIDTH ; 0 ; Signed Integer ;; ERROR_WIDTH ; 0 ; Signed Integer ;; USE_PACKETS ; 0 ; Signed Integer ;; USE_FILL_LEVEL ; 0 ; Signed Integer ;; USE_STORE_FORWARD ; 0 ; Signed Integer ;; USE_ALMOST_FULL_IF ; 0 ; Signed Integer ;; USE_ALMOST_EMPTY_IF ; 0 ; Signed Integer ;; EMPTY_LATENCY ; 0 ; Signed Integer ;; USE_MEMORY_BLOCKS ; 0 ; Signed Integer ;; DATA_WIDTH ; 34 ; Signed Integer ;; EMPTY_WIDTH ; 0 ; Signed Integer ;+---------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_rx_s1_agent ;+---------------------------+-------+------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+---------------------------+-------+------------------------------------------------------------------------------------------------------------------------+; PKT_BEGIN_BURST ; 93 ; Signed Integer ;; PKT_DATA_H ; 31 ; Signed Integer ;; PKT_DATA_L ; 0 ; Signed Integer ;; PKT_SYMBOL_W ; 8 ; Signed Integer ;; PKT_BYTEEN_H ; 35 ; Signed Integer ;; PKT_BYTEEN_L ; 32 ; Signed Integer ;; PKT_ADDR_H ; 65 ; Signed Integer ;; PKT_ADDR_L ; 36 ; Signed Integer ;; PKT_TRANS_LOCK ; 70 ; Signed Integer ;; PKT_TRANS_COMPRESSED_READ ; 66 ; Signed Integer ;; PKT_TRANS_POSTED ; 67 ; Signed Integer ;; PKT_TRANS_WRITE ; 68 ; Signed Integer ;; PKT_TRANS_READ ; 69 ; Signed Integer ;; PKT_SRC_ID_H ; 99 ; Signed Integer ;; PKT_SRC_ID_L ; 95 ; Signed Integer ;; PKT_DEST_ID_H ; 104 ; Signed Integer ;; PKT_DEST_ID_L ; 100 ; Signed Integer ;; PKT_BURSTWRAP_H ; 85 ; Signed Integer ;; PKT_BURSTWRAP_L ; 79 ; Signed Integer ;; PKT_BYTE_CNT_H ; 78 ; Signed Integer ;; PKT_BYTE_CNT_L ; 72 ; Signed Integer ;; PKT_PROTECTION_H ; 119 ; Signed Integer ;; PKT_PROTECTION_L ; 117 ; Signed Integer ;; PKT_RESPONSE_STATUS_H ; 125 ; Signed Integer ;; PKT_RESPONSE_STATUS_L ; 124 ; Signed Integer ;; PKT_BURST_SIZE_H ; 88 ; Signed Integer ;; PKT_BURST_SIZE_L ; 86 ; Signed Integer ;; PKT_ORI_BURST_SIZE_L ; 126 ; Signed Integer ;; PKT_ORI_BURST_SIZE_H ; 128 ; Signed Integer ;; ST_DATA_W ; 129 ; Signed Integer ;; ST_CHANNEL_W ; 22 ; Signed Integer ;; ADDR_W ; 30 ; Signed Integer ;; AVS_DATA_W ; 32 ; Signed Integer ;; AVS_BURSTCOUNT_W ; 3 ; Signed Integer ;; PKT_SYMBOLS ; 4 ; Signed Integer ;; PREVENT_FIFO_OVERFLOW ; 1 ; Signed Integer ;; SUPPRESS_0_BYTEEN_CMD ; 1 ; Signed Integer ;; USE_READRESPONSE ; 0 ; Signed Integer ;; USE_WRITERESPONSE ; 0 ; Signed Integer ;; AVS_BE_W ; 4 ; Signed Integer ;; BURST_SIZE_W ; 3 ; Signed Integer ;; FIFO_DATA_W ; 130 ; Signed Integer ;; ECC_ENABLE ; 0 ; Signed Integer ;+---------------------------+-------+------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_rx_s1_agent|altera_merlin_burst_uncompressor:uncompressor ;+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; ADDR_W ; 30 ; Signed Integer ;; BURSTWRAP_W ; 7 ; Signed Integer ;; BYTE_CNT_W ; 7 ; Signed Integer ;; PKT_SYMBOLS ; 4 ; Signed Integer ;; BURST_SIZE_W ; 3 ; Signed Integer ;+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+-----------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rsp_fifo ;+---------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+---------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------+; SYMBOLS_PER_BEAT ; 1 ; Signed Integer ;; BITS_PER_SYMBOL ; 130 ; Signed Integer ;; FIFO_DEPTH ; 2 ; Signed Integer ;; CHANNEL_WIDTH ; 0 ; Signed Integer ;; ERROR_WIDTH ; 0 ; Signed Integer ;; USE_PACKETS ; 1 ; Signed Integer ;; USE_FILL_LEVEL ; 0 ; Signed Integer ;; USE_STORE_FORWARD ; 0 ; Signed Integer ;; USE_ALMOST_FULL_IF ; 0 ; Signed Integer ;; USE_ALMOST_EMPTY_IF ; 0 ; Signed Integer ;; EMPTY_LATENCY ; 1 ; Signed Integer ;; USE_MEMORY_BLOCKS ; 0 ; Signed Integer ;; DATA_WIDTH ; 130 ; Signed Integer ;; EMPTY_WIDTH ; 0 ; Signed Integer ;+---------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+-------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rdata_fifo ;+---------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+---------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------+; SYMBOLS_PER_BEAT ; 1 ; Signed Integer ;; BITS_PER_SYMBOL ; 34 ; Signed Integer ;; FIFO_DEPTH ; 2 ; Signed Integer ;; CHANNEL_WIDTH ; 0 ; Signed Integer ;; ERROR_WIDTH ; 0 ; Signed Integer ;; USE_PACKETS ; 0 ; Signed Integer ;; USE_FILL_LEVEL ; 0 ; Signed Integer ;; USE_STORE_FORWARD ; 0 ; Signed Integer ;; USE_ALMOST_FULL_IF ; 0 ; Signed Integer ;; USE_ALMOST_EMPTY_IF ; 0 ; Signed Integer ;; EMPTY_LATENCY ; 0 ; Signed Integer ;; USE_MEMORY_BLOCKS ; 0 ; Signed Integer ;; DATA_WIDTH ; 34 ; Signed Integer ;; EMPTY_WIDTH ; 0 ; Signed Integer ;+---------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_ready_rx_s1_agent ;+---------------------------+-------+------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+---------------------------+-------+------------------------------------------------------------------------------------------------------------------------------+; PKT_BEGIN_BURST ; 93 ; Signed Integer ;; PKT_DATA_H ; 31 ; Signed Integer ;; PKT_DATA_L ; 0 ; Signed Integer ;; PKT_SYMBOL_W ; 8 ; Signed Integer ;; PKT_BYTEEN_H ; 35 ; Signed Integer ;; PKT_BYTEEN_L ; 32 ; Signed Integer ;; PKT_ADDR_H ; 65 ; Signed Integer ;; PKT_ADDR_L ; 36 ; Signed Integer ;; PKT_TRANS_LOCK ; 70 ; Signed Integer ;; PKT_TRANS_COMPRESSED_READ ; 66 ; Signed Integer ;; PKT_TRANS_POSTED ; 67 ; Signed Integer ;; PKT_TRANS_WRITE ; 68 ; Signed Integer ;; PKT_TRANS_READ ; 69 ; Signed Integer ;; PKT_SRC_ID_H ; 99 ; Signed Integer ;; PKT_SRC_ID_L ; 95 ; Signed Integer ;; PKT_DEST_ID_H ; 104 ; Signed Integer ;; PKT_DEST_ID_L ; 100 ; Signed Integer ;; PKT_BURSTWRAP_H ; 85 ; Signed Integer ;; PKT_BURSTWRAP_L ; 79 ; Signed Integer ;; PKT_BYTE_CNT_H ; 78 ; Signed Integer ;; PKT_BYTE_CNT_L ; 72 ; Signed Integer ;; PKT_PROTECTION_H ; 119 ; Signed Integer ;; PKT_PROTECTION_L ; 117 ; Signed Integer ;; PKT_RESPONSE_STATUS_H ; 125 ; Signed Integer ;; PKT_RESPONSE_STATUS_L ; 124 ; Signed Integer ;; PKT_BURST_SIZE_H ; 88 ; Signed Integer ;; PKT_BURST_SIZE_L ; 86 ; Signed Integer ;; PKT_ORI_BURST_SIZE_L ; 126 ; Signed Integer ;; PKT_ORI_BURST_SIZE_H ; 128 ; Signed Integer ;; ST_DATA_W ; 129 ; Signed Integer ;; ST_CHANNEL_W ; 22 ; Signed Integer ;; ADDR_W ; 30 ; Signed Integer ;; AVS_DATA_W ; 32 ; Signed Integer ;; AVS_BURSTCOUNT_W ; 3 ; Signed Integer ;; PKT_SYMBOLS ; 4 ; Signed Integer ;; PREVENT_FIFO_OVERFLOW ; 1 ; Signed Integer ;; SUPPRESS_0_BYTEEN_CMD ; 1 ; Signed Integer ;; USE_READRESPONSE ; 0 ; Signed Integer ;; USE_WRITERESPONSE ; 0 ; Signed Integer ;; AVS_BE_W ; 4 ; Signed Integer ;; BURST_SIZE_W ; 3 ; Signed Integer ;; FIFO_DATA_W ; 130 ; Signed Integer ;; ECC_ENABLE ; 0 ; Signed Integer ;+---------------------------+-------+------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_ready_rx_s1_agent|altera_merlin_burst_uncompressor:uncompressor ;+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; ADDR_W ; 30 ; Signed Integer ;; BURSTWRAP_W ; 7 ; Signed Integer ;; BYTE_CNT_W ; 7 ; Signed Integer ;; PKT_SYMBOLS ; 4 ; Signed Integer ;; BURST_SIZE_W ; 3 ; Signed Integer ;+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rsp_fifo ;+---------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+---------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------+; SYMBOLS_PER_BEAT ; 1 ; Signed Integer ;; BITS_PER_SYMBOL ; 130 ; Signed Integer ;; FIFO_DEPTH ; 2 ; Signed Integer ;; CHANNEL_WIDTH ; 0 ; Signed Integer ;; ERROR_WIDTH ; 0 ; Signed Integer ;; USE_PACKETS ; 1 ; Signed Integer ;; USE_FILL_LEVEL ; 0 ; Signed Integer ;; USE_STORE_FORWARD ; 0 ; Signed Integer ;; USE_ALMOST_FULL_IF ; 0 ; Signed Integer ;; USE_ALMOST_EMPTY_IF ; 0 ; Signed Integer ;; EMPTY_LATENCY ; 1 ; Signed Integer ;; USE_MEMORY_BLOCKS ; 0 ; Signed Integer ;; DATA_WIDTH ; 130 ; Signed Integer ;; EMPTY_WIDTH ; 0 ; Signed Integer ;+---------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo ;+---------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+---------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------+; SYMBOLS_PER_BEAT ; 1 ; Signed Integer ;; BITS_PER_SYMBOL ; 34 ; Signed Integer ;; FIFO_DEPTH ; 2 ; Signed Integer ;; CHANNEL_WIDTH ; 0 ; Signed Integer ;; ERROR_WIDTH ; 0 ; Signed Integer ;; USE_PACKETS ; 0 ; Signed Integer ;; USE_FILL_LEVEL ; 0 ; Signed Integer ;; USE_STORE_FORWARD ; 0 ; Signed Integer ;; USE_ALMOST_FULL_IF ; 0 ; Signed Integer ;; USE_ALMOST_EMPTY_IF ; 0 ; Signed Integer ;; EMPTY_LATENCY ; 0 ; Signed Integer ;; USE_MEMORY_BLOCKS ; 0 ; Signed Integer ;; DATA_WIDTH ; 34 ; Signed Integer ;; EMPTY_WIDTH ; 0 ; Signed Integer ;+---------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+-------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:data_flag_rx_s1_agent ;+---------------------------+-------+-------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+---------------------------+-------+-------------------------------------------------------------------------------------------------------------------------+; PKT_BEGIN_BURST ; 93 ; Signed Integer ;; PKT_DATA_H ; 31 ; Signed Integer ;; PKT_DATA_L ; 0 ; Signed Integer ;; PKT_SYMBOL_W ; 8 ; Signed Integer ;; PKT_BYTEEN_H ; 35 ; Signed Integer ;; PKT_BYTEEN_L ; 32 ; Signed Integer ;; PKT_ADDR_H ; 65 ; Signed Integer ;; PKT_ADDR_L ; 36 ; Signed Integer ;; PKT_TRANS_LOCK ; 70 ; Signed Integer ;; PKT_TRANS_COMPRESSED_READ ; 66 ; Signed Integer ;; PKT_TRANS_POSTED ; 67 ; Signed Integer ;; PKT_TRANS_WRITE ; 68 ; Signed Integer ;; PKT_TRANS_READ ; 69 ; Signed Integer ;; PKT_SRC_ID_H ; 99 ; Signed Integer ;; PKT_SRC_ID_L ; 95 ; Signed Integer ;; PKT_DEST_ID_H ; 104 ; Signed Integer ;; PKT_DEST_ID_L ; 100 ; Signed Integer ;; PKT_BURSTWRAP_H ; 85 ; Signed Integer ;; PKT_BURSTWRAP_L ; 79 ; Signed Integer ;; PKT_BYTE_CNT_H ; 78 ; Signed Integer ;; PKT_BYTE_CNT_L ; 72 ; Signed Integer ;; PKT_PROTECTION_H ; 119 ; Signed Integer ;; PKT_PROTECTION_L ; 117 ; Signed Integer ;; PKT_RESPONSE_STATUS_H ; 125 ; Signed Integer ;; PKT_RESPONSE_STATUS_L ; 124 ; Signed Integer ;; PKT_BURST_SIZE_H ; 88 ; Signed Integer ;; PKT_BURST_SIZE_L ; 86 ; Signed Integer ;; PKT_ORI_BURST_SIZE_L ; 126 ; Signed Integer ;; PKT_ORI_BURST_SIZE_H ; 128 ; Signed Integer ;; ST_DATA_W ; 129 ; Signed Integer ;; ST_CHANNEL_W ; 22 ; Signed Integer ;; ADDR_W ; 30 ; Signed Integer ;; AVS_DATA_W ; 32 ; Signed Integer ;; AVS_BURSTCOUNT_W ; 3 ; Signed Integer ;; PKT_SYMBOLS ; 4 ; Signed Integer ;; PREVENT_FIFO_OVERFLOW ; 1 ; Signed Integer ;; SUPPRESS_0_BYTEEN_CMD ; 1 ; Signed Integer ;; USE_READRESPONSE ; 0 ; Signed Integer ;; USE_WRITERESPONSE ; 0 ; Signed Integer ;; AVS_BE_W ; 4 ; Signed Integer ;; BURST_SIZE_W ; 3 ; Signed Integer ;; FIFO_DATA_W ; 130 ; Signed Integer ;; ECC_ENABLE ; 0 ; Signed Integer ;+---------------------------+-------+-------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:data_flag_rx_s1_agent|altera_merlin_burst_uncompressor:uncompressor ;+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; ADDR_W ; 30 ; Signed Integer ;; BURSTWRAP_W ; 7 ; Signed Integer ;; BYTE_CNT_W ; 7 ; Signed Integer ;; PKT_SYMBOLS ; 4 ; Signed Integer ;; BURST_SIZE_W ; 3 ; Signed Integer ;+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rsp_fifo ;+---------------------+-------+------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+---------------------+-------+------------------------------------------------------------------------------------------------------------------------------------+; SYMBOLS_PER_BEAT ; 1 ; Signed Integer ;; BITS_PER_SYMBOL ; 130 ; Signed Integer ;; FIFO_DEPTH ; 2 ; Signed Integer ;; CHANNEL_WIDTH ; 0 ; Signed Integer ;; ERROR_WIDTH ; 0 ; Signed Integer ;; USE_PACKETS ; 1 ; Signed Integer ;; USE_FILL_LEVEL ; 0 ; Signed Integer ;; USE_STORE_FORWARD ; 0 ; Signed Integer ;; USE_ALMOST_FULL_IF ; 0 ; Signed Integer ;; USE_ALMOST_EMPTY_IF ; 0 ; Signed Integer ;; EMPTY_LATENCY ; 1 ; Signed Integer ;; USE_MEMORY_BLOCKS ; 0 ; Signed Integer ;; DATA_WIDTH ; 130 ; Signed Integer ;; EMPTY_WIDTH ; 0 ; Signed Integer ;+---------------------+-------+------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+--------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo ;+---------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+---------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------+; SYMBOLS_PER_BEAT ; 1 ; Signed Integer ;; BITS_PER_SYMBOL ; 34 ; Signed Integer ;; FIFO_DEPTH ; 2 ; Signed Integer ;; CHANNEL_WIDTH ; 0 ; Signed Integer ;; ERROR_WIDTH ; 0 ; Signed Integer ;; USE_PACKETS ; 0 ; Signed Integer ;; USE_FILL_LEVEL ; 0 ; Signed Integer ;; USE_STORE_FORWARD ; 0 ; Signed Integer ;; USE_ALMOST_FULL_IF ; 0 ; Signed Integer ;; USE_ALMOST_EMPTY_IF ; 0 ; Signed Integer ;; EMPTY_LATENCY ; 0 ; Signed Integer ;; USE_MEMORY_BLOCKS ; 0 ; Signed Integer ;; DATA_WIDTH ; 34 ; Signed Integer ;; EMPTY_WIDTH ; 0 ; Signed Integer ;+---------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+----------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:data_read_en_rx_s1_agent ;+---------------------------+-------+----------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+---------------------------+-------+----------------------------------------------------------------------------------------------------------------------------+; PKT_BEGIN_BURST ; 93 ; Signed Integer ;; PKT_DATA_H ; 31 ; Signed Integer ;; PKT_DATA_L ; 0 ; Signed Integer ;; PKT_SYMBOL_W ; 8 ; Signed Integer ;; PKT_BYTEEN_H ; 35 ; Signed Integer ;; PKT_BYTEEN_L ; 32 ; Signed Integer ;; PKT_ADDR_H ; 65 ; Signed Integer ;; PKT_ADDR_L ; 36 ; Signed Integer ;; PKT_TRANS_LOCK ; 70 ; Signed Integer ;; PKT_TRANS_COMPRESSED_READ ; 66 ; Signed Integer ;; PKT_TRANS_POSTED ; 67 ; Signed Integer ;; PKT_TRANS_WRITE ; 68 ; Signed Integer ;; PKT_TRANS_READ ; 69 ; Signed Integer ;; PKT_SRC_ID_H ; 99 ; Signed Integer ;; PKT_SRC_ID_L ; 95 ; Signed Integer ;; PKT_DEST_ID_H ; 104 ; Signed Integer ;; PKT_DEST_ID_L ; 100 ; Signed Integer ;; PKT_BURSTWRAP_H ; 85 ; Signed Integer ;; PKT_BURSTWRAP_L ; 79 ; Signed Integer ;; PKT_BYTE_CNT_H ; 78 ; Signed Integer ;; PKT_BYTE_CNT_L ; 72 ; Signed Integer ;; PKT_PROTECTION_H ; 119 ; Signed Integer ;; PKT_PROTECTION_L ; 117 ; Signed Integer ;; PKT_RESPONSE_STATUS_H ; 125 ; Signed Integer ;; PKT_RESPONSE_STATUS_L ; 124 ; Signed Integer ;; PKT_BURST_SIZE_H ; 88 ; Signed Integer ;; PKT_BURST_SIZE_L ; 86 ; Signed Integer ;; PKT_ORI_BURST_SIZE_L ; 126 ; Signed Integer ;; PKT_ORI_BURST_SIZE_H ; 128 ; Signed Integer ;; ST_DATA_W ; 129 ; Signed Integer ;; ST_CHANNEL_W ; 22 ; Signed Integer ;; ADDR_W ; 30 ; Signed Integer ;; AVS_DATA_W ; 32 ; Signed Integer ;; AVS_BURSTCOUNT_W ; 3 ; Signed Integer ;; PKT_SYMBOLS ; 4 ; Signed Integer ;; PREVENT_FIFO_OVERFLOW ; 1 ; Signed Integer ;; SUPPRESS_0_BYTEEN_CMD ; 1 ; Signed Integer ;; USE_READRESPONSE ; 0 ; Signed Integer ;; USE_WRITERESPONSE ; 0 ; Signed Integer ;; AVS_BE_W ; 4 ; Signed Integer ;; BURST_SIZE_W ; 3 ; Signed Integer ;; FIFO_DATA_W ; 130 ; Signed Integer ;; ECC_ENABLE ; 0 ; Signed Integer ;+---------------------------+-------+----------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:data_read_en_rx_s1_agent|altera_merlin_burst_uncompressor:uncompressor ;+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; ADDR_W ; 30 ; Signed Integer ;; BURSTWRAP_W ; 7 ; Signed Integer ;; BYTE_CNT_W ; 7 ; Signed Integer ;; PKT_SYMBOLS ; 4 ; Signed Integer ;; BURST_SIZE_W ; 3 ; Signed Integer ;+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+---------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rsp_fifo ;+---------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+---------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------+; SYMBOLS_PER_BEAT ; 1 ; Signed Integer ;; BITS_PER_SYMBOL ; 130 ; Signed Integer ;; FIFO_DEPTH ; 2 ; Signed Integer ;; CHANNEL_WIDTH ; 0 ; Signed Integer ;; ERROR_WIDTH ; 0 ; Signed Integer ;; USE_PACKETS ; 1 ; Signed Integer ;; USE_FILL_LEVEL ; 0 ; Signed Integer ;; USE_STORE_FORWARD ; 0 ; Signed Integer ;; USE_ALMOST_FULL_IF ; 0 ; Signed Integer ;; USE_ALMOST_EMPTY_IF ; 0 ; Signed Integer ;; EMPTY_LATENCY ; 1 ; Signed Integer ;; USE_MEMORY_BLOCKS ; 0 ; Signed Integer ;; DATA_WIDTH ; 130 ; Signed Integer ;; EMPTY_WIDTH ; 0 ; Signed Integer ;+---------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo ;+---------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+---------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------+; SYMBOLS_PER_BEAT ; 1 ; Signed Integer ;; BITS_PER_SYMBOL ; 34 ; Signed Integer ;; FIFO_DEPTH ; 2 ; Signed Integer ;; CHANNEL_WIDTH ; 0 ; Signed Integer ;; ERROR_WIDTH ; 0 ; Signed Integer ;; USE_PACKETS ; 0 ; Signed Integer ;; USE_FILL_LEVEL ; 0 ; Signed Integer ;; USE_STORE_FORWARD ; 0 ; Signed Integer ;; USE_ALMOST_FULL_IF ; 0 ; Signed Integer ;; USE_ALMOST_EMPTY_IF ; 0 ; Signed Integer ;; EMPTY_LATENCY ; 0 ; Signed Integer ;; USE_MEMORY_BLOCKS ; 0 ; Signed Integer ;; DATA_WIDTH ; 34 ; Signed Integer ;; EMPTY_WIDTH ; 0 ; Signed Integer ;+---------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+--------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fifo_full_rx_status_s1_agent ;+---------------------------+-------+--------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+---------------------------+-------+--------------------------------------------------------------------------------------------------------------------------------+; PKT_BEGIN_BURST ; 93 ; Signed Integer ;; PKT_DATA_H ; 31 ; Signed Integer ;; PKT_DATA_L ; 0 ; Signed Integer ;; PKT_SYMBOL_W ; 8 ; Signed Integer ;; PKT_BYTEEN_H ; 35 ; Signed Integer ;; PKT_BYTEEN_L ; 32 ; Signed Integer ;; PKT_ADDR_H ; 65 ; Signed Integer ;; PKT_ADDR_L ; 36 ; Signed Integer ;; PKT_TRANS_LOCK ; 70 ; Signed Integer ;; PKT_TRANS_COMPRESSED_READ ; 66 ; Signed Integer ;; PKT_TRANS_POSTED ; 67 ; Signed Integer ;; PKT_TRANS_WRITE ; 68 ; Signed Integer ;; PKT_TRANS_READ ; 69 ; Signed Integer ;; PKT_SRC_ID_H ; 99 ; Signed Integer ;; PKT_SRC_ID_L ; 95 ; Signed Integer ;; PKT_DEST_ID_H ; 104 ; Signed Integer ;; PKT_DEST_ID_L ; 100 ; Signed Integer ;; PKT_BURSTWRAP_H ; 85 ; Signed Integer ;; PKT_BURSTWRAP_L ; 79 ; Signed Integer ;; PKT_BYTE_CNT_H ; 78 ; Signed Integer ;; PKT_BYTE_CNT_L ; 72 ; Signed Integer ;; PKT_PROTECTION_H ; 119 ; Signed Integer ;; PKT_PROTECTION_L ; 117 ; Signed Integer ;; PKT_RESPONSE_STATUS_H ; 125 ; Signed Integer ;; PKT_RESPONSE_STATUS_L ; 124 ; Signed Integer ;; PKT_BURST_SIZE_H ; 88 ; Signed Integer ;; PKT_BURST_SIZE_L ; 86 ; Signed Integer ;; PKT_ORI_BURST_SIZE_L ; 126 ; Signed Integer ;; PKT_ORI_BURST_SIZE_H ; 128 ; Signed Integer ;; ST_DATA_W ; 129 ; Signed Integer ;; ST_CHANNEL_W ; 22 ; Signed Integer ;; ADDR_W ; 30 ; Signed Integer ;; AVS_DATA_W ; 32 ; Signed Integer ;; AVS_BURSTCOUNT_W ; 3 ; Signed Integer ;; PKT_SYMBOLS ; 4 ; Signed Integer ;; PREVENT_FIFO_OVERFLOW ; 1 ; Signed Integer ;; SUPPRESS_0_BYTEEN_CMD ; 1 ; Signed Integer ;; USE_READRESPONSE ; 0 ; Signed Integer ;; USE_WRITERESPONSE ; 0 ; Signed Integer ;; AVS_BE_W ; 4 ; Signed Integer ;; BURST_SIZE_W ; 3 ; Signed Integer ;; FIFO_DATA_W ; 130 ; Signed Integer ;; ECC_ENABLE ; 0 ; Signed Integer ;+---------------------------+-------+--------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fifo_full_rx_status_s1_agent|altera_merlin_burst_uncompressor:uncompressor ;+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; ADDR_W ; 30 ; Signed Integer ;; BURSTWRAP_W ; 7 ; Signed Integer ;; BYTE_CNT_W ; 7 ; Signed Integer ;; PKT_SYMBOLS ; 4 ; Signed Integer ;; BURST_SIZE_W ; 3 ; Signed Integer ;+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rsp_fifo ;+---------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+---------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------+; SYMBOLS_PER_BEAT ; 1 ; Signed Integer ;; BITS_PER_SYMBOL ; 130 ; Signed Integer ;; FIFO_DEPTH ; 2 ; Signed Integer ;; CHANNEL_WIDTH ; 0 ; Signed Integer ;; ERROR_WIDTH ; 0 ; Signed Integer ;; USE_PACKETS ; 1 ; Signed Integer ;; USE_FILL_LEVEL ; 0 ; Signed Integer ;; USE_STORE_FORWARD ; 0 ; Signed Integer ;; USE_ALMOST_FULL_IF ; 0 ; Signed Integer ;; USE_ALMOST_EMPTY_IF ; 0 ; Signed Integer ;; EMPTY_LATENCY ; 1 ; Signed Integer ;; USE_MEMORY_BLOCKS ; 0 ; Signed Integer ;; DATA_WIDTH ; 130 ; Signed Integer ;; EMPTY_WIDTH ; 0 ; Signed Integer ;+---------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo ;+---------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+---------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------+; SYMBOLS_PER_BEAT ; 1 ; Signed Integer ;; BITS_PER_SYMBOL ; 34 ; Signed Integer ;; FIFO_DEPTH ; 2 ; Signed Integer ;; CHANNEL_WIDTH ; 0 ; Signed Integer ;; ERROR_WIDTH ; 0 ; Signed Integer ;; USE_PACKETS ; 0 ; Signed Integer ;; USE_FILL_LEVEL ; 0 ; Signed Integer ;; USE_STORE_FORWARD ; 0 ; Signed Integer ;; USE_ALMOST_FULL_IF ; 0 ; Signed Integer ;; USE_ALMOST_EMPTY_IF ; 0 ; Signed Integer ;; EMPTY_LATENCY ; 0 ; Signed Integer ;; USE_MEMORY_BLOCKS ; 0 ; Signed Integer ;; DATA_WIDTH ; 34 ; Signed Integer ;; EMPTY_WIDTH ; 0 ; Signed Integer ;+---------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+---------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fifo_empty_rx_status_s1_agent ;+---------------------------+-------+---------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+---------------------------+-------+---------------------------------------------------------------------------------------------------------------------------------+; PKT_BEGIN_BURST ; 93 ; Signed Integer ;; PKT_DATA_H ; 31 ; Signed Integer ;; PKT_DATA_L ; 0 ; Signed Integer ;; PKT_SYMBOL_W ; 8 ; Signed Integer ;; PKT_BYTEEN_H ; 35 ; Signed Integer ;; PKT_BYTEEN_L ; 32 ; Signed Integer ;; PKT_ADDR_H ; 65 ; Signed Integer ;; PKT_ADDR_L ; 36 ; Signed Integer ;; PKT_TRANS_LOCK ; 70 ; Signed Integer ;; PKT_TRANS_COMPRESSED_READ ; 66 ; Signed Integer ;; PKT_TRANS_POSTED ; 67 ; Signed Integer ;; PKT_TRANS_WRITE ; 68 ; Signed Integer ;; PKT_TRANS_READ ; 69 ; Signed Integer ;; PKT_SRC_ID_H ; 99 ; Signed Integer ;; PKT_SRC_ID_L ; 95 ; Signed Integer ;; PKT_DEST_ID_H ; 104 ; Signed Integer ;; PKT_DEST_ID_L ; 100 ; Signed Integer ;; PKT_BURSTWRAP_H ; 85 ; Signed Integer ;; PKT_BURSTWRAP_L ; 79 ; Signed Integer ;; PKT_BYTE_CNT_H ; 78 ; Signed Integer ;; PKT_BYTE_CNT_L ; 72 ; Signed Integer ;; PKT_PROTECTION_H ; 119 ; Signed Integer ;; PKT_PROTECTION_L ; 117 ; Signed Integer ;; PKT_RESPONSE_STATUS_H ; 125 ; Signed Integer ;; PKT_RESPONSE_STATUS_L ; 124 ; Signed Integer ;; PKT_BURST_SIZE_H ; 88 ; Signed Integer ;; PKT_BURST_SIZE_L ; 86 ; Signed Integer ;; PKT_ORI_BURST_SIZE_L ; 126 ; Signed Integer ;; PKT_ORI_BURST_SIZE_H ; 128 ; Signed Integer ;; ST_DATA_W ; 129 ; Signed Integer ;; ST_CHANNEL_W ; 22 ; Signed Integer ;; ADDR_W ; 30 ; Signed Integer ;; AVS_DATA_W ; 32 ; Signed Integer ;; AVS_BURSTCOUNT_W ; 3 ; Signed Integer ;; PKT_SYMBOLS ; 4 ; Signed Integer ;; PREVENT_FIFO_OVERFLOW ; 1 ; Signed Integer ;; SUPPRESS_0_BYTEEN_CMD ; 1 ; Signed Integer ;; USE_READRESPONSE ; 0 ; Signed Integer ;; USE_WRITERESPONSE ; 0 ; Signed Integer ;; AVS_BE_W ; 4 ; Signed Integer ;; BURST_SIZE_W ; 3 ; Signed Integer ;; FIFO_DATA_W ; 130 ; Signed Integer ;; ECC_ENABLE ; 0 ; Signed Integer ;+---------------------------+-------+---------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fifo_empty_rx_status_s1_agent|altera_merlin_burst_uncompressor:uncompressor ;+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; ADDR_W ; 30 ; Signed Integer ;; BURSTWRAP_W ; 7 ; Signed Integer ;; BYTE_CNT_W ; 7 ; Signed Integer ;; PKT_SYMBOLS ; 4 ; Signed Integer ;; BURST_SIZE_W ; 3 ; Signed Integer ;+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rsp_fifo ;+---------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+---------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------+; SYMBOLS_PER_BEAT ; 1 ; Signed Integer ;; BITS_PER_SYMBOL ; 130 ; Signed Integer ;; FIFO_DEPTH ; 2 ; Signed Integer ;; CHANNEL_WIDTH ; 0 ; Signed Integer ;; ERROR_WIDTH ; 0 ; Signed Integer ;; USE_PACKETS ; 1 ; Signed Integer ;; USE_FILL_LEVEL ; 0 ; Signed Integer ;; USE_STORE_FORWARD ; 0 ; Signed Integer ;; USE_ALMOST_FULL_IF ; 0 ; Signed Integer ;; USE_ALMOST_EMPTY_IF ; 0 ; Signed Integer ;; EMPTY_LATENCY ; 1 ; Signed Integer ;; USE_MEMORY_BLOCKS ; 0 ; Signed Integer ;; DATA_WIDTH ; 130 ; Signed Integer ;; EMPTY_WIDTH ; 0 ; Signed Integer ;+---------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo ;+---------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+---------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------+; SYMBOLS_PER_BEAT ; 1 ; Signed Integer ;; BITS_PER_SYMBOL ; 34 ; Signed Integer ;; FIFO_DEPTH ; 2 ; Signed Integer ;; CHANNEL_WIDTH ; 0 ; Signed Integer ;; ERROR_WIDTH ; 0 ; Signed Integer ;; USE_PACKETS ; 0 ; Signed Integer ;; USE_FILL_LEVEL ; 0 ; Signed Integer ;; USE_STORE_FORWARD ; 0 ; Signed Integer ;; USE_ALMOST_FULL_IF ; 0 ; Signed Integer ;; USE_ALMOST_EMPTY_IF ; 0 ; Signed Integer ;; EMPTY_LATENCY ; 0 ; Signed Integer ;; USE_MEMORY_BLOCKS ; 0 ; Signed Integer ;; DATA_WIDTH ; 34 ; Signed Integer ;; EMPTY_WIDTH ; 0 ; Signed Integer ;+---------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+-----------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:link_start_s1_agent ;+---------------------------+-------+-----------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+---------------------------+-------+-----------------------------------------------------------------------------------------------------------------------+; PKT_BEGIN_BURST ; 93 ; Signed Integer ;; PKT_DATA_H ; 31 ; Signed Integer ;; PKT_DATA_L ; 0 ; Signed Integer ;; PKT_SYMBOL_W ; 8 ; Signed Integer ;; PKT_BYTEEN_H ; 35 ; Signed Integer ;; PKT_BYTEEN_L ; 32 ; Signed Integer ;; PKT_ADDR_H ; 65 ; Signed Integer ;; PKT_ADDR_L ; 36 ; Signed Integer ;; PKT_TRANS_LOCK ; 70 ; Signed Integer ;; PKT_TRANS_COMPRESSED_READ ; 66 ; Signed Integer ;; PKT_TRANS_POSTED ; 67 ; Signed Integer ;; PKT_TRANS_WRITE ; 68 ; Signed Integer ;; PKT_TRANS_READ ; 69 ; Signed Integer ;; PKT_SRC_ID_H ; 99 ; Signed Integer ;; PKT_SRC_ID_L ; 95 ; Signed Integer ;; PKT_DEST_ID_H ; 104 ; Signed Integer ;; PKT_DEST_ID_L ; 100 ; Signed Integer ;; PKT_BURSTWRAP_H ; 85 ; Signed Integer ;; PKT_BURSTWRAP_L ; 79 ; Signed Integer ;; PKT_BYTE_CNT_H ; 78 ; Signed Integer ;; PKT_BYTE_CNT_L ; 72 ; Signed Integer ;; PKT_PROTECTION_H ; 119 ; Signed Integer ;; PKT_PROTECTION_L ; 117 ; Signed Integer ;; PKT_RESPONSE_STATUS_H ; 125 ; Signed Integer ;; PKT_RESPONSE_STATUS_L ; 124 ; Signed Integer ;; PKT_BURST_SIZE_H ; 88 ; Signed Integer ;; PKT_BURST_SIZE_L ; 86 ; Signed Integer ;; PKT_ORI_BURST_SIZE_L ; 126 ; Signed Integer ;; PKT_ORI_BURST_SIZE_H ; 128 ; Signed Integer ;; ST_DATA_W ; 129 ; Signed Integer ;; ST_CHANNEL_W ; 22 ; Signed Integer ;; ADDR_W ; 30 ; Signed Integer ;; AVS_DATA_W ; 32 ; Signed Integer ;; AVS_BURSTCOUNT_W ; 3 ; Signed Integer ;; PKT_SYMBOLS ; 4 ; Signed Integer ;; PREVENT_FIFO_OVERFLOW ; 1 ; Signed Integer ;; SUPPRESS_0_BYTEEN_CMD ; 1 ; Signed Integer ;; USE_READRESPONSE ; 0 ; Signed Integer ;; USE_WRITERESPONSE ; 0 ; Signed Integer ;; AVS_BE_W ; 4 ; Signed Integer ;; BURST_SIZE_W ; 3 ; Signed Integer ;; FIFO_DATA_W ; 130 ; Signed Integer ;; ECC_ENABLE ; 0 ; Signed Integer ;+---------------------------+-------+-----------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:link_start_s1_agent|altera_merlin_burst_uncompressor:uncompressor ;+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; ADDR_W ; 30 ; Signed Integer ;; BURSTWRAP_W ; 7 ; Signed Integer ;; BYTE_CNT_W ; 7 ; Signed Integer ;; PKT_SYMBOLS ; 4 ; Signed Integer ;; BURST_SIZE_W ; 3 ; Signed Integer ;+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+----------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rsp_fifo ;+---------------------+-------+----------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+---------------------+-------+----------------------------------------------------------------------------------------------------------------------------------+; SYMBOLS_PER_BEAT ; 1 ; Signed Integer ;; BITS_PER_SYMBOL ; 130 ; Signed Integer ;; FIFO_DEPTH ; 2 ; Signed Integer ;; CHANNEL_WIDTH ; 0 ; Signed Integer ;; ERROR_WIDTH ; 0 ; Signed Integer ;; USE_PACKETS ; 1 ; Signed Integer ;; USE_FILL_LEVEL ; 0 ; Signed Integer ;; USE_STORE_FORWARD ; 0 ; Signed Integer ;; USE_ALMOST_FULL_IF ; 0 ; Signed Integer ;; USE_ALMOST_EMPTY_IF ; 0 ; Signed Integer ;; EMPTY_LATENCY ; 1 ; Signed Integer ;; USE_MEMORY_BLOCKS ; 0 ; Signed Integer ;; DATA_WIDTH ; 130 ; Signed Integer ;; EMPTY_WIDTH ; 0 ; Signed Integer ;+---------------------+-------+----------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo ;+---------------------+-------+------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+---------------------+-------+------------------------------------------------------------------------------------------------------------------------------------+; SYMBOLS_PER_BEAT ; 1 ; Signed Integer ;; BITS_PER_SYMBOL ; 34 ; Signed Integer ;; FIFO_DEPTH ; 2 ; Signed Integer ;; CHANNEL_WIDTH ; 0 ; Signed Integer ;; ERROR_WIDTH ; 0 ; Signed Integer ;; USE_PACKETS ; 0 ; Signed Integer ;; USE_FILL_LEVEL ; 0 ; Signed Integer ;; USE_STORE_FORWARD ; 0 ; Signed Integer ;; USE_ALMOST_FULL_IF ; 0 ; Signed Integer ;; USE_ALMOST_EMPTY_IF ; 0 ; Signed Integer ;; EMPTY_LATENCY ; 0 ; Signed Integer ;; USE_MEMORY_BLOCKS ; 0 ; Signed Integer ;; DATA_WIDTH ; 34 ; Signed Integer ;; EMPTY_WIDTH ; 0 ; Signed Integer ;+---------------------+-------+------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+-----------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:auto_start_s1_agent ;+---------------------------+-------+-----------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+---------------------------+-------+-----------------------------------------------------------------------------------------------------------------------+; PKT_BEGIN_BURST ; 93 ; Signed Integer ;; PKT_DATA_H ; 31 ; Signed Integer ;; PKT_DATA_L ; 0 ; Signed Integer ;; PKT_SYMBOL_W ; 8 ; Signed Integer ;; PKT_BYTEEN_H ; 35 ; Signed Integer ;; PKT_BYTEEN_L ; 32 ; Signed Integer ;; PKT_ADDR_H ; 65 ; Signed Integer ;; PKT_ADDR_L ; 36 ; Signed Integer ;; PKT_TRANS_LOCK ; 70 ; Signed Integer ;; PKT_TRANS_COMPRESSED_READ ; 66 ; Signed Integer ;; PKT_TRANS_POSTED ; 67 ; Signed Integer ;; PKT_TRANS_WRITE ; 68 ; Signed Integer ;; PKT_TRANS_READ ; 69 ; Signed Integer ;; PKT_SRC_ID_H ; 99 ; Signed Integer ;; PKT_SRC_ID_L ; 95 ; Signed Integer ;; PKT_DEST_ID_H ; 104 ; Signed Integer ;; PKT_DEST_ID_L ; 100 ; Signed Integer ;; PKT_BURSTWRAP_H ; 85 ; Signed Integer ;; PKT_BURSTWRAP_L ; 79 ; Signed Integer ;; PKT_BYTE_CNT_H ; 78 ; Signed Integer ;; PKT_BYTE_CNT_L ; 72 ; Signed Integer ;; PKT_PROTECTION_H ; 119 ; Signed Integer ;; PKT_PROTECTION_L ; 117 ; Signed Integer ;; PKT_RESPONSE_STATUS_H ; 125 ; Signed Integer ;; PKT_RESPONSE_STATUS_L ; 124 ; Signed Integer ;; PKT_BURST_SIZE_H ; 88 ; Signed Integer ;; PKT_BURST_SIZE_L ; 86 ; Signed Integer ;; PKT_ORI_BURST_SIZE_L ; 126 ; Signed Integer ;; PKT_ORI_BURST_SIZE_H ; 128 ; Signed Integer ;; ST_DATA_W ; 129 ; Signed Integer ;; ST_CHANNEL_W ; 22 ; Signed Integer ;; ADDR_W ; 30 ; Signed Integer ;; AVS_DATA_W ; 32 ; Signed Integer ;; AVS_BURSTCOUNT_W ; 3 ; Signed Integer ;; PKT_SYMBOLS ; 4 ; Signed Integer ;; PREVENT_FIFO_OVERFLOW ; 1 ; Signed Integer ;; SUPPRESS_0_BYTEEN_CMD ; 1 ; Signed Integer ;; USE_READRESPONSE ; 0 ; Signed Integer ;; USE_WRITERESPONSE ; 0 ; Signed Integer ;; AVS_BE_W ; 4 ; Signed Integer ;; BURST_SIZE_W ; 3 ; Signed Integer ;; FIFO_DATA_W ; 130 ; Signed Integer ;; ECC_ENABLE ; 0 ; Signed Integer ;+---------------------------+-------+-----------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:auto_start_s1_agent|altera_merlin_burst_uncompressor:uncompressor ;+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; ADDR_W ; 30 ; Signed Integer ;; BURSTWRAP_W ; 7 ; Signed Integer ;; BYTE_CNT_W ; 7 ; Signed Integer ;; PKT_SYMBOLS ; 4 ; Signed Integer ;; BURST_SIZE_W ; 3 ; Signed Integer ;+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+----------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rsp_fifo ;+---------------------+-------+----------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+---------------------+-------+----------------------------------------------------------------------------------------------------------------------------------+; SYMBOLS_PER_BEAT ; 1 ; Signed Integer ;; BITS_PER_SYMBOL ; 130 ; Signed Integer ;; FIFO_DEPTH ; 2 ; Signed Integer ;; CHANNEL_WIDTH ; 0 ; Signed Integer ;; ERROR_WIDTH ; 0 ; Signed Integer ;; USE_PACKETS ; 1 ; Signed Integer ;; USE_FILL_LEVEL ; 0 ; Signed Integer ;; USE_STORE_FORWARD ; 0 ; Signed Integer ;; USE_ALMOST_FULL_IF ; 0 ; Signed Integer ;; USE_ALMOST_EMPTY_IF ; 0 ; Signed Integer ;; EMPTY_LATENCY ; 1 ; Signed Integer ;; USE_MEMORY_BLOCKS ; 0 ; Signed Integer ;; DATA_WIDTH ; 130 ; Signed Integer ;; EMPTY_WIDTH ; 0 ; Signed Integer ;+---------------------+-------+----------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo ;+---------------------+-------+------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+---------------------+-------+------------------------------------------------------------------------------------------------------------------------------------+; SYMBOLS_PER_BEAT ; 1 ; Signed Integer ;; BITS_PER_SYMBOL ; 34 ; Signed Integer ;; FIFO_DEPTH ; 2 ; Signed Integer ;; CHANNEL_WIDTH ; 0 ; Signed Integer ;; ERROR_WIDTH ; 0 ; Signed Integer ;; USE_PACKETS ; 0 ; Signed Integer ;; USE_FILL_LEVEL ; 0 ; Signed Integer ;; USE_STORE_FORWARD ; 0 ; Signed Integer ;; USE_ALMOST_FULL_IF ; 0 ; Signed Integer ;; USE_ALMOST_EMPTY_IF ; 0 ; Signed Integer ;; EMPTY_LATENCY ; 0 ; Signed Integer ;; USE_MEMORY_BLOCKS ; 0 ; Signed Integer ;; DATA_WIDTH ; 34 ; Signed Integer ;; EMPTY_WIDTH ; 0 ; Signed Integer ;+---------------------+-------+------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+-------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:link_disable_s1_agent ;+---------------------------+-------+-------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+---------------------------+-------+-------------------------------------------------------------------------------------------------------------------------+; PKT_BEGIN_BURST ; 93 ; Signed Integer ;; PKT_DATA_H ; 31 ; Signed Integer ;; PKT_DATA_L ; 0 ; Signed Integer ;; PKT_SYMBOL_W ; 8 ; Signed Integer ;; PKT_BYTEEN_H ; 35 ; Signed Integer ;; PKT_BYTEEN_L ; 32 ; Signed Integer ;; PKT_ADDR_H ; 65 ; Signed Integer ;; PKT_ADDR_L ; 36 ; Signed Integer ;; PKT_TRANS_LOCK ; 70 ; Signed Integer ;; PKT_TRANS_COMPRESSED_READ ; 66 ; Signed Integer ;; PKT_TRANS_POSTED ; 67 ; Signed Integer ;; PKT_TRANS_WRITE ; 68 ; Signed Integer ;; PKT_TRANS_READ ; 69 ; Signed Integer ;; PKT_SRC_ID_H ; 99 ; Signed Integer ;; PKT_SRC_ID_L ; 95 ; Signed Integer ;; PKT_DEST_ID_H ; 104 ; Signed Integer ;; PKT_DEST_ID_L ; 100 ; Signed Integer ;; PKT_BURSTWRAP_H ; 85 ; Signed Integer ;; PKT_BURSTWRAP_L ; 79 ; Signed Integer ;; PKT_BYTE_CNT_H ; 78 ; Signed Integer ;; PKT_BYTE_CNT_L ; 72 ; Signed Integer ;; PKT_PROTECTION_H ; 119 ; Signed Integer ;; PKT_PROTECTION_L ; 117 ; Signed Integer ;; PKT_RESPONSE_STATUS_H ; 125 ; Signed Integer ;; PKT_RESPONSE_STATUS_L ; 124 ; Signed Integer ;; PKT_BURST_SIZE_H ; 88 ; Signed Integer ;; PKT_BURST_SIZE_L ; 86 ; Signed Integer ;; PKT_ORI_BURST_SIZE_L ; 126 ; Signed Integer ;; PKT_ORI_BURST_SIZE_H ; 128 ; Signed Integer ;; ST_DATA_W ; 129 ; Signed Integer ;; ST_CHANNEL_W ; 22 ; Signed Integer ;; ADDR_W ; 30 ; Signed Integer ;; AVS_DATA_W ; 32 ; Signed Integer ;; AVS_BURSTCOUNT_W ; 3 ; Signed Integer ;; PKT_SYMBOLS ; 4 ; Signed Integer ;; PREVENT_FIFO_OVERFLOW ; 1 ; Signed Integer ;; SUPPRESS_0_BYTEEN_CMD ; 1 ; Signed Integer ;; USE_READRESPONSE ; 0 ; Signed Integer ;; USE_WRITERESPONSE ; 0 ; Signed Integer ;; AVS_BE_W ; 4 ; Signed Integer ;; BURST_SIZE_W ; 3 ; Signed Integer ;; FIFO_DATA_W ; 130 ; Signed Integer ;; ECC_ENABLE ; 0 ; Signed Integer ;+---------------------------+-------+-------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:link_disable_s1_agent|altera_merlin_burst_uncompressor:uncompressor ;+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; ADDR_W ; 30 ; Signed Integer ;; BURSTWRAP_W ; 7 ; Signed Integer ;; BYTE_CNT_W ; 7 ; Signed Integer ;; PKT_SYMBOLS ; 4 ; Signed Integer ;; BURST_SIZE_W ; 3 ; Signed Integer ;+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rsp_fifo ;+---------------------+-------+------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+---------------------+-------+------------------------------------------------------------------------------------------------------------------------------------+; SYMBOLS_PER_BEAT ; 1 ; Signed Integer ;; BITS_PER_SYMBOL ; 130 ; Signed Integer ;; FIFO_DEPTH ; 2 ; Signed Integer ;; CHANNEL_WIDTH ; 0 ; Signed Integer ;; ERROR_WIDTH ; 0 ; Signed Integer ;; USE_PACKETS ; 1 ; Signed Integer ;; USE_FILL_LEVEL ; 0 ; Signed Integer ;; USE_STORE_FORWARD ; 0 ; Signed Integer ;; USE_ALMOST_FULL_IF ; 0 ; Signed Integer ;; USE_ALMOST_EMPTY_IF ; 0 ; Signed Integer ;; EMPTY_LATENCY ; 1 ; Signed Integer ;; USE_MEMORY_BLOCKS ; 0 ; Signed Integer ;; DATA_WIDTH ; 130 ; Signed Integer ;; EMPTY_WIDTH ; 0 ; Signed Integer ;+---------------------+-------+------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+--------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo ;+---------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+---------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------+; SYMBOLS_PER_BEAT ; 1 ; Signed Integer ;; BITS_PER_SYMBOL ; 34 ; Signed Integer ;; FIFO_DEPTH ; 2 ; Signed Integer ;; CHANNEL_WIDTH ; 0 ; Signed Integer ;; ERROR_WIDTH ; 0 ; Signed Integer ;; USE_PACKETS ; 0 ; Signed Integer ;; USE_FILL_LEVEL ; 0 ; Signed Integer ;; USE_STORE_FORWARD ; 0 ; Signed Integer ;; USE_ALMOST_FULL_IF ; 0 ; Signed Integer ;; USE_ALMOST_EMPTY_IF ; 0 ; Signed Integer ;; EMPTY_LATENCY ; 0 ; Signed Integer ;; USE_MEMORY_BLOCKS ; 0 ; Signed Integer ;; DATA_WIDTH ; 34 ; Signed Integer ;; EMPTY_WIDTH ; 0 ; Signed Integer ;+---------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+-------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:write_data_fifo_tx_s1_agent ;+---------------------------+-------+-------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+---------------------------+-------+-------------------------------------------------------------------------------------------------------------------------------+; PKT_BEGIN_BURST ; 93 ; Signed Integer ;; PKT_DATA_H ; 31 ; Signed Integer ;; PKT_DATA_L ; 0 ; Signed Integer ;; PKT_SYMBOL_W ; 8 ; Signed Integer ;; PKT_BYTEEN_H ; 35 ; Signed Integer ;; PKT_BYTEEN_L ; 32 ; Signed Integer ;; PKT_ADDR_H ; 65 ; Signed Integer ;; PKT_ADDR_L ; 36 ; Signed Integer ;; PKT_TRANS_LOCK ; 70 ; Signed Integer ;; PKT_TRANS_COMPRESSED_READ ; 66 ; Signed Integer ;; PKT_TRANS_POSTED ; 67 ; Signed Integer ;; PKT_TRANS_WRITE ; 68 ; Signed Integer ;; PKT_TRANS_READ ; 69 ; Signed Integer ;; PKT_SRC_ID_H ; 99 ; Signed Integer ;; PKT_SRC_ID_L ; 95 ; Signed Integer ;; PKT_DEST_ID_H ; 104 ; Signed Integer ;; PKT_DEST_ID_L ; 100 ; Signed Integer ;; PKT_BURSTWRAP_H ; 85 ; Signed Integer ;; PKT_BURSTWRAP_L ; 79 ; Signed Integer ;; PKT_BYTE_CNT_H ; 78 ; Signed Integer ;; PKT_BYTE_CNT_L ; 72 ; Signed Integer ;; PKT_PROTECTION_H ; 119 ; Signed Integer ;; PKT_PROTECTION_L ; 117 ; Signed Integer ;; PKT_RESPONSE_STATUS_H ; 125 ; Signed Integer ;; PKT_RESPONSE_STATUS_L ; 124 ; Signed Integer ;; PKT_BURST_SIZE_H ; 88 ; Signed Integer ;; PKT_BURST_SIZE_L ; 86 ; Signed Integer ;; PKT_ORI_BURST_SIZE_L ; 126 ; Signed Integer ;; PKT_ORI_BURST_SIZE_H ; 128 ; Signed Integer ;; ST_DATA_W ; 129 ; Signed Integer ;; ST_CHANNEL_W ; 22 ; Signed Integer ;; ADDR_W ; 30 ; Signed Integer ;; AVS_DATA_W ; 32 ; Signed Integer ;; AVS_BURSTCOUNT_W ; 3 ; Signed Integer ;; PKT_SYMBOLS ; 4 ; Signed Integer ;; PREVENT_FIFO_OVERFLOW ; 1 ; Signed Integer ;; SUPPRESS_0_BYTEEN_CMD ; 1 ; Signed Integer ;; USE_READRESPONSE ; 0 ; Signed Integer ;; USE_WRITERESPONSE ; 0 ; Signed Integer ;; AVS_BE_W ; 4 ; Signed Integer ;; BURST_SIZE_W ; 3 ; Signed Integer ;; FIFO_DATA_W ; 130 ; Signed Integer ;; ECC_ENABLE ; 0 ; Signed Integer ;+---------------------------+-------+-------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:write_data_fifo_tx_s1_agent|altera_merlin_burst_uncompressor:uncompressor ;+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; ADDR_W ; 30 ; Signed Integer ;; BURSTWRAP_W ; 7 ; Signed Integer ;; BYTE_CNT_W ; 7 ; Signed Integer ;; PKT_SYMBOLS ; 4 ; Signed Integer ;; BURST_SIZE_W ; 3 ; Signed Integer ;+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rsp_fifo ;+---------------------+-------+------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+---------------------+-------+------------------------------------------------------------------------------------------------------------------------------------------+; SYMBOLS_PER_BEAT ; 1 ; Signed Integer ;; BITS_PER_SYMBOL ; 130 ; Signed Integer ;; FIFO_DEPTH ; 2 ; Signed Integer ;; CHANNEL_WIDTH ; 0 ; Signed Integer ;; ERROR_WIDTH ; 0 ; Signed Integer ;; USE_PACKETS ; 1 ; Signed Integer ;; USE_FILL_LEVEL ; 0 ; Signed Integer ;; USE_STORE_FORWARD ; 0 ; Signed Integer ;; USE_ALMOST_FULL_IF ; 0 ; Signed Integer ;; USE_ALMOST_EMPTY_IF ; 0 ; Signed Integer ;; EMPTY_LATENCY ; 1 ; Signed Integer ;; USE_MEMORY_BLOCKS ; 0 ; Signed Integer ;; DATA_WIDTH ; 130 ; Signed Integer ;; EMPTY_WIDTH ; 0 ; Signed Integer ;+---------------------+-------+------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rdata_fifo ;+---------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+---------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------+; SYMBOLS_PER_BEAT ; 1 ; Signed Integer ;; BITS_PER_SYMBOL ; 34 ; Signed Integer ;; FIFO_DEPTH ; 2 ; Signed Integer ;; CHANNEL_WIDTH ; 0 ; Signed Integer ;; ERROR_WIDTH ; 0 ; Signed Integer ;; USE_PACKETS ; 0 ; Signed Integer ;; USE_FILL_LEVEL ; 0 ; Signed Integer ;; USE_STORE_FORWARD ; 0 ; Signed Integer ;; USE_ALMOST_FULL_IF ; 0 ; Signed Integer ;; USE_ALMOST_EMPTY_IF ; 0 ; Signed Integer ;; EMPTY_LATENCY ; 0 ; Signed Integer ;; USE_MEMORY_BLOCKS ; 0 ; Signed Integer ;; DATA_WIDTH ; 34 ; Signed Integer ;; EMPTY_WIDTH ; 0 ; Signed Integer ;+---------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:write_en_tx_s1_agent ;+---------------------------+-------+------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+---------------------------+-------+------------------------------------------------------------------------------------------------------------------------+; PKT_BEGIN_BURST ; 93 ; Signed Integer ;; PKT_DATA_H ; 31 ; Signed Integer ;; PKT_DATA_L ; 0 ; Signed Integer ;; PKT_SYMBOL_W ; 8 ; Signed Integer ;; PKT_BYTEEN_H ; 35 ; Signed Integer ;; PKT_BYTEEN_L ; 32 ; Signed Integer ;; PKT_ADDR_H ; 65 ; Signed Integer ;; PKT_ADDR_L ; 36 ; Signed Integer ;; PKT_TRANS_LOCK ; 70 ; Signed Integer ;; PKT_TRANS_COMPRESSED_READ ; 66 ; Signed Integer ;; PKT_TRANS_POSTED ; 67 ; Signed Integer ;; PKT_TRANS_WRITE ; 68 ; Signed Integer ;; PKT_TRANS_READ ; 69 ; Signed Integer ;; PKT_SRC_ID_H ; 99 ; Signed Integer ;; PKT_SRC_ID_L ; 95 ; Signed Integer ;; PKT_DEST_ID_H ; 104 ; Signed Integer ;; PKT_DEST_ID_L ; 100 ; Signed Integer ;; PKT_BURSTWRAP_H ; 85 ; Signed Integer ;; PKT_BURSTWRAP_L ; 79 ; Signed Integer ;; PKT_BYTE_CNT_H ; 78 ; Signed Integer ;; PKT_BYTE_CNT_L ; 72 ; Signed Integer ;; PKT_PROTECTION_H ; 119 ; Signed Integer ;; PKT_PROTECTION_L ; 117 ; Signed Integer ;; PKT_RESPONSE_STATUS_H ; 125 ; Signed Integer ;; PKT_RESPONSE_STATUS_L ; 124 ; Signed Integer ;; PKT_BURST_SIZE_H ; 88 ; Signed Integer ;; PKT_BURST_SIZE_L ; 86 ; Signed Integer ;; PKT_ORI_BURST_SIZE_L ; 126 ; Signed Integer ;; PKT_ORI_BURST_SIZE_H ; 128 ; Signed Integer ;; ST_DATA_W ; 129 ; Signed Integer ;; ST_CHANNEL_W ; 22 ; Signed Integer ;; ADDR_W ; 30 ; Signed Integer ;; AVS_DATA_W ; 32 ; Signed Integer ;; AVS_BURSTCOUNT_W ; 3 ; Signed Integer ;; PKT_SYMBOLS ; 4 ; Signed Integer ;; PREVENT_FIFO_OVERFLOW ; 1 ; Signed Integer ;; SUPPRESS_0_BYTEEN_CMD ; 1 ; Signed Integer ;; USE_READRESPONSE ; 0 ; Signed Integer ;; USE_WRITERESPONSE ; 0 ; Signed Integer ;; AVS_BE_W ; 4 ; Signed Integer ;; BURST_SIZE_W ; 3 ; Signed Integer ;; FIFO_DATA_W ; 130 ; Signed Integer ;; ECC_ENABLE ; 0 ; Signed Integer ;+---------------------------+-------+------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:write_en_tx_s1_agent|altera_merlin_burst_uncompressor:uncompressor ;+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; ADDR_W ; 30 ; Signed Integer ;; BURSTWRAP_W ; 7 ; Signed Integer ;; BYTE_CNT_W ; 7 ; Signed Integer ;; PKT_SYMBOLS ; 4 ; Signed Integer ;; BURST_SIZE_W ; 3 ; Signed Integer ;+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+-----------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rsp_fifo ;+---------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+---------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------+; SYMBOLS_PER_BEAT ; 1 ; Signed Integer ;; BITS_PER_SYMBOL ; 130 ; Signed Integer ;; FIFO_DEPTH ; 2 ; Signed Integer ;; CHANNEL_WIDTH ; 0 ; Signed Integer ;; ERROR_WIDTH ; 0 ; Signed Integer ;; USE_PACKETS ; 1 ; Signed Integer ;; USE_FILL_LEVEL ; 0 ; Signed Integer ;; USE_STORE_FORWARD ; 0 ; Signed Integer ;; USE_ALMOST_FULL_IF ; 0 ; Signed Integer ;; USE_ALMOST_EMPTY_IF ; 0 ; Signed Integer ;; EMPTY_LATENCY ; 1 ; Signed Integer ;; USE_MEMORY_BLOCKS ; 0 ; Signed Integer ;; DATA_WIDTH ; 130 ; Signed Integer ;; EMPTY_WIDTH ; 0 ; Signed Integer ;+---------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+-------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo ;+---------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+---------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------+; SYMBOLS_PER_BEAT ; 1 ; Signed Integer ;; BITS_PER_SYMBOL ; 34 ; Signed Integer ;; FIFO_DEPTH ; 2 ; Signed Integer ;; CHANNEL_WIDTH ; 0 ; Signed Integer ;; ERROR_WIDTH ; 0 ; Signed Integer ;; USE_PACKETS ; 0 ; Signed Integer ;; USE_FILL_LEVEL ; 0 ; Signed Integer ;; USE_STORE_FORWARD ; 0 ; Signed Integer ;; USE_ALMOST_FULL_IF ; 0 ; Signed Integer ;; USE_ALMOST_EMPTY_IF ; 0 ; Signed Integer ;; EMPTY_LATENCY ; 0 ; Signed Integer ;; USE_MEMORY_BLOCKS ; 0 ; Signed Integer ;; DATA_WIDTH ; 34 ; Signed Integer ;; EMPTY_WIDTH ; 0 ; Signed Integer ;+---------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+--------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fifo_full_tx_status_s1_agent ;+---------------------------+-------+--------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+---------------------------+-------+--------------------------------------------------------------------------------------------------------------------------------+; PKT_BEGIN_BURST ; 93 ; Signed Integer ;; PKT_DATA_H ; 31 ; Signed Integer ;; PKT_DATA_L ; 0 ; Signed Integer ;; PKT_SYMBOL_W ; 8 ; Signed Integer ;; PKT_BYTEEN_H ; 35 ; Signed Integer ;; PKT_BYTEEN_L ; 32 ; Signed Integer ;; PKT_ADDR_H ; 65 ; Signed Integer ;; PKT_ADDR_L ; 36 ; Signed Integer ;; PKT_TRANS_LOCK ; 70 ; Signed Integer ;; PKT_TRANS_COMPRESSED_READ ; 66 ; Signed Integer ;; PKT_TRANS_POSTED ; 67 ; Signed Integer ;; PKT_TRANS_WRITE ; 68 ; Signed Integer ;; PKT_TRANS_READ ; 69 ; Signed Integer ;; PKT_SRC_ID_H ; 99 ; Signed Integer ;; PKT_SRC_ID_L ; 95 ; Signed Integer ;; PKT_DEST_ID_H ; 104 ; Signed Integer ;; PKT_DEST_ID_L ; 100 ; Signed Integer ;; PKT_BURSTWRAP_H ; 85 ; Signed Integer ;; PKT_BURSTWRAP_L ; 79 ; Signed Integer ;; PKT_BYTE_CNT_H ; 78 ; Signed Integer ;; PKT_BYTE_CNT_L ; 72 ; Signed Integer ;; PKT_PROTECTION_H ; 119 ; Signed Integer ;; PKT_PROTECTION_L ; 117 ; Signed Integer ;; PKT_RESPONSE_STATUS_H ; 125 ; Signed Integer ;; PKT_RESPONSE_STATUS_L ; 124 ; Signed Integer ;; PKT_BURST_SIZE_H ; 88 ; Signed Integer ;; PKT_BURST_SIZE_L ; 86 ; Signed Integer ;; PKT_ORI_BURST_SIZE_L ; 126 ; Signed Integer ;; PKT_ORI_BURST_SIZE_H ; 128 ; Signed Integer ;; ST_DATA_W ; 129 ; Signed Integer ;; ST_CHANNEL_W ; 22 ; Signed Integer ;; ADDR_W ; 30 ; Signed Integer ;; AVS_DATA_W ; 32 ; Signed Integer ;; AVS_BURSTCOUNT_W ; 3 ; Signed Integer ;; PKT_SYMBOLS ; 4 ; Signed Integer ;; PREVENT_FIFO_OVERFLOW ; 1 ; Signed Integer ;; SUPPRESS_0_BYTEEN_CMD ; 1 ; Signed Integer ;; USE_READRESPONSE ; 0 ; Signed Integer ;; USE_WRITERESPONSE ; 0 ; Signed Integer ;; AVS_BE_W ; 4 ; Signed Integer ;; BURST_SIZE_W ; 3 ; Signed Integer ;; FIFO_DATA_W ; 130 ; Signed Integer ;; ECC_ENABLE ; 0 ; Signed Integer ;+---------------------------+-------+--------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fifo_full_tx_status_s1_agent|altera_merlin_burst_uncompressor:uncompressor ;+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; ADDR_W ; 30 ; Signed Integer ;; BURSTWRAP_W ; 7 ; Signed Integer ;; BYTE_CNT_W ; 7 ; Signed Integer ;; PKT_SYMBOLS ; 4 ; Signed Integer ;; BURST_SIZE_W ; 3 ; Signed Integer ;+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rsp_fifo ;+---------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+---------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------+; SYMBOLS_PER_BEAT ; 1 ; Signed Integer ;; BITS_PER_SYMBOL ; 130 ; Signed Integer ;; FIFO_DEPTH ; 2 ; Signed Integer ;; CHANNEL_WIDTH ; 0 ; Signed Integer ;; ERROR_WIDTH ; 0 ; Signed Integer ;; USE_PACKETS ; 1 ; Signed Integer ;; USE_FILL_LEVEL ; 0 ; Signed Integer ;; USE_STORE_FORWARD ; 0 ; Signed Integer ;; USE_ALMOST_FULL_IF ; 0 ; Signed Integer ;; USE_ALMOST_EMPTY_IF ; 0 ; Signed Integer ;; EMPTY_LATENCY ; 1 ; Signed Integer ;; USE_MEMORY_BLOCKS ; 0 ; Signed Integer ;; DATA_WIDTH ; 130 ; Signed Integer ;; EMPTY_WIDTH ; 0 ; Signed Integer ;+---------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo ;+---------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+---------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------+; SYMBOLS_PER_BEAT ; 1 ; Signed Integer ;; BITS_PER_SYMBOL ; 34 ; Signed Integer ;; FIFO_DEPTH ; 2 ; Signed Integer ;; CHANNEL_WIDTH ; 0 ; Signed Integer ;; ERROR_WIDTH ; 0 ; Signed Integer ;; USE_PACKETS ; 0 ; Signed Integer ;; USE_FILL_LEVEL ; 0 ; Signed Integer ;; USE_STORE_FORWARD ; 0 ; Signed Integer ;; USE_ALMOST_FULL_IF ; 0 ; Signed Integer ;; USE_ALMOST_EMPTY_IF ; 0 ; Signed Integer ;; EMPTY_LATENCY ; 0 ; Signed Integer ;; USE_MEMORY_BLOCKS ; 0 ; Signed Integer ;; DATA_WIDTH ; 34 ; Signed Integer ;; EMPTY_WIDTH ; 0 ; Signed Integer ;+---------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+---------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fifo_empty_tx_status_s1_agent ;+---------------------------+-------+---------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+---------------------------+-------+---------------------------------------------------------------------------------------------------------------------------------+; PKT_BEGIN_BURST ; 93 ; Signed Integer ;; PKT_DATA_H ; 31 ; Signed Integer ;; PKT_DATA_L ; 0 ; Signed Integer ;; PKT_SYMBOL_W ; 8 ; Signed Integer ;; PKT_BYTEEN_H ; 35 ; Signed Integer ;; PKT_BYTEEN_L ; 32 ; Signed Integer ;; PKT_ADDR_H ; 65 ; Signed Integer ;; PKT_ADDR_L ; 36 ; Signed Integer ;; PKT_TRANS_LOCK ; 70 ; Signed Integer ;; PKT_TRANS_COMPRESSED_READ ; 66 ; Signed Integer ;; PKT_TRANS_POSTED ; 67 ; Signed Integer ;; PKT_TRANS_WRITE ; 68 ; Signed Integer ;; PKT_TRANS_READ ; 69 ; Signed Integer ;; PKT_SRC_ID_H ; 99 ; Signed Integer ;; PKT_SRC_ID_L ; 95 ; Signed Integer ;; PKT_DEST_ID_H ; 104 ; Signed Integer ;; PKT_DEST_ID_L ; 100 ; Signed Integer ;; PKT_BURSTWRAP_H ; 85 ; Signed Integer ;; PKT_BURSTWRAP_L ; 79 ; Signed Integer ;; PKT_BYTE_CNT_H ; 78 ; Signed Integer ;; PKT_BYTE_CNT_L ; 72 ; Signed Integer ;; PKT_PROTECTION_H ; 119 ; Signed Integer ;; PKT_PROTECTION_L ; 117 ; Signed Integer ;; PKT_RESPONSE_STATUS_H ; 125 ; Signed Integer ;; PKT_RESPONSE_STATUS_L ; 124 ; Signed Integer ;; PKT_BURST_SIZE_H ; 88 ; Signed Integer ;; PKT_BURST_SIZE_L ; 86 ; Signed Integer ;; PKT_ORI_BURST_SIZE_L ; 126 ; Signed Integer ;; PKT_ORI_BURST_SIZE_H ; 128 ; Signed Integer ;; ST_DATA_W ; 129 ; Signed Integer ;; ST_CHANNEL_W ; 22 ; Signed Integer ;; ADDR_W ; 30 ; Signed Integer ;; AVS_DATA_W ; 32 ; Signed Integer ;; AVS_BURSTCOUNT_W ; 3 ; Signed Integer ;; PKT_SYMBOLS ; 4 ; Signed Integer ;; PREVENT_FIFO_OVERFLOW ; 1 ; Signed Integer ;; SUPPRESS_0_BYTEEN_CMD ; 1 ; Signed Integer ;; USE_READRESPONSE ; 0 ; Signed Integer ;; USE_WRITERESPONSE ; 0 ; Signed Integer ;; AVS_BE_W ; 4 ; Signed Integer ;; BURST_SIZE_W ; 3 ; Signed Integer ;; FIFO_DATA_W ; 130 ; Signed Integer ;; ECC_ENABLE ; 0 ; Signed Integer ;+---------------------------+-------+---------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fifo_empty_tx_status_s1_agent|altera_merlin_burst_uncompressor:uncompressor ;+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; ADDR_W ; 30 ; Signed Integer ;; BURSTWRAP_W ; 7 ; Signed Integer ;; BYTE_CNT_W ; 7 ; Signed Integer ;; PKT_SYMBOLS ; 4 ; Signed Integer ;; BURST_SIZE_W ; 3 ; Signed Integer ;+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rsp_fifo ;+---------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+---------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------+; SYMBOLS_PER_BEAT ; 1 ; Signed Integer ;; BITS_PER_SYMBOL ; 130 ; Signed Integer ;; FIFO_DEPTH ; 2 ; Signed Integer ;; CHANNEL_WIDTH ; 0 ; Signed Integer ;; ERROR_WIDTH ; 0 ; Signed Integer ;; USE_PACKETS ; 1 ; Signed Integer ;; USE_FILL_LEVEL ; 0 ; Signed Integer ;; USE_STORE_FORWARD ; 0 ; Signed Integer ;; USE_ALMOST_FULL_IF ; 0 ; Signed Integer ;; USE_ALMOST_EMPTY_IF ; 0 ; Signed Integer ;; EMPTY_LATENCY ; 1 ; Signed Integer ;; USE_MEMORY_BLOCKS ; 0 ; Signed Integer ;; DATA_WIDTH ; 130 ; Signed Integer ;; EMPTY_WIDTH ; 0 ; Signed Integer ;+---------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rdata_fifo ;+---------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+---------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------+; SYMBOLS_PER_BEAT ; 1 ; Signed Integer ;; BITS_PER_SYMBOL ; 34 ; Signed Integer ;; FIFO_DEPTH ; 2 ; Signed Integer ;; CHANNEL_WIDTH ; 0 ; Signed Integer ;; ERROR_WIDTH ; 0 ; Signed Integer ;; USE_PACKETS ; 0 ; Signed Integer ;; USE_FILL_LEVEL ; 0 ; Signed Integer ;; USE_STORE_FORWARD ; 0 ; Signed Integer ;; USE_ALMOST_FULL_IF ; 0 ; Signed Integer ;; USE_ALMOST_EMPTY_IF ; 0 ; Signed Integer ;; EMPTY_LATENCY ; 0 ; Signed Integer ;; USE_MEMORY_BLOCKS ; 0 ; Signed Integer ;; DATA_WIDTH ; 34 ; Signed Integer ;; EMPTY_WIDTH ; 0 ; Signed Integer ;+---------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+-----------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_tx_data_s1_agent ;+---------------------------+-------+-----------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+---------------------------+-------+-----------------------------------------------------------------------------------------------------------------------------+; PKT_BEGIN_BURST ; 93 ; Signed Integer ;; PKT_DATA_H ; 31 ; Signed Integer ;; PKT_DATA_L ; 0 ; Signed Integer ;; PKT_SYMBOL_W ; 8 ; Signed Integer ;; PKT_BYTEEN_H ; 35 ; Signed Integer ;; PKT_BYTEEN_L ; 32 ; Signed Integer ;; PKT_ADDR_H ; 65 ; Signed Integer ;; PKT_ADDR_L ; 36 ; Signed Integer ;; PKT_TRANS_LOCK ; 70 ; Signed Integer ;; PKT_TRANS_COMPRESSED_READ ; 66 ; Signed Integer ;; PKT_TRANS_POSTED ; 67 ; Signed Integer ;; PKT_TRANS_WRITE ; 68 ; Signed Integer ;; PKT_TRANS_READ ; 69 ; Signed Integer ;; PKT_SRC_ID_H ; 99 ; Signed Integer ;; PKT_SRC_ID_L ; 95 ; Signed Integer ;; PKT_DEST_ID_H ; 104 ; Signed Integer ;; PKT_DEST_ID_L ; 100 ; Signed Integer ;; PKT_BURSTWRAP_H ; 85 ; Signed Integer ;; PKT_BURSTWRAP_L ; 79 ; Signed Integer ;; PKT_BYTE_CNT_H ; 78 ; Signed Integer ;; PKT_BYTE_CNT_L ; 72 ; Signed Integer ;; PKT_PROTECTION_H ; 119 ; Signed Integer ;; PKT_PROTECTION_L ; 117 ; Signed Integer ;; PKT_RESPONSE_STATUS_H ; 125 ; Signed Integer ;; PKT_RESPONSE_STATUS_L ; 124 ; Signed Integer ;; PKT_BURST_SIZE_H ; 88 ; Signed Integer ;; PKT_BURST_SIZE_L ; 86 ; Signed Integer ;; PKT_ORI_BURST_SIZE_L ; 126 ; Signed Integer ;; PKT_ORI_BURST_SIZE_H ; 128 ; Signed Integer ;; ST_DATA_W ; 129 ; Signed Integer ;; ST_CHANNEL_W ; 22 ; Signed Integer ;; ADDR_W ; 30 ; Signed Integer ;; AVS_DATA_W ; 32 ; Signed Integer ;; AVS_BURSTCOUNT_W ; 3 ; Signed Integer ;; PKT_SYMBOLS ; 4 ; Signed Integer ;; PREVENT_FIFO_OVERFLOW ; 1 ; Signed Integer ;; SUPPRESS_0_BYTEEN_CMD ; 1 ; Signed Integer ;; USE_READRESPONSE ; 0 ; Signed Integer ;; USE_WRITERESPONSE ; 0 ; Signed Integer ;; AVS_BE_W ; 4 ; Signed Integer ;; BURST_SIZE_W ; 3 ; Signed Integer ;; FIFO_DATA_W ; 130 ; Signed Integer ;; ECC_ENABLE ; 0 ; Signed Integer ;+---------------------------+-------+-----------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_tx_data_s1_agent|altera_merlin_burst_uncompressor:uncompressor ;+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; ADDR_W ; 30 ; Signed Integer ;; BURSTWRAP_W ; 7 ; Signed Integer ;; BYTE_CNT_W ; 7 ; Signed Integer ;; PKT_SYMBOLS ; 4 ; Signed Integer ;; BURST_SIZE_W ; 3 ; Signed Integer ;+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+----------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rsp_fifo ;+---------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+---------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------+; SYMBOLS_PER_BEAT ; 1 ; Signed Integer ;; BITS_PER_SYMBOL ; 130 ; Signed Integer ;; FIFO_DEPTH ; 2 ; Signed Integer ;; CHANNEL_WIDTH ; 0 ; Signed Integer ;; ERROR_WIDTH ; 0 ; Signed Integer ;; USE_PACKETS ; 1 ; Signed Integer ;; USE_FILL_LEVEL ; 0 ; Signed Integer ;; USE_STORE_FORWARD ; 0 ; Signed Integer ;; USE_ALMOST_FULL_IF ; 0 ; Signed Integer ;; USE_ALMOST_EMPTY_IF ; 0 ; Signed Integer ;; EMPTY_LATENCY ; 1 ; Signed Integer ;; USE_MEMORY_BLOCKS ; 0 ; Signed Integer ;; DATA_WIDTH ; 130 ; Signed Integer ;; EMPTY_WIDTH ; 0 ; Signed Integer ;+---------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rdata_fifo ;+---------------------+-------+------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+---------------------+-------+------------------------------------------------------------------------------------------------------------------------------------------+; SYMBOLS_PER_BEAT ; 1 ; Signed Integer ;; BITS_PER_SYMBOL ; 34 ; Signed Integer ;; FIFO_DEPTH ; 2 ; Signed Integer ;; CHANNEL_WIDTH ; 0 ; Signed Integer ;; ERROR_WIDTH ; 0 ; Signed Integer ;; USE_PACKETS ; 0 ; Signed Integer ;; USE_FILL_LEVEL ; 0 ; Signed Integer ;; USE_STORE_FORWARD ; 0 ; Signed Integer ;; USE_ALMOST_FULL_IF ; 0 ; Signed Integer ;; USE_ALMOST_EMPTY_IF ; 0 ; Signed Integer ;; EMPTY_LATENCY ; 0 ; Signed Integer ;; USE_MEMORY_BLOCKS ; 0 ; Signed Integer ;; DATA_WIDTH ; 34 ; Signed Integer ;; EMPTY_WIDTH ; 0 ; Signed Integer ;+---------------------+-------+------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+-------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_tx_enable_s1_agent ;+---------------------------+-------+-------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+---------------------------+-------+-------------------------------------------------------------------------------------------------------------------------------+; PKT_BEGIN_BURST ; 93 ; Signed Integer ;; PKT_DATA_H ; 31 ; Signed Integer ;; PKT_DATA_L ; 0 ; Signed Integer ;; PKT_SYMBOL_W ; 8 ; Signed Integer ;; PKT_BYTEEN_H ; 35 ; Signed Integer ;; PKT_BYTEEN_L ; 32 ; Signed Integer ;; PKT_ADDR_H ; 65 ; Signed Integer ;; PKT_ADDR_L ; 36 ; Signed Integer ;; PKT_TRANS_LOCK ; 70 ; Signed Integer ;; PKT_TRANS_COMPRESSED_READ ; 66 ; Signed Integer ;; PKT_TRANS_POSTED ; 67 ; Signed Integer ;; PKT_TRANS_WRITE ; 68 ; Signed Integer ;; PKT_TRANS_READ ; 69 ; Signed Integer ;; PKT_SRC_ID_H ; 99 ; Signed Integer ;; PKT_SRC_ID_L ; 95 ; Signed Integer ;; PKT_DEST_ID_H ; 104 ; Signed Integer ;; PKT_DEST_ID_L ; 100 ; Signed Integer ;; PKT_BURSTWRAP_H ; 85 ; Signed Integer ;; PKT_BURSTWRAP_L ; 79 ; Signed Integer ;; PKT_BYTE_CNT_H ; 78 ; Signed Integer ;; PKT_BYTE_CNT_L ; 72 ; Signed Integer ;; PKT_PROTECTION_H ; 119 ; Signed Integer ;; PKT_PROTECTION_L ; 117 ; Signed Integer ;; PKT_RESPONSE_STATUS_H ; 125 ; Signed Integer ;; PKT_RESPONSE_STATUS_L ; 124 ; Signed Integer ;; PKT_BURST_SIZE_H ; 88 ; Signed Integer ;; PKT_BURST_SIZE_L ; 86 ; Signed Integer ;; PKT_ORI_BURST_SIZE_L ; 126 ; Signed Integer ;; PKT_ORI_BURST_SIZE_H ; 128 ; Signed Integer ;; ST_DATA_W ; 129 ; Signed Integer ;; ST_CHANNEL_W ; 22 ; Signed Integer ;; ADDR_W ; 30 ; Signed Integer ;; AVS_DATA_W ; 32 ; Signed Integer ;; AVS_BURSTCOUNT_W ; 3 ; Signed Integer ;; PKT_SYMBOLS ; 4 ; Signed Integer ;; PREVENT_FIFO_OVERFLOW ; 1 ; Signed Integer ;; SUPPRESS_0_BYTEEN_CMD ; 1 ; Signed Integer ;; USE_READRESPONSE ; 0 ; Signed Integer ;; USE_WRITERESPONSE ; 0 ; Signed Integer ;; AVS_BE_W ; 4 ; Signed Integer ;; BURST_SIZE_W ; 3 ; Signed Integer ;; FIFO_DATA_W ; 130 ; Signed Integer ;; ECC_ENABLE ; 0 ; Signed Integer ;+---------------------------+-------+-------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_tx_enable_s1_agent|altera_merlin_burst_uncompressor:uncompressor ;+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; ADDR_W ; 30 ; Signed Integer ;; BURSTWRAP_W ; 7 ; Signed Integer ;; BYTE_CNT_W ; 7 ; Signed Integer ;; PKT_SYMBOLS ; 4 ; Signed Integer ;; BURST_SIZE_W ; 3 ; Signed Integer ;+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rsp_fifo ;+---------------------+-------+------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+---------------------+-------+------------------------------------------------------------------------------------------------------------------------------------------+; SYMBOLS_PER_BEAT ; 1 ; Signed Integer ;; BITS_PER_SYMBOL ; 130 ; Signed Integer ;; FIFO_DEPTH ; 2 ; Signed Integer ;; CHANNEL_WIDTH ; 0 ; Signed Integer ;; ERROR_WIDTH ; 0 ; Signed Integer ;; USE_PACKETS ; 1 ; Signed Integer ;; USE_FILL_LEVEL ; 0 ; Signed Integer ;; USE_STORE_FORWARD ; 0 ; Signed Integer ;; USE_ALMOST_FULL_IF ; 0 ; Signed Integer ;; USE_ALMOST_EMPTY_IF ; 0 ; Signed Integer ;; EMPTY_LATENCY ; 1 ; Signed Integer ;; USE_MEMORY_BLOCKS ; 0 ; Signed Integer ;; DATA_WIDTH ; 130 ; Signed Integer ;; EMPTY_WIDTH ; 0 ; Signed Integer ;+---------------------+-------+------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rdata_fifo ;+---------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+---------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------+; SYMBOLS_PER_BEAT ; 1 ; Signed Integer ;; BITS_PER_SYMBOL ; 34 ; Signed Integer ;; FIFO_DEPTH ; 2 ; Signed Integer ;; CHANNEL_WIDTH ; 0 ; Signed Integer ;; ERROR_WIDTH ; 0 ; Signed Integer ;; USE_PACKETS ; 0 ; Signed Integer ;; USE_FILL_LEVEL ; 0 ; Signed Integer ;; USE_STORE_FORWARD ; 0 ; Signed Integer ;; USE_ALMOST_FULL_IF ; 0 ; Signed Integer ;; USE_ALMOST_EMPTY_IF ; 0 ; Signed Integer ;; EMPTY_LATENCY ; 0 ; Signed Integer ;; USE_MEMORY_BLOCKS ; 0 ; Signed Integer ;; DATA_WIDTH ; 34 ; Signed Integer ;; EMPTY_WIDTH ; 0 ; Signed Integer ;+---------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_tx_ready_s1_agent ;+---------------------------+-------+------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+---------------------------+-------+------------------------------------------------------------------------------------------------------------------------------+; PKT_BEGIN_BURST ; 93 ; Signed Integer ;; PKT_DATA_H ; 31 ; Signed Integer ;; PKT_DATA_L ; 0 ; Signed Integer ;; PKT_SYMBOL_W ; 8 ; Signed Integer ;; PKT_BYTEEN_H ; 35 ; Signed Integer ;; PKT_BYTEEN_L ; 32 ; Signed Integer ;; PKT_ADDR_H ; 65 ; Signed Integer ;; PKT_ADDR_L ; 36 ; Signed Integer ;; PKT_TRANS_LOCK ; 70 ; Signed Integer ;; PKT_TRANS_COMPRESSED_READ ; 66 ; Signed Integer ;; PKT_TRANS_POSTED ; 67 ; Signed Integer ;; PKT_TRANS_WRITE ; 68 ; Signed Integer ;; PKT_TRANS_READ ; 69 ; Signed Integer ;; PKT_SRC_ID_H ; 99 ; Signed Integer ;; PKT_SRC_ID_L ; 95 ; Signed Integer ;; PKT_DEST_ID_H ; 104 ; Signed Integer ;; PKT_DEST_ID_L ; 100 ; Signed Integer ;; PKT_BURSTWRAP_H ; 85 ; Signed Integer ;; PKT_BURSTWRAP_L ; 79 ; Signed Integer ;; PKT_BYTE_CNT_H ; 78 ; Signed Integer ;; PKT_BYTE_CNT_L ; 72 ; Signed Integer ;; PKT_PROTECTION_H ; 119 ; Signed Integer ;; PKT_PROTECTION_L ; 117 ; Signed Integer ;; PKT_RESPONSE_STATUS_H ; 125 ; Signed Integer ;; PKT_RESPONSE_STATUS_L ; 124 ; Signed Integer ;; PKT_BURST_SIZE_H ; 88 ; Signed Integer ;; PKT_BURST_SIZE_L ; 86 ; Signed Integer ;; PKT_ORI_BURST_SIZE_L ; 126 ; Signed Integer ;; PKT_ORI_BURST_SIZE_H ; 128 ; Signed Integer ;; ST_DATA_W ; 129 ; Signed Integer ;; ST_CHANNEL_W ; 22 ; Signed Integer ;; ADDR_W ; 30 ; Signed Integer ;; AVS_DATA_W ; 32 ; Signed Integer ;; AVS_BURSTCOUNT_W ; 3 ; Signed Integer ;; PKT_SYMBOLS ; 4 ; Signed Integer ;; PREVENT_FIFO_OVERFLOW ; 1 ; Signed Integer ;; SUPPRESS_0_BYTEEN_CMD ; 1 ; Signed Integer ;; USE_READRESPONSE ; 0 ; Signed Integer ;; USE_WRITERESPONSE ; 0 ; Signed Integer ;; AVS_BE_W ; 4 ; Signed Integer ;; BURST_SIZE_W ; 3 ; Signed Integer ;; FIFO_DATA_W ; 130 ; Signed Integer ;; ECC_ENABLE ; 0 ; Signed Integer ;+---------------------------+-------+------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_tx_ready_s1_agent|altera_merlin_burst_uncompressor:uncompressor ;+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; ADDR_W ; 30 ; Signed Integer ;; BURSTWRAP_W ; 7 ; Signed Integer ;; BYTE_CNT_W ; 7 ; Signed Integer ;; PKT_SYMBOLS ; 4 ; Signed Integer ;; BURST_SIZE_W ; 3 ; Signed Integer ;+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rsp_fifo ;+---------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+---------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------+; SYMBOLS_PER_BEAT ; 1 ; Signed Integer ;; BITS_PER_SYMBOL ; 130 ; Signed Integer ;; FIFO_DEPTH ; 2 ; Signed Integer ;; CHANNEL_WIDTH ; 0 ; Signed Integer ;; ERROR_WIDTH ; 0 ; Signed Integer ;; USE_PACKETS ; 1 ; Signed Integer ;; USE_FILL_LEVEL ; 0 ; Signed Integer ;; USE_STORE_FORWARD ; 0 ; Signed Integer ;; USE_ALMOST_FULL_IF ; 0 ; Signed Integer ;; USE_ALMOST_EMPTY_IF ; 0 ; Signed Integer ;; EMPTY_LATENCY ; 1 ; Signed Integer ;; USE_MEMORY_BLOCKS ; 0 ; Signed Integer ;; DATA_WIDTH ; 130 ; Signed Integer ;; EMPTY_WIDTH ; 0 ; Signed Integer ;+---------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rdata_fifo ;+---------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+---------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------+; SYMBOLS_PER_BEAT ; 1 ; Signed Integer ;; BITS_PER_SYMBOL ; 34 ; Signed Integer ;; FIFO_DEPTH ; 2 ; Signed Integer ;; CHANNEL_WIDTH ; 0 ; Signed Integer ;; ERROR_WIDTH ; 0 ; Signed Integer ;; USE_PACKETS ; 0 ; Signed Integer ;; USE_FILL_LEVEL ; 0 ; Signed Integer ;; USE_STORE_FORWARD ; 0 ; Signed Integer ;; USE_ALMOST_FULL_IF ; 0 ; Signed Integer ;; USE_ALMOST_EMPTY_IF ; 0 ; Signed Integer ;; EMPTY_LATENCY ; 0 ; Signed Integer ;; USE_MEMORY_BLOCKS ; 0 ; Signed Integer ;; DATA_WIDTH ; 34 ; Signed Integer ;; EMPTY_WIDTH ; 0 ; Signed Integer ;+---------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+----------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:data_info_s1_agent ;+---------------------------+-------+----------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+---------------------------+-------+----------------------------------------------------------------------------------------------------------------------+; PKT_BEGIN_BURST ; 93 ; Signed Integer ;; PKT_DATA_H ; 31 ; Signed Integer ;; PKT_DATA_L ; 0 ; Signed Integer ;; PKT_SYMBOL_W ; 8 ; Signed Integer ;; PKT_BYTEEN_H ; 35 ; Signed Integer ;; PKT_BYTEEN_L ; 32 ; Signed Integer ;; PKT_ADDR_H ; 65 ; Signed Integer ;; PKT_ADDR_L ; 36 ; Signed Integer ;; PKT_TRANS_LOCK ; 70 ; Signed Integer ;; PKT_TRANS_COMPRESSED_READ ; 66 ; Signed Integer ;; PKT_TRANS_POSTED ; 67 ; Signed Integer ;; PKT_TRANS_WRITE ; 68 ; Signed Integer ;; PKT_TRANS_READ ; 69 ; Signed Integer ;; PKT_SRC_ID_H ; 99 ; Signed Integer ;; PKT_SRC_ID_L ; 95 ; Signed Integer ;; PKT_DEST_ID_H ; 104 ; Signed Integer ;; PKT_DEST_ID_L ; 100 ; Signed Integer ;; PKT_BURSTWRAP_H ; 85 ; Signed Integer ;; PKT_BURSTWRAP_L ; 79 ; Signed Integer ;; PKT_BYTE_CNT_H ; 78 ; Signed Integer ;; PKT_BYTE_CNT_L ; 72 ; Signed Integer ;; PKT_PROTECTION_H ; 119 ; Signed Integer ;; PKT_PROTECTION_L ; 117 ; Signed Integer ;; PKT_RESPONSE_STATUS_H ; 125 ; Signed Integer ;; PKT_RESPONSE_STATUS_L ; 124 ; Signed Integer ;; PKT_BURST_SIZE_H ; 88 ; Signed Integer ;; PKT_BURST_SIZE_L ; 86 ; Signed Integer ;; PKT_ORI_BURST_SIZE_L ; 126 ; Signed Integer ;; PKT_ORI_BURST_SIZE_H ; 128 ; Signed Integer ;; ST_DATA_W ; 129 ; Signed Integer ;; ST_CHANNEL_W ; 22 ; Signed Integer ;; ADDR_W ; 30 ; Signed Integer ;; AVS_DATA_W ; 32 ; Signed Integer ;; AVS_BURSTCOUNT_W ; 3 ; Signed Integer ;; PKT_SYMBOLS ; 4 ; Signed Integer ;; PREVENT_FIFO_OVERFLOW ; 1 ; Signed Integer ;; SUPPRESS_0_BYTEEN_CMD ; 1 ; Signed Integer ;; USE_READRESPONSE ; 0 ; Signed Integer ;; USE_WRITERESPONSE ; 0 ; Signed Integer ;; AVS_BE_W ; 4 ; Signed Integer ;; BURST_SIZE_W ; 3 ; Signed Integer ;; FIFO_DATA_W ; 130 ; Signed Integer ;; ECC_ENABLE ; 0 ; Signed Integer ;+---------------------------+-------+----------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:data_info_s1_agent|altera_merlin_burst_uncompressor:uncompressor ;+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; ADDR_W ; 30 ; Signed Integer ;; BURSTWRAP_W ; 7 ; Signed Integer ;; BYTE_CNT_W ; 7 ; Signed Integer ;; PKT_SYMBOLS ; 4 ; Signed Integer ;; BURST_SIZE_W ; 3 ; Signed Integer ;+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+---------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rsp_fifo ;+---------------------+-------+---------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+---------------------+-------+---------------------------------------------------------------------------------------------------------------------------------+; SYMBOLS_PER_BEAT ; 1 ; Signed Integer ;; BITS_PER_SYMBOL ; 130 ; Signed Integer ;; FIFO_DEPTH ; 2 ; Signed Integer ;; CHANNEL_WIDTH ; 0 ; Signed Integer ;; ERROR_WIDTH ; 0 ; Signed Integer ;; USE_PACKETS ; 1 ; Signed Integer ;; USE_FILL_LEVEL ; 0 ; Signed Integer ;; USE_STORE_FORWARD ; 0 ; Signed Integer ;; USE_ALMOST_FULL_IF ; 0 ; Signed Integer ;; USE_ALMOST_EMPTY_IF ; 0 ; Signed Integer ;; EMPTY_LATENCY ; 1 ; Signed Integer ;; USE_MEMORY_BLOCKS ; 0 ; Signed Integer ;; DATA_WIDTH ; 130 ; Signed Integer ;; EMPTY_WIDTH ; 0 ; Signed Integer ;+---------------------+-------+---------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+-----------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo ;+---------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+---------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------+; SYMBOLS_PER_BEAT ; 1 ; Signed Integer ;; BITS_PER_SYMBOL ; 34 ; Signed Integer ;; FIFO_DEPTH ; 2 ; Signed Integer ;; CHANNEL_WIDTH ; 0 ; Signed Integer ;; ERROR_WIDTH ; 0 ; Signed Integer ;; USE_PACKETS ; 0 ; Signed Integer ;; USE_FILL_LEVEL ; 0 ; Signed Integer ;; USE_STORE_FORWARD ; 0 ; Signed Integer ;; USE_ALMOST_FULL_IF ; 0 ; Signed Integer ;; USE_ALMOST_EMPTY_IF ; 0 ; Signed Integer ;; EMPTY_LATENCY ; 0 ; Signed Integer ;; USE_MEMORY_BLOCKS ; 0 ; Signed Integer ;; DATA_WIDTH ; 34 ; Signed Integer ;; EMPTY_WIDTH ; 0 ; Signed Integer ;+---------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+----------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:clock_sel_s1_agent ;+---------------------------+-------+----------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+---------------------------+-------+----------------------------------------------------------------------------------------------------------------------+; PKT_BEGIN_BURST ; 93 ; Signed Integer ;; PKT_DATA_H ; 31 ; Signed Integer ;; PKT_DATA_L ; 0 ; Signed Integer ;; PKT_SYMBOL_W ; 8 ; Signed Integer ;; PKT_BYTEEN_H ; 35 ; Signed Integer ;; PKT_BYTEEN_L ; 32 ; Signed Integer ;; PKT_ADDR_H ; 65 ; Signed Integer ;; PKT_ADDR_L ; 36 ; Signed Integer ;; PKT_TRANS_LOCK ; 70 ; Signed Integer ;; PKT_TRANS_COMPRESSED_READ ; 66 ; Signed Integer ;; PKT_TRANS_POSTED ; 67 ; Signed Integer ;; PKT_TRANS_WRITE ; 68 ; Signed Integer ;; PKT_TRANS_READ ; 69 ; Signed Integer ;; PKT_SRC_ID_H ; 99 ; Signed Integer ;; PKT_SRC_ID_L ; 95 ; Signed Integer ;; PKT_DEST_ID_H ; 104 ; Signed Integer ;; PKT_DEST_ID_L ; 100 ; Signed Integer ;; PKT_BURSTWRAP_H ; 85 ; Signed Integer ;; PKT_BURSTWRAP_L ; 79 ; Signed Integer ;; PKT_BYTE_CNT_H ; 78 ; Signed Integer ;; PKT_BYTE_CNT_L ; 72 ; Signed Integer ;; PKT_PROTECTION_H ; 119 ; Signed Integer ;; PKT_PROTECTION_L ; 117 ; Signed Integer ;; PKT_RESPONSE_STATUS_H ; 125 ; Signed Integer ;; PKT_RESPONSE_STATUS_L ; 124 ; Signed Integer ;; PKT_BURST_SIZE_H ; 88 ; Signed Integer ;; PKT_BURST_SIZE_L ; 86 ; Signed Integer ;; PKT_ORI_BURST_SIZE_L ; 126 ; Signed Integer ;; PKT_ORI_BURST_SIZE_H ; 128 ; Signed Integer ;; ST_DATA_W ; 129 ; Signed Integer ;; ST_CHANNEL_W ; 22 ; Signed Integer ;; ADDR_W ; 30 ; Signed Integer ;; AVS_DATA_W ; 32 ; Signed Integer ;; AVS_BURSTCOUNT_W ; 3 ; Signed Integer ;; PKT_SYMBOLS ; 4 ; Signed Integer ;; PREVENT_FIFO_OVERFLOW ; 1 ; Signed Integer ;; SUPPRESS_0_BYTEEN_CMD ; 1 ; Signed Integer ;; USE_READRESPONSE ; 0 ; Signed Integer ;; USE_WRITERESPONSE ; 0 ; Signed Integer ;; AVS_BE_W ; 4 ; Signed Integer ;; BURST_SIZE_W ; 3 ; Signed Integer ;; FIFO_DATA_W ; 130 ; Signed Integer ;; ECC_ENABLE ; 0 ; Signed Integer ;+---------------------------+-------+----------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:clock_sel_s1_agent|altera_merlin_burst_uncompressor:uncompressor ;+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; ADDR_W ; 30 ; Signed Integer ;; BURSTWRAP_W ; 7 ; Signed Integer ;; BYTE_CNT_W ; 7 ; Signed Integer ;; PKT_SYMBOLS ; 4 ; Signed Integer ;; BURST_SIZE_W ; 3 ; Signed Integer ;+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+---------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rsp_fifo ;+---------------------+-------+---------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+---------------------+-------+---------------------------------------------------------------------------------------------------------------------------------+; SYMBOLS_PER_BEAT ; 1 ; Signed Integer ;; BITS_PER_SYMBOL ; 130 ; Signed Integer ;; FIFO_DEPTH ; 2 ; Signed Integer ;; CHANNEL_WIDTH ; 0 ; Signed Integer ;; ERROR_WIDTH ; 0 ; Signed Integer ;; USE_PACKETS ; 1 ; Signed Integer ;; USE_FILL_LEVEL ; 0 ; Signed Integer ;; USE_STORE_FORWARD ; 0 ; Signed Integer ;; USE_ALMOST_FULL_IF ; 0 ; Signed Integer ;; USE_ALMOST_EMPTY_IF ; 0 ; Signed Integer ;; EMPTY_LATENCY ; 1 ; Signed Integer ;; USE_MEMORY_BLOCKS ; 0 ; Signed Integer ;; DATA_WIDTH ; 130 ; Signed Integer ;; EMPTY_WIDTH ; 0 ; Signed Integer ;+---------------------+-------+---------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+-----------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rdata_fifo ;+---------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+---------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------+; SYMBOLS_PER_BEAT ; 1 ; Signed Integer ;; BITS_PER_SYMBOL ; 34 ; Signed Integer ;; FIFO_DEPTH ; 2 ; Signed Integer ;; CHANNEL_WIDTH ; 0 ; Signed Integer ;; ERROR_WIDTH ; 0 ; Signed Integer ;; USE_PACKETS ; 0 ; Signed Integer ;; USE_FILL_LEVEL ; 0 ; Signed Integer ;; USE_STORE_FORWARD ; 0 ; Signed Integer ;; USE_ALMOST_FULL_IF ; 0 ; Signed Integer ;; USE_ALMOST_EMPTY_IF ; 0 ; Signed Integer ;; EMPTY_LATENCY ; 0 ; Signed Integer ;; USE_MEMORY_BLOCKS ; 0 ; Signed Integer ;; DATA_WIDTH ; 34 ; Signed Integer ;; EMPTY_WIDTH ; 0 ; Signed Integer ;+---------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+---------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fsm_info_s1_agent ;+---------------------------+-------+---------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+---------------------------+-------+---------------------------------------------------------------------------------------------------------------------+; PKT_BEGIN_BURST ; 93 ; Signed Integer ;; PKT_DATA_H ; 31 ; Signed Integer ;; PKT_DATA_L ; 0 ; Signed Integer ;; PKT_SYMBOL_W ; 8 ; Signed Integer ;; PKT_BYTEEN_H ; 35 ; Signed Integer ;; PKT_BYTEEN_L ; 32 ; Signed Integer ;; PKT_ADDR_H ; 65 ; Signed Integer ;; PKT_ADDR_L ; 36 ; Signed Integer ;; PKT_TRANS_LOCK ; 70 ; Signed Integer ;; PKT_TRANS_COMPRESSED_READ ; 66 ; Signed Integer ;; PKT_TRANS_POSTED ; 67 ; Signed Integer ;; PKT_TRANS_WRITE ; 68 ; Signed Integer ;; PKT_TRANS_READ ; 69 ; Signed Integer ;; PKT_SRC_ID_H ; 99 ; Signed Integer ;; PKT_SRC_ID_L ; 95 ; Signed Integer ;; PKT_DEST_ID_H ; 104 ; Signed Integer ;; PKT_DEST_ID_L ; 100 ; Signed Integer ;; PKT_BURSTWRAP_H ; 85 ; Signed Integer ;; PKT_BURSTWRAP_L ; 79 ; Signed Integer ;; PKT_BYTE_CNT_H ; 78 ; Signed Integer ;; PKT_BYTE_CNT_L ; 72 ; Signed Integer ;; PKT_PROTECTION_H ; 119 ; Signed Integer ;; PKT_PROTECTION_L ; 117 ; Signed Integer ;; PKT_RESPONSE_STATUS_H ; 125 ; Signed Integer ;; PKT_RESPONSE_STATUS_L ; 124 ; Signed Integer ;; PKT_BURST_SIZE_H ; 88 ; Signed Integer ;; PKT_BURST_SIZE_L ; 86 ; Signed Integer ;; PKT_ORI_BURST_SIZE_L ; 126 ; Signed Integer ;; PKT_ORI_BURST_SIZE_H ; 128 ; Signed Integer ;; ST_DATA_W ; 129 ; Signed Integer ;; ST_CHANNEL_W ; 22 ; Signed Integer ;; ADDR_W ; 30 ; Signed Integer ;; AVS_DATA_W ; 32 ; Signed Integer ;; AVS_BURSTCOUNT_W ; 3 ; Signed Integer ;; PKT_SYMBOLS ; 4 ; Signed Integer ;; PREVENT_FIFO_OVERFLOW ; 1 ; Signed Integer ;; SUPPRESS_0_BYTEEN_CMD ; 1 ; Signed Integer ;; USE_READRESPONSE ; 0 ; Signed Integer ;; USE_WRITERESPONSE ; 0 ; Signed Integer ;; AVS_BE_W ; 4 ; Signed Integer ;; BURST_SIZE_W ; 3 ; Signed Integer ;; FIFO_DATA_W ; 130 ; Signed Integer ;; ECC_ENABLE ; 0 ; Signed Integer ;+---------------------------+-------+---------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fsm_info_s1_agent|altera_merlin_burst_uncompressor:uncompressor ;+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; ADDR_W ; 30 ; Signed Integer ;; BURSTWRAP_W ; 7 ; Signed Integer ;; BYTE_CNT_W ; 7 ; Signed Integer ;; PKT_SYMBOLS ; 4 ; Signed Integer ;; BURST_SIZE_W ; 3 ; Signed Integer ;+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+--------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rsp_fifo ;+---------------------+-------+--------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+---------------------+-------+--------------------------------------------------------------------------------------------------------------------------------+; SYMBOLS_PER_BEAT ; 1 ; Signed Integer ;; BITS_PER_SYMBOL ; 130 ; Signed Integer ;; FIFO_DEPTH ; 2 ; Signed Integer ;; CHANNEL_WIDTH ; 0 ; Signed Integer ;; ERROR_WIDTH ; 0 ; Signed Integer ;; USE_PACKETS ; 1 ; Signed Integer ;; USE_FILL_LEVEL ; 0 ; Signed Integer ;; USE_STORE_FORWARD ; 0 ; Signed Integer ;; USE_ALMOST_FULL_IF ; 0 ; Signed Integer ;; USE_ALMOST_EMPTY_IF ; 0 ; Signed Integer ;; EMPTY_LATENCY ; 1 ; Signed Integer ;; USE_MEMORY_BLOCKS ; 0 ; Signed Integer ;; DATA_WIDTH ; 130 ; Signed Integer ;; EMPTY_WIDTH ; 0 ; Signed Integer ;+---------------------+-------+--------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+----------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo ;+---------------------+-------+----------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+---------------------+-------+----------------------------------------------------------------------------------------------------------------------------------+; SYMBOLS_PER_BEAT ; 1 ; Signed Integer ;; BITS_PER_SYMBOL ; 34 ; Signed Integer ;; FIFO_DEPTH ; 2 ; Signed Integer ;; CHANNEL_WIDTH ; 0 ; Signed Integer ;; ERROR_WIDTH ; 0 ; Signed Integer ;; USE_PACKETS ; 0 ; Signed Integer ;; USE_FILL_LEVEL ; 0 ; Signed Integer ;; USE_STORE_FORWARD ; 0 ; Signed Integer ;; USE_ALMOST_FULL_IF ; 0 ; Signed Integer ;; USE_ALMOST_EMPTY_IF ; 0 ; Signed Integer ;; EMPTY_LATENCY ; 0 ; Signed Integer ;; USE_MEMORY_BLOCKS ; 0 ; Signed Integer ;; DATA_WIDTH ; 34 ; Signed Integer ;; EMPTY_WIDTH ; 0 ; Signed Integer ;+---------------------+-------+----------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+----------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:counter_tx_fifo_s1_agent ;+---------------------------+-------+----------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+---------------------------+-------+----------------------------------------------------------------------------------------------------------------------------+; PKT_BEGIN_BURST ; 93 ; Signed Integer ;; PKT_DATA_H ; 31 ; Signed Integer ;; PKT_DATA_L ; 0 ; Signed Integer ;; PKT_SYMBOL_W ; 8 ; Signed Integer ;; PKT_BYTEEN_H ; 35 ; Signed Integer ;; PKT_BYTEEN_L ; 32 ; Signed Integer ;; PKT_ADDR_H ; 65 ; Signed Integer ;; PKT_ADDR_L ; 36 ; Signed Integer ;; PKT_TRANS_LOCK ; 70 ; Signed Integer ;; PKT_TRANS_COMPRESSED_READ ; 66 ; Signed Integer ;; PKT_TRANS_POSTED ; 67 ; Signed Integer ;; PKT_TRANS_WRITE ; 68 ; Signed Integer ;; PKT_TRANS_READ ; 69 ; Signed Integer ;; PKT_SRC_ID_H ; 99 ; Signed Integer ;; PKT_SRC_ID_L ; 95 ; Signed Integer ;; PKT_DEST_ID_H ; 104 ; Signed Integer ;; PKT_DEST_ID_L ; 100 ; Signed Integer ;; PKT_BURSTWRAP_H ; 85 ; Signed Integer ;; PKT_BURSTWRAP_L ; 79 ; Signed Integer ;; PKT_BYTE_CNT_H ; 78 ; Signed Integer ;; PKT_BYTE_CNT_L ; 72 ; Signed Integer ;; PKT_PROTECTION_H ; 119 ; Signed Integer ;; PKT_PROTECTION_L ; 117 ; Signed Integer ;; PKT_RESPONSE_STATUS_H ; 125 ; Signed Integer ;; PKT_RESPONSE_STATUS_L ; 124 ; Signed Integer ;; PKT_BURST_SIZE_H ; 88 ; Signed Integer ;; PKT_BURST_SIZE_L ; 86 ; Signed Integer ;; PKT_ORI_BURST_SIZE_L ; 126 ; Signed Integer ;; PKT_ORI_BURST_SIZE_H ; 128 ; Signed Integer ;; ST_DATA_W ; 129 ; Signed Integer ;; ST_CHANNEL_W ; 22 ; Signed Integer ;; ADDR_W ; 30 ; Signed Integer ;; AVS_DATA_W ; 32 ; Signed Integer ;; AVS_BURSTCOUNT_W ; 3 ; Signed Integer ;; PKT_SYMBOLS ; 4 ; Signed Integer ;; PREVENT_FIFO_OVERFLOW ; 1 ; Signed Integer ;; SUPPRESS_0_BYTEEN_CMD ; 1 ; Signed Integer ;; USE_READRESPONSE ; 0 ; Signed Integer ;; USE_WRITERESPONSE ; 0 ; Signed Integer ;; AVS_BE_W ; 4 ; Signed Integer ;; BURST_SIZE_W ; 3 ; Signed Integer ;; FIFO_DATA_W ; 130 ; Signed Integer ;; ECC_ENABLE ; 0 ; Signed Integer ;+---------------------------+-------+----------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:counter_tx_fifo_s1_agent|altera_merlin_burst_uncompressor:uncompressor ;+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; ADDR_W ; 30 ; Signed Integer ;; BURSTWRAP_W ; 7 ; Signed Integer ;; BYTE_CNT_W ; 7 ; Signed Integer ;; PKT_SYMBOLS ; 4 ; Signed Integer ;; BURST_SIZE_W ; 3 ; Signed Integer ;+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+---------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rsp_fifo ;+---------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+---------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------+; SYMBOLS_PER_BEAT ; 1 ; Signed Integer ;; BITS_PER_SYMBOL ; 130 ; Signed Integer ;; FIFO_DEPTH ; 2 ; Signed Integer ;; CHANNEL_WIDTH ; 0 ; Signed Integer ;; ERROR_WIDTH ; 0 ; Signed Integer ;; USE_PACKETS ; 1 ; Signed Integer ;; USE_FILL_LEVEL ; 0 ; Signed Integer ;; USE_STORE_FORWARD ; 0 ; Signed Integer ;; USE_ALMOST_FULL_IF ; 0 ; Signed Integer ;; USE_ALMOST_EMPTY_IF ; 0 ; Signed Integer ;; EMPTY_LATENCY ; 1 ; Signed Integer ;; USE_MEMORY_BLOCKS ; 0 ; Signed Integer ;; DATA_WIDTH ; 130 ; Signed Integer ;; EMPTY_WIDTH ; 0 ; Signed Integer ;+---------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rdata_fifo ;+---------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+---------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------+; SYMBOLS_PER_BEAT ; 1 ; Signed Integer ;; BITS_PER_SYMBOL ; 34 ; Signed Integer ;; FIFO_DEPTH ; 2 ; Signed Integer ;; CHANNEL_WIDTH ; 0 ; Signed Integer ;; ERROR_WIDTH ; 0 ; Signed Integer ;; USE_PACKETS ; 0 ; Signed Integer ;; USE_FILL_LEVEL ; 0 ; Signed Integer ;; USE_STORE_FORWARD ; 0 ; Signed Integer ;; USE_ALMOST_FULL_IF ; 0 ; Signed Integer ;; USE_ALMOST_EMPTY_IF ; 0 ; Signed Integer ;; EMPTY_LATENCY ; 0 ; Signed Integer ;; USE_MEMORY_BLOCKS ; 0 ; Signed Integer ;; DATA_WIDTH ; 34 ; Signed Integer ;; EMPTY_WIDTH ; 0 ; Signed Integer ;+---------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+----------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:counter_rx_fifo_s1_agent ;+---------------------------+-------+----------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+---------------------------+-------+----------------------------------------------------------------------------------------------------------------------------+; PKT_BEGIN_BURST ; 93 ; Signed Integer ;; PKT_DATA_H ; 31 ; Signed Integer ;; PKT_DATA_L ; 0 ; Signed Integer ;; PKT_SYMBOL_W ; 8 ; Signed Integer ;; PKT_BYTEEN_H ; 35 ; Signed Integer ;; PKT_BYTEEN_L ; 32 ; Signed Integer ;; PKT_ADDR_H ; 65 ; Signed Integer ;; PKT_ADDR_L ; 36 ; Signed Integer ;; PKT_TRANS_LOCK ; 70 ; Signed Integer ;; PKT_TRANS_COMPRESSED_READ ; 66 ; Signed Integer ;; PKT_TRANS_POSTED ; 67 ; Signed Integer ;; PKT_TRANS_WRITE ; 68 ; Signed Integer ;; PKT_TRANS_READ ; 69 ; Signed Integer ;; PKT_SRC_ID_H ; 99 ; Signed Integer ;; PKT_SRC_ID_L ; 95 ; Signed Integer ;; PKT_DEST_ID_H ; 104 ; Signed Integer ;; PKT_DEST_ID_L ; 100 ; Signed Integer ;; PKT_BURSTWRAP_H ; 85 ; Signed Integer ;; PKT_BURSTWRAP_L ; 79 ; Signed Integer ;; PKT_BYTE_CNT_H ; 78 ; Signed Integer ;; PKT_BYTE_CNT_L ; 72 ; Signed Integer ;; PKT_PROTECTION_H ; 119 ; Signed Integer ;; PKT_PROTECTION_L ; 117 ; Signed Integer ;; PKT_RESPONSE_STATUS_H ; 125 ; Signed Integer ;; PKT_RESPONSE_STATUS_L ; 124 ; Signed Integer ;; PKT_BURST_SIZE_H ; 88 ; Signed Integer ;; PKT_BURST_SIZE_L ; 86 ; Signed Integer ;; PKT_ORI_BURST_SIZE_L ; 126 ; Signed Integer ;; PKT_ORI_BURST_SIZE_H ; 128 ; Signed Integer ;; ST_DATA_W ; 129 ; Signed Integer ;; ST_CHANNEL_W ; 22 ; Signed Integer ;; ADDR_W ; 30 ; Signed Integer ;; AVS_DATA_W ; 32 ; Signed Integer ;; AVS_BURSTCOUNT_W ; 3 ; Signed Integer ;; PKT_SYMBOLS ; 4 ; Signed Integer ;; PREVENT_FIFO_OVERFLOW ; 1 ; Signed Integer ;; SUPPRESS_0_BYTEEN_CMD ; 1 ; Signed Integer ;; USE_READRESPONSE ; 0 ; Signed Integer ;; USE_WRITERESPONSE ; 0 ; Signed Integer ;; AVS_BE_W ; 4 ; Signed Integer ;; BURST_SIZE_W ; 3 ; Signed Integer ;; FIFO_DATA_W ; 130 ; Signed Integer ;; ECC_ENABLE ; 0 ; Signed Integer ;+---------------------------+-------+----------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:counter_rx_fifo_s1_agent|altera_merlin_burst_uncompressor:uncompressor ;+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; ADDR_W ; 30 ; Signed Integer ;; BURSTWRAP_W ; 7 ; Signed Integer ;; BYTE_CNT_W ; 7 ; Signed Integer ;; PKT_SYMBOLS ; 4 ; Signed Integer ;; BURST_SIZE_W ; 3 ; Signed Integer ;+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+---------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rsp_fifo ;+---------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+---------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------+; SYMBOLS_PER_BEAT ; 1 ; Signed Integer ;; BITS_PER_SYMBOL ; 130 ; Signed Integer ;; FIFO_DEPTH ; 2 ; Signed Integer ;; CHANNEL_WIDTH ; 0 ; Signed Integer ;; ERROR_WIDTH ; 0 ; Signed Integer ;; USE_PACKETS ; 1 ; Signed Integer ;; USE_FILL_LEVEL ; 0 ; Signed Integer ;; USE_STORE_FORWARD ; 0 ; Signed Integer ;; USE_ALMOST_FULL_IF ; 0 ; Signed Integer ;; USE_ALMOST_EMPTY_IF ; 0 ; Signed Integer ;; EMPTY_LATENCY ; 1 ; Signed Integer ;; USE_MEMORY_BLOCKS ; 0 ; Signed Integer ;; DATA_WIDTH ; 130 ; Signed Integer ;; EMPTY_WIDTH ; 0 ; Signed Integer ;+---------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo ;+---------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+---------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------+; SYMBOLS_PER_BEAT ; 1 ; Signed Integer ;; BITS_PER_SYMBOL ; 34 ; Signed Integer ;; FIFO_DEPTH ; 2 ; Signed Integer ;; CHANNEL_WIDTH ; 0 ; Signed Integer ;; ERROR_WIDTH ; 0 ; Signed Integer ;; USE_PACKETS ; 0 ; Signed Integer ;; USE_FILL_LEVEL ; 0 ; Signed Integer ;; USE_STORE_FORWARD ; 0 ; Signed Integer ;; USE_ALMOST_FULL_IF ; 0 ; Signed Integer ;; USE_ALMOST_EMPTY_IF ; 0 ; Signed Integer ;; EMPTY_LATENCY ; 0 ; Signed Integer ;; USE_MEMORY_BLOCKS ; 0 ; Signed Integer ;; DATA_WIDTH ; 34 ; Signed Integer ;; EMPTY_WIDTH ; 0 ; Signed Integer ;+---------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_router:router|ulight_fifo_mm_interconnect_0_router_default_decode:the_default_decode ;+--------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+--------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; DEFAULT_CHANNEL ; 0 ; Signed Integer ;; DEFAULT_WR_CHANNEL ; -1 ; Signed Integer ;; DEFAULT_RD_CHANNEL ; -1 ; Signed Integer ;; DEFAULT_DESTID ; 12 ; Signed Integer ;+--------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_router:router_001|ulight_fifo_mm_interconnect_0_router_default_decode:the_default_decode ;+--------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+--------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; DEFAULT_CHANNEL ; 0 ; Signed Integer ;; DEFAULT_WR_CHANNEL ; -1 ; Signed Integer ;; DEFAULT_RD_CHANNEL ; -1 ; Signed Integer ;; DEFAULT_DESTID ; 12 ; Signed Integer ;+--------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_router_002:router_002|ulight_fifo_mm_interconnect_0_router_002_default_decode:the_default_decode ;+--------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+--------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; DEFAULT_CHANNEL ; -1 ; Signed Integer ;; DEFAULT_WR_CHANNEL ; 0 ; Signed Integer ;; DEFAULT_RD_CHANNEL ; 1 ; Signed Integer ;; DEFAULT_DESTID ; 0 ; Signed Integer ;+--------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_router_002:router_003|ulight_fifo_mm_interconnect_0_router_002_default_decode:the_default_decode ;+--------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+--------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; DEFAULT_CHANNEL ; -1 ; Signed Integer ;; DEFAULT_WR_CHANNEL ; 0 ; Signed Integer ;; DEFAULT_RD_CHANNEL ; 1 ; Signed Integer ;; DEFAULT_DESTID ; 0 ; Signed Integer ;+--------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_router_002:router_004|ulight_fifo_mm_interconnect_0_router_002_default_decode:the_default_decode ;+--------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+--------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; DEFAULT_CHANNEL ; -1 ; Signed Integer ;; DEFAULT_WR_CHANNEL ; 0 ; Signed Integer ;; DEFAULT_RD_CHANNEL ; 1 ; Signed Integer ;; DEFAULT_DESTID ; 0 ; Signed Integer ;+--------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_router_002:router_005|ulight_fifo_mm_interconnect_0_router_002_default_decode:the_default_decode ;+--------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+--------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; DEFAULT_CHANNEL ; -1 ; Signed Integer ;; DEFAULT_WR_CHANNEL ; 0 ; Signed Integer ;; DEFAULT_RD_CHANNEL ; 1 ; Signed Integer ;; DEFAULT_DESTID ; 0 ; Signed Integer ;+--------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_router_002:router_006|ulight_fifo_mm_interconnect_0_router_002_default_decode:the_default_decode ;+--------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+--------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; DEFAULT_CHANNEL ; -1 ; Signed Integer ;; DEFAULT_WR_CHANNEL ; 0 ; Signed Integer ;; DEFAULT_RD_CHANNEL ; 1 ; Signed Integer ;; DEFAULT_DESTID ; 0 ; Signed Integer ;+--------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_router_002:router_007|ulight_fifo_mm_interconnect_0_router_002_default_decode:the_default_decode ;+--------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+--------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; DEFAULT_CHANNEL ; -1 ; Signed Integer ;; DEFAULT_WR_CHANNEL ; 0 ; Signed Integer ;; DEFAULT_RD_CHANNEL ; 1 ; Signed Integer ;; DEFAULT_DESTID ; 0 ; Signed Integer ;+--------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_router_002:router_008|ulight_fifo_mm_interconnect_0_router_002_default_decode:the_default_decode ;+--------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+--------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; DEFAULT_CHANNEL ; -1 ; Signed Integer ;; DEFAULT_WR_CHANNEL ; 0 ; Signed Integer ;; DEFAULT_RD_CHANNEL ; 1 ; Signed Integer ;; DEFAULT_DESTID ; 0 ; Signed Integer ;+--------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_router_002:router_009|ulight_fifo_mm_interconnect_0_router_002_default_decode:the_default_decode ;+--------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+--------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; DEFAULT_CHANNEL ; -1 ; Signed Integer ;; DEFAULT_WR_CHANNEL ; 0 ; Signed Integer ;; DEFAULT_RD_CHANNEL ; 1 ; Signed Integer ;; DEFAULT_DESTID ; 0 ; Signed Integer ;+--------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_router_002:router_010|ulight_fifo_mm_interconnect_0_router_002_default_decode:the_default_decode ;+--------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+--------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; DEFAULT_CHANNEL ; -1 ; Signed Integer ;; DEFAULT_WR_CHANNEL ; 0 ; Signed Integer ;; DEFAULT_RD_CHANNEL ; 1 ; Signed Integer ;; DEFAULT_DESTID ; 0 ; Signed Integer ;+--------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_router_002:router_011|ulight_fifo_mm_interconnect_0_router_002_default_decode:the_default_decode ;+--------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+--------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; DEFAULT_CHANNEL ; -1 ; Signed Integer ;; DEFAULT_WR_CHANNEL ; 0 ; Signed Integer ;; DEFAULT_RD_CHANNEL ; 1 ; Signed Integer ;; DEFAULT_DESTID ; 0 ; Signed Integer ;+--------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_router_002:router_012|ulight_fifo_mm_interconnect_0_router_002_default_decode:the_default_decode ;+--------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+--------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; DEFAULT_CHANNEL ; -1 ; Signed Integer ;; DEFAULT_WR_CHANNEL ; 0 ; Signed Integer ;; DEFAULT_RD_CHANNEL ; 1 ; Signed Integer ;; DEFAULT_DESTID ; 0 ; Signed Integer ;+--------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_router_002:router_013|ulight_fifo_mm_interconnect_0_router_002_default_decode:the_default_decode ;+--------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+--------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; DEFAULT_CHANNEL ; -1 ; Signed Integer ;; DEFAULT_WR_CHANNEL ; 0 ; Signed Integer ;; DEFAULT_RD_CHANNEL ; 1 ; Signed Integer ;; DEFAULT_DESTID ; 0 ; Signed Integer ;+--------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_router_002:router_014|ulight_fifo_mm_interconnect_0_router_002_default_decode:the_default_decode ;+--------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+--------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; DEFAULT_CHANNEL ; -1 ; Signed Integer ;; DEFAULT_WR_CHANNEL ; 0 ; Signed Integer ;; DEFAULT_RD_CHANNEL ; 1 ; Signed Integer ;; DEFAULT_DESTID ; 0 ; Signed Integer ;+--------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_router_002:router_015|ulight_fifo_mm_interconnect_0_router_002_default_decode:the_default_decode ;+--------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+--------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; DEFAULT_CHANNEL ; -1 ; Signed Integer ;; DEFAULT_WR_CHANNEL ; 0 ; Signed Integer ;; DEFAULT_RD_CHANNEL ; 1 ; Signed Integer ;; DEFAULT_DESTID ; 0 ; Signed Integer ;+--------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_router_002:router_016|ulight_fifo_mm_interconnect_0_router_002_default_decode:the_default_decode ;+--------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+--------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; DEFAULT_CHANNEL ; -1 ; Signed Integer ;; DEFAULT_WR_CHANNEL ; 0 ; Signed Integer ;; DEFAULT_RD_CHANNEL ; 1 ; Signed Integer ;; DEFAULT_DESTID ; 0 ; Signed Integer ;+--------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_router_002:router_017|ulight_fifo_mm_interconnect_0_router_002_default_decode:the_default_decode ;+--------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+--------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; DEFAULT_CHANNEL ; -1 ; Signed Integer ;; DEFAULT_WR_CHANNEL ; 0 ; Signed Integer ;; DEFAULT_RD_CHANNEL ; 1 ; Signed Integer ;; DEFAULT_DESTID ; 0 ; Signed Integer ;+--------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_router_002:router_018|ulight_fifo_mm_interconnect_0_router_002_default_decode:the_default_decode ;+--------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+--------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; DEFAULT_CHANNEL ; -1 ; Signed Integer ;; DEFAULT_WR_CHANNEL ; 0 ; Signed Integer ;; DEFAULT_RD_CHANNEL ; 1 ; Signed Integer ;; DEFAULT_DESTID ; 0 ; Signed Integer ;+--------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_router_002:router_019|ulight_fifo_mm_interconnect_0_router_002_default_decode:the_default_decode ;+--------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+--------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; DEFAULT_CHANNEL ; -1 ; Signed Integer ;; DEFAULT_WR_CHANNEL ; 0 ; Signed Integer ;; DEFAULT_RD_CHANNEL ; 1 ; Signed Integer ;; DEFAULT_DESTID ; 0 ; Signed Integer ;+--------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_router_002:router_020|ulight_fifo_mm_interconnect_0_router_002_default_decode:the_default_decode ;+--------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+--------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; DEFAULT_CHANNEL ; -1 ; Signed Integer ;; DEFAULT_WR_CHANNEL ; 0 ; Signed Integer ;; DEFAULT_RD_CHANNEL ; 1 ; Signed Integer ;; DEFAULT_DESTID ; 0 ; Signed Integer ;+--------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_router_002:router_021|ulight_fifo_mm_interconnect_0_router_002_default_decode:the_default_decode ;+--------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+--------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; DEFAULT_CHANNEL ; -1 ; Signed Integer ;; DEFAULT_WR_CHANNEL ; 0 ; Signed Integer ;; DEFAULT_RD_CHANNEL ; 1 ; Signed Integer ;; DEFAULT_DESTID ; 0 ; Signed Integer ;+--------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_router_002:router_022|ulight_fifo_mm_interconnect_0_router_002_default_decode:the_default_decode ;+--------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+--------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; DEFAULT_CHANNEL ; -1 ; Signed Integer ;; DEFAULT_WR_CHANNEL ; 0 ; Signed Integer ;; DEFAULT_RD_CHANNEL ; 1 ; Signed Integer ;; DEFAULT_DESTID ; 0 ; Signed Integer ;+--------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_router_002:router_023|ulight_fifo_mm_interconnect_0_router_002_default_decode:the_default_decode ;+--------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+--------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; DEFAULT_CHANNEL ; -1 ; Signed Integer ;; DEFAULT_WR_CHANNEL ; 0 ; Signed Integer ;; DEFAULT_RD_CHANNEL ; 1 ; Signed Integer ;; DEFAULT_DESTID ; 0 ; Signed Integer ;+--------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_traffic_limiter:hps_0_h2f_axi_master_wr_limiter ;+---------------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+---------------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------+; PKT_TRANS_POSTED ; 67 ; Signed Integer ;; PKT_DEST_ID_H ; 104 ; Signed Integer ;; PKT_DEST_ID_L ; 100 ; Signed Integer ;; PKT_SRC_ID_H ; 99 ; Signed Integer ;; PKT_SRC_ID_L ; 95 ; Signed Integer ;; PKT_BYTE_CNT_H ; 78 ; Signed Integer ;; PKT_BYTE_CNT_L ; 72 ; Signed Integer ;; PKT_BYTEEN_H ; 35 ; Signed Integer ;; PKT_BYTEEN_L ; 32 ; Signed Integer ;; PKT_TRANS_WRITE ; 68 ; Signed Integer ;; PKT_TRANS_READ ; 0 ; Signed Integer ;; ST_DATA_W ; 129 ; Signed Integer ;; ST_CHANNEL_W ; 22 ; Signed Integer ;; MAX_OUTSTANDING_RESPONSES ; 3 ; Signed Integer ;; PIPELINED ; 0 ; Signed Integer ;; ENFORCE_ORDER ; 1 ; Signed Integer ;; VALID_WIDTH ; 22 ; Signed Integer ;; PREVENT_HAZARDS ; 0 ; Signed Integer ;; SUPPORTS_POSTED_WRITES ; 1 ; Signed Integer ;; SUPPORTS_NONPOSTED_WRITES ; 0 ; Signed Integer ;; REORDER ; 0 ; Signed Integer ;+---------------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_traffic_limiter:hps_0_h2f_axi_master_rd_limiter ;+---------------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+---------------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------+; PKT_TRANS_POSTED ; 67 ; Signed Integer ;; PKT_DEST_ID_H ; 104 ; Signed Integer ;; PKT_DEST_ID_L ; 100 ; Signed Integer ;; PKT_SRC_ID_H ; 99 ; Signed Integer ;; PKT_SRC_ID_L ; 95 ; Signed Integer ;; PKT_BYTE_CNT_H ; 78 ; Signed Integer ;; PKT_BYTE_CNT_L ; 72 ; Signed Integer ;; PKT_BYTEEN_H ; 35 ; Signed Integer ;; PKT_BYTEEN_L ; 32 ; Signed Integer ;; PKT_TRANS_WRITE ; 68 ; Signed Integer ;; PKT_TRANS_READ ; 0 ; Signed Integer ;; ST_DATA_W ; 129 ; Signed Integer ;; ST_CHANNEL_W ; 22 ; Signed Integer ;; MAX_OUTSTANDING_RESPONSES ; 3 ; Signed Integer ;; PIPELINED ; 0 ; Signed Integer ;; ENFORCE_ORDER ; 1 ; Signed Integer ;; VALID_WIDTH ; 22 ; Signed Integer ;; PREVENT_HAZARDS ; 0 ; Signed Integer ;; SUPPORTS_POSTED_WRITES ; 1 ; Signed Integer ;; SUPPORTS_NONPOSTED_WRITES ; 0 ; Signed Integer ;; REORDER ; 0 ; Signed Integer ;+---------------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter ;+---------------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+---------------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------+; ADAPTER_VERSION ; 13.1 ; String ;; COMPRESSED_READ_SUPPORT ; 1 ; Signed Integer ;; PKT_BEGIN_BURST ; 93 ; Signed Integer ;; PKT_ADDR_H ; 65 ; Signed Integer ;; PKT_ADDR_L ; 36 ; Signed Integer ;; PKT_BYTE_CNT_H ; 78 ; Signed Integer ;; PKT_BYTE_CNT_L ; 72 ; Signed Integer ;; PKT_BURSTWRAP_H ; 85 ; Signed Integer ;; PKT_BURSTWRAP_L ; 79 ; Signed Integer ;; PKT_TRANS_COMPRESSED_READ ; 66 ; Signed Integer ;; PKT_TRANS_WRITE ; 68 ; Signed Integer ;; PKT_TRANS_READ ; 69 ; Signed Integer ;; PKT_BYTEEN_H ; 35 ; Signed Integer ;; PKT_BYTEEN_L ; 32 ; Signed Integer ;; PKT_BURST_TYPE_H ; 90 ; Signed Integer ;; PKT_BURST_TYPE_L ; 89 ; Signed Integer ;; PKT_BURST_SIZE_H ; 88 ; Signed Integer ;; PKT_BURST_SIZE_L ; 86 ; Signed Integer ;; ST_DATA_W ; 129 ; Signed Integer ;; ST_CHANNEL_W ; 22 ; Signed Integer ;; IN_NARROW_SIZE ; 1 ; Signed Integer ;; NO_WRAP_SUPPORT ; 0 ; Signed Integer ;; INCOMPLETE_WRAP_SUPPORT ; 0 ; Signed Integer ;; BURSTWRAP_CONST_MASK ; 0 ; Signed Integer ;; BURSTWRAP_CONST_VALUE ; 0 ; Signed Integer ;; OUT_NARROW_SIZE ; 0 ; Signed Integer ;; OUT_FIXED ; 0 ; Signed Integer ;; OUT_COMPLETE_WRAP ; 0 ; Signed Integer ;; BYTEENABLE_SYNTHESIS ; 1 ; Signed Integer ;; PIPE_INPUTS ; 0 ; Signed Integer ;; OUT_BYTE_CNT_H ; 74 ; Signed Integer ;; OUT_BURSTWRAP_H ; 85 ; Signed Integer ;+---------------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ;+---------------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+---------------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; PKT_BEGIN_BURST ; 93 ; Signed Integer ;; PKT_ADDR_H ; 65 ; Signed Integer ;; PKT_ADDR_L ; 36 ; Signed Integer ;; PKT_BYTE_CNT_H ; 78 ; Signed Integer ;; PKT_BYTE_CNT_L ; 72 ; Signed Integer ;; PKT_BURSTWRAP_H ; 85 ; Signed Integer ;; PKT_BURSTWRAP_L ; 79 ; Signed Integer ;; PKT_TRANS_COMPRESSED_READ ; 66 ; Signed Integer ;; PKT_TRANS_WRITE ; 68 ; Signed Integer ;; PKT_TRANS_READ ; 69 ; Signed Integer ;; PKT_BYTEEN_H ; 35 ; Signed Integer ;; PKT_BYTEEN_L ; 32 ; Signed Integer ;; PKT_BURST_TYPE_H ; 90 ; Signed Integer ;; PKT_BURST_TYPE_L ; 89 ; Signed Integer ;; PKT_BURST_SIZE_H ; 88 ; Signed Integer ;; PKT_BURST_SIZE_L ; 86 ; Signed Integer ;; IN_NARROW_SIZE ; 1 ; Signed Integer ;; OUT_NARROW_SIZE ; 0 ; Signed Integer ;; OUT_FIXED ; 0 ; Signed Integer ;; OUT_COMPLETE_WRAP ; 0 ; Signed Integer ;; ST_DATA_W ; 129 ; Signed Integer ;; ST_CHANNEL_W ; 22 ; Signed Integer ;; BYTEENABLE_SYNTHESIS ; 1 ; Signed Integer ;; BURSTWRAP_CONST_MASK ; 0 ; Signed Integer ;; PIPE_INPUTS ; 0 ; Signed Integer ;; NO_WRAP_SUPPORT ; 0 ; Signed Integer ;; BURSTWRAP_CONST_VALUE ; 0 ; Signed Integer ;; OUT_BYTE_CNT_H ; 74 ; Signed Integer ;; OUT_BURSTWRAP_H ; 85 ; Signed Integer ;+---------------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size ;+-------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+-------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; ADDR_W ; 30 ; Signed Integer ;; BURSTWRAP_W ; 1 ; Signed Integer ;; TYPE_W ; 0 ; Signed Integer ;; SIZE_W ; 3 ; Signed Integer ;; INCREMENT_ADDRESS ; 0 ; Signed Integer ;; NUMSYMBOLS ; 4 ; Signed Integer ;; SELECT_BITS ; 2 ; Signed Integer ;; IN_DATA_W ; 33 ; Signed Integer ;; OUT_DATA_W ; 32 ; Signed Integer ;+-------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_burstwrap_increment:the_burstwrap_increment ;+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 7 ; Signed Integer ;+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min ;+-------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+-------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; PKT_BYTE_CNT_W ; 7 ; Signed Integer ;; PKT_BURSTWRAP_W ; 7 ; Signed Integer ;; PIPELINE_POSITION ; 2 ; Signed Integer ;+-------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ab_sub ;+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ab_sub|altera_merlin_burst_adapter_adder:subtract ;+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ac_sub ;+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ac_sub|altera_merlin_burst_adapter_adder:subtract ;+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:bc_sub ;+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:bc_sub|altera_merlin_burst_adapter_adder:subtract ;+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:da_sub ;+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:da_sub|altera_merlin_burst_adapter_adder:subtract ;+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:db_sub ;+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:db_sub|altera_merlin_burst_adapter_adder:subtract ;+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:dc_sub ;+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:dc_sub|altera_merlin_burst_adapter_adder:subtract ;+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+----------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter ;+---------------------------+-------+----------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+---------------------------+-------+----------------------------------------------------------------------------------------------------------------------------------+; ADAPTER_VERSION ; 13.1 ; String ;; COMPRESSED_READ_SUPPORT ; 1 ; Signed Integer ;; PKT_BEGIN_BURST ; 93 ; Signed Integer ;; PKT_ADDR_H ; 65 ; Signed Integer ;; PKT_ADDR_L ; 36 ; Signed Integer ;; PKT_BYTE_CNT_H ; 78 ; Signed Integer ;; PKT_BYTE_CNT_L ; 72 ; Signed Integer ;; PKT_BURSTWRAP_H ; 85 ; Signed Integer ;; PKT_BURSTWRAP_L ; 79 ; Signed Integer ;; PKT_TRANS_COMPRESSED_READ ; 66 ; Signed Integer ;; PKT_TRANS_WRITE ; 68 ; Signed Integer ;; PKT_TRANS_READ ; 69 ; Signed Integer ;; PKT_BYTEEN_H ; 35 ; Signed Integer ;; PKT_BYTEEN_L ; 32 ; Signed Integer ;; PKT_BURST_TYPE_H ; 90 ; Signed Integer ;; PKT_BURST_TYPE_L ; 89 ; Signed Integer ;; PKT_BURST_SIZE_H ; 88 ; Signed Integer ;; PKT_BURST_SIZE_L ; 86 ; Signed Integer ;; ST_DATA_W ; 129 ; Signed Integer ;; ST_CHANNEL_W ; 22 ; Signed Integer ;; IN_NARROW_SIZE ; 1 ; Signed Integer ;; NO_WRAP_SUPPORT ; 0 ; Signed Integer ;; INCOMPLETE_WRAP_SUPPORT ; 0 ; Signed Integer ;; BURSTWRAP_CONST_MASK ; 0 ; Signed Integer ;; BURSTWRAP_CONST_VALUE ; 0 ; Signed Integer ;; OUT_NARROW_SIZE ; 0 ; Signed Integer ;; OUT_FIXED ; 0 ; Signed Integer ;; OUT_COMPLETE_WRAP ; 0 ; Signed Integer ;; BYTEENABLE_SYNTHESIS ; 1 ; Signed Integer ;; PIPE_INPUTS ; 0 ; Signed Integer ;; OUT_BYTE_CNT_H ; 74 ; Signed Integer ;; OUT_BURSTWRAP_H ; 85 ; Signed Integer ;+---------------------------+-------+----------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ;+---------------------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+---------------------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; PKT_BEGIN_BURST ; 93 ; Signed Integer ;; PKT_ADDR_H ; 65 ; Signed Integer ;; PKT_ADDR_L ; 36 ; Signed Integer ;; PKT_BYTE_CNT_H ; 78 ; Signed Integer ;; PKT_BYTE_CNT_L ; 72 ; Signed Integer ;; PKT_BURSTWRAP_H ; 85 ; Signed Integer ;; PKT_BURSTWRAP_L ; 79 ; Signed Integer ;; PKT_TRANS_COMPRESSED_READ ; 66 ; Signed Integer ;; PKT_TRANS_WRITE ; 68 ; Signed Integer ;; PKT_TRANS_READ ; 69 ; Signed Integer ;; PKT_BYTEEN_H ; 35 ; Signed Integer ;; PKT_BYTEEN_L ; 32 ; Signed Integer ;; PKT_BURST_TYPE_H ; 90 ; Signed Integer ;; PKT_BURST_TYPE_L ; 89 ; Signed Integer ;; PKT_BURST_SIZE_H ; 88 ; Signed Integer ;; PKT_BURST_SIZE_L ; 86 ; Signed Integer ;; IN_NARROW_SIZE ; 1 ; Signed Integer ;; OUT_NARROW_SIZE ; 0 ; Signed Integer ;; OUT_FIXED ; 0 ; Signed Integer ;; OUT_COMPLETE_WRAP ; 0 ; Signed Integer ;; ST_DATA_W ; 129 ; Signed Integer ;; ST_CHANNEL_W ; 22 ; Signed Integer ;; BYTEENABLE_SYNTHESIS ; 1 ; Signed Integer ;; BURSTWRAP_CONST_MASK ; 0 ; Signed Integer ;; PIPE_INPUTS ; 0 ; Signed Integer ;; NO_WRAP_SUPPORT ; 0 ; Signed Integer ;; BURSTWRAP_CONST_VALUE ; 0 ; Signed Integer ;; OUT_BYTE_CNT_H ; 74 ; Signed Integer ;; OUT_BURSTWRAP_H ; 85 ; Signed Integer ;+---------------------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size ;+-------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+-------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; ADDR_W ; 30 ; Signed Integer ;; BURSTWRAP_W ; 1 ; Signed Integer ;; TYPE_W ; 0 ; Signed Integer ;; SIZE_W ; 3 ; Signed Integer ;; INCREMENT_ADDRESS ; 0 ; Signed Integer ;; NUMSYMBOLS ; 4 ; Signed Integer ;; SELECT_BITS ; 2 ; Signed Integer ;; IN_DATA_W ; 33 ; Signed Integer ;; OUT_DATA_W ; 32 ; Signed Integer ;+-------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_burstwrap_increment:the_burstwrap_increment ;+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 7 ; Signed Integer ;+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min ;+-------------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+-------------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; PKT_BYTE_CNT_W ; 7 ; Signed Integer ;; PKT_BURSTWRAP_W ; 7 ; Signed Integer ;; PIPELINE_POSITION ; 2 ; Signed Integer ;+-------------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ab_sub ;+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ab_sub|altera_merlin_burst_adapter_adder:subtract ;+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ac_sub ;+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ac_sub|altera_merlin_burst_adapter_adder:subtract ;+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:bc_sub ;+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:bc_sub|altera_merlin_burst_adapter_adder:subtract ;+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:da_sub ;+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:da_sub|altera_merlin_burst_adapter_adder:subtract ;+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:db_sub ;+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:db_sub|altera_merlin_burst_adapter_adder:subtract ;+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:dc_sub ;+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:dc_sub|altera_merlin_burst_adapter_adder:subtract ;+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter ;+---------------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+---------------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------+; ADAPTER_VERSION ; 13.1 ; String ;; COMPRESSED_READ_SUPPORT ; 1 ; Signed Integer ;; PKT_BEGIN_BURST ; 93 ; Signed Integer ;; PKT_ADDR_H ; 65 ; Signed Integer ;; PKT_ADDR_L ; 36 ; Signed Integer ;; PKT_BYTE_CNT_H ; 78 ; Signed Integer ;; PKT_BYTE_CNT_L ; 72 ; Signed Integer ;; PKT_BURSTWRAP_H ; 85 ; Signed Integer ;; PKT_BURSTWRAP_L ; 79 ; Signed Integer ;; PKT_TRANS_COMPRESSED_READ ; 66 ; Signed Integer ;; PKT_TRANS_WRITE ; 68 ; Signed Integer ;; PKT_TRANS_READ ; 69 ; Signed Integer ;; PKT_BYTEEN_H ; 35 ; Signed Integer ;; PKT_BYTEEN_L ; 32 ; Signed Integer ;; PKT_BURST_TYPE_H ; 90 ; Signed Integer ;; PKT_BURST_TYPE_L ; 89 ; Signed Integer ;; PKT_BURST_SIZE_H ; 88 ; Signed Integer ;; PKT_BURST_SIZE_L ; 86 ; Signed Integer ;; ST_DATA_W ; 129 ; Signed Integer ;; ST_CHANNEL_W ; 22 ; Signed Integer ;; IN_NARROW_SIZE ; 1 ; Signed Integer ;; NO_WRAP_SUPPORT ; 0 ; Signed Integer ;; INCOMPLETE_WRAP_SUPPORT ; 0 ; Signed Integer ;; BURSTWRAP_CONST_MASK ; 0 ; Signed Integer ;; BURSTWRAP_CONST_VALUE ; 0 ; Signed Integer ;; OUT_NARROW_SIZE ; 0 ; Signed Integer ;; OUT_FIXED ; 0 ; Signed Integer ;; OUT_COMPLETE_WRAP ; 0 ; Signed Integer ;; BYTEENABLE_SYNTHESIS ; 1 ; Signed Integer ;; PIPE_INPUTS ; 0 ; Signed Integer ;; OUT_BYTE_CNT_H ; 74 ; Signed Integer ;; OUT_BURSTWRAP_H ; 85 ; Signed Integer ;+---------------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ;+---------------------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+---------------------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; PKT_BEGIN_BURST ; 93 ; Signed Integer ;; PKT_ADDR_H ; 65 ; Signed Integer ;; PKT_ADDR_L ; 36 ; Signed Integer ;; PKT_BYTE_CNT_H ; 78 ; Signed Integer ;; PKT_BYTE_CNT_L ; 72 ; Signed Integer ;; PKT_BURSTWRAP_H ; 85 ; Signed Integer ;; PKT_BURSTWRAP_L ; 79 ; Signed Integer ;; PKT_TRANS_COMPRESSED_READ ; 66 ; Signed Integer ;; PKT_TRANS_WRITE ; 68 ; Signed Integer ;; PKT_TRANS_READ ; 69 ; Signed Integer ;; PKT_BYTEEN_H ; 35 ; Signed Integer ;; PKT_BYTEEN_L ; 32 ; Signed Integer ;; PKT_BURST_TYPE_H ; 90 ; Signed Integer ;; PKT_BURST_TYPE_L ; 89 ; Signed Integer ;; PKT_BURST_SIZE_H ; 88 ; Signed Integer ;; PKT_BURST_SIZE_L ; 86 ; Signed Integer ;; IN_NARROW_SIZE ; 1 ; Signed Integer ;; OUT_NARROW_SIZE ; 0 ; Signed Integer ;; OUT_FIXED ; 0 ; Signed Integer ;; OUT_COMPLETE_WRAP ; 0 ; Signed Integer ;; ST_DATA_W ; 129 ; Signed Integer ;; ST_CHANNEL_W ; 22 ; Signed Integer ;; BYTEENABLE_SYNTHESIS ; 1 ; Signed Integer ;; BURSTWRAP_CONST_MASK ; 0 ; Signed Integer ;; PIPE_INPUTS ; 0 ; Signed Integer ;; NO_WRAP_SUPPORT ; 0 ; Signed Integer ;; BURSTWRAP_CONST_VALUE ; 0 ; Signed Integer ;; OUT_BYTE_CNT_H ; 74 ; Signed Integer ;; OUT_BURSTWRAP_H ; 85 ; Signed Integer ;+---------------------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size ;+-------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+-------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; ADDR_W ; 30 ; Signed Integer ;; BURSTWRAP_W ; 1 ; Signed Integer ;; TYPE_W ; 0 ; Signed Integer ;; SIZE_W ; 3 ; Signed Integer ;; INCREMENT_ADDRESS ; 0 ; Signed Integer ;; NUMSYMBOLS ; 4 ; Signed Integer ;; SELECT_BITS ; 2 ; Signed Integer ;; IN_DATA_W ; 33 ; Signed Integer ;; OUT_DATA_W ; 32 ; Signed Integer ;+-------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_burstwrap_increment:the_burstwrap_increment ;+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 7 ; Signed Integer ;+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min ;+-------------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+-------------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; PKT_BYTE_CNT_W ; 7 ; Signed Integer ;; PKT_BURSTWRAP_W ; 7 ; Signed Integer ;; PIPELINE_POSITION ; 2 ; Signed Integer ;+-------------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ab_sub ;+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ab_sub|altera_merlin_burst_adapter_adder:subtract ;+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ac_sub ;+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ac_sub|altera_merlin_burst_adapter_adder:subtract ;+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:bc_sub ;+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:bc_sub|altera_merlin_burst_adapter_adder:subtract ;+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:da_sub ;+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:da_sub|altera_merlin_burst_adapter_adder:subtract ;+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:db_sub ;+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:db_sub|altera_merlin_burst_adapter_adder:subtract ;+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:dc_sub ;+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:dc_sub|altera_merlin_burst_adapter_adder:subtract ;+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter ;+---------------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+---------------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------+; ADAPTER_VERSION ; 13.1 ; String ;; COMPRESSED_READ_SUPPORT ; 1 ; Signed Integer ;; PKT_BEGIN_BURST ; 93 ; Signed Integer ;; PKT_ADDR_H ; 65 ; Signed Integer ;; PKT_ADDR_L ; 36 ; Signed Integer ;; PKT_BYTE_CNT_H ; 78 ; Signed Integer ;; PKT_BYTE_CNT_L ; 72 ; Signed Integer ;; PKT_BURSTWRAP_H ; 85 ; Signed Integer ;; PKT_BURSTWRAP_L ; 79 ; Signed Integer ;; PKT_TRANS_COMPRESSED_READ ; 66 ; Signed Integer ;; PKT_TRANS_WRITE ; 68 ; Signed Integer ;; PKT_TRANS_READ ; 69 ; Signed Integer ;; PKT_BYTEEN_H ; 35 ; Signed Integer ;; PKT_BYTEEN_L ; 32 ; Signed Integer ;; PKT_BURST_TYPE_H ; 90 ; Signed Integer ;; PKT_BURST_TYPE_L ; 89 ; Signed Integer ;; PKT_BURST_SIZE_H ; 88 ; Signed Integer ;; PKT_BURST_SIZE_L ; 86 ; Signed Integer ;; ST_DATA_W ; 129 ; Signed Integer ;; ST_CHANNEL_W ; 22 ; Signed Integer ;; IN_NARROW_SIZE ; 1 ; Signed Integer ;; NO_WRAP_SUPPORT ; 0 ; Signed Integer ;; INCOMPLETE_WRAP_SUPPORT ; 0 ; Signed Integer ;; BURSTWRAP_CONST_MASK ; 0 ; Signed Integer ;; BURSTWRAP_CONST_VALUE ; 0 ; Signed Integer ;; OUT_NARROW_SIZE ; 0 ; Signed Integer ;; OUT_FIXED ; 0 ; Signed Integer ;; OUT_COMPLETE_WRAP ; 0 ; Signed Integer ;; BYTEENABLE_SYNTHESIS ; 1 ; Signed Integer ;; PIPE_INPUTS ; 0 ; Signed Integer ;; OUT_BYTE_CNT_H ; 74 ; Signed Integer ;; OUT_BURSTWRAP_H ; 85 ; Signed Integer ;+---------------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ;+---------------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+---------------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; PKT_BEGIN_BURST ; 93 ; Signed Integer ;; PKT_ADDR_H ; 65 ; Signed Integer ;; PKT_ADDR_L ; 36 ; Signed Integer ;; PKT_BYTE_CNT_H ; 78 ; Signed Integer ;; PKT_BYTE_CNT_L ; 72 ; Signed Integer ;; PKT_BURSTWRAP_H ; 85 ; Signed Integer ;; PKT_BURSTWRAP_L ; 79 ; Signed Integer ;; PKT_TRANS_COMPRESSED_READ ; 66 ; Signed Integer ;; PKT_TRANS_WRITE ; 68 ; Signed Integer ;; PKT_TRANS_READ ; 69 ; Signed Integer ;; PKT_BYTEEN_H ; 35 ; Signed Integer ;; PKT_BYTEEN_L ; 32 ; Signed Integer ;; PKT_BURST_TYPE_H ; 90 ; Signed Integer ;; PKT_BURST_TYPE_L ; 89 ; Signed Integer ;; PKT_BURST_SIZE_H ; 88 ; Signed Integer ;; PKT_BURST_SIZE_L ; 86 ; Signed Integer ;; IN_NARROW_SIZE ; 1 ; Signed Integer ;; OUT_NARROW_SIZE ; 0 ; Signed Integer ;; OUT_FIXED ; 0 ; Signed Integer ;; OUT_COMPLETE_WRAP ; 0 ; Signed Integer ;; ST_DATA_W ; 129 ; Signed Integer ;; ST_CHANNEL_W ; 22 ; Signed Integer ;; BYTEENABLE_SYNTHESIS ; 1 ; Signed Integer ;; BURSTWRAP_CONST_MASK ; 0 ; Signed Integer ;; PIPE_INPUTS ; 0 ; Signed Integer ;; NO_WRAP_SUPPORT ; 0 ; Signed Integer ;; BURSTWRAP_CONST_VALUE ; 0 ; Signed Integer ;; OUT_BYTE_CNT_H ; 74 ; Signed Integer ;; OUT_BURSTWRAP_H ; 85 ; Signed Integer ;+---------------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size ;+-------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+-------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; ADDR_W ; 30 ; Signed Integer ;; BURSTWRAP_W ; 1 ; Signed Integer ;; TYPE_W ; 0 ; Signed Integer ;; SIZE_W ; 3 ; Signed Integer ;; INCREMENT_ADDRESS ; 0 ; Signed Integer ;; NUMSYMBOLS ; 4 ; Signed Integer ;; SELECT_BITS ; 2 ; Signed Integer ;; IN_DATA_W ; 33 ; Signed Integer ;; OUT_DATA_W ; 32 ; Signed Integer ;+-------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_burstwrap_increment:the_burstwrap_increment ;+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 7 ; Signed Integer ;+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min ;+-------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+-------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; PKT_BYTE_CNT_W ; 7 ; Signed Integer ;; PKT_BURSTWRAP_W ; 7 ; Signed Integer ;; PIPELINE_POSITION ; 2 ; Signed Integer ;+-------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ab_sub ;+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ab_sub|altera_merlin_burst_adapter_adder:subtract ;+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ac_sub ;+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ac_sub|altera_merlin_burst_adapter_adder:subtract ;+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:bc_sub ;+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:bc_sub|altera_merlin_burst_adapter_adder:subtract ;+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:da_sub ;+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:da_sub|altera_merlin_burst_adapter_adder:subtract ;+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:db_sub ;+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:db_sub|altera_merlin_burst_adapter_adder:subtract ;+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:dc_sub ;+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:dc_sub|altera_merlin_burst_adapter_adder:subtract ;+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter ;+---------------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+---------------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------+; ADAPTER_VERSION ; 13.1 ; String ;; COMPRESSED_READ_SUPPORT ; 1 ; Signed Integer ;; PKT_BEGIN_BURST ; 93 ; Signed Integer ;; PKT_ADDR_H ; 65 ; Signed Integer ;; PKT_ADDR_L ; 36 ; Signed Integer ;; PKT_BYTE_CNT_H ; 78 ; Signed Integer ;; PKT_BYTE_CNT_L ; 72 ; Signed Integer ;; PKT_BURSTWRAP_H ; 85 ; Signed Integer ;; PKT_BURSTWRAP_L ; 79 ; Signed Integer ;; PKT_TRANS_COMPRESSED_READ ; 66 ; Signed Integer ;; PKT_TRANS_WRITE ; 68 ; Signed Integer ;; PKT_TRANS_READ ; 69 ; Signed Integer ;; PKT_BYTEEN_H ; 35 ; Signed Integer ;; PKT_BYTEEN_L ; 32 ; Signed Integer ;; PKT_BURST_TYPE_H ; 90 ; Signed Integer ;; PKT_BURST_TYPE_L ; 89 ; Signed Integer ;; PKT_BURST_SIZE_H ; 88 ; Signed Integer ;; PKT_BURST_SIZE_L ; 86 ; Signed Integer ;; ST_DATA_W ; 129 ; Signed Integer ;; ST_CHANNEL_W ; 22 ; Signed Integer ;; IN_NARROW_SIZE ; 1 ; Signed Integer ;; NO_WRAP_SUPPORT ; 0 ; Signed Integer ;; INCOMPLETE_WRAP_SUPPORT ; 0 ; Signed Integer ;; BURSTWRAP_CONST_MASK ; 0 ; Signed Integer ;; BURSTWRAP_CONST_VALUE ; 0 ; Signed Integer ;; OUT_NARROW_SIZE ; 0 ; Signed Integer ;; OUT_FIXED ; 0 ; Signed Integer ;; OUT_COMPLETE_WRAP ; 0 ; Signed Integer ;; BYTEENABLE_SYNTHESIS ; 1 ; Signed Integer ;; PIPE_INPUTS ; 0 ; Signed Integer ;; OUT_BYTE_CNT_H ; 74 ; Signed Integer ;; OUT_BURSTWRAP_H ; 85 ; Signed Integer ;+---------------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ;+---------------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+---------------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; PKT_BEGIN_BURST ; 93 ; Signed Integer ;; PKT_ADDR_H ; 65 ; Signed Integer ;; PKT_ADDR_L ; 36 ; Signed Integer ;; PKT_BYTE_CNT_H ; 78 ; Signed Integer ;; PKT_BYTE_CNT_L ; 72 ; Signed Integer ;; PKT_BURSTWRAP_H ; 85 ; Signed Integer ;; PKT_BURSTWRAP_L ; 79 ; Signed Integer ;; PKT_TRANS_COMPRESSED_READ ; 66 ; Signed Integer ;; PKT_TRANS_WRITE ; 68 ; Signed Integer ;; PKT_TRANS_READ ; 69 ; Signed Integer ;; PKT_BYTEEN_H ; 35 ; Signed Integer ;; PKT_BYTEEN_L ; 32 ; Signed Integer ;; PKT_BURST_TYPE_H ; 90 ; Signed Integer ;; PKT_BURST_TYPE_L ; 89 ; Signed Integer ;; PKT_BURST_SIZE_H ; 88 ; Signed Integer ;; PKT_BURST_SIZE_L ; 86 ; Signed Integer ;; IN_NARROW_SIZE ; 1 ; Signed Integer ;; OUT_NARROW_SIZE ; 0 ; Signed Integer ;; OUT_FIXED ; 0 ; Signed Integer ;; OUT_COMPLETE_WRAP ; 0 ; Signed Integer ;; ST_DATA_W ; 129 ; Signed Integer ;; ST_CHANNEL_W ; 22 ; Signed Integer ;; BYTEENABLE_SYNTHESIS ; 1 ; Signed Integer ;; BURSTWRAP_CONST_MASK ; 0 ; Signed Integer ;; PIPE_INPUTS ; 0 ; Signed Integer ;; NO_WRAP_SUPPORT ; 0 ; Signed Integer ;; BURSTWRAP_CONST_VALUE ; 0 ; Signed Integer ;; OUT_BYTE_CNT_H ; 74 ; Signed Integer ;; OUT_BURSTWRAP_H ; 85 ; Signed Integer ;+---------------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size ;+-------------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+-------------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; ADDR_W ; 30 ; Signed Integer ;; BURSTWRAP_W ; 1 ; Signed Integer ;; TYPE_W ; 0 ; Signed Integer ;; SIZE_W ; 3 ; Signed Integer ;; INCREMENT_ADDRESS ; 0 ; Signed Integer ;; NUMSYMBOLS ; 4 ; Signed Integer ;; SELECT_BITS ; 2 ; Signed Integer ;; IN_DATA_W ; 33 ; Signed Integer ;; OUT_DATA_W ; 32 ; Signed Integer ;+-------------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_burstwrap_increment:the_burstwrap_increment ;+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 7 ; Signed Integer ;+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min ;+-------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+-------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; PKT_BYTE_CNT_W ; 7 ; Signed Integer ;; PKT_BURSTWRAP_W ; 7 ; Signed Integer ;; PIPELINE_POSITION ; 2 ; Signed Integer ;+-------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ab_sub ;+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ab_sub|altera_merlin_burst_adapter_adder:subtract ;+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ac_sub ;+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ac_sub|altera_merlin_burst_adapter_adder:subtract ;+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:bc_sub ;+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:bc_sub|altera_merlin_burst_adapter_adder:subtract ;+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:da_sub ;+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:da_sub|altera_merlin_burst_adapter_adder:subtract ;+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:db_sub ;+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:db_sub|altera_merlin_burst_adapter_adder:subtract ;+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:dc_sub ;+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:dc_sub|altera_merlin_burst_adapter_adder:subtract ;+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter ;+---------------------------+-------+------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+---------------------------+-------+------------------------------------------------------------------------------------------------------------------------------------------+; ADAPTER_VERSION ; 13.1 ; String ;; COMPRESSED_READ_SUPPORT ; 1 ; Signed Integer ;; PKT_BEGIN_BURST ; 93 ; Signed Integer ;; PKT_ADDR_H ; 65 ; Signed Integer ;; PKT_ADDR_L ; 36 ; Signed Integer ;; PKT_BYTE_CNT_H ; 78 ; Signed Integer ;; PKT_BYTE_CNT_L ; 72 ; Signed Integer ;; PKT_BURSTWRAP_H ; 85 ; Signed Integer ;; PKT_BURSTWRAP_L ; 79 ; Signed Integer ;; PKT_TRANS_COMPRESSED_READ ; 66 ; Signed Integer ;; PKT_TRANS_WRITE ; 68 ; Signed Integer ;; PKT_TRANS_READ ; 69 ; Signed Integer ;; PKT_BYTEEN_H ; 35 ; Signed Integer ;; PKT_BYTEEN_L ; 32 ; Signed Integer ;; PKT_BURST_TYPE_H ; 90 ; Signed Integer ;; PKT_BURST_TYPE_L ; 89 ; Signed Integer ;; PKT_BURST_SIZE_H ; 88 ; Signed Integer ;; PKT_BURST_SIZE_L ; 86 ; Signed Integer ;; ST_DATA_W ; 129 ; Signed Integer ;; ST_CHANNEL_W ; 22 ; Signed Integer ;; IN_NARROW_SIZE ; 1 ; Signed Integer ;; NO_WRAP_SUPPORT ; 0 ; Signed Integer ;; INCOMPLETE_WRAP_SUPPORT ; 0 ; Signed Integer ;; BURSTWRAP_CONST_MASK ; 0 ; Signed Integer ;; BURSTWRAP_CONST_VALUE ; 0 ; Signed Integer ;; OUT_NARROW_SIZE ; 0 ; Signed Integer ;; OUT_FIXED ; 0 ; Signed Integer ;; OUT_COMPLETE_WRAP ; 0 ; Signed Integer ;; BYTEENABLE_SYNTHESIS ; 1 ; Signed Integer ;; PIPE_INPUTS ; 0 ; Signed Integer ;; OUT_BYTE_CNT_H ; 74 ; Signed Integer ;; OUT_BURSTWRAP_H ; 85 ; Signed Integer ;+---------------------------+-------+------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ;+---------------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+---------------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; PKT_BEGIN_BURST ; 93 ; Signed Integer ;; PKT_ADDR_H ; 65 ; Signed Integer ;; PKT_ADDR_L ; 36 ; Signed Integer ;; PKT_BYTE_CNT_H ; 78 ; Signed Integer ;; PKT_BYTE_CNT_L ; 72 ; Signed Integer ;; PKT_BURSTWRAP_H ; 85 ; Signed Integer ;; PKT_BURSTWRAP_L ; 79 ; Signed Integer ;; PKT_TRANS_COMPRESSED_READ ; 66 ; Signed Integer ;; PKT_TRANS_WRITE ; 68 ; Signed Integer ;; PKT_TRANS_READ ; 69 ; Signed Integer ;; PKT_BYTEEN_H ; 35 ; Signed Integer ;; PKT_BYTEEN_L ; 32 ; Signed Integer ;; PKT_BURST_TYPE_H ; 90 ; Signed Integer ;; PKT_BURST_TYPE_L ; 89 ; Signed Integer ;; PKT_BURST_SIZE_H ; 88 ; Signed Integer ;; PKT_BURST_SIZE_L ; 86 ; Signed Integer ;; IN_NARROW_SIZE ; 1 ; Signed Integer ;; OUT_NARROW_SIZE ; 0 ; Signed Integer ;; OUT_FIXED ; 0 ; Signed Integer ;; OUT_COMPLETE_WRAP ; 0 ; Signed Integer ;; ST_DATA_W ; 129 ; Signed Integer ;; ST_CHANNEL_W ; 22 ; Signed Integer ;; BYTEENABLE_SYNTHESIS ; 1 ; Signed Integer ;; BURSTWRAP_CONST_MASK ; 0 ; Signed Integer ;; PIPE_INPUTS ; 0 ; Signed Integer ;; NO_WRAP_SUPPORT ; 0 ; Signed Integer ;; BURSTWRAP_CONST_VALUE ; 0 ; Signed Integer ;; OUT_BYTE_CNT_H ; 74 ; Signed Integer ;; OUT_BURSTWRAP_H ; 85 ; Signed Integer ;+---------------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size ;+-------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+-------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; ADDR_W ; 30 ; Signed Integer ;; BURSTWRAP_W ; 1 ; Signed Integer ;; TYPE_W ; 0 ; Signed Integer ;; SIZE_W ; 3 ; Signed Integer ;; INCREMENT_ADDRESS ; 0 ; Signed Integer ;; NUMSYMBOLS ; 4 ; Signed Integer ;; SELECT_BITS ; 2 ; Signed Integer ;; IN_DATA_W ; 33 ; Signed Integer ;; OUT_DATA_W ; 32 ; Signed Integer ;+-------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_burstwrap_increment:the_burstwrap_increment ;+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 7 ; Signed Integer ;+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min ;+-------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+-------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; PKT_BYTE_CNT_W ; 7 ; Signed Integer ;; PKT_BURSTWRAP_W ; 7 ; Signed Integer ;; PIPELINE_POSITION ; 2 ; Signed Integer ;+-------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ab_sub ;+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ab_sub|altera_merlin_burst_adapter_adder:subtract ;+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ac_sub ;+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ac_sub|altera_merlin_burst_adapter_adder:subtract ;+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:bc_sub ;+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:bc_sub|altera_merlin_burst_adapter_adder:subtract ;+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:da_sub ;+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:da_sub|altera_merlin_burst_adapter_adder:subtract ;+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:db_sub ;+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:db_sub|altera_merlin_burst_adapter_adder:subtract ;+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:dc_sub ;+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:dc_sub|altera_merlin_burst_adapter_adder:subtract ;+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter ;+---------------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+---------------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------+; ADAPTER_VERSION ; 13.1 ; String ;; COMPRESSED_READ_SUPPORT ; 1 ; Signed Integer ;; PKT_BEGIN_BURST ; 93 ; Signed Integer ;; PKT_ADDR_H ; 65 ; Signed Integer ;; PKT_ADDR_L ; 36 ; Signed Integer ;; PKT_BYTE_CNT_H ; 78 ; Signed Integer ;; PKT_BYTE_CNT_L ; 72 ; Signed Integer ;; PKT_BURSTWRAP_H ; 85 ; Signed Integer ;; PKT_BURSTWRAP_L ; 79 ; Signed Integer ;; PKT_TRANS_COMPRESSED_READ ; 66 ; Signed Integer ;; PKT_TRANS_WRITE ; 68 ; Signed Integer ;; PKT_TRANS_READ ; 69 ; Signed Integer ;; PKT_BYTEEN_H ; 35 ; Signed Integer ;; PKT_BYTEEN_L ; 32 ; Signed Integer ;; PKT_BURST_TYPE_H ; 90 ; Signed Integer ;; PKT_BURST_TYPE_L ; 89 ; Signed Integer ;; PKT_BURST_SIZE_H ; 88 ; Signed Integer ;; PKT_BURST_SIZE_L ; 86 ; Signed Integer ;; ST_DATA_W ; 129 ; Signed Integer ;; ST_CHANNEL_W ; 22 ; Signed Integer ;; IN_NARROW_SIZE ; 1 ; Signed Integer ;; NO_WRAP_SUPPORT ; 0 ; Signed Integer ;; INCOMPLETE_WRAP_SUPPORT ; 0 ; Signed Integer ;; BURSTWRAP_CONST_MASK ; 0 ; Signed Integer ;; BURSTWRAP_CONST_VALUE ; 0 ; Signed Integer ;; OUT_NARROW_SIZE ; 0 ; Signed Integer ;; OUT_FIXED ; 0 ; Signed Integer ;; OUT_COMPLETE_WRAP ; 0 ; Signed Integer ;; BYTEENABLE_SYNTHESIS ; 1 ; Signed Integer ;; PIPE_INPUTS ; 0 ; Signed Integer ;; OUT_BYTE_CNT_H ; 74 ; Signed Integer ;; OUT_BURSTWRAP_H ; 85 ; Signed Integer ;+---------------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ;+---------------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+---------------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; PKT_BEGIN_BURST ; 93 ; Signed Integer ;; PKT_ADDR_H ; 65 ; Signed Integer ;; PKT_ADDR_L ; 36 ; Signed Integer ;; PKT_BYTE_CNT_H ; 78 ; Signed Integer ;; PKT_BYTE_CNT_L ; 72 ; Signed Integer ;; PKT_BURSTWRAP_H ; 85 ; Signed Integer ;; PKT_BURSTWRAP_L ; 79 ; Signed Integer ;; PKT_TRANS_COMPRESSED_READ ; 66 ; Signed Integer ;; PKT_TRANS_WRITE ; 68 ; Signed Integer ;; PKT_TRANS_READ ; 69 ; Signed Integer ;; PKT_BYTEEN_H ; 35 ; Signed Integer ;; PKT_BYTEEN_L ; 32 ; Signed Integer ;; PKT_BURST_TYPE_H ; 90 ; Signed Integer ;; PKT_BURST_TYPE_L ; 89 ; Signed Integer ;; PKT_BURST_SIZE_H ; 88 ; Signed Integer ;; PKT_BURST_SIZE_L ; 86 ; Signed Integer ;; IN_NARROW_SIZE ; 1 ; Signed Integer ;; OUT_NARROW_SIZE ; 0 ; Signed Integer ;; OUT_FIXED ; 0 ; Signed Integer ;; OUT_COMPLETE_WRAP ; 0 ; Signed Integer ;; ST_DATA_W ; 129 ; Signed Integer ;; ST_CHANNEL_W ; 22 ; Signed Integer ;; BYTEENABLE_SYNTHESIS ; 1 ; Signed Integer ;; BURSTWRAP_CONST_MASK ; 0 ; Signed Integer ;; PIPE_INPUTS ; 0 ; Signed Integer ;; NO_WRAP_SUPPORT ; 0 ; Signed Integer ;; BURSTWRAP_CONST_VALUE ; 0 ; Signed Integer ;; OUT_BYTE_CNT_H ; 74 ; Signed Integer ;; OUT_BURSTWRAP_H ; 85 ; Signed Integer ;+---------------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size ;+-------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+-------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; ADDR_W ; 30 ; Signed Integer ;; BURSTWRAP_W ; 1 ; Signed Integer ;; TYPE_W ; 0 ; Signed Integer ;; SIZE_W ; 3 ; Signed Integer ;; INCREMENT_ADDRESS ; 0 ; Signed Integer ;; NUMSYMBOLS ; 4 ; Signed Integer ;; SELECT_BITS ; 2 ; Signed Integer ;; IN_DATA_W ; 33 ; Signed Integer ;; OUT_DATA_W ; 32 ; Signed Integer ;+-------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_burstwrap_increment:the_burstwrap_increment ;+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 7 ; Signed Integer ;+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min ;+-------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+-------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; PKT_BYTE_CNT_W ; 7 ; Signed Integer ;; PKT_BURSTWRAP_W ; 7 ; Signed Integer ;; PIPELINE_POSITION ; 2 ; Signed Integer ;+-------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ab_sub ;+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ab_sub|altera_merlin_burst_adapter_adder:subtract ;+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ac_sub ;+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ac_sub|altera_merlin_burst_adapter_adder:subtract ;+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:bc_sub ;+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:bc_sub|altera_merlin_burst_adapter_adder:subtract ;+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:da_sub ;+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:da_sub|altera_merlin_burst_adapter_adder:subtract ;+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:db_sub ;+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:db_sub|altera_merlin_burst_adapter_adder:subtract ;+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:dc_sub ;+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:dc_sub|altera_merlin_burst_adapter_adder:subtract ;+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+---------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter ;+---------------------------+-------+---------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+---------------------------+-------+---------------------------------------------------------------------------------------------------------------------------------+; ADAPTER_VERSION ; 13.1 ; String ;; COMPRESSED_READ_SUPPORT ; 1 ; Signed Integer ;; PKT_BEGIN_BURST ; 93 ; Signed Integer ;; PKT_ADDR_H ; 65 ; Signed Integer ;; PKT_ADDR_L ; 36 ; Signed Integer ;; PKT_BYTE_CNT_H ; 78 ; Signed Integer ;; PKT_BYTE_CNT_L ; 72 ; Signed Integer ;; PKT_BURSTWRAP_H ; 85 ; Signed Integer ;; PKT_BURSTWRAP_L ; 79 ; Signed Integer ;; PKT_TRANS_COMPRESSED_READ ; 66 ; Signed Integer ;; PKT_TRANS_WRITE ; 68 ; Signed Integer ;; PKT_TRANS_READ ; 69 ; Signed Integer ;; PKT_BYTEEN_H ; 35 ; Signed Integer ;; PKT_BYTEEN_L ; 32 ; Signed Integer ;; PKT_BURST_TYPE_H ; 90 ; Signed Integer ;; PKT_BURST_TYPE_L ; 89 ; Signed Integer ;; PKT_BURST_SIZE_H ; 88 ; Signed Integer ;; PKT_BURST_SIZE_L ; 86 ; Signed Integer ;; ST_DATA_W ; 129 ; Signed Integer ;; ST_CHANNEL_W ; 22 ; Signed Integer ;; IN_NARROW_SIZE ; 1 ; Signed Integer ;; NO_WRAP_SUPPORT ; 0 ; Signed Integer ;; INCOMPLETE_WRAP_SUPPORT ; 0 ; Signed Integer ;; BURSTWRAP_CONST_MASK ; 0 ; Signed Integer ;; BURSTWRAP_CONST_VALUE ; 0 ; Signed Integer ;; OUT_NARROW_SIZE ; 0 ; Signed Integer ;; OUT_FIXED ; 0 ; Signed Integer ;; OUT_COMPLETE_WRAP ; 0 ; Signed Integer ;; BYTEENABLE_SYNTHESIS ; 1 ; Signed Integer ;; PIPE_INPUTS ; 0 ; Signed Integer ;; OUT_BYTE_CNT_H ; 74 ; Signed Integer ;; OUT_BURSTWRAP_H ; 85 ; Signed Integer ;+---------------------------+-------+---------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ;+---------------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+---------------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; PKT_BEGIN_BURST ; 93 ; Signed Integer ;; PKT_ADDR_H ; 65 ; Signed Integer ;; PKT_ADDR_L ; 36 ; Signed Integer ;; PKT_BYTE_CNT_H ; 78 ; Signed Integer ;; PKT_BYTE_CNT_L ; 72 ; Signed Integer ;; PKT_BURSTWRAP_H ; 85 ; Signed Integer ;; PKT_BURSTWRAP_L ; 79 ; Signed Integer ;; PKT_TRANS_COMPRESSED_READ ; 66 ; Signed Integer ;; PKT_TRANS_WRITE ; 68 ; Signed Integer ;; PKT_TRANS_READ ; 69 ; Signed Integer ;; PKT_BYTEEN_H ; 35 ; Signed Integer ;; PKT_BYTEEN_L ; 32 ; Signed Integer ;; PKT_BURST_TYPE_H ; 90 ; Signed Integer ;; PKT_BURST_TYPE_L ; 89 ; Signed Integer ;; PKT_BURST_SIZE_H ; 88 ; Signed Integer ;; PKT_BURST_SIZE_L ; 86 ; Signed Integer ;; IN_NARROW_SIZE ; 1 ; Signed Integer ;; OUT_NARROW_SIZE ; 0 ; Signed Integer ;; OUT_FIXED ; 0 ; Signed Integer ;; OUT_COMPLETE_WRAP ; 0 ; Signed Integer ;; ST_DATA_W ; 129 ; Signed Integer ;; ST_CHANNEL_W ; 22 ; Signed Integer ;; BYTEENABLE_SYNTHESIS ; 1 ; Signed Integer ;; BURSTWRAP_CONST_MASK ; 0 ; Signed Integer ;; PIPE_INPUTS ; 0 ; Signed Integer ;; NO_WRAP_SUPPORT ; 0 ; Signed Integer ;; BURSTWRAP_CONST_VALUE ; 0 ; Signed Integer ;; OUT_BYTE_CNT_H ; 74 ; Signed Integer ;; OUT_BURSTWRAP_H ; 85 ; Signed Integer ;+---------------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size ;+-------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+-------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; ADDR_W ; 30 ; Signed Integer ;; BURSTWRAP_W ; 1 ; Signed Integer ;; TYPE_W ; 0 ; Signed Integer ;; SIZE_W ; 3 ; Signed Integer ;; INCREMENT_ADDRESS ; 0 ; Signed Integer ;; NUMSYMBOLS ; 4 ; Signed Integer ;; SELECT_BITS ; 2 ; Signed Integer ;; IN_DATA_W ; 33 ; Signed Integer ;; OUT_DATA_W ; 32 ; Signed Integer ;+-------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_burstwrap_increment:the_burstwrap_increment ;+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 7 ; Signed Integer ;+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min ;+-------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+-------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; PKT_BYTE_CNT_W ; 7 ; Signed Integer ;; PKT_BURSTWRAP_W ; 7 ; Signed Integer ;; PIPELINE_POSITION ; 2 ; Signed Integer ;+-------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ab_sub ;+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ab_sub|altera_merlin_burst_adapter_adder:subtract ;+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ac_sub ;+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ac_sub|altera_merlin_burst_adapter_adder:subtract ;+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:bc_sub ;+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:bc_sub|altera_merlin_burst_adapter_adder:subtract ;+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:da_sub ;+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:da_sub|altera_merlin_burst_adapter_adder:subtract ;+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:db_sub ;+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:db_sub|altera_merlin_burst_adapter_adder:subtract ;+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:dc_sub ;+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:dc_sub|altera_merlin_burst_adapter_adder:subtract ;+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+---------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter ;+---------------------------+-------+---------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+---------------------------+-------+---------------------------------------------------------------------------------------------------------------------------------+; ADAPTER_VERSION ; 13.1 ; String ;; COMPRESSED_READ_SUPPORT ; 1 ; Signed Integer ;; PKT_BEGIN_BURST ; 93 ; Signed Integer ;; PKT_ADDR_H ; 65 ; Signed Integer ;; PKT_ADDR_L ; 36 ; Signed Integer ;; PKT_BYTE_CNT_H ; 78 ; Signed Integer ;; PKT_BYTE_CNT_L ; 72 ; Signed Integer ;; PKT_BURSTWRAP_H ; 85 ; Signed Integer ;; PKT_BURSTWRAP_L ; 79 ; Signed Integer ;; PKT_TRANS_COMPRESSED_READ ; 66 ; Signed Integer ;; PKT_TRANS_WRITE ; 68 ; Signed Integer ;; PKT_TRANS_READ ; 69 ; Signed Integer ;; PKT_BYTEEN_H ; 35 ; Signed Integer ;; PKT_BYTEEN_L ; 32 ; Signed Integer ;; PKT_BURST_TYPE_H ; 90 ; Signed Integer ;; PKT_BURST_TYPE_L ; 89 ; Signed Integer ;; PKT_BURST_SIZE_H ; 88 ; Signed Integer ;; PKT_BURST_SIZE_L ; 86 ; Signed Integer ;; ST_DATA_W ; 129 ; Signed Integer ;; ST_CHANNEL_W ; 22 ; Signed Integer ;; IN_NARROW_SIZE ; 1 ; Signed Integer ;; NO_WRAP_SUPPORT ; 0 ; Signed Integer ;; INCOMPLETE_WRAP_SUPPORT ; 0 ; Signed Integer ;; BURSTWRAP_CONST_MASK ; 0 ; Signed Integer ;; BURSTWRAP_CONST_VALUE ; 0 ; Signed Integer ;; OUT_NARROW_SIZE ; 0 ; Signed Integer ;; OUT_FIXED ; 0 ; Signed Integer ;; OUT_COMPLETE_WRAP ; 0 ; Signed Integer ;; BYTEENABLE_SYNTHESIS ; 1 ; Signed Integer ;; PIPE_INPUTS ; 0 ; Signed Integer ;; OUT_BYTE_CNT_H ; 74 ; Signed Integer ;; OUT_BURSTWRAP_H ; 85 ; Signed Integer ;+---------------------------+-------+---------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ;+---------------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+---------------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; PKT_BEGIN_BURST ; 93 ; Signed Integer ;; PKT_ADDR_H ; 65 ; Signed Integer ;; PKT_ADDR_L ; 36 ; Signed Integer ;; PKT_BYTE_CNT_H ; 78 ; Signed Integer ;; PKT_BYTE_CNT_L ; 72 ; Signed Integer ;; PKT_BURSTWRAP_H ; 85 ; Signed Integer ;; PKT_BURSTWRAP_L ; 79 ; Signed Integer ;; PKT_TRANS_COMPRESSED_READ ; 66 ; Signed Integer ;; PKT_TRANS_WRITE ; 68 ; Signed Integer ;; PKT_TRANS_READ ; 69 ; Signed Integer ;; PKT_BYTEEN_H ; 35 ; Signed Integer ;; PKT_BYTEEN_L ; 32 ; Signed Integer ;; PKT_BURST_TYPE_H ; 90 ; Signed Integer ;; PKT_BURST_TYPE_L ; 89 ; Signed Integer ;; PKT_BURST_SIZE_H ; 88 ; Signed Integer ;; PKT_BURST_SIZE_L ; 86 ; Signed Integer ;; IN_NARROW_SIZE ; 1 ; Signed Integer ;; OUT_NARROW_SIZE ; 0 ; Signed Integer ;; OUT_FIXED ; 0 ; Signed Integer ;; OUT_COMPLETE_WRAP ; 0 ; Signed Integer ;; ST_DATA_W ; 129 ; Signed Integer ;; ST_CHANNEL_W ; 22 ; Signed Integer ;; BYTEENABLE_SYNTHESIS ; 1 ; Signed Integer ;; BURSTWRAP_CONST_MASK ; 0 ; Signed Integer ;; PIPE_INPUTS ; 0 ; Signed Integer ;; NO_WRAP_SUPPORT ; 0 ; Signed Integer ;; BURSTWRAP_CONST_VALUE ; 0 ; Signed Integer ;; OUT_BYTE_CNT_H ; 74 ; Signed Integer ;; OUT_BURSTWRAP_H ; 85 ; Signed Integer ;+---------------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size ;+-------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+-------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; ADDR_W ; 30 ; Signed Integer ;; BURSTWRAP_W ; 1 ; Signed Integer ;; TYPE_W ; 0 ; Signed Integer ;; SIZE_W ; 3 ; Signed Integer ;; INCREMENT_ADDRESS ; 0 ; Signed Integer ;; NUMSYMBOLS ; 4 ; Signed Integer ;; SELECT_BITS ; 2 ; Signed Integer ;; IN_DATA_W ; 33 ; Signed Integer ;; OUT_DATA_W ; 32 ; Signed Integer ;+-------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_burstwrap_increment:the_burstwrap_increment ;+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 7 ; Signed Integer ;+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min ;+-------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+-------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; PKT_BYTE_CNT_W ; 7 ; Signed Integer ;; PKT_BURSTWRAP_W ; 7 ; Signed Integer ;; PIPELINE_POSITION ; 2 ; Signed Integer ;+-------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ab_sub ;+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ab_sub|altera_merlin_burst_adapter_adder:subtract ;+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ac_sub ;+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ac_sub|altera_merlin_burst_adapter_adder:subtract ;+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:bc_sub ;+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:bc_sub|altera_merlin_burst_adapter_adder:subtract ;+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:da_sub ;+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:da_sub|altera_merlin_burst_adapter_adder:subtract ;+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:db_sub ;+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:db_sub|altera_merlin_burst_adapter_adder:subtract ;+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:dc_sub ;+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:dc_sub|altera_merlin_burst_adapter_adder:subtract ;+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter ;+---------------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+---------------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------+; ADAPTER_VERSION ; 13.1 ; String ;; COMPRESSED_READ_SUPPORT ; 1 ; Signed Integer ;; PKT_BEGIN_BURST ; 93 ; Signed Integer ;; PKT_ADDR_H ; 65 ; Signed Integer ;; PKT_ADDR_L ; 36 ; Signed Integer ;; PKT_BYTE_CNT_H ; 78 ; Signed Integer ;; PKT_BYTE_CNT_L ; 72 ; Signed Integer ;; PKT_BURSTWRAP_H ; 85 ; Signed Integer ;; PKT_BURSTWRAP_L ; 79 ; Signed Integer ;; PKT_TRANS_COMPRESSED_READ ; 66 ; Signed Integer ;; PKT_TRANS_WRITE ; 68 ; Signed Integer ;; PKT_TRANS_READ ; 69 ; Signed Integer ;; PKT_BYTEEN_H ; 35 ; Signed Integer ;; PKT_BYTEEN_L ; 32 ; Signed Integer ;; PKT_BURST_TYPE_H ; 90 ; Signed Integer ;; PKT_BURST_TYPE_L ; 89 ; Signed Integer ;; PKT_BURST_SIZE_H ; 88 ; Signed Integer ;; PKT_BURST_SIZE_L ; 86 ; Signed Integer ;; ST_DATA_W ; 129 ; Signed Integer ;; ST_CHANNEL_W ; 22 ; Signed Integer ;; IN_NARROW_SIZE ; 1 ; Signed Integer ;; NO_WRAP_SUPPORT ; 0 ; Signed Integer ;; INCOMPLETE_WRAP_SUPPORT ; 0 ; Signed Integer ;; BURSTWRAP_CONST_MASK ; 0 ; Signed Integer ;; BURSTWRAP_CONST_VALUE ; 0 ; Signed Integer ;; OUT_NARROW_SIZE ; 0 ; Signed Integer ;; OUT_FIXED ; 0 ; Signed Integer ;; OUT_COMPLETE_WRAP ; 0 ; Signed Integer ;; BYTEENABLE_SYNTHESIS ; 1 ; Signed Integer ;; PIPE_INPUTS ; 0 ; Signed Integer ;; OUT_BYTE_CNT_H ; 74 ; Signed Integer ;; OUT_BURSTWRAP_H ; 85 ; Signed Integer ;+---------------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ;+---------------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+---------------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; PKT_BEGIN_BURST ; 93 ; Signed Integer ;; PKT_ADDR_H ; 65 ; Signed Integer ;; PKT_ADDR_L ; 36 ; Signed Integer ;; PKT_BYTE_CNT_H ; 78 ; Signed Integer ;; PKT_BYTE_CNT_L ; 72 ; Signed Integer ;; PKT_BURSTWRAP_H ; 85 ; Signed Integer ;; PKT_BURSTWRAP_L ; 79 ; Signed Integer ;; PKT_TRANS_COMPRESSED_READ ; 66 ; Signed Integer ;; PKT_TRANS_WRITE ; 68 ; Signed Integer ;; PKT_TRANS_READ ; 69 ; Signed Integer ;; PKT_BYTEEN_H ; 35 ; Signed Integer ;; PKT_BYTEEN_L ; 32 ; Signed Integer ;; PKT_BURST_TYPE_H ; 90 ; Signed Integer ;; PKT_BURST_TYPE_L ; 89 ; Signed Integer ;; PKT_BURST_SIZE_H ; 88 ; Signed Integer ;; PKT_BURST_SIZE_L ; 86 ; Signed Integer ;; IN_NARROW_SIZE ; 1 ; Signed Integer ;; OUT_NARROW_SIZE ; 0 ; Signed Integer ;; OUT_FIXED ; 0 ; Signed Integer ;; OUT_COMPLETE_WRAP ; 0 ; Signed Integer ;; ST_DATA_W ; 129 ; Signed Integer ;; ST_CHANNEL_W ; 22 ; Signed Integer ;; BYTEENABLE_SYNTHESIS ; 1 ; Signed Integer ;; BURSTWRAP_CONST_MASK ; 0 ; Signed Integer ;; PIPE_INPUTS ; 0 ; Signed Integer ;; NO_WRAP_SUPPORT ; 0 ; Signed Integer ;; BURSTWRAP_CONST_VALUE ; 0 ; Signed Integer ;; OUT_BYTE_CNT_H ; 74 ; Signed Integer ;; OUT_BURSTWRAP_H ; 85 ; Signed Integer ;+---------------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size ;+-------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+-------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; ADDR_W ; 30 ; Signed Integer ;; BURSTWRAP_W ; 1 ; Signed Integer ;; TYPE_W ; 0 ; Signed Integer ;; SIZE_W ; 3 ; Signed Integer ;; INCREMENT_ADDRESS ; 0 ; Signed Integer ;; NUMSYMBOLS ; 4 ; Signed Integer ;; SELECT_BITS ; 2 ; Signed Integer ;; IN_DATA_W ; 33 ; Signed Integer ;; OUT_DATA_W ; 32 ; Signed Integer ;+-------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_burstwrap_increment:the_burstwrap_increment ;+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 7 ; Signed Integer ;+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min ;+-------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+-------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; PKT_BYTE_CNT_W ; 7 ; Signed Integer ;; PKT_BURSTWRAP_W ; 7 ; Signed Integer ;; PIPELINE_POSITION ; 2 ; Signed Integer ;+-------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ab_sub ;+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ab_sub|altera_merlin_burst_adapter_adder:subtract ;+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ac_sub ;+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ac_sub|altera_merlin_burst_adapter_adder:subtract ;+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:bc_sub ;+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:bc_sub|altera_merlin_burst_adapter_adder:subtract ;+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:da_sub ;+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:da_sub|altera_merlin_burst_adapter_adder:subtract ;+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:db_sub ;+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:db_sub|altera_merlin_burst_adapter_adder:subtract ;+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:dc_sub ;+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:dc_sub|altera_merlin_burst_adapter_adder:subtract ;+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter ;+---------------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+---------------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------+; ADAPTER_VERSION ; 13.1 ; String ;; COMPRESSED_READ_SUPPORT ; 1 ; Signed Integer ;; PKT_BEGIN_BURST ; 93 ; Signed Integer ;; PKT_ADDR_H ; 65 ; Signed Integer ;; PKT_ADDR_L ; 36 ; Signed Integer ;; PKT_BYTE_CNT_H ; 78 ; Signed Integer ;; PKT_BYTE_CNT_L ; 72 ; Signed Integer ;; PKT_BURSTWRAP_H ; 85 ; Signed Integer ;; PKT_BURSTWRAP_L ; 79 ; Signed Integer ;; PKT_TRANS_COMPRESSED_READ ; 66 ; Signed Integer ;; PKT_TRANS_WRITE ; 68 ; Signed Integer ;; PKT_TRANS_READ ; 69 ; Signed Integer ;; PKT_BYTEEN_H ; 35 ; Signed Integer ;; PKT_BYTEEN_L ; 32 ; Signed Integer ;; PKT_BURST_TYPE_H ; 90 ; Signed Integer ;; PKT_BURST_TYPE_L ; 89 ; Signed Integer ;; PKT_BURST_SIZE_H ; 88 ; Signed Integer ;; PKT_BURST_SIZE_L ; 86 ; Signed Integer ;; ST_DATA_W ; 129 ; Signed Integer ;; ST_CHANNEL_W ; 22 ; Signed Integer ;; IN_NARROW_SIZE ; 1 ; Signed Integer ;; NO_WRAP_SUPPORT ; 0 ; Signed Integer ;; INCOMPLETE_WRAP_SUPPORT ; 0 ; Signed Integer ;; BURSTWRAP_CONST_MASK ; 0 ; Signed Integer ;; BURSTWRAP_CONST_VALUE ; 0 ; Signed Integer ;; OUT_NARROW_SIZE ; 0 ; Signed Integer ;; OUT_FIXED ; 0 ; Signed Integer ;; OUT_COMPLETE_WRAP ; 0 ; Signed Integer ;; BYTEENABLE_SYNTHESIS ; 1 ; Signed Integer ;; PIPE_INPUTS ; 0 ; Signed Integer ;; OUT_BYTE_CNT_H ; 74 ; Signed Integer ;; OUT_BURSTWRAP_H ; 85 ; Signed Integer ;+---------------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ;+---------------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+---------------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; PKT_BEGIN_BURST ; 93 ; Signed Integer ;; PKT_ADDR_H ; 65 ; Signed Integer ;; PKT_ADDR_L ; 36 ; Signed Integer ;; PKT_BYTE_CNT_H ; 78 ; Signed Integer ;; PKT_BYTE_CNT_L ; 72 ; Signed Integer ;; PKT_BURSTWRAP_H ; 85 ; Signed Integer ;; PKT_BURSTWRAP_L ; 79 ; Signed Integer ;; PKT_TRANS_COMPRESSED_READ ; 66 ; Signed Integer ;; PKT_TRANS_WRITE ; 68 ; Signed Integer ;; PKT_TRANS_READ ; 69 ; Signed Integer ;; PKT_BYTEEN_H ; 35 ; Signed Integer ;; PKT_BYTEEN_L ; 32 ; Signed Integer ;; PKT_BURST_TYPE_H ; 90 ; Signed Integer ;; PKT_BURST_TYPE_L ; 89 ; Signed Integer ;; PKT_BURST_SIZE_H ; 88 ; Signed Integer ;; PKT_BURST_SIZE_L ; 86 ; Signed Integer ;; IN_NARROW_SIZE ; 1 ; Signed Integer ;; OUT_NARROW_SIZE ; 0 ; Signed Integer ;; OUT_FIXED ; 0 ; Signed Integer ;; OUT_COMPLETE_WRAP ; 0 ; Signed Integer ;; ST_DATA_W ; 129 ; Signed Integer ;; ST_CHANNEL_W ; 22 ; Signed Integer ;; BYTEENABLE_SYNTHESIS ; 1 ; Signed Integer ;; BURSTWRAP_CONST_MASK ; 0 ; Signed Integer ;; PIPE_INPUTS ; 0 ; Signed Integer ;; NO_WRAP_SUPPORT ; 0 ; Signed Integer ;; BURSTWRAP_CONST_VALUE ; 0 ; Signed Integer ;; OUT_BYTE_CNT_H ; 74 ; Signed Integer ;; OUT_BURSTWRAP_H ; 85 ; Signed Integer ;+---------------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size ;+-------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+-------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; ADDR_W ; 30 ; Signed Integer ;; BURSTWRAP_W ; 1 ; Signed Integer ;; TYPE_W ; 0 ; Signed Integer ;; SIZE_W ; 3 ; Signed Integer ;; INCREMENT_ADDRESS ; 0 ; Signed Integer ;; NUMSYMBOLS ; 4 ; Signed Integer ;; SELECT_BITS ; 2 ; Signed Integer ;; IN_DATA_W ; 33 ; Signed Integer ;; OUT_DATA_W ; 32 ; Signed Integer ;+-------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_burstwrap_increment:the_burstwrap_increment ;+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 7 ; Signed Integer ;+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min ;+-------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+-------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; PKT_BYTE_CNT_W ; 7 ; Signed Integer ;; PKT_BURSTWRAP_W ; 7 ; Signed Integer ;; PIPELINE_POSITION ; 2 ; Signed Integer ;+-------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ab_sub ;+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ab_sub|altera_merlin_burst_adapter_adder:subtract ;+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ac_sub ;+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ac_sub|altera_merlin_burst_adapter_adder:subtract ;+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:bc_sub ;+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:bc_sub|altera_merlin_burst_adapter_adder:subtract ;+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:da_sub ;+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:da_sub|altera_merlin_burst_adapter_adder:subtract ;+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:db_sub ;+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:db_sub|altera_merlin_burst_adapter_adder:subtract ;+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:dc_sub ;+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:dc_sub|altera_merlin_burst_adapter_adder:subtract ;+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+----------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter ;+---------------------------+-------+----------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+---------------------------+-------+----------------------------------------------------------------------------------------------------------------------------------+; ADAPTER_VERSION ; 13.1 ; String ;; COMPRESSED_READ_SUPPORT ; 1 ; Signed Integer ;; PKT_BEGIN_BURST ; 93 ; Signed Integer ;; PKT_ADDR_H ; 65 ; Signed Integer ;; PKT_ADDR_L ; 36 ; Signed Integer ;; PKT_BYTE_CNT_H ; 78 ; Signed Integer ;; PKT_BYTE_CNT_L ; 72 ; Signed Integer ;; PKT_BURSTWRAP_H ; 85 ; Signed Integer ;; PKT_BURSTWRAP_L ; 79 ; Signed Integer ;; PKT_TRANS_COMPRESSED_READ ; 66 ; Signed Integer ;; PKT_TRANS_WRITE ; 68 ; Signed Integer ;; PKT_TRANS_READ ; 69 ; Signed Integer ;; PKT_BYTEEN_H ; 35 ; Signed Integer ;; PKT_BYTEEN_L ; 32 ; Signed Integer ;; PKT_BURST_TYPE_H ; 90 ; Signed Integer ;; PKT_BURST_TYPE_L ; 89 ; Signed Integer ;; PKT_BURST_SIZE_H ; 88 ; Signed Integer ;; PKT_BURST_SIZE_L ; 86 ; Signed Integer ;; ST_DATA_W ; 129 ; Signed Integer ;; ST_CHANNEL_W ; 22 ; Signed Integer ;; IN_NARROW_SIZE ; 1 ; Signed Integer ;; NO_WRAP_SUPPORT ; 0 ; Signed Integer ;; INCOMPLETE_WRAP_SUPPORT ; 0 ; Signed Integer ;; BURSTWRAP_CONST_MASK ; 0 ; Signed Integer ;; BURSTWRAP_CONST_VALUE ; 0 ; Signed Integer ;; OUT_NARROW_SIZE ; 0 ; Signed Integer ;; OUT_FIXED ; 0 ; Signed Integer ;; OUT_COMPLETE_WRAP ; 0 ; Signed Integer ;; BYTEENABLE_SYNTHESIS ; 1 ; Signed Integer ;; PIPE_INPUTS ; 0 ; Signed Integer ;; OUT_BYTE_CNT_H ; 74 ; Signed Integer ;; OUT_BURSTWRAP_H ; 85 ; Signed Integer ;+---------------------------+-------+----------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ;+---------------------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+---------------------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; PKT_BEGIN_BURST ; 93 ; Signed Integer ;; PKT_ADDR_H ; 65 ; Signed Integer ;; PKT_ADDR_L ; 36 ; Signed Integer ;; PKT_BYTE_CNT_H ; 78 ; Signed Integer ;; PKT_BYTE_CNT_L ; 72 ; Signed Integer ;; PKT_BURSTWRAP_H ; 85 ; Signed Integer ;; PKT_BURSTWRAP_L ; 79 ; Signed Integer ;; PKT_TRANS_COMPRESSED_READ ; 66 ; Signed Integer ;; PKT_TRANS_WRITE ; 68 ; Signed Integer ;; PKT_TRANS_READ ; 69 ; Signed Integer ;; PKT_BYTEEN_H ; 35 ; Signed Integer ;; PKT_BYTEEN_L ; 32 ; Signed Integer ;; PKT_BURST_TYPE_H ; 90 ; Signed Integer ;; PKT_BURST_TYPE_L ; 89 ; Signed Integer ;; PKT_BURST_SIZE_H ; 88 ; Signed Integer ;; PKT_BURST_SIZE_L ; 86 ; Signed Integer ;; IN_NARROW_SIZE ; 1 ; Signed Integer ;; OUT_NARROW_SIZE ; 0 ; Signed Integer ;; OUT_FIXED ; 0 ; Signed Integer ;; OUT_COMPLETE_WRAP ; 0 ; Signed Integer ;; ST_DATA_W ; 129 ; Signed Integer ;; ST_CHANNEL_W ; 22 ; Signed Integer ;; BYTEENABLE_SYNTHESIS ; 1 ; Signed Integer ;; BURSTWRAP_CONST_MASK ; 0 ; Signed Integer ;; PIPE_INPUTS ; 0 ; Signed Integer ;; NO_WRAP_SUPPORT ; 0 ; Signed Integer ;; BURSTWRAP_CONST_VALUE ; 0 ; Signed Integer ;; OUT_BYTE_CNT_H ; 74 ; Signed Integer ;; OUT_BURSTWRAP_H ; 85 ; Signed Integer ;+---------------------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size ;+-------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+-------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; ADDR_W ; 30 ; Signed Integer ;; BURSTWRAP_W ; 1 ; Signed Integer ;; TYPE_W ; 0 ; Signed Integer ;; SIZE_W ; 3 ; Signed Integer ;; INCREMENT_ADDRESS ; 0 ; Signed Integer ;; NUMSYMBOLS ; 4 ; Signed Integer ;; SELECT_BITS ; 2 ; Signed Integer ;; IN_DATA_W ; 33 ; Signed Integer ;; OUT_DATA_W ; 32 ; Signed Integer ;+-------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_burstwrap_increment:the_burstwrap_increment ;+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 7 ; Signed Integer ;+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min ;+-------------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+-------------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; PKT_BYTE_CNT_W ; 7 ; Signed Integer ;; PKT_BURSTWRAP_W ; 7 ; Signed Integer ;; PIPELINE_POSITION ; 2 ; Signed Integer ;+-------------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ab_sub ;+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ab_sub|altera_merlin_burst_adapter_adder:subtract ;+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ac_sub ;+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ac_sub|altera_merlin_burst_adapter_adder:subtract ;+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:bc_sub ;+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:bc_sub|altera_merlin_burst_adapter_adder:subtract ;+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:da_sub ;+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:da_sub|altera_merlin_burst_adapter_adder:subtract ;+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:db_sub ;+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:db_sub|altera_merlin_burst_adapter_adder:subtract ;+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:dc_sub ;+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:dc_sub|altera_merlin_burst_adapter_adder:subtract ;+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter ;+---------------------------+-------+------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+---------------------------+-------+------------------------------------------------------------------------------------------------------------------------------------------+; ADAPTER_VERSION ; 13.1 ; String ;; COMPRESSED_READ_SUPPORT ; 1 ; Signed Integer ;; PKT_BEGIN_BURST ; 93 ; Signed Integer ;; PKT_ADDR_H ; 65 ; Signed Integer ;; PKT_ADDR_L ; 36 ; Signed Integer ;; PKT_BYTE_CNT_H ; 78 ; Signed Integer ;; PKT_BYTE_CNT_L ; 72 ; Signed Integer ;; PKT_BURSTWRAP_H ; 85 ; Signed Integer ;; PKT_BURSTWRAP_L ; 79 ; Signed Integer ;; PKT_TRANS_COMPRESSED_READ ; 66 ; Signed Integer ;; PKT_TRANS_WRITE ; 68 ; Signed Integer ;; PKT_TRANS_READ ; 69 ; Signed Integer ;; PKT_BYTEEN_H ; 35 ; Signed Integer ;; PKT_BYTEEN_L ; 32 ; Signed Integer ;; PKT_BURST_TYPE_H ; 90 ; Signed Integer ;; PKT_BURST_TYPE_L ; 89 ; Signed Integer ;; PKT_BURST_SIZE_H ; 88 ; Signed Integer ;; PKT_BURST_SIZE_L ; 86 ; Signed Integer ;; ST_DATA_W ; 129 ; Signed Integer ;; ST_CHANNEL_W ; 22 ; Signed Integer ;; IN_NARROW_SIZE ; 1 ; Signed Integer ;; NO_WRAP_SUPPORT ; 0 ; Signed Integer ;; INCOMPLETE_WRAP_SUPPORT ; 0 ; Signed Integer ;; BURSTWRAP_CONST_MASK ; 0 ; Signed Integer ;; BURSTWRAP_CONST_VALUE ; 0 ; Signed Integer ;; OUT_NARROW_SIZE ; 0 ; Signed Integer ;; OUT_FIXED ; 0 ; Signed Integer ;; OUT_COMPLETE_WRAP ; 0 ; Signed Integer ;; BYTEENABLE_SYNTHESIS ; 1 ; Signed Integer ;; PIPE_INPUTS ; 0 ; Signed Integer ;; OUT_BYTE_CNT_H ; 74 ; Signed Integer ;; OUT_BURSTWRAP_H ; 85 ; Signed Integer ;+---------------------------+-------+------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ;+---------------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+---------------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; PKT_BEGIN_BURST ; 93 ; Signed Integer ;; PKT_ADDR_H ; 65 ; Signed Integer ;; PKT_ADDR_L ; 36 ; Signed Integer ;; PKT_BYTE_CNT_H ; 78 ; Signed Integer ;; PKT_BYTE_CNT_L ; 72 ; Signed Integer ;; PKT_BURSTWRAP_H ; 85 ; Signed Integer ;; PKT_BURSTWRAP_L ; 79 ; Signed Integer ;; PKT_TRANS_COMPRESSED_READ ; 66 ; Signed Integer ;; PKT_TRANS_WRITE ; 68 ; Signed Integer ;; PKT_TRANS_READ ; 69 ; Signed Integer ;; PKT_BYTEEN_H ; 35 ; Signed Integer ;; PKT_BYTEEN_L ; 32 ; Signed Integer ;; PKT_BURST_TYPE_H ; 90 ; Signed Integer ;; PKT_BURST_TYPE_L ; 89 ; Signed Integer ;; PKT_BURST_SIZE_H ; 88 ; Signed Integer ;; PKT_BURST_SIZE_L ; 86 ; Signed Integer ;; IN_NARROW_SIZE ; 1 ; Signed Integer ;; OUT_NARROW_SIZE ; 0 ; Signed Integer ;; OUT_FIXED ; 0 ; Signed Integer ;; OUT_COMPLETE_WRAP ; 0 ; Signed Integer ;; ST_DATA_W ; 129 ; Signed Integer ;; ST_CHANNEL_W ; 22 ; Signed Integer ;; BYTEENABLE_SYNTHESIS ; 1 ; Signed Integer ;; BURSTWRAP_CONST_MASK ; 0 ; Signed Integer ;; PIPE_INPUTS ; 0 ; Signed Integer ;; NO_WRAP_SUPPORT ; 0 ; Signed Integer ;; BURSTWRAP_CONST_VALUE ; 0 ; Signed Integer ;; OUT_BYTE_CNT_H ; 74 ; Signed Integer ;; OUT_BURSTWRAP_H ; 85 ; Signed Integer ;+---------------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size ;+-------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+-------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; ADDR_W ; 30 ; Signed Integer ;; BURSTWRAP_W ; 1 ; Signed Integer ;; TYPE_W ; 0 ; Signed Integer ;; SIZE_W ; 3 ; Signed Integer ;; INCREMENT_ADDRESS ; 0 ; Signed Integer ;; NUMSYMBOLS ; 4 ; Signed Integer ;; SELECT_BITS ; 2 ; Signed Integer ;; IN_DATA_W ; 33 ; Signed Integer ;; OUT_DATA_W ; 32 ; Signed Integer ;+-------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_burstwrap_increment:the_burstwrap_increment ;+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 7 ; Signed Integer ;+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min ;+-------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+-------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; PKT_BYTE_CNT_W ; 7 ; Signed Integer ;; PKT_BURSTWRAP_W ; 7 ; Signed Integer ;; PIPELINE_POSITION ; 2 ; Signed Integer ;+-------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ab_sub ;+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ab_sub|altera_merlin_burst_adapter_adder:subtract ;+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ac_sub ;+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ac_sub|altera_merlin_burst_adapter_adder:subtract ;+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:bc_sub ;+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:bc_sub|altera_merlin_burst_adapter_adder:subtract ;+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:da_sub ;+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:da_sub|altera_merlin_burst_adapter_adder:subtract ;+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:db_sub ;+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:db_sub|altera_merlin_burst_adapter_adder:subtract ;+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:dc_sub ;+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:dc_sub|altera_merlin_burst_adapter_adder:subtract ;+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter ;+---------------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+---------------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------+; ADAPTER_VERSION ; 13.1 ; String ;; COMPRESSED_READ_SUPPORT ; 1 ; Signed Integer ;; PKT_BEGIN_BURST ; 93 ; Signed Integer ;; PKT_ADDR_H ; 65 ; Signed Integer ;; PKT_ADDR_L ; 36 ; Signed Integer ;; PKT_BYTE_CNT_H ; 78 ; Signed Integer ;; PKT_BYTE_CNT_L ; 72 ; Signed Integer ;; PKT_BURSTWRAP_H ; 85 ; Signed Integer ;; PKT_BURSTWRAP_L ; 79 ; Signed Integer ;; PKT_TRANS_COMPRESSED_READ ; 66 ; Signed Integer ;; PKT_TRANS_WRITE ; 68 ; Signed Integer ;; PKT_TRANS_READ ; 69 ; Signed Integer ;; PKT_BYTEEN_H ; 35 ; Signed Integer ;; PKT_BYTEEN_L ; 32 ; Signed Integer ;; PKT_BURST_TYPE_H ; 90 ; Signed Integer ;; PKT_BURST_TYPE_L ; 89 ; Signed Integer ;; PKT_BURST_SIZE_H ; 88 ; Signed Integer ;; PKT_BURST_SIZE_L ; 86 ; Signed Integer ;; ST_DATA_W ; 129 ; Signed Integer ;; ST_CHANNEL_W ; 22 ; Signed Integer ;; IN_NARROW_SIZE ; 1 ; Signed Integer ;; NO_WRAP_SUPPORT ; 0 ; Signed Integer ;; INCOMPLETE_WRAP_SUPPORT ; 0 ; Signed Integer ;; BURSTWRAP_CONST_MASK ; 0 ; Signed Integer ;; BURSTWRAP_CONST_VALUE ; 0 ; Signed Integer ;; OUT_NARROW_SIZE ; 0 ; Signed Integer ;; OUT_FIXED ; 0 ; Signed Integer ;; OUT_COMPLETE_WRAP ; 0 ; Signed Integer ;; BYTEENABLE_SYNTHESIS ; 1 ; Signed Integer ;; PIPE_INPUTS ; 0 ; Signed Integer ;; OUT_BYTE_CNT_H ; 74 ; Signed Integer ;; OUT_BURSTWRAP_H ; 85 ; Signed Integer ;+---------------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ;+---------------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+---------------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; PKT_BEGIN_BURST ; 93 ; Signed Integer ;; PKT_ADDR_H ; 65 ; Signed Integer ;; PKT_ADDR_L ; 36 ; Signed Integer ;; PKT_BYTE_CNT_H ; 78 ; Signed Integer ;; PKT_BYTE_CNT_L ; 72 ; Signed Integer ;; PKT_BURSTWRAP_H ; 85 ; Signed Integer ;; PKT_BURSTWRAP_L ; 79 ; Signed Integer ;; PKT_TRANS_COMPRESSED_READ ; 66 ; Signed Integer ;; PKT_TRANS_WRITE ; 68 ; Signed Integer ;; PKT_TRANS_READ ; 69 ; Signed Integer ;; PKT_BYTEEN_H ; 35 ; Signed Integer ;; PKT_BYTEEN_L ; 32 ; Signed Integer ;; PKT_BURST_TYPE_H ; 90 ; Signed Integer ;; PKT_BURST_TYPE_L ; 89 ; Signed Integer ;; PKT_BURST_SIZE_H ; 88 ; Signed Integer ;; PKT_BURST_SIZE_L ; 86 ; Signed Integer ;; IN_NARROW_SIZE ; 1 ; Signed Integer ;; OUT_NARROW_SIZE ; 0 ; Signed Integer ;; OUT_FIXED ; 0 ; Signed Integer ;; OUT_COMPLETE_WRAP ; 0 ; Signed Integer ;; ST_DATA_W ; 129 ; Signed Integer ;; ST_CHANNEL_W ; 22 ; Signed Integer ;; BYTEENABLE_SYNTHESIS ; 1 ; Signed Integer ;; BURSTWRAP_CONST_MASK ; 0 ; Signed Integer ;; PIPE_INPUTS ; 0 ; Signed Integer ;; NO_WRAP_SUPPORT ; 0 ; Signed Integer ;; BURSTWRAP_CONST_VALUE ; 0 ; Signed Integer ;; OUT_BYTE_CNT_H ; 74 ; Signed Integer ;; OUT_BURSTWRAP_H ; 85 ; Signed Integer ;+---------------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size ;+-------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+-------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; ADDR_W ; 30 ; Signed Integer ;; BURSTWRAP_W ; 1 ; Signed Integer ;; TYPE_W ; 0 ; Signed Integer ;; SIZE_W ; 3 ; Signed Integer ;; INCREMENT_ADDRESS ; 0 ; Signed Integer ;; NUMSYMBOLS ; 4 ; Signed Integer ;; SELECT_BITS ; 2 ; Signed Integer ;; IN_DATA_W ; 33 ; Signed Integer ;; OUT_DATA_W ; 32 ; Signed Integer ;+-------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_burstwrap_increment:the_burstwrap_increment ;+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 7 ; Signed Integer ;+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min ;+-------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+-------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; PKT_BYTE_CNT_W ; 7 ; Signed Integer ;; PKT_BURSTWRAP_W ; 7 ; Signed Integer ;; PIPELINE_POSITION ; 2 ; Signed Integer ;+-------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ab_sub ;+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ab_sub|altera_merlin_burst_adapter_adder:subtract ;+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ac_sub ;+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ac_sub|altera_merlin_burst_adapter_adder:subtract ;+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:bc_sub ;+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:bc_sub|altera_merlin_burst_adapter_adder:subtract ;+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:da_sub ;+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:da_sub|altera_merlin_burst_adapter_adder:subtract ;+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:db_sub ;+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:db_sub|altera_merlin_burst_adapter_adder:subtract ;+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:dc_sub ;+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:dc_sub|altera_merlin_burst_adapter_adder:subtract ;+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter ;+---------------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+---------------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------+; ADAPTER_VERSION ; 13.1 ; String ;; COMPRESSED_READ_SUPPORT ; 1 ; Signed Integer ;; PKT_BEGIN_BURST ; 93 ; Signed Integer ;; PKT_ADDR_H ; 65 ; Signed Integer ;; PKT_ADDR_L ; 36 ; Signed Integer ;; PKT_BYTE_CNT_H ; 78 ; Signed Integer ;; PKT_BYTE_CNT_L ; 72 ; Signed Integer ;; PKT_BURSTWRAP_H ; 85 ; Signed Integer ;; PKT_BURSTWRAP_L ; 79 ; Signed Integer ;; PKT_TRANS_COMPRESSED_READ ; 66 ; Signed Integer ;; PKT_TRANS_WRITE ; 68 ; Signed Integer ;; PKT_TRANS_READ ; 69 ; Signed Integer ;; PKT_BYTEEN_H ; 35 ; Signed Integer ;; PKT_BYTEEN_L ; 32 ; Signed Integer ;; PKT_BURST_TYPE_H ; 90 ; Signed Integer ;; PKT_BURST_TYPE_L ; 89 ; Signed Integer ;; PKT_BURST_SIZE_H ; 88 ; Signed Integer ;; PKT_BURST_SIZE_L ; 86 ; Signed Integer ;; ST_DATA_W ; 129 ; Signed Integer ;; ST_CHANNEL_W ; 22 ; Signed Integer ;; IN_NARROW_SIZE ; 1 ; Signed Integer ;; NO_WRAP_SUPPORT ; 0 ; Signed Integer ;; INCOMPLETE_WRAP_SUPPORT ; 0 ; Signed Integer ;; BURSTWRAP_CONST_MASK ; 0 ; Signed Integer ;; BURSTWRAP_CONST_VALUE ; 0 ; Signed Integer ;; OUT_NARROW_SIZE ; 0 ; Signed Integer ;; OUT_FIXED ; 0 ; Signed Integer ;; OUT_COMPLETE_WRAP ; 0 ; Signed Integer ;; BYTEENABLE_SYNTHESIS ; 1 ; Signed Integer ;; PIPE_INPUTS ; 0 ; Signed Integer ;; OUT_BYTE_CNT_H ; 74 ; Signed Integer ;; OUT_BURSTWRAP_H ; 85 ; Signed Integer ;+---------------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ;+---------------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+---------------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; PKT_BEGIN_BURST ; 93 ; Signed Integer ;; PKT_ADDR_H ; 65 ; Signed Integer ;; PKT_ADDR_L ; 36 ; Signed Integer ;; PKT_BYTE_CNT_H ; 78 ; Signed Integer ;; PKT_BYTE_CNT_L ; 72 ; Signed Integer ;; PKT_BURSTWRAP_H ; 85 ; Signed Integer ;; PKT_BURSTWRAP_L ; 79 ; Signed Integer ;; PKT_TRANS_COMPRESSED_READ ; 66 ; Signed Integer ;; PKT_TRANS_WRITE ; 68 ; Signed Integer ;; PKT_TRANS_READ ; 69 ; Signed Integer ;; PKT_BYTEEN_H ; 35 ; Signed Integer ;; PKT_BYTEEN_L ; 32 ; Signed Integer ;; PKT_BURST_TYPE_H ; 90 ; Signed Integer ;; PKT_BURST_TYPE_L ; 89 ; Signed Integer ;; PKT_BURST_SIZE_H ; 88 ; Signed Integer ;; PKT_BURST_SIZE_L ; 86 ; Signed Integer ;; IN_NARROW_SIZE ; 1 ; Signed Integer ;; OUT_NARROW_SIZE ; 0 ; Signed Integer ;; OUT_FIXED ; 0 ; Signed Integer ;; OUT_COMPLETE_WRAP ; 0 ; Signed Integer ;; ST_DATA_W ; 129 ; Signed Integer ;; ST_CHANNEL_W ; 22 ; Signed Integer ;; BYTEENABLE_SYNTHESIS ; 1 ; Signed Integer ;; BURSTWRAP_CONST_MASK ; 0 ; Signed Integer ;; PIPE_INPUTS ; 0 ; Signed Integer ;; NO_WRAP_SUPPORT ; 0 ; Signed Integer ;; BURSTWRAP_CONST_VALUE ; 0 ; Signed Integer ;; OUT_BYTE_CNT_H ; 74 ; Signed Integer ;; OUT_BURSTWRAP_H ; 85 ; Signed Integer ;+---------------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size ;+-------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+-------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; ADDR_W ; 30 ; Signed Integer ;; BURSTWRAP_W ; 1 ; Signed Integer ;; TYPE_W ; 0 ; Signed Integer ;; SIZE_W ; 3 ; Signed Integer ;; INCREMENT_ADDRESS ; 0 ; Signed Integer ;; NUMSYMBOLS ; 4 ; Signed Integer ;; SELECT_BITS ; 2 ; Signed Integer ;; IN_DATA_W ; 33 ; Signed Integer ;; OUT_DATA_W ; 32 ; Signed Integer ;+-------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_burstwrap_increment:the_burstwrap_increment ;+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 7 ; Signed Integer ;+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min ;+-------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+-------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; PKT_BYTE_CNT_W ; 7 ; Signed Integer ;; PKT_BURSTWRAP_W ; 7 ; Signed Integer ;; PIPELINE_POSITION ; 2 ; Signed Integer ;+-------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ab_sub ;+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ab_sub|altera_merlin_burst_adapter_adder:subtract ;+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ac_sub ;+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ac_sub|altera_merlin_burst_adapter_adder:subtract ;+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:bc_sub ;+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:bc_sub|altera_merlin_burst_adapter_adder:subtract ;+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:da_sub ;+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:da_sub|altera_merlin_burst_adapter_adder:subtract ;+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:db_sub ;+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:db_sub|altera_merlin_burst_adapter_adder:subtract ;+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:dc_sub ;+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:dc_sub|altera_merlin_burst_adapter_adder:subtract ;+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter ;+---------------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+---------------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------+; ADAPTER_VERSION ; 13.1 ; String ;; COMPRESSED_READ_SUPPORT ; 1 ; Signed Integer ;; PKT_BEGIN_BURST ; 93 ; Signed Integer ;; PKT_ADDR_H ; 65 ; Signed Integer ;; PKT_ADDR_L ; 36 ; Signed Integer ;; PKT_BYTE_CNT_H ; 78 ; Signed Integer ;; PKT_BYTE_CNT_L ; 72 ; Signed Integer ;; PKT_BURSTWRAP_H ; 85 ; Signed Integer ;; PKT_BURSTWRAP_L ; 79 ; Signed Integer ;; PKT_TRANS_COMPRESSED_READ ; 66 ; Signed Integer ;; PKT_TRANS_WRITE ; 68 ; Signed Integer ;; PKT_TRANS_READ ; 69 ; Signed Integer ;; PKT_BYTEEN_H ; 35 ; Signed Integer ;; PKT_BYTEEN_L ; 32 ; Signed Integer ;; PKT_BURST_TYPE_H ; 90 ; Signed Integer ;; PKT_BURST_TYPE_L ; 89 ; Signed Integer ;; PKT_BURST_SIZE_H ; 88 ; Signed Integer ;; PKT_BURST_SIZE_L ; 86 ; Signed Integer ;; ST_DATA_W ; 129 ; Signed Integer ;; ST_CHANNEL_W ; 22 ; Signed Integer ;; IN_NARROW_SIZE ; 1 ; Signed Integer ;; NO_WRAP_SUPPORT ; 0 ; Signed Integer ;; INCOMPLETE_WRAP_SUPPORT ; 0 ; Signed Integer ;; BURSTWRAP_CONST_MASK ; 0 ; Signed Integer ;; BURSTWRAP_CONST_VALUE ; 0 ; Signed Integer ;; OUT_NARROW_SIZE ; 0 ; Signed Integer ;; OUT_FIXED ; 0 ; Signed Integer ;; OUT_COMPLETE_WRAP ; 0 ; Signed Integer ;; BYTEENABLE_SYNTHESIS ; 1 ; Signed Integer ;; PIPE_INPUTS ; 0 ; Signed Integer ;; OUT_BYTE_CNT_H ; 74 ; Signed Integer ;; OUT_BURSTWRAP_H ; 85 ; Signed Integer ;+---------------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ;+---------------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+---------------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; PKT_BEGIN_BURST ; 93 ; Signed Integer ;; PKT_ADDR_H ; 65 ; Signed Integer ;; PKT_ADDR_L ; 36 ; Signed Integer ;; PKT_BYTE_CNT_H ; 78 ; Signed Integer ;; PKT_BYTE_CNT_L ; 72 ; Signed Integer ;; PKT_BURSTWRAP_H ; 85 ; Signed Integer ;; PKT_BURSTWRAP_L ; 79 ; Signed Integer ;; PKT_TRANS_COMPRESSED_READ ; 66 ; Signed Integer ;; PKT_TRANS_WRITE ; 68 ; Signed Integer ;; PKT_TRANS_READ ; 69 ; Signed Integer ;; PKT_BYTEEN_H ; 35 ; Signed Integer ;; PKT_BYTEEN_L ; 32 ; Signed Integer ;; PKT_BURST_TYPE_H ; 90 ; Signed Integer ;; PKT_BURST_TYPE_L ; 89 ; Signed Integer ;; PKT_BURST_SIZE_H ; 88 ; Signed Integer ;; PKT_BURST_SIZE_L ; 86 ; Signed Integer ;; IN_NARROW_SIZE ; 1 ; Signed Integer ;; OUT_NARROW_SIZE ; 0 ; Signed Integer ;; OUT_FIXED ; 0 ; Signed Integer ;; OUT_COMPLETE_WRAP ; 0 ; Signed Integer ;; ST_DATA_W ; 129 ; Signed Integer ;; ST_CHANNEL_W ; 22 ; Signed Integer ;; BYTEENABLE_SYNTHESIS ; 1 ; Signed Integer ;; BURSTWRAP_CONST_MASK ; 0 ; Signed Integer ;; PIPE_INPUTS ; 0 ; Signed Integer ;; NO_WRAP_SUPPORT ; 0 ; Signed Integer ;; BURSTWRAP_CONST_VALUE ; 0 ; Signed Integer ;; OUT_BYTE_CNT_H ; 74 ; Signed Integer ;; OUT_BURSTWRAP_H ; 85 ; Signed Integer ;+---------------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size ;+-------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+-------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; ADDR_W ; 30 ; Signed Integer ;; BURSTWRAP_W ; 1 ; Signed Integer ;; TYPE_W ; 0 ; Signed Integer ;; SIZE_W ; 3 ; Signed Integer ;; INCREMENT_ADDRESS ; 0 ; Signed Integer ;; NUMSYMBOLS ; 4 ; Signed Integer ;; SELECT_BITS ; 2 ; Signed Integer ;; IN_DATA_W ; 33 ; Signed Integer ;; OUT_DATA_W ; 32 ; Signed Integer ;+-------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_burstwrap_increment:the_burstwrap_increment ;+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 7 ; Signed Integer ;+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min ;+-------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+-------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; PKT_BYTE_CNT_W ; 7 ; Signed Integer ;; PKT_BURSTWRAP_W ; 7 ; Signed Integer ;; PIPELINE_POSITION ; 2 ; Signed Integer ;+-------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ab_sub ;+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ab_sub|altera_merlin_burst_adapter_adder:subtract ;+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ac_sub ;+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ac_sub|altera_merlin_burst_adapter_adder:subtract ;+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:bc_sub ;+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:bc_sub|altera_merlin_burst_adapter_adder:subtract ;+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:da_sub ;+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:da_sub|altera_merlin_burst_adapter_adder:subtract ;+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:db_sub ;+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:db_sub|altera_merlin_burst_adapter_adder:subtract ;+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:dc_sub ;+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:dc_sub|altera_merlin_burst_adapter_adder:subtract ;+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter ;+---------------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+---------------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------+; ADAPTER_VERSION ; 13.1 ; String ;; COMPRESSED_READ_SUPPORT ; 1 ; Signed Integer ;; PKT_BEGIN_BURST ; 93 ; Signed Integer ;; PKT_ADDR_H ; 65 ; Signed Integer ;; PKT_ADDR_L ; 36 ; Signed Integer ;; PKT_BYTE_CNT_H ; 78 ; Signed Integer ;; PKT_BYTE_CNT_L ; 72 ; Signed Integer ;; PKT_BURSTWRAP_H ; 85 ; Signed Integer ;; PKT_BURSTWRAP_L ; 79 ; Signed Integer ;; PKT_TRANS_COMPRESSED_READ ; 66 ; Signed Integer ;; PKT_TRANS_WRITE ; 68 ; Signed Integer ;; PKT_TRANS_READ ; 69 ; Signed Integer ;; PKT_BYTEEN_H ; 35 ; Signed Integer ;; PKT_BYTEEN_L ; 32 ; Signed Integer ;; PKT_BURST_TYPE_H ; 90 ; Signed Integer ;; PKT_BURST_TYPE_L ; 89 ; Signed Integer ;; PKT_BURST_SIZE_H ; 88 ; Signed Integer ;; PKT_BURST_SIZE_L ; 86 ; Signed Integer ;; ST_DATA_W ; 129 ; Signed Integer ;; ST_CHANNEL_W ; 22 ; Signed Integer ;; IN_NARROW_SIZE ; 1 ; Signed Integer ;; NO_WRAP_SUPPORT ; 0 ; Signed Integer ;; INCOMPLETE_WRAP_SUPPORT ; 0 ; Signed Integer ;; BURSTWRAP_CONST_MASK ; 0 ; Signed Integer ;; BURSTWRAP_CONST_VALUE ; 0 ; Signed Integer ;; OUT_NARROW_SIZE ; 0 ; Signed Integer ;; OUT_FIXED ; 0 ; Signed Integer ;; OUT_COMPLETE_WRAP ; 0 ; Signed Integer ;; BYTEENABLE_SYNTHESIS ; 1 ; Signed Integer ;; PIPE_INPUTS ; 0 ; Signed Integer ;; OUT_BYTE_CNT_H ; 74 ; Signed Integer ;; OUT_BURSTWRAP_H ; 85 ; Signed Integer ;+---------------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ;+---------------------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+---------------------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; PKT_BEGIN_BURST ; 93 ; Signed Integer ;; PKT_ADDR_H ; 65 ; Signed Integer ;; PKT_ADDR_L ; 36 ; Signed Integer ;; PKT_BYTE_CNT_H ; 78 ; Signed Integer ;; PKT_BYTE_CNT_L ; 72 ; Signed Integer ;; PKT_BURSTWRAP_H ; 85 ; Signed Integer ;; PKT_BURSTWRAP_L ; 79 ; Signed Integer ;; PKT_TRANS_COMPRESSED_READ ; 66 ; Signed Integer ;; PKT_TRANS_WRITE ; 68 ; Signed Integer ;; PKT_TRANS_READ ; 69 ; Signed Integer ;; PKT_BYTEEN_H ; 35 ; Signed Integer ;; PKT_BYTEEN_L ; 32 ; Signed Integer ;; PKT_BURST_TYPE_H ; 90 ; Signed Integer ;; PKT_BURST_TYPE_L ; 89 ; Signed Integer ;; PKT_BURST_SIZE_H ; 88 ; Signed Integer ;; PKT_BURST_SIZE_L ; 86 ; Signed Integer ;; IN_NARROW_SIZE ; 1 ; Signed Integer ;; OUT_NARROW_SIZE ; 0 ; Signed Integer ;; OUT_FIXED ; 0 ; Signed Integer ;; OUT_COMPLETE_WRAP ; 0 ; Signed Integer ;; ST_DATA_W ; 129 ; Signed Integer ;; ST_CHANNEL_W ; 22 ; Signed Integer ;; BYTEENABLE_SYNTHESIS ; 1 ; Signed Integer ;; BURSTWRAP_CONST_MASK ; 0 ; Signed Integer ;; PIPE_INPUTS ; 0 ; Signed Integer ;; NO_WRAP_SUPPORT ; 0 ; Signed Integer ;; BURSTWRAP_CONST_VALUE ; 0 ; Signed Integer ;; OUT_BYTE_CNT_H ; 74 ; Signed Integer ;; OUT_BURSTWRAP_H ; 85 ; Signed Integer ;+---------------------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size ;+-------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+-------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; ADDR_W ; 30 ; Signed Integer ;; BURSTWRAP_W ; 1 ; Signed Integer ;; TYPE_W ; 0 ; Signed Integer ;; SIZE_W ; 3 ; Signed Integer ;; INCREMENT_ADDRESS ; 0 ; Signed Integer ;; NUMSYMBOLS ; 4 ; Signed Integer ;; SELECT_BITS ; 2 ; Signed Integer ;; IN_DATA_W ; 33 ; Signed Integer ;; OUT_DATA_W ; 32 ; Signed Integer ;+-------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_burstwrap_increment:the_burstwrap_increment ;+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 7 ; Signed Integer ;+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min ;+-------------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+-------------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; PKT_BYTE_CNT_W ; 7 ; Signed Integer ;; PKT_BURSTWRAP_W ; 7 ; Signed Integer ;; PIPELINE_POSITION ; 2 ; Signed Integer ;+-------------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ab_sub ;+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ab_sub|altera_merlin_burst_adapter_adder:subtract ;+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ac_sub ;+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ac_sub|altera_merlin_burst_adapter_adder:subtract ;+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:bc_sub ;+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:bc_sub|altera_merlin_burst_adapter_adder:subtract ;+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:da_sub ;+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:da_sub|altera_merlin_burst_adapter_adder:subtract ;+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:db_sub ;+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:db_sub|altera_merlin_burst_adapter_adder:subtract ;+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:dc_sub ;+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:dc_sub|altera_merlin_burst_adapter_adder:subtract ;+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+--------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter ;+---------------------------+-------+--------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+---------------------------+-------+--------------------------------------------------------------------------------------------------------------------------------+; ADAPTER_VERSION ; 13.1 ; String ;; COMPRESSED_READ_SUPPORT ; 1 ; Signed Integer ;; PKT_BEGIN_BURST ; 93 ; Signed Integer ;; PKT_ADDR_H ; 65 ; Signed Integer ;; PKT_ADDR_L ; 36 ; Signed Integer ;; PKT_BYTE_CNT_H ; 78 ; Signed Integer ;; PKT_BYTE_CNT_L ; 72 ; Signed Integer ;; PKT_BURSTWRAP_H ; 85 ; Signed Integer ;; PKT_BURSTWRAP_L ; 79 ; Signed Integer ;; PKT_TRANS_COMPRESSED_READ ; 66 ; Signed Integer ;; PKT_TRANS_WRITE ; 68 ; Signed Integer ;; PKT_TRANS_READ ; 69 ; Signed Integer ;; PKT_BYTEEN_H ; 35 ; Signed Integer ;; PKT_BYTEEN_L ; 32 ; Signed Integer ;; PKT_BURST_TYPE_H ; 90 ; Signed Integer ;; PKT_BURST_TYPE_L ; 89 ; Signed Integer ;; PKT_BURST_SIZE_H ; 88 ; Signed Integer ;; PKT_BURST_SIZE_L ; 86 ; Signed Integer ;; ST_DATA_W ; 129 ; Signed Integer ;; ST_CHANNEL_W ; 22 ; Signed Integer ;; IN_NARROW_SIZE ; 1 ; Signed Integer ;; NO_WRAP_SUPPORT ; 0 ; Signed Integer ;; INCOMPLETE_WRAP_SUPPORT ; 0 ; Signed Integer ;; BURSTWRAP_CONST_MASK ; 0 ; Signed Integer ;; BURSTWRAP_CONST_VALUE ; 0 ; Signed Integer ;; OUT_NARROW_SIZE ; 0 ; Signed Integer ;; OUT_FIXED ; 0 ; Signed Integer ;; OUT_COMPLETE_WRAP ; 0 ; Signed Integer ;; BYTEENABLE_SYNTHESIS ; 1 ; Signed Integer ;; PIPE_INPUTS ; 0 ; Signed Integer ;; OUT_BYTE_CNT_H ; 74 ; Signed Integer ;; OUT_BURSTWRAP_H ; 85 ; Signed Integer ;+---------------------------+-------+--------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ;+---------------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+---------------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; PKT_BEGIN_BURST ; 93 ; Signed Integer ;; PKT_ADDR_H ; 65 ; Signed Integer ;; PKT_ADDR_L ; 36 ; Signed Integer ;; PKT_BYTE_CNT_H ; 78 ; Signed Integer ;; PKT_BYTE_CNT_L ; 72 ; Signed Integer ;; PKT_BURSTWRAP_H ; 85 ; Signed Integer ;; PKT_BURSTWRAP_L ; 79 ; Signed Integer ;; PKT_TRANS_COMPRESSED_READ ; 66 ; Signed Integer ;; PKT_TRANS_WRITE ; 68 ; Signed Integer ;; PKT_TRANS_READ ; 69 ; Signed Integer ;; PKT_BYTEEN_H ; 35 ; Signed Integer ;; PKT_BYTEEN_L ; 32 ; Signed Integer ;; PKT_BURST_TYPE_H ; 90 ; Signed Integer ;; PKT_BURST_TYPE_L ; 89 ; Signed Integer ;; PKT_BURST_SIZE_H ; 88 ; Signed Integer ;; PKT_BURST_SIZE_L ; 86 ; Signed Integer ;; IN_NARROW_SIZE ; 1 ; Signed Integer ;; OUT_NARROW_SIZE ; 0 ; Signed Integer ;; OUT_FIXED ; 0 ; Signed Integer ;; OUT_COMPLETE_WRAP ; 0 ; Signed Integer ;; ST_DATA_W ; 129 ; Signed Integer ;; ST_CHANNEL_W ; 22 ; Signed Integer ;; BYTEENABLE_SYNTHESIS ; 1 ; Signed Integer ;; BURSTWRAP_CONST_MASK ; 0 ; Signed Integer ;; PIPE_INPUTS ; 0 ; Signed Integer ;; NO_WRAP_SUPPORT ; 0 ; Signed Integer ;; BURSTWRAP_CONST_VALUE ; 0 ; Signed Integer ;; OUT_BYTE_CNT_H ; 74 ; Signed Integer ;; OUT_BURSTWRAP_H ; 85 ; Signed Integer ;+---------------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size ;+-------------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+-------------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; ADDR_W ; 30 ; Signed Integer ;; BURSTWRAP_W ; 1 ; Signed Integer ;; TYPE_W ; 0 ; Signed Integer ;; SIZE_W ; 3 ; Signed Integer ;; INCREMENT_ADDRESS ; 0 ; Signed Integer ;; NUMSYMBOLS ; 4 ; Signed Integer ;; SELECT_BITS ; 2 ; Signed Integer ;; IN_DATA_W ; 33 ; Signed Integer ;; OUT_DATA_W ; 32 ; Signed Integer ;+-------------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_burstwrap_increment:the_burstwrap_increment ;+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 7 ; Signed Integer ;+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min ;+-------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+-------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; PKT_BYTE_CNT_W ; 7 ; Signed Integer ;; PKT_BURSTWRAP_W ; 7 ; Signed Integer ;; PIPELINE_POSITION ; 2 ; Signed Integer ;+-------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ab_sub ;+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ab_sub|altera_merlin_burst_adapter_adder:subtract ;+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ac_sub ;+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ac_sub|altera_merlin_burst_adapter_adder:subtract ;+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:bc_sub ;+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:bc_sub|altera_merlin_burst_adapter_adder:subtract ;+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:da_sub ;+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:da_sub|altera_merlin_burst_adapter_adder:subtract ;+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:db_sub ;+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:db_sub|altera_merlin_burst_adapter_adder:subtract ;+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:dc_sub ;+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:dc_sub|altera_merlin_burst_adapter_adder:subtract ;+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+--------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter ;+---------------------------+-------+--------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+---------------------------+-------+--------------------------------------------------------------------------------------------------------------------------------+; ADAPTER_VERSION ; 13.1 ; String ;; COMPRESSED_READ_SUPPORT ; 1 ; Signed Integer ;; PKT_BEGIN_BURST ; 93 ; Signed Integer ;; PKT_ADDR_H ; 65 ; Signed Integer ;; PKT_ADDR_L ; 36 ; Signed Integer ;; PKT_BYTE_CNT_H ; 78 ; Signed Integer ;; PKT_BYTE_CNT_L ; 72 ; Signed Integer ;; PKT_BURSTWRAP_H ; 85 ; Signed Integer ;; PKT_BURSTWRAP_L ; 79 ; Signed Integer ;; PKT_TRANS_COMPRESSED_READ ; 66 ; Signed Integer ;; PKT_TRANS_WRITE ; 68 ; Signed Integer ;; PKT_TRANS_READ ; 69 ; Signed Integer ;; PKT_BYTEEN_H ; 35 ; Signed Integer ;; PKT_BYTEEN_L ; 32 ; Signed Integer ;; PKT_BURST_TYPE_H ; 90 ; Signed Integer ;; PKT_BURST_TYPE_L ; 89 ; Signed Integer ;; PKT_BURST_SIZE_H ; 88 ; Signed Integer ;; PKT_BURST_SIZE_L ; 86 ; Signed Integer ;; ST_DATA_W ; 129 ; Signed Integer ;; ST_CHANNEL_W ; 22 ; Signed Integer ;; IN_NARROW_SIZE ; 1 ; Signed Integer ;; NO_WRAP_SUPPORT ; 0 ; Signed Integer ;; INCOMPLETE_WRAP_SUPPORT ; 0 ; Signed Integer ;; BURSTWRAP_CONST_MASK ; 0 ; Signed Integer ;; BURSTWRAP_CONST_VALUE ; 0 ; Signed Integer ;; OUT_NARROW_SIZE ; 0 ; Signed Integer ;; OUT_FIXED ; 0 ; Signed Integer ;; OUT_COMPLETE_WRAP ; 0 ; Signed Integer ;; BYTEENABLE_SYNTHESIS ; 1 ; Signed Integer ;; PIPE_INPUTS ; 0 ; Signed Integer ;; OUT_BYTE_CNT_H ; 74 ; Signed Integer ;; OUT_BURSTWRAP_H ; 85 ; Signed Integer ;+---------------------------+-------+--------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ;+---------------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+---------------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; PKT_BEGIN_BURST ; 93 ; Signed Integer ;; PKT_ADDR_H ; 65 ; Signed Integer ;; PKT_ADDR_L ; 36 ; Signed Integer ;; PKT_BYTE_CNT_H ; 78 ; Signed Integer ;; PKT_BYTE_CNT_L ; 72 ; Signed Integer ;; PKT_BURSTWRAP_H ; 85 ; Signed Integer ;; PKT_BURSTWRAP_L ; 79 ; Signed Integer ;; PKT_TRANS_COMPRESSED_READ ; 66 ; Signed Integer ;; PKT_TRANS_WRITE ; 68 ; Signed Integer ;; PKT_TRANS_READ ; 69 ; Signed Integer ;; PKT_BYTEEN_H ; 35 ; Signed Integer ;; PKT_BYTEEN_L ; 32 ; Signed Integer ;; PKT_BURST_TYPE_H ; 90 ; Signed Integer ;; PKT_BURST_TYPE_L ; 89 ; Signed Integer ;; PKT_BURST_SIZE_H ; 88 ; Signed Integer ;; PKT_BURST_SIZE_L ; 86 ; Signed Integer ;; IN_NARROW_SIZE ; 1 ; Signed Integer ;; OUT_NARROW_SIZE ; 0 ; Signed Integer ;; OUT_FIXED ; 0 ; Signed Integer ;; OUT_COMPLETE_WRAP ; 0 ; Signed Integer ;; ST_DATA_W ; 129 ; Signed Integer ;; ST_CHANNEL_W ; 22 ; Signed Integer ;; BYTEENABLE_SYNTHESIS ; 1 ; Signed Integer ;; BURSTWRAP_CONST_MASK ; 0 ; Signed Integer ;; PIPE_INPUTS ; 0 ; Signed Integer ;; NO_WRAP_SUPPORT ; 0 ; Signed Integer ;; BURSTWRAP_CONST_VALUE ; 0 ; Signed Integer ;; OUT_BYTE_CNT_H ; 74 ; Signed Integer ;; OUT_BURSTWRAP_H ; 85 ; Signed Integer ;+---------------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size ;+-------------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+-------------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; ADDR_W ; 30 ; Signed Integer ;; BURSTWRAP_W ; 1 ; Signed Integer ;; TYPE_W ; 0 ; Signed Integer ;; SIZE_W ; 3 ; Signed Integer ;; INCREMENT_ADDRESS ; 0 ; Signed Integer ;; NUMSYMBOLS ; 4 ; Signed Integer ;; SELECT_BITS ; 2 ; Signed Integer ;; IN_DATA_W ; 33 ; Signed Integer ;; OUT_DATA_W ; 32 ; Signed Integer ;+-------------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_burstwrap_increment:the_burstwrap_increment ;+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 7 ; Signed Integer ;+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min ;+-------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+-------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; PKT_BYTE_CNT_W ; 7 ; Signed Integer ;; PKT_BURSTWRAP_W ; 7 ; Signed Integer ;; PIPELINE_POSITION ; 2 ; Signed Integer ;+-------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ab_sub ;+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ab_sub|altera_merlin_burst_adapter_adder:subtract ;+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ac_sub ;+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ac_sub|altera_merlin_burst_adapter_adder:subtract ;+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:bc_sub ;+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:bc_sub|altera_merlin_burst_adapter_adder:subtract ;+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:da_sub ;+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:da_sub|altera_merlin_burst_adapter_adder:subtract ;+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:db_sub ;+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:db_sub|altera_merlin_burst_adapter_adder:subtract ;+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:dc_sub ;+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:dc_sub|altera_merlin_burst_adapter_adder:subtract ;+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+-------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter ;+---------------------------+-------+-------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+---------------------------+-------+-------------------------------------------------------------------------------------------------------------------------------+; ADAPTER_VERSION ; 13.1 ; String ;; COMPRESSED_READ_SUPPORT ; 1 ; Signed Integer ;; PKT_BEGIN_BURST ; 93 ; Signed Integer ;; PKT_ADDR_H ; 65 ; Signed Integer ;; PKT_ADDR_L ; 36 ; Signed Integer ;; PKT_BYTE_CNT_H ; 78 ; Signed Integer ;; PKT_BYTE_CNT_L ; 72 ; Signed Integer ;; PKT_BURSTWRAP_H ; 85 ; Signed Integer ;; PKT_BURSTWRAP_L ; 79 ; Signed Integer ;; PKT_TRANS_COMPRESSED_READ ; 66 ; Signed Integer ;; PKT_TRANS_WRITE ; 68 ; Signed Integer ;; PKT_TRANS_READ ; 69 ; Signed Integer ;; PKT_BYTEEN_H ; 35 ; Signed Integer ;; PKT_BYTEEN_L ; 32 ; Signed Integer ;; PKT_BURST_TYPE_H ; 90 ; Signed Integer ;; PKT_BURST_TYPE_L ; 89 ; Signed Integer ;; PKT_BURST_SIZE_H ; 88 ; Signed Integer ;; PKT_BURST_SIZE_L ; 86 ; Signed Integer ;; ST_DATA_W ; 129 ; Signed Integer ;; ST_CHANNEL_W ; 22 ; Signed Integer ;; IN_NARROW_SIZE ; 1 ; Signed Integer ;; NO_WRAP_SUPPORT ; 0 ; Signed Integer ;; INCOMPLETE_WRAP_SUPPORT ; 0 ; Signed Integer ;; BURSTWRAP_CONST_MASK ; 0 ; Signed Integer ;; BURSTWRAP_CONST_VALUE ; 0 ; Signed Integer ;; OUT_NARROW_SIZE ; 0 ; Signed Integer ;; OUT_FIXED ; 0 ; Signed Integer ;; OUT_COMPLETE_WRAP ; 0 ; Signed Integer ;; BYTEENABLE_SYNTHESIS ; 1 ; Signed Integer ;; PIPE_INPUTS ; 0 ; Signed Integer ;; OUT_BYTE_CNT_H ; 74 ; Signed Integer ;; OUT_BURSTWRAP_H ; 85 ; Signed Integer ;+---------------------------+-------+-------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ;+---------------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+---------------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; PKT_BEGIN_BURST ; 93 ; Signed Integer ;; PKT_ADDR_H ; 65 ; Signed Integer ;; PKT_ADDR_L ; 36 ; Signed Integer ;; PKT_BYTE_CNT_H ; 78 ; Signed Integer ;; PKT_BYTE_CNT_L ; 72 ; Signed Integer ;; PKT_BURSTWRAP_H ; 85 ; Signed Integer ;; PKT_BURSTWRAP_L ; 79 ; Signed Integer ;; PKT_TRANS_COMPRESSED_READ ; 66 ; Signed Integer ;; PKT_TRANS_WRITE ; 68 ; Signed Integer ;; PKT_TRANS_READ ; 69 ; Signed Integer ;; PKT_BYTEEN_H ; 35 ; Signed Integer ;; PKT_BYTEEN_L ; 32 ; Signed Integer ;; PKT_BURST_TYPE_H ; 90 ; Signed Integer ;; PKT_BURST_TYPE_L ; 89 ; Signed Integer ;; PKT_BURST_SIZE_H ; 88 ; Signed Integer ;; PKT_BURST_SIZE_L ; 86 ; Signed Integer ;; IN_NARROW_SIZE ; 1 ; Signed Integer ;; OUT_NARROW_SIZE ; 0 ; Signed Integer ;; OUT_FIXED ; 0 ; Signed Integer ;; OUT_COMPLETE_WRAP ; 0 ; Signed Integer ;; ST_DATA_W ; 129 ; Signed Integer ;; ST_CHANNEL_W ; 22 ; Signed Integer ;; BYTEENABLE_SYNTHESIS ; 1 ; Signed Integer ;; BURSTWRAP_CONST_MASK ; 0 ; Signed Integer ;; PIPE_INPUTS ; 0 ; Signed Integer ;; NO_WRAP_SUPPORT ; 0 ; Signed Integer ;; BURSTWRAP_CONST_VALUE ; 0 ; Signed Integer ;; OUT_BYTE_CNT_H ; 74 ; Signed Integer ;; OUT_BURSTWRAP_H ; 85 ; Signed Integer ;+---------------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size ;+-------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+-------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; ADDR_W ; 30 ; Signed Integer ;; BURSTWRAP_W ; 1 ; Signed Integer ;; TYPE_W ; 0 ; Signed Integer ;; SIZE_W ; 3 ; Signed Integer ;; INCREMENT_ADDRESS ; 0 ; Signed Integer ;; NUMSYMBOLS ; 4 ; Signed Integer ;; SELECT_BITS ; 2 ; Signed Integer ;; IN_DATA_W ; 33 ; Signed Integer ;; OUT_DATA_W ; 32 ; Signed Integer ;+-------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_burstwrap_increment:the_burstwrap_increment ;+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 7 ; Signed Integer ;+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min ;+-------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+-------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; PKT_BYTE_CNT_W ; 7 ; Signed Integer ;; PKT_BURSTWRAP_W ; 7 ; Signed Integer ;; PIPELINE_POSITION ; 2 ; Signed Integer ;+-------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ab_sub ;+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ab_sub|altera_merlin_burst_adapter_adder:subtract ;+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ac_sub ;+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ac_sub|altera_merlin_burst_adapter_adder:subtract ;+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:bc_sub ;+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:bc_sub|altera_merlin_burst_adapter_adder:subtract ;+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:da_sub ;+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:da_sub|altera_merlin_burst_adapter_adder:subtract ;+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:db_sub ;+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:db_sub|altera_merlin_burst_adapter_adder:subtract ;+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:dc_sub ;+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:dc_sub|altera_merlin_burst_adapter_adder:subtract ;+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter ;+---------------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+---------------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------+; ADAPTER_VERSION ; 13.1 ; String ;; COMPRESSED_READ_SUPPORT ; 1 ; Signed Integer ;; PKT_BEGIN_BURST ; 93 ; Signed Integer ;; PKT_ADDR_H ; 65 ; Signed Integer ;; PKT_ADDR_L ; 36 ; Signed Integer ;; PKT_BYTE_CNT_H ; 78 ; Signed Integer ;; PKT_BYTE_CNT_L ; 72 ; Signed Integer ;; PKT_BURSTWRAP_H ; 85 ; Signed Integer ;; PKT_BURSTWRAP_L ; 79 ; Signed Integer ;; PKT_TRANS_COMPRESSED_READ ; 66 ; Signed Integer ;; PKT_TRANS_WRITE ; 68 ; Signed Integer ;; PKT_TRANS_READ ; 69 ; Signed Integer ;; PKT_BYTEEN_H ; 35 ; Signed Integer ;; PKT_BYTEEN_L ; 32 ; Signed Integer ;; PKT_BURST_TYPE_H ; 90 ; Signed Integer ;; PKT_BURST_TYPE_L ; 89 ; Signed Integer ;; PKT_BURST_SIZE_H ; 88 ; Signed Integer ;; PKT_BURST_SIZE_L ; 86 ; Signed Integer ;; ST_DATA_W ; 129 ; Signed Integer ;; ST_CHANNEL_W ; 22 ; Signed Integer ;; IN_NARROW_SIZE ; 1 ; Signed Integer ;; NO_WRAP_SUPPORT ; 0 ; Signed Integer ;; INCOMPLETE_WRAP_SUPPORT ; 0 ; Signed Integer ;; BURSTWRAP_CONST_MASK ; 0 ; Signed Integer ;; BURSTWRAP_CONST_VALUE ; 0 ; Signed Integer ;; OUT_NARROW_SIZE ; 0 ; Signed Integer ;; OUT_FIXED ; 0 ; Signed Integer ;; OUT_COMPLETE_WRAP ; 0 ; Signed Integer ;; BYTEENABLE_SYNTHESIS ; 1 ; Signed Integer ;; PIPE_INPUTS ; 0 ; Signed Integer ;; OUT_BYTE_CNT_H ; 74 ; Signed Integer ;; OUT_BURSTWRAP_H ; 85 ; Signed Integer ;+---------------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ;+---------------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+---------------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; PKT_BEGIN_BURST ; 93 ; Signed Integer ;; PKT_ADDR_H ; 65 ; Signed Integer ;; PKT_ADDR_L ; 36 ; Signed Integer ;; PKT_BYTE_CNT_H ; 78 ; Signed Integer ;; PKT_BYTE_CNT_L ; 72 ; Signed Integer ;; PKT_BURSTWRAP_H ; 85 ; Signed Integer ;; PKT_BURSTWRAP_L ; 79 ; Signed Integer ;; PKT_TRANS_COMPRESSED_READ ; 66 ; Signed Integer ;; PKT_TRANS_WRITE ; 68 ; Signed Integer ;; PKT_TRANS_READ ; 69 ; Signed Integer ;; PKT_BYTEEN_H ; 35 ; Signed Integer ;; PKT_BYTEEN_L ; 32 ; Signed Integer ;; PKT_BURST_TYPE_H ; 90 ; Signed Integer ;; PKT_BURST_TYPE_L ; 89 ; Signed Integer ;; PKT_BURST_SIZE_H ; 88 ; Signed Integer ;; PKT_BURST_SIZE_L ; 86 ; Signed Integer ;; IN_NARROW_SIZE ; 1 ; Signed Integer ;; OUT_NARROW_SIZE ; 0 ; Signed Integer ;; OUT_FIXED ; 0 ; Signed Integer ;; OUT_COMPLETE_WRAP ; 0 ; Signed Integer ;; ST_DATA_W ; 129 ; Signed Integer ;; ST_CHANNEL_W ; 22 ; Signed Integer ;; BYTEENABLE_SYNTHESIS ; 1 ; Signed Integer ;; BURSTWRAP_CONST_MASK ; 0 ; Signed Integer ;; PIPE_INPUTS ; 0 ; Signed Integer ;; NO_WRAP_SUPPORT ; 0 ; Signed Integer ;; BURSTWRAP_CONST_VALUE ; 0 ; Signed Integer ;; OUT_BYTE_CNT_H ; 74 ; Signed Integer ;; OUT_BURSTWRAP_H ; 85 ; Signed Integer ;+---------------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size ;+-------------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+-------------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; ADDR_W ; 30 ; Signed Integer ;; BURSTWRAP_W ; 1 ; Signed Integer ;; TYPE_W ; 0 ; Signed Integer ;; SIZE_W ; 3 ; Signed Integer ;; INCREMENT_ADDRESS ; 0 ; Signed Integer ;; NUMSYMBOLS ; 4 ; Signed Integer ;; SELECT_BITS ; 2 ; Signed Integer ;; IN_DATA_W ; 33 ; Signed Integer ;; OUT_DATA_W ; 32 ; Signed Integer ;+-------------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_burstwrap_increment:the_burstwrap_increment ;+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 7 ; Signed Integer ;+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min ;+-------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+-------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; PKT_BYTE_CNT_W ; 7 ; Signed Integer ;; PKT_BURSTWRAP_W ; 7 ; Signed Integer ;; PIPELINE_POSITION ; 2 ; Signed Integer ;+-------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ab_sub ;+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ab_sub|altera_merlin_burst_adapter_adder:subtract ;+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ac_sub ;+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ac_sub|altera_merlin_burst_adapter_adder:subtract ;+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:bc_sub ;+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:bc_sub|altera_merlin_burst_adapter_adder:subtract ;+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:da_sub ;+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:da_sub|altera_merlin_burst_adapter_adder:subtract ;+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:db_sub ;+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:db_sub|altera_merlin_burst_adapter_adder:subtract ;+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:dc_sub ;+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:dc_sub|altera_merlin_burst_adapter_adder:subtract ;+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter ;+---------------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+---------------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------+; ADAPTER_VERSION ; 13.1 ; String ;; COMPRESSED_READ_SUPPORT ; 1 ; Signed Integer ;; PKT_BEGIN_BURST ; 93 ; Signed Integer ;; PKT_ADDR_H ; 65 ; Signed Integer ;; PKT_ADDR_L ; 36 ; Signed Integer ;; PKT_BYTE_CNT_H ; 78 ; Signed Integer ;; PKT_BYTE_CNT_L ; 72 ; Signed Integer ;; PKT_BURSTWRAP_H ; 85 ; Signed Integer ;; PKT_BURSTWRAP_L ; 79 ; Signed Integer ;; PKT_TRANS_COMPRESSED_READ ; 66 ; Signed Integer ;; PKT_TRANS_WRITE ; 68 ; Signed Integer ;; PKT_TRANS_READ ; 69 ; Signed Integer ;; PKT_BYTEEN_H ; 35 ; Signed Integer ;; PKT_BYTEEN_L ; 32 ; Signed Integer ;; PKT_BURST_TYPE_H ; 90 ; Signed Integer ;; PKT_BURST_TYPE_L ; 89 ; Signed Integer ;; PKT_BURST_SIZE_H ; 88 ; Signed Integer ;; PKT_BURST_SIZE_L ; 86 ; Signed Integer ;; ST_DATA_W ; 129 ; Signed Integer ;; ST_CHANNEL_W ; 22 ; Signed Integer ;; IN_NARROW_SIZE ; 1 ; Signed Integer ;; NO_WRAP_SUPPORT ; 0 ; Signed Integer ;; INCOMPLETE_WRAP_SUPPORT ; 0 ; Signed Integer ;; BURSTWRAP_CONST_MASK ; 0 ; Signed Integer ;; BURSTWRAP_CONST_VALUE ; 0 ; Signed Integer ;; OUT_NARROW_SIZE ; 0 ; Signed Integer ;; OUT_FIXED ; 0 ; Signed Integer ;; OUT_COMPLETE_WRAP ; 0 ; Signed Integer ;; BYTEENABLE_SYNTHESIS ; 1 ; Signed Integer ;; PIPE_INPUTS ; 0 ; Signed Integer ;; OUT_BYTE_CNT_H ; 74 ; Signed Integer ;; OUT_BURSTWRAP_H ; 85 ; Signed Integer ;+---------------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ;+---------------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+---------------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; PKT_BEGIN_BURST ; 93 ; Signed Integer ;; PKT_ADDR_H ; 65 ; Signed Integer ;; PKT_ADDR_L ; 36 ; Signed Integer ;; PKT_BYTE_CNT_H ; 78 ; Signed Integer ;; PKT_BYTE_CNT_L ; 72 ; Signed Integer ;; PKT_BURSTWRAP_H ; 85 ; Signed Integer ;; PKT_BURSTWRAP_L ; 79 ; Signed Integer ;; PKT_TRANS_COMPRESSED_READ ; 66 ; Signed Integer ;; PKT_TRANS_WRITE ; 68 ; Signed Integer ;; PKT_TRANS_READ ; 69 ; Signed Integer ;; PKT_BYTEEN_H ; 35 ; Signed Integer ;; PKT_BYTEEN_L ; 32 ; Signed Integer ;; PKT_BURST_TYPE_H ; 90 ; Signed Integer ;; PKT_BURST_TYPE_L ; 89 ; Signed Integer ;; PKT_BURST_SIZE_H ; 88 ; Signed Integer ;; PKT_BURST_SIZE_L ; 86 ; Signed Integer ;; IN_NARROW_SIZE ; 1 ; Signed Integer ;; OUT_NARROW_SIZE ; 0 ; Signed Integer ;; OUT_FIXED ; 0 ; Signed Integer ;; OUT_COMPLETE_WRAP ; 0 ; Signed Integer ;; ST_DATA_W ; 129 ; Signed Integer ;; ST_CHANNEL_W ; 22 ; Signed Integer ;; BYTEENABLE_SYNTHESIS ; 1 ; Signed Integer ;; BURSTWRAP_CONST_MASK ; 0 ; Signed Integer ;; PIPE_INPUTS ; 0 ; Signed Integer ;; NO_WRAP_SUPPORT ; 0 ; Signed Integer ;; BURSTWRAP_CONST_VALUE ; 0 ; Signed Integer ;; OUT_BYTE_CNT_H ; 74 ; Signed Integer ;; OUT_BURSTWRAP_H ; 85 ; Signed Integer ;+---------------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size ;+-------------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+-------------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; ADDR_W ; 30 ; Signed Integer ;; BURSTWRAP_W ; 1 ; Signed Integer ;; TYPE_W ; 0 ; Signed Integer ;; SIZE_W ; 3 ; Signed Integer ;; INCREMENT_ADDRESS ; 0 ; Signed Integer ;; NUMSYMBOLS ; 4 ; Signed Integer ;; SELECT_BITS ; 2 ; Signed Integer ;; IN_DATA_W ; 33 ; Signed Integer ;; OUT_DATA_W ; 32 ; Signed Integer ;+-------------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_burstwrap_increment:the_burstwrap_increment ;+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 7 ; Signed Integer ;+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min ;+-------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+-------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; PKT_BYTE_CNT_W ; 7 ; Signed Integer ;; PKT_BURSTWRAP_W ; 7 ; Signed Integer ;; PIPELINE_POSITION ; 2 ; Signed Integer ;+-------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ab_sub ;+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ab_sub|altera_merlin_burst_adapter_adder:subtract ;+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ac_sub ;+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ac_sub|altera_merlin_burst_adapter_adder:subtract ;+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:bc_sub ;+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:bc_sub|altera_merlin_burst_adapter_adder:subtract ;+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:da_sub ;+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:da_sub|altera_merlin_burst_adapter_adder:subtract ;+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:db_sub ;+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:db_sub|altera_merlin_burst_adapter_adder:subtract ;+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:dc_sub ;+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:dc_sub|altera_merlin_burst_adapter_adder:subtract ;+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 8 ; Signed Integer ;+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux|altera_merlin_arbitrator:arb ;+----------------+-------------+---------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------------+---------------------------------------------------------------------------------------------------------------------------------------------------------+; NUM_REQUESTERS ; 2 ; Signed Integer ;; SCHEME ; round-robin ; String ;; PIPELINE ; 1 ; Signed Integer ;+----------------+-------------+---------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder ;+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 4 ; Signed Integer ;+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_001|altera_merlin_arbitrator:arb ;+----------------+-------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------+; NUM_REQUESTERS ; 2 ; Signed Integer ;; SCHEME ; round-robin ; String ;; PIPELINE ; 1 ; Signed Integer ;+----------------+-------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_001|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder ;+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 4 ; Signed Integer ;+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_002|altera_merlin_arbitrator:arb ;+----------------+-------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------+; NUM_REQUESTERS ; 2 ; Signed Integer ;; SCHEME ; round-robin ; String ;; PIPELINE ; 1 ; Signed Integer ;+----------------+-------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_002|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder ;+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 4 ; Signed Integer ;+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_003|altera_merlin_arbitrator:arb ;+----------------+-------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------+; NUM_REQUESTERS ; 2 ; Signed Integer ;; SCHEME ; round-robin ; String ;; PIPELINE ; 1 ; Signed Integer ;+----------------+-------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_003|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder ;+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 4 ; Signed Integer ;+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_004|altera_merlin_arbitrator:arb ;+----------------+-------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------+; NUM_REQUESTERS ; 2 ; Signed Integer ;; SCHEME ; round-robin ; String ;; PIPELINE ; 1 ; Signed Integer ;+----------------+-------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_004|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder ;+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 4 ; Signed Integer ;+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_005|altera_merlin_arbitrator:arb ;+----------------+-------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------+; NUM_REQUESTERS ; 2 ; Signed Integer ;; SCHEME ; round-robin ; String ;; PIPELINE ; 1 ; Signed Integer ;+----------------+-------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_005|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder ;+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 4 ; Signed Integer ;+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_006|altera_merlin_arbitrator:arb ;+----------------+-------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------+; NUM_REQUESTERS ; 2 ; Signed Integer ;; SCHEME ; round-robin ; String ;; PIPELINE ; 1 ; Signed Integer ;+----------------+-------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_006|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder ;+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 4 ; Signed Integer ;+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_007|altera_merlin_arbitrator:arb ;+----------------+-------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------+; NUM_REQUESTERS ; 2 ; Signed Integer ;; SCHEME ; round-robin ; String ;; PIPELINE ; 1 ; Signed Integer ;+----------------+-------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_007|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder ;+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 4 ; Signed Integer ;+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_008|altera_merlin_arbitrator:arb ;+----------------+-------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------+; NUM_REQUESTERS ; 2 ; Signed Integer ;; SCHEME ; round-robin ; String ;; PIPELINE ; 1 ; Signed Integer ;+----------------+-------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_008|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder ;+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 4 ; Signed Integer ;+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_009|altera_merlin_arbitrator:arb ;+----------------+-------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------+; NUM_REQUESTERS ; 2 ; Signed Integer ;; SCHEME ; round-robin ; String ;; PIPELINE ; 1 ; Signed Integer ;+----------------+-------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_009|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder ;+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 4 ; Signed Integer ;+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_010|altera_merlin_arbitrator:arb ;+----------------+-------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------+; NUM_REQUESTERS ; 2 ; Signed Integer ;; SCHEME ; round-robin ; String ;; PIPELINE ; 1 ; Signed Integer ;+----------------+-------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_010|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder ;+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 4 ; Signed Integer ;+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_011|altera_merlin_arbitrator:arb ;+----------------+-------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------+; NUM_REQUESTERS ; 2 ; Signed Integer ;; SCHEME ; round-robin ; String ;; PIPELINE ; 1 ; Signed Integer ;+----------------+-------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_011|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder ;+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 4 ; Signed Integer ;+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_012|altera_merlin_arbitrator:arb ;+----------------+-------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------+; NUM_REQUESTERS ; 2 ; Signed Integer ;; SCHEME ; round-robin ; String ;; PIPELINE ; 1 ; Signed Integer ;+----------------+-------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_012|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder ;+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 4 ; Signed Integer ;+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_013|altera_merlin_arbitrator:arb ;+----------------+-------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------+; NUM_REQUESTERS ; 2 ; Signed Integer ;; SCHEME ; round-robin ; String ;; PIPELINE ; 1 ; Signed Integer ;+----------------+-------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_013|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder ;+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 4 ; Signed Integer ;+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_014|altera_merlin_arbitrator:arb ;+----------------+-------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------+; NUM_REQUESTERS ; 2 ; Signed Integer ;; SCHEME ; round-robin ; String ;; PIPELINE ; 1 ; Signed Integer ;+----------------+-------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_014|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder ;+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 4 ; Signed Integer ;+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_015|altera_merlin_arbitrator:arb ;+----------------+-------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------+; NUM_REQUESTERS ; 2 ; Signed Integer ;; SCHEME ; round-robin ; String ;; PIPELINE ; 1 ; Signed Integer ;+----------------+-------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_015|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder ;+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 4 ; Signed Integer ;+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_016|altera_merlin_arbitrator:arb ;+----------------+-------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------+; NUM_REQUESTERS ; 2 ; Signed Integer ;; SCHEME ; round-robin ; String ;; PIPELINE ; 1 ; Signed Integer ;+----------------+-------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_016|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder ;+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 4 ; Signed Integer ;+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_017|altera_merlin_arbitrator:arb ;+----------------+-------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------+; NUM_REQUESTERS ; 2 ; Signed Integer ;; SCHEME ; round-robin ; String ;; PIPELINE ; 1 ; Signed Integer ;+----------------+-------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_017|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder ;+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 4 ; Signed Integer ;+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_018|altera_merlin_arbitrator:arb ;+----------------+-------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------+; NUM_REQUESTERS ; 2 ; Signed Integer ;; SCHEME ; round-robin ; String ;; PIPELINE ; 1 ; Signed Integer ;+----------------+-------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_018|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder ;+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 4 ; Signed Integer ;+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_019|altera_merlin_arbitrator:arb ;+----------------+-------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------+; NUM_REQUESTERS ; 2 ; Signed Integer ;; SCHEME ; round-robin ; String ;; PIPELINE ; 1 ; Signed Integer ;+----------------+-------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_019|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder ;+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 4 ; Signed Integer ;+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_020|altera_merlin_arbitrator:arb ;+----------------+-------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------+; NUM_REQUESTERS ; 2 ; Signed Integer ;; SCHEME ; round-robin ; String ;; PIPELINE ; 1 ; Signed Integer ;+----------------+-------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_020|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder ;+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 4 ; Signed Integer ;+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_021|altera_merlin_arbitrator:arb ;+----------------+-------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------+; NUM_REQUESTERS ; 2 ; Signed Integer ;; SCHEME ; round-robin ; String ;; PIPELINE ; 1 ; Signed Integer ;+----------------+-------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_021|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder ;+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 4 ; Signed Integer ;+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_mux:rsp_mux|altera_merlin_arbitrator:arb ;+----------------+--------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+--------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+; NUM_REQUESTERS ; 22 ; Signed Integer ;; SCHEME ; no-arb ; String ;; PIPELINE ; 0 ; Signed Integer ;+----------------+--------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_mux:rsp_mux|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder ;+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 44 ; Signed Integer ;+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_mux:rsp_mux_001|altera_merlin_arbitrator:arb ;+----------------+--------+------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+--------+------------------------------------------------------------------------------------------------------------------------------------------------------------------+; NUM_REQUESTERS ; 22 ; Signed Integer ;; SCHEME ; no-arb ; String ;; PIPELINE ; 0 ; Signed Integer ;+----------------+--------+------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_mux:rsp_mux_001|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder ;+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; WIDTH ; 44 ; Signed Integer ;+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter ;+-----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+-----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------+; inBitsPerSymbol ; 34 ; Signed Integer ;; inUsePackets ; 0 ; Signed Integer ;; inDataWidth ; 34 ; Signed Integer ;; inChannelWidth ; 0 ; Signed Integer ;; inErrorWidth ; 0 ; Signed Integer ;; inUseEmptyPort ; 0 ; Signed Integer ;; inUseValid ; 1 ; Signed Integer ;; inUseReady ; 1 ; Signed Integer ;; inReadyLatency ; 0 ; Signed Integer ;; outDataWidth ; 34 ; Signed Integer ;; outChannelWidth ; 0 ; Signed Integer ;; outErrorWidth ; 1 ; Signed Integer ;; outUseEmptyPort ; 0 ; Signed Integer ;; outUseValid ; 1 ; Signed Integer ;; outUseReady ; 1 ; Signed Integer ;; outReadyLatency ; 0 ; Signed Integer ;+-----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_001 ;+-----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+-----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------+; inBitsPerSymbol ; 34 ; Signed Integer ;; inUsePackets ; 0 ; Signed Integer ;; inDataWidth ; 34 ; Signed Integer ;; inChannelWidth ; 0 ; Signed Integer ;; inErrorWidth ; 0 ; Signed Integer ;; inUseEmptyPort ; 0 ; Signed Integer ;; inUseValid ; 1 ; Signed Integer ;; inUseReady ; 1 ; Signed Integer ;; inReadyLatency ; 0 ; Signed Integer ;; outDataWidth ; 34 ; Signed Integer ;; outChannelWidth ; 0 ; Signed Integer ;; outErrorWidth ; 1 ; Signed Integer ;; outUseEmptyPort ; 0 ; Signed Integer ;; outUseValid ; 1 ; Signed Integer ;; outUseReady ; 1 ; Signed Integer ;; outReadyLatency ; 0 ; Signed Integer ;+-----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_002 ;+-----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+-----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------+; inBitsPerSymbol ; 34 ; Signed Integer ;; inUsePackets ; 0 ; Signed Integer ;; inDataWidth ; 34 ; Signed Integer ;; inChannelWidth ; 0 ; Signed Integer ;; inErrorWidth ; 0 ; Signed Integer ;; inUseEmptyPort ; 0 ; Signed Integer ;; inUseValid ; 1 ; Signed Integer ;; inUseReady ; 1 ; Signed Integer ;; inReadyLatency ; 0 ; Signed Integer ;; outDataWidth ; 34 ; Signed Integer ;; outChannelWidth ; 0 ; Signed Integer ;; outErrorWidth ; 1 ; Signed Integer ;; outUseEmptyPort ; 0 ; Signed Integer ;; outUseValid ; 1 ; Signed Integer ;; outUseReady ; 1 ; Signed Integer ;; outReadyLatency ; 0 ; Signed Integer ;+-----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_003 ;+-----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+-----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------+; inBitsPerSymbol ; 34 ; Signed Integer ;; inUsePackets ; 0 ; Signed Integer ;; inDataWidth ; 34 ; Signed Integer ;; inChannelWidth ; 0 ; Signed Integer ;; inErrorWidth ; 0 ; Signed Integer ;; inUseEmptyPort ; 0 ; Signed Integer ;; inUseValid ; 1 ; Signed Integer ;; inUseReady ; 1 ; Signed Integer ;; inReadyLatency ; 0 ; Signed Integer ;; outDataWidth ; 34 ; Signed Integer ;; outChannelWidth ; 0 ; Signed Integer ;; outErrorWidth ; 1 ; Signed Integer ;; outUseEmptyPort ; 0 ; Signed Integer ;; outUseValid ; 1 ; Signed Integer ;; outUseReady ; 1 ; Signed Integer ;; outReadyLatency ; 0 ; Signed Integer ;+-----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_004 ;+-----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+-----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------+; inBitsPerSymbol ; 34 ; Signed Integer ;; inUsePackets ; 0 ; Signed Integer ;; inDataWidth ; 34 ; Signed Integer ;; inChannelWidth ; 0 ; Signed Integer ;; inErrorWidth ; 0 ; Signed Integer ;; inUseEmptyPort ; 0 ; Signed Integer ;; inUseValid ; 1 ; Signed Integer ;; inUseReady ; 1 ; Signed Integer ;; inReadyLatency ; 0 ; Signed Integer ;; outDataWidth ; 34 ; Signed Integer ;; outChannelWidth ; 0 ; Signed Integer ;; outErrorWidth ; 1 ; Signed Integer ;; outUseEmptyPort ; 0 ; Signed Integer ;; outUseValid ; 1 ; Signed Integer ;; outUseReady ; 1 ; Signed Integer ;; outReadyLatency ; 0 ; Signed Integer ;+-----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_005 ;+-----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+-----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------+; inBitsPerSymbol ; 34 ; Signed Integer ;; inUsePackets ; 0 ; Signed Integer ;; inDataWidth ; 34 ; Signed Integer ;; inChannelWidth ; 0 ; Signed Integer ;; inErrorWidth ; 0 ; Signed Integer ;; inUseEmptyPort ; 0 ; Signed Integer ;; inUseValid ; 1 ; Signed Integer ;; inUseReady ; 1 ; Signed Integer ;; inReadyLatency ; 0 ; Signed Integer ;; outDataWidth ; 34 ; Signed Integer ;; outChannelWidth ; 0 ; Signed Integer ;; outErrorWidth ; 1 ; Signed Integer ;; outUseEmptyPort ; 0 ; Signed Integer ;; outUseValid ; 1 ; Signed Integer ;; outUseReady ; 1 ; Signed Integer ;; outReadyLatency ; 0 ; Signed Integer ;+-----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_006 ;+-----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+-----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------+; inBitsPerSymbol ; 34 ; Signed Integer ;; inUsePackets ; 0 ; Signed Integer ;; inDataWidth ; 34 ; Signed Integer ;; inChannelWidth ; 0 ; Signed Integer ;; inErrorWidth ; 0 ; Signed Integer ;; inUseEmptyPort ; 0 ; Signed Integer ;; inUseValid ; 1 ; Signed Integer ;; inUseReady ; 1 ; Signed Integer ;; inReadyLatency ; 0 ; Signed Integer ;; outDataWidth ; 34 ; Signed Integer ;; outChannelWidth ; 0 ; Signed Integer ;; outErrorWidth ; 1 ; Signed Integer ;; outUseEmptyPort ; 0 ; Signed Integer ;; outUseValid ; 1 ; Signed Integer ;; outUseReady ; 1 ; Signed Integer ;; outReadyLatency ; 0 ; Signed Integer ;+-----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_007 ;+-----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+-----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------+; inBitsPerSymbol ; 34 ; Signed Integer ;; inUsePackets ; 0 ; Signed Integer ;; inDataWidth ; 34 ; Signed Integer ;; inChannelWidth ; 0 ; Signed Integer ;; inErrorWidth ; 0 ; Signed Integer ;; inUseEmptyPort ; 0 ; Signed Integer ;; inUseValid ; 1 ; Signed Integer ;; inUseReady ; 1 ; Signed Integer ;; inReadyLatency ; 0 ; Signed Integer ;; outDataWidth ; 34 ; Signed Integer ;; outChannelWidth ; 0 ; Signed Integer ;; outErrorWidth ; 1 ; Signed Integer ;; outUseEmptyPort ; 0 ; Signed Integer ;; outUseValid ; 1 ; Signed Integer ;; outUseReady ; 1 ; Signed Integer ;; outReadyLatency ; 0 ; Signed Integer ;+-----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_008 ;+-----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+-----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------+; inBitsPerSymbol ; 34 ; Signed Integer ;; inUsePackets ; 0 ; Signed Integer ;; inDataWidth ; 34 ; Signed Integer ;; inChannelWidth ; 0 ; Signed Integer ;; inErrorWidth ; 0 ; Signed Integer ;; inUseEmptyPort ; 0 ; Signed Integer ;; inUseValid ; 1 ; Signed Integer ;; inUseReady ; 1 ; Signed Integer ;; inReadyLatency ; 0 ; Signed Integer ;; outDataWidth ; 34 ; Signed Integer ;; outChannelWidth ; 0 ; Signed Integer ;; outErrorWidth ; 1 ; Signed Integer ;; outUseEmptyPort ; 0 ; Signed Integer ;; outUseValid ; 1 ; Signed Integer ;; outUseReady ; 1 ; Signed Integer ;; outReadyLatency ; 0 ; Signed Integer ;+-----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_009 ;+-----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+-----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------+; inBitsPerSymbol ; 34 ; Signed Integer ;; inUsePackets ; 0 ; Signed Integer ;; inDataWidth ; 34 ; Signed Integer ;; inChannelWidth ; 0 ; Signed Integer ;; inErrorWidth ; 0 ; Signed Integer ;; inUseEmptyPort ; 0 ; Signed Integer ;; inUseValid ; 1 ; Signed Integer ;; inUseReady ; 1 ; Signed Integer ;; inReadyLatency ; 0 ; Signed Integer ;; outDataWidth ; 34 ; Signed Integer ;; outChannelWidth ; 0 ; Signed Integer ;; outErrorWidth ; 1 ; Signed Integer ;; outUseEmptyPort ; 0 ; Signed Integer ;; outUseValid ; 1 ; Signed Integer ;; outUseReady ; 1 ; Signed Integer ;; outReadyLatency ; 0 ; Signed Integer ;+-----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_010 ;+-----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+-----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------+; inBitsPerSymbol ; 34 ; Signed Integer ;; inUsePackets ; 0 ; Signed Integer ;; inDataWidth ; 34 ; Signed Integer ;; inChannelWidth ; 0 ; Signed Integer ;; inErrorWidth ; 0 ; Signed Integer ;; inUseEmptyPort ; 0 ; Signed Integer ;; inUseValid ; 1 ; Signed Integer ;; inUseReady ; 1 ; Signed Integer ;; inReadyLatency ; 0 ; Signed Integer ;; outDataWidth ; 34 ; Signed Integer ;; outChannelWidth ; 0 ; Signed Integer ;; outErrorWidth ; 1 ; Signed Integer ;; outUseEmptyPort ; 0 ; Signed Integer ;; outUseValid ; 1 ; Signed Integer ;; outUseReady ; 1 ; Signed Integer ;; outReadyLatency ; 0 ; Signed Integer ;+-----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_011 ;+-----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+-----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------+; inBitsPerSymbol ; 34 ; Signed Integer ;; inUsePackets ; 0 ; Signed Integer ;; inDataWidth ; 34 ; Signed Integer ;; inChannelWidth ; 0 ; Signed Integer ;; inErrorWidth ; 0 ; Signed Integer ;; inUseEmptyPort ; 0 ; Signed Integer ;; inUseValid ; 1 ; Signed Integer ;; inUseReady ; 1 ; Signed Integer ;; inReadyLatency ; 0 ; Signed Integer ;; outDataWidth ; 34 ; Signed Integer ;; outChannelWidth ; 0 ; Signed Integer ;; outErrorWidth ; 1 ; Signed Integer ;; outUseEmptyPort ; 0 ; Signed Integer ;; outUseValid ; 1 ; Signed Integer ;; outUseReady ; 1 ; Signed Integer ;; outReadyLatency ; 0 ; Signed Integer ;+-----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_012 ;+-----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+-----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------+; inBitsPerSymbol ; 34 ; Signed Integer ;; inUsePackets ; 0 ; Signed Integer ;; inDataWidth ; 34 ; Signed Integer ;; inChannelWidth ; 0 ; Signed Integer ;; inErrorWidth ; 0 ; Signed Integer ;; inUseEmptyPort ; 0 ; Signed Integer ;; inUseValid ; 1 ; Signed Integer ;; inUseReady ; 1 ; Signed Integer ;; inReadyLatency ; 0 ; Signed Integer ;; outDataWidth ; 34 ; Signed Integer ;; outChannelWidth ; 0 ; Signed Integer ;; outErrorWidth ; 1 ; Signed Integer ;; outUseEmptyPort ; 0 ; Signed Integer ;; outUseValid ; 1 ; Signed Integer ;; outUseReady ; 1 ; Signed Integer ;; outReadyLatency ; 0 ; Signed Integer ;+-----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_013 ;+-----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+-----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------+; inBitsPerSymbol ; 34 ; Signed Integer ;; inUsePackets ; 0 ; Signed Integer ;; inDataWidth ; 34 ; Signed Integer ;; inChannelWidth ; 0 ; Signed Integer ;; inErrorWidth ; 0 ; Signed Integer ;; inUseEmptyPort ; 0 ; Signed Integer ;; inUseValid ; 1 ; Signed Integer ;; inUseReady ; 1 ; Signed Integer ;; inReadyLatency ; 0 ; Signed Integer ;; outDataWidth ; 34 ; Signed Integer ;; outChannelWidth ; 0 ; Signed Integer ;; outErrorWidth ; 1 ; Signed Integer ;; outUseEmptyPort ; 0 ; Signed Integer ;; outUseValid ; 1 ; Signed Integer ;; outUseReady ; 1 ; Signed Integer ;; outReadyLatency ; 0 ; Signed Integer ;+-----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_014 ;+-----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+-----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------+; inBitsPerSymbol ; 34 ; Signed Integer ;; inUsePackets ; 0 ; Signed Integer ;; inDataWidth ; 34 ; Signed Integer ;; inChannelWidth ; 0 ; Signed Integer ;; inErrorWidth ; 0 ; Signed Integer ;; inUseEmptyPort ; 0 ; Signed Integer ;; inUseValid ; 1 ; Signed Integer ;; inUseReady ; 1 ; Signed Integer ;; inReadyLatency ; 0 ; Signed Integer ;; outDataWidth ; 34 ; Signed Integer ;; outChannelWidth ; 0 ; Signed Integer ;; outErrorWidth ; 1 ; Signed Integer ;; outUseEmptyPort ; 0 ; Signed Integer ;; outUseValid ; 1 ; Signed Integer ;; outUseReady ; 1 ; Signed Integer ;; outReadyLatency ; 0 ; Signed Integer ;+-----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_015 ;+-----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+-----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------+; inBitsPerSymbol ; 34 ; Signed Integer ;; inUsePackets ; 0 ; Signed Integer ;; inDataWidth ; 34 ; Signed Integer ;; inChannelWidth ; 0 ; Signed Integer ;; inErrorWidth ; 0 ; Signed Integer ;; inUseEmptyPort ; 0 ; Signed Integer ;; inUseValid ; 1 ; Signed Integer ;; inUseReady ; 1 ; Signed Integer ;; inReadyLatency ; 0 ; Signed Integer ;; outDataWidth ; 34 ; Signed Integer ;; outChannelWidth ; 0 ; Signed Integer ;; outErrorWidth ; 1 ; Signed Integer ;; outUseEmptyPort ; 0 ; Signed Integer ;; outUseValid ; 1 ; Signed Integer ;; outUseReady ; 1 ; Signed Integer ;; outReadyLatency ; 0 ; Signed Integer ;+-----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_016 ;+-----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+-----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------+; inBitsPerSymbol ; 34 ; Signed Integer ;; inUsePackets ; 0 ; Signed Integer ;; inDataWidth ; 34 ; Signed Integer ;; inChannelWidth ; 0 ; Signed Integer ;; inErrorWidth ; 0 ; Signed Integer ;; inUseEmptyPort ; 0 ; Signed Integer ;; inUseValid ; 1 ; Signed Integer ;; inUseReady ; 1 ; Signed Integer ;; inReadyLatency ; 0 ; Signed Integer ;; outDataWidth ; 34 ; Signed Integer ;; outChannelWidth ; 0 ; Signed Integer ;; outErrorWidth ; 1 ; Signed Integer ;; outUseEmptyPort ; 0 ; Signed Integer ;; outUseValid ; 1 ; Signed Integer ;; outUseReady ; 1 ; Signed Integer ;; outReadyLatency ; 0 ; Signed Integer ;+-----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_017 ;+-----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+-----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------+; inBitsPerSymbol ; 34 ; Signed Integer ;; inUsePackets ; 0 ; Signed Integer ;; inDataWidth ; 34 ; Signed Integer ;; inChannelWidth ; 0 ; Signed Integer ;; inErrorWidth ; 0 ; Signed Integer ;; inUseEmptyPort ; 0 ; Signed Integer ;; inUseValid ; 1 ; Signed Integer ;; inUseReady ; 1 ; Signed Integer ;; inReadyLatency ; 0 ; Signed Integer ;; outDataWidth ; 34 ; Signed Integer ;; outChannelWidth ; 0 ; Signed Integer ;; outErrorWidth ; 1 ; Signed Integer ;; outUseEmptyPort ; 0 ; Signed Integer ;; outUseValid ; 1 ; Signed Integer ;; outUseReady ; 1 ; Signed Integer ;; outReadyLatency ; 0 ; Signed Integer ;+-----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_018 ;+-----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+-----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------+; inBitsPerSymbol ; 34 ; Signed Integer ;; inUsePackets ; 0 ; Signed Integer ;; inDataWidth ; 34 ; Signed Integer ;; inChannelWidth ; 0 ; Signed Integer ;; inErrorWidth ; 0 ; Signed Integer ;; inUseEmptyPort ; 0 ; Signed Integer ;; inUseValid ; 1 ; Signed Integer ;; inUseReady ; 1 ; Signed Integer ;; inReadyLatency ; 0 ; Signed Integer ;; outDataWidth ; 34 ; Signed Integer ;; outChannelWidth ; 0 ; Signed Integer ;; outErrorWidth ; 1 ; Signed Integer ;; outUseEmptyPort ; 0 ; Signed Integer ;; outUseValid ; 1 ; Signed Integer ;; outUseReady ; 1 ; Signed Integer ;; outReadyLatency ; 0 ; Signed Integer ;+-----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_019 ;+-----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+-----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------+; inBitsPerSymbol ; 34 ; Signed Integer ;; inUsePackets ; 0 ; Signed Integer ;; inDataWidth ; 34 ; Signed Integer ;; inChannelWidth ; 0 ; Signed Integer ;; inErrorWidth ; 0 ; Signed Integer ;; inUseEmptyPort ; 0 ; Signed Integer ;; inUseValid ; 1 ; Signed Integer ;; inUseReady ; 1 ; Signed Integer ;; inReadyLatency ; 0 ; Signed Integer ;; outDataWidth ; 34 ; Signed Integer ;; outChannelWidth ; 0 ; Signed Integer ;; outErrorWidth ; 1 ; Signed Integer ;; outUseEmptyPort ; 0 ; Signed Integer ;; outUseValid ; 1 ; Signed Integer ;; outUseReady ; 1 ; Signed Integer ;; outReadyLatency ; 0 ; Signed Integer ;+-----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_020 ;+-----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+-----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------+; inBitsPerSymbol ; 34 ; Signed Integer ;; inUsePackets ; 0 ; Signed Integer ;; inDataWidth ; 34 ; Signed Integer ;; inChannelWidth ; 0 ; Signed Integer ;; inErrorWidth ; 0 ; Signed Integer ;; inUseEmptyPort ; 0 ; Signed Integer ;; inUseValid ; 1 ; Signed Integer ;; inUseReady ; 1 ; Signed Integer ;; inReadyLatency ; 0 ; Signed Integer ;; outDataWidth ; 34 ; Signed Integer ;; outChannelWidth ; 0 ; Signed Integer ;; outErrorWidth ; 1 ; Signed Integer ;; outUseEmptyPort ; 0 ; Signed Integer ;; outUseValid ; 1 ; Signed Integer ;; outUseReady ; 1 ; Signed Integer ;; outReadyLatency ; 0 ; Signed Integer ;+-----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_021 ;+-----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+-----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------+; inBitsPerSymbol ; 34 ; Signed Integer ;; inUsePackets ; 0 ; Signed Integer ;; inDataWidth ; 34 ; Signed Integer ;; inChannelWidth ; 0 ; Signed Integer ;; inErrorWidth ; 0 ; Signed Integer ;; inUseEmptyPort ; 0 ; Signed Integer ;; inUseValid ; 1 ; Signed Integer ;; inUseReady ; 1 ; Signed Integer ;; inReadyLatency ; 0 ; Signed Integer ;; outDataWidth ; 34 ; Signed Integer ;; outChannelWidth ; 0 ; Signed Integer ;; outErrorWidth ; 1 ; Signed Integer ;; outUseEmptyPort ; 0 ; Signed Integer ;; outUseValid ; 1 ; Signed Integer ;; outUseReady ; 1 ; Signed Integer ;; outReadyLatency ; 0 ; Signed Integer ;+-----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+----------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|altera_reset_controller:rst_controller ;+---------------------------+----------+-------------------------------------------------------------+; Parameter Name ; Value ; Type ;+---------------------------+----------+-------------------------------------------------------------+; NUM_RESET_INPUTS ; 1 ; Signed Integer ;; USE_RESET_REQUEST_IN0 ; 0 ; Signed Integer ;; USE_RESET_REQUEST_IN1 ; 0 ; Signed Integer ;; USE_RESET_REQUEST_IN2 ; 0 ; Signed Integer ;; USE_RESET_REQUEST_IN3 ; 0 ; Signed Integer ;; USE_RESET_REQUEST_IN4 ; 0 ; Signed Integer ;; USE_RESET_REQUEST_IN5 ; 0 ; Signed Integer ;; USE_RESET_REQUEST_IN6 ; 0 ; Signed Integer ;; USE_RESET_REQUEST_IN7 ; 0 ; Signed Integer ;; USE_RESET_REQUEST_IN8 ; 0 ; Signed Integer ;; USE_RESET_REQUEST_IN9 ; 0 ; Signed Integer ;; USE_RESET_REQUEST_IN10 ; 0 ; Signed Integer ;; USE_RESET_REQUEST_IN11 ; 0 ; Signed Integer ;; USE_RESET_REQUEST_IN12 ; 0 ; Signed Integer ;; USE_RESET_REQUEST_IN13 ; 0 ; Signed Integer ;; USE_RESET_REQUEST_IN14 ; 0 ; Signed Integer ;; USE_RESET_REQUEST_IN15 ; 0 ; Signed Integer ;; OUTPUT_RESET_SYNC_EDGES ; deassert ; String ;; SYNC_DEPTH ; 2 ; Signed Integer ;; RESET_REQUEST_PRESENT ; 0 ; Signed Integer ;; RESET_REQ_WAIT_TIME ; 1 ; Signed Integer ;; MIN_RST_ASSERTION_TIME ; 3 ; Signed Integer ;; RESET_REQ_EARLY_DSRT_TIME ; 1 ; Signed Integer ;; ADAPT_RESET_REQUEST ; 0 ; Signed Integer ;+---------------------------+----------+-------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+-----------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1 ;+----------------+-------+----------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+----------------------------------------------------------------------------------------------------------------------+; ASYNC_RESET ; 1 ; Unsigned Binary ;; DEPTH ; 2 ; Signed Integer ;+----------------+-------+----------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+---------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_req_sync_uq1 ;+----------------+-------+--------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+--------------------------------------------------------------------------------------------------------------------------+; ASYNC_RESET ; 0 ; Signed Integer ;; DEPTH ; 2 ; Signed Integer ;+----------------+-------+--------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+--------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|altera_reset_controller:rst_controller_001 ;+---------------------------+----------+-----------------------------------------------------------------+; Parameter Name ; Value ; Type ;+---------------------------+----------+-----------------------------------------------------------------+; NUM_RESET_INPUTS ; 1 ; Signed Integer ;; USE_RESET_REQUEST_IN0 ; 0 ; Signed Integer ;; USE_RESET_REQUEST_IN1 ; 0 ; Signed Integer ;; USE_RESET_REQUEST_IN2 ; 0 ; Signed Integer ;; USE_RESET_REQUEST_IN3 ; 0 ; Signed Integer ;; USE_RESET_REQUEST_IN4 ; 0 ; Signed Integer ;; USE_RESET_REQUEST_IN5 ; 0 ; Signed Integer ;; USE_RESET_REQUEST_IN6 ; 0 ; Signed Integer ;; USE_RESET_REQUEST_IN7 ; 0 ; Signed Integer ;; USE_RESET_REQUEST_IN8 ; 0 ; Signed Integer ;; USE_RESET_REQUEST_IN9 ; 0 ; Signed Integer ;; USE_RESET_REQUEST_IN10 ; 0 ; Signed Integer ;; USE_RESET_REQUEST_IN11 ; 0 ; Signed Integer ;; USE_RESET_REQUEST_IN12 ; 0 ; Signed Integer ;; USE_RESET_REQUEST_IN13 ; 0 ; Signed Integer ;; USE_RESET_REQUEST_IN14 ; 0 ; Signed Integer ;; USE_RESET_REQUEST_IN15 ; 0 ; Signed Integer ;; OUTPUT_RESET_SYNC_EDGES ; deassert ; String ;; SYNC_DEPTH ; 2 ; Signed Integer ;; RESET_REQUEST_PRESENT ; 0 ; Signed Integer ;; RESET_REQ_WAIT_TIME ; 1 ; Signed Integer ;; MIN_RST_ASSERTION_TIME ; 3 ; Signed Integer ;; RESET_REQ_EARLY_DSRT_TIME ; 1 ; Signed Integer ;; ADAPT_RESET_REQUEST ; 0 ; Signed Integer ;+---------------------------+----------+-----------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+---------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1 ;+----------------+-------+--------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+--------------------------------------------------------------------------------------------------------------------------+; ASYNC_RESET ; 1 ; Unsigned Binary ;; DEPTH ; 2 ; Signed Integer ;+----------------+-------+--------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+-------------------------------------------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: ulight_fifo:u0|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_req_sync_uq1 ;+----------------+-------+------------------------------------------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+------------------------------------------------------------------------------------------------------------------------------+; ASYNC_RESET ; 0 ; Signed Integer ;; DEPTH ; 2 ; Signed Integer ;+----------------+-------+------------------------------------------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+---------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data ;+----------------+-------+--------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+--------------------------------------------------------------------+; DWIDTH ; 9 ; Signed Integer ;; AWIDTH ; 6 ; Signed Integer ;+----------------+-------+--------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+----------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx ;+----------------+-------+---------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+---------------------------------------------------------------------------------------------+; DWIDTH ; 9 ; Signed Integer ;; AWIDTH ; 6 ; Signed Integer ;+----------------+-------+---------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+---------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data ;+----------------+-------+--------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+--------------------------------------------------------------------+; DWIDTH ; 9 ; Signed Integer ;; AWIDTH ; 6 ; Signed Integer ;+----------------+-------+--------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+----------------------------------------------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx ;+----------------+-------+---------------------------------------------------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+---------------------------------------------------------------------------------------------+; DWIDTH ; 9 ; Signed Integer ;; AWIDTH ; 6 ; Signed Integer ;+----------------+-------+---------------------------------------------------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+-------------------------------------------------------------------------------------------------------------------+; Port Connectivity Checks: "detector_tokens:m_x|bit_capture_control:capture_c" ;+---------+--------+----------+-------------------------------------------------------------------------------------+; Port ; Type ; Severity ; Details ;+---------+--------+----------+-------------------------------------------------------------------------------------+; bit_c_0 ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;; bit_c_1 ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;+---------+--------+----------+-------------------------------------------------------------------------------------++-------------------------------------------------------------------------------------------------------------------+; Port Connectivity Checks: "detector_tokens:m_x|bit_capture_data:capture_d" ;+---------+--------+----------+-------------------------------------------------------------------------------------+; Port ; Type ; Severity ; Details ;+---------+--------+----------+-------------------------------------------------------------------------------------+; bit_d_0 ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;; bit_d_1 ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;; bit_d_2 ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;; bit_d_3 ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;; bit_d_4 ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;; bit_d_5 ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;; bit_d_6 ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;; bit_d_7 ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;+---------+--------+----------+-------------------------------------------------------------------------------------++---------------------------------------------------------------------------------------+; Port Connectivity Checks: "ulight_fifo:u0|altera_reset_controller:rst_controller_001" ;+----------------+--------+----------+--------------------------------------------------+; Port ; Type ; Severity ; Details ;+----------------+--------+----------+--------------------------------------------------+; reset_req ; Output ; Info ; Explicitly unconnected ;; reset_req_in0 ; Input ; Info ; Stuck at GND ;; reset_in1 ; Input ; Info ; Stuck at GND ;; reset_req_in1 ; Input ; Info ; Stuck at GND ;; reset_in2 ; Input ; Info ; Stuck at GND ;; reset_req_in2 ; Input ; Info ; Stuck at GND ;; reset_in3 ; Input ; Info ; Stuck at GND ;; reset_req_in3 ; Input ; Info ; Stuck at GND ;; reset_in4 ; Input ; Info ; Stuck at GND ;; reset_req_in4 ; Input ; Info ; Stuck at GND ;; reset_in5 ; Input ; Info ; Stuck at GND ;; reset_req_in5 ; Input ; Info ; Stuck at GND ;; reset_in6 ; Input ; Info ; Stuck at GND ;; reset_req_in6 ; Input ; Info ; Stuck at GND ;; reset_in7 ; Input ; Info ; Stuck at GND ;; reset_req_in7 ; Input ; Info ; Stuck at GND ;; reset_in8 ; Input ; Info ; Stuck at GND ;; reset_req_in8 ; Input ; Info ; Stuck at GND ;; reset_in9 ; Input ; Info ; Stuck at GND ;; reset_req_in9 ; Input ; Info ; Stuck at GND ;; reset_in10 ; Input ; Info ; Stuck at GND ;; reset_req_in10 ; Input ; Info ; Stuck at GND ;; reset_in11 ; Input ; Info ; Stuck at GND ;; reset_req_in11 ; Input ; Info ; Stuck at GND ;; reset_in12 ; Input ; Info ; Stuck at GND ;; reset_req_in12 ; Input ; Info ; Stuck at GND ;; reset_in13 ; Input ; Info ; Stuck at GND ;; reset_req_in13 ; Input ; Info ; Stuck at GND ;; reset_in14 ; Input ; Info ; Stuck at GND ;; reset_req_in14 ; Input ; Info ; Stuck at GND ;; reset_in15 ; Input ; Info ; Stuck at GND ;; reset_req_in15 ; Input ; Info ; Stuck at GND ;+----------------+--------+----------+--------------------------------------------------++----------------------------------------------------------------------------------------------------------------------------------+; Port Connectivity Checks: "ulight_fifo:u0|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_req_sync_uq1" ;+----------+-------+----------+----------------------------------------------------------------------------------------------------+; Port ; Type ; Severity ; Details ;+----------+-------+----------+----------------------------------------------------------------------------------------------------+; reset_in ; Input ; Info ; Stuck at GND ;+----------+-------+----------+----------------------------------------------------------------------------------------------------++-----------------------------------------------------------------------------------+; Port Connectivity Checks: "ulight_fifo:u0|altera_reset_controller:rst_controller" ;+----------------+--------+----------+----------------------------------------------+; Port ; Type ; Severity ; Details ;+----------------+--------+----------+----------------------------------------------+; reset_req ; Output ; Info ; Explicitly unconnected ;; reset_req_in0 ; Input ; Info ; Stuck at GND ;; reset_in1 ; Input ; Info ; Stuck at GND ;; reset_req_in1 ; Input ; Info ; Stuck at GND ;; reset_in2 ; Input ; Info ; Stuck at GND ;; reset_req_in2 ; Input ; Info ; Stuck at GND ;; reset_in3 ; Input ; Info ; Stuck at GND ;; reset_req_in3 ; Input ; Info ; Stuck at GND ;; reset_in4 ; Input ; Info ; Stuck at GND ;; reset_req_in4 ; Input ; Info ; Stuck at GND ;; reset_in5 ; Input ; Info ; Stuck at GND ;; reset_req_in5 ; Input ; Info ; Stuck at GND ;; reset_in6 ; Input ; Info ; Stuck at GND ;; reset_req_in6 ; Input ; Info ; Stuck at GND ;; reset_in7 ; Input ; Info ; Stuck at GND ;; reset_req_in7 ; Input ; Info ; Stuck at GND ;; reset_in8 ; Input ; Info ; Stuck at GND ;; reset_req_in8 ; Input ; Info ; Stuck at GND ;; reset_in9 ; Input ; Info ; Stuck at GND ;; reset_req_in9 ; Input ; Info ; Stuck at GND ;; reset_in10 ; Input ; Info ; Stuck at GND ;; reset_req_in10 ; Input ; Info ; Stuck at GND ;; reset_in11 ; Input ; Info ; Stuck at GND ;; reset_req_in11 ; Input ; Info ; Stuck at GND ;; reset_in12 ; Input ; Info ; Stuck at GND ;; reset_req_in12 ; Input ; Info ; Stuck at GND ;; reset_in13 ; Input ; Info ; Stuck at GND ;; reset_req_in13 ; Input ; Info ; Stuck at GND ;; reset_in14 ; Input ; Info ; Stuck at GND ;; reset_req_in14 ; Input ; Info ; Stuck at GND ;; reset_in15 ; Input ; Info ; Stuck at GND ;; reset_req_in15 ; Input ; Info ; Stuck at GND ;+----------------+--------+----------+----------------------------------------------++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_mux:rsp_mux|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder" ;+----------+--------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Port ; Type ; Severity ; Details ;+----------+--------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------+; b[43..1] ; Input ; Info ; Stuck at GND ;; b[0] ; Input ; Info ; Stuck at VCC ;; sum ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;+----------+--------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder" ;+---------+-------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Port ; Type ; Severity ; Details ;+---------+-------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; b[3..2] ; Input ; Info ; Stuck at GND ;+---------+-------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:dc_sub" ;+------+--------+----------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Port ; Type ; Severity ; Details ;+------+--------+----------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; a[7] ; Input ; Info ; Stuck at GND ;; b[7] ; Input ; Info ; Stuck at GND ;; diff ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;+------+--------+----------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:db_sub" ;+------------+--------+----------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Port ; Type ; Severity ; Details ;+------------+--------+----------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; a[7] ; Input ; Info ; Stuck at GND ;; b[7] ; Input ; Info ; Stuck at GND ;; diff[6..0] ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;+------------+--------+----------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:da_sub" ;+------------+--------+----------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Port ; Type ; Severity ; Details ;+------------+--------+----------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; a[7] ; Input ; Info ; Stuck at GND ;; b[7] ; Input ; Info ; Stuck at GND ;; diff[6..0] ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;+------------+--------+----------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:bc_sub" ;+------------+--------+----------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Port ; Type ; Severity ; Details ;+------------+--------+----------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; a[7] ; Input ; Info ; Stuck at GND ;; b[7] ; Input ; Info ; Stuck at GND ;; diff[6..0] ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;+------------+--------+----------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ac_sub" ;+------------+--------+----------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Port ; Type ; Severity ; Details ;+------------+--------+----------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; a[7] ; Input ; Info ; Stuck at GND ;; b[7] ; Input ; Info ; Stuck at GND ;; diff[6..0] ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;+------------+--------+----------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ab_sub|altera_merlin_burst_adapter_adder:subtract" ;+------+-------+----------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Port ; Type ; Severity ; Details ;+------+-------+----------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; cin ; Input ; Info ; Stuck at VCC ;+------+-------+----------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ab_sub" ;+------------+--------+----------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Port ; Type ; Severity ; Details ;+------------+--------+----------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; a[7] ; Input ; Info ; Stuck at GND ;; b[7] ; Input ; Info ; Stuck at GND ;; diff[6..0] ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;+------------+--------+----------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min" ;+---------+-------+----------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Port ; Type ; Severity ; Details ;+---------+-------+----------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; d[6..3] ; Input ; Info ; Stuck at GND ;; d[1..0] ; Input ; Info ; Stuck at GND ;; d[2] ; Input ; Info ; Stuck at VCC ;+---------+-------+----------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size" ;+------------------+--------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Port ; Type ; Severity ; Details ;+------------------+--------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; clk ; Input ; Info ; Stuck at GND ;; reset ; Input ; Info ; Stuck at GND ;; in_valid ; Input ; Info ; Stuck at GND ;; in_sop ; Input ; Info ; Stuck at GND ;; in_eop ; Input ; Info ; Stuck at GND ;; out_ready ; Input ; Info ; Explicitly unconnected ;; out_data[31..30] ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;+------------------+--------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_router_002:router_002|ulight_fifo_mm_interconnect_0_router_002_default_decode:the_default_decode" ;+------------------------+--------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Port ; Type ; Severity ; Details ;+------------------------+--------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; default_destination_id ; Output ; Info ; Explicitly unconnected ;; default_src_channel ; Output ; Info ; Explicitly unconnected ;+------------------------+--------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_router:router|ulight_fifo_mm_interconnect_0_router_default_decode:the_default_decode" ;+--------------------+--------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Port ; Type ; Severity ; Details ;+--------------------+--------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------+; default_wr_channel ; Output ; Info ; Explicitly unconnected ;; default_rd_channel ; Output ; Info ; Explicitly unconnected ;+--------------------+--------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------++------------------------------------------------------------------------------------------------------------------------------------------------------+; Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo" ;+-------------------+--------+----------+--------------------------------------------------------------------------------------------------------------+; Port ; Type ; Severity ; Details ;+-------------------+--------+----------+--------------------------------------------------------------------------------------------------------------+; csr_address ; Input ; Info ; Stuck at GND ;; csr_read ; Input ; Info ; Stuck at GND ;; csr_write ; Input ; Info ; Stuck at GND ;; csr_readdata ; Output ; Info ; Explicitly unconnected ;; csr_writedata ; Input ; Info ; Stuck at GND ;; almost_full_data ; Output ; Info ; Explicitly unconnected ;; almost_empty_data ; Output ; Info ; Explicitly unconnected ;; in_startofpacket ; Input ; Info ; Stuck at GND ;; in_endofpacket ; Input ; Info ; Stuck at GND ;; out_startofpacket ; Output ; Info ; Explicitly unconnected ;; out_endofpacket ; Output ; Info ; Explicitly unconnected ;; in_empty ; Input ; Info ; Stuck at GND ;; out_empty ; Output ; Info ; Explicitly unconnected ;; in_error ; Input ; Info ; Stuck at GND ;; out_error ; Output ; Info ; Explicitly unconnected ;; in_channel ; Input ; Info ; Stuck at GND ;; out_channel ; Output ; Info ; Explicitly unconnected ;+-------------------+--------+----------+--------------------------------------------------------------------------------------------------------------++----------------------------------------------------------------------------------------------------------------------------------------------------+; Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rsp_fifo" ;+-------------------+--------+----------+------------------------------------------------------------------------------------------------------------+; Port ; Type ; Severity ; Details ;+-------------------+--------+----------+------------------------------------------------------------------------------------------------------------+; csr_address ; Input ; Info ; Stuck at GND ;; csr_read ; Input ; Info ; Stuck at GND ;; csr_write ; Input ; Info ; Stuck at GND ;; csr_readdata ; Output ; Info ; Explicitly unconnected ;; csr_writedata ; Input ; Info ; Stuck at GND ;; almost_full_data ; Output ; Info ; Explicitly unconnected ;; almost_empty_data ; Output ; Info ; Explicitly unconnected ;; in_empty ; Input ; Info ; Stuck at GND ;; out_empty ; Output ; Info ; Explicitly unconnected ;; in_error ; Input ; Info ; Stuck at GND ;; out_error ; Output ; Info ; Explicitly unconnected ;; in_channel ; Input ; Info ; Stuck at GND ;; out_channel ; Output ; Info ; Explicitly unconnected ;+-------------------+--------+----------+------------------------------------------------------------------------------------------------------------++-----------------------------------------------------------------------------------------------------------------------------------------------+; Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:counter_rx_fifo_s1_agent" ;+-----------------------+-------+----------+----------------------------------------------------------------------------------------------------+; Port ; Type ; Severity ; Details ;+-----------------------+-------+----------+----------------------------------------------------------------------------------------------------+; m0_response ; Input ; Info ; Stuck at GND ;; m0_writeresponsevalid ; Input ; Info ; Stuck at GND ;+-----------------------+-------+----------+----------------------------------------------------------------------------------------------------++------------------------------------------------------------------------------------------------------------------------------------------------------+; Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rdata_fifo" ;+-------------------+--------+----------+--------------------------------------------------------------------------------------------------------------+; Port ; Type ; Severity ; Details ;+-------------------+--------+----------+--------------------------------------------------------------------------------------------------------------+; csr_address ; Input ; Info ; Stuck at GND ;; csr_read ; Input ; Info ; Stuck at GND ;; csr_write ; Input ; Info ; Stuck at GND ;; csr_readdata ; Output ; Info ; Explicitly unconnected ;; csr_writedata ; Input ; Info ; Stuck at GND ;; almost_full_data ; Output ; Info ; Explicitly unconnected ;; almost_empty_data ; Output ; Info ; Explicitly unconnected ;; in_startofpacket ; Input ; Info ; Stuck at GND ;; in_endofpacket ; Input ; Info ; Stuck at GND ;; out_startofpacket ; Output ; Info ; Explicitly unconnected ;; out_endofpacket ; Output ; Info ; Explicitly unconnected ;; in_empty ; Input ; Info ; Stuck at GND ;; out_empty ; Output ; Info ; Explicitly unconnected ;; in_error ; Input ; Info ; Stuck at GND ;; out_error ; Output ; Info ; Explicitly unconnected ;; in_channel ; Input ; Info ; Stuck at GND ;; out_channel ; Output ; Info ; Explicitly unconnected ;+-------------------+--------+----------+--------------------------------------------------------------------------------------------------------------++----------------------------------------------------------------------------------------------------------------------------------------------------+; Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rsp_fifo" ;+-------------------+--------+----------+------------------------------------------------------------------------------------------------------------+; Port ; Type ; Severity ; Details ;+-------------------+--------+----------+------------------------------------------------------------------------------------------------------------+; csr_address ; Input ; Info ; Stuck at GND ;; csr_read ; Input ; Info ; Stuck at GND ;; csr_write ; Input ; Info ; Stuck at GND ;; csr_readdata ; Output ; Info ; Explicitly unconnected ;; csr_writedata ; Input ; Info ; Stuck at GND ;; almost_full_data ; Output ; Info ; Explicitly unconnected ;; almost_empty_data ; Output ; Info ; Explicitly unconnected ;; in_empty ; Input ; Info ; Stuck at GND ;; out_empty ; Output ; Info ; Explicitly unconnected ;; in_error ; Input ; Info ; Stuck at GND ;; out_error ; Output ; Info ; Explicitly unconnected ;; in_channel ; Input ; Info ; Stuck at GND ;; out_channel ; Output ; Info ; Explicitly unconnected ;+-------------------+--------+----------+------------------------------------------------------------------------------------------------------------++-----------------------------------------------------------------------------------------------------------------------------------------------+; Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:counter_tx_fifo_s1_agent" ;+-----------------------+-------+----------+----------------------------------------------------------------------------------------------------+; Port ; Type ; Severity ; Details ;+-----------------------+-------+----------+----------------------------------------------------------------------------------------------------+; m0_response ; Input ; Info ; Stuck at GND ;; m0_writeresponsevalid ; Input ; Info ; Stuck at GND ;+-----------------------+-------+----------+----------------------------------------------------------------------------------------------------++-----------------------------------------------------------------------------------------------------------------------------------------------+; Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo" ;+-------------------+--------+----------+-------------------------------------------------------------------------------------------------------+; Port ; Type ; Severity ; Details ;+-------------------+--------+----------+-------------------------------------------------------------------------------------------------------+; csr_address ; Input ; Info ; Stuck at GND ;; csr_read ; Input ; Info ; Stuck at GND ;; csr_write ; Input ; Info ; Stuck at GND ;; csr_readdata ; Output ; Info ; Explicitly unconnected ;; csr_writedata ; Input ; Info ; Stuck at GND ;; almost_full_data ; Output ; Info ; Explicitly unconnected ;; almost_empty_data ; Output ; Info ; Explicitly unconnected ;; in_startofpacket ; Input ; Info ; Stuck at GND ;; in_endofpacket ; Input ; Info ; Stuck at GND ;; out_startofpacket ; Output ; Info ; Explicitly unconnected ;; out_endofpacket ; Output ; Info ; Explicitly unconnected ;; in_empty ; Input ; Info ; Stuck at GND ;; out_empty ; Output ; Info ; Explicitly unconnected ;; in_error ; Input ; Info ; Stuck at GND ;; out_error ; Output ; Info ; Explicitly unconnected ;; in_channel ; Input ; Info ; Stuck at GND ;; out_channel ; Output ; Info ; Explicitly unconnected ;+-------------------+--------+----------+-------------------------------------------------------------------------------------------------------++---------------------------------------------------------------------------------------------------------------------------------------------+; Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rsp_fifo" ;+-------------------+--------+----------+-----------------------------------------------------------------------------------------------------+; Port ; Type ; Severity ; Details ;+-------------------+--------+----------+-----------------------------------------------------------------------------------------------------+; csr_address ; Input ; Info ; Stuck at GND ;; csr_read ; Input ; Info ; Stuck at GND ;; csr_write ; Input ; Info ; Stuck at GND ;; csr_readdata ; Output ; Info ; Explicitly unconnected ;; csr_writedata ; Input ; Info ; Stuck at GND ;; almost_full_data ; Output ; Info ; Explicitly unconnected ;; almost_empty_data ; Output ; Info ; Explicitly unconnected ;; in_empty ; Input ; Info ; Stuck at GND ;; out_empty ; Output ; Info ; Explicitly unconnected ;; in_error ; Input ; Info ; Stuck at GND ;; out_error ; Output ; Info ; Explicitly unconnected ;; in_channel ; Input ; Info ; Stuck at GND ;; out_channel ; Output ; Info ; Explicitly unconnected ;+-------------------+--------+----------+-----------------------------------------------------------------------------------------------------++----------------------------------------------------------------------------------------------------------------------------------------+; Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fsm_info_s1_agent" ;+-----------------------+-------+----------+---------------------------------------------------------------------------------------------+; Port ; Type ; Severity ; Details ;+-----------------------+-------+----------+---------------------------------------------------------------------------------------------+; m0_response ; Input ; Info ; Stuck at GND ;; m0_writeresponsevalid ; Input ; Info ; Stuck at GND ;+-----------------------+-------+----------+---------------------------------------------------------------------------------------------++------------------------------------------------------------------------------------------------------------------------------------------------+; Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rdata_fifo" ;+-------------------+--------+----------+--------------------------------------------------------------------------------------------------------+; Port ; Type ; Severity ; Details ;+-------------------+--------+----------+--------------------------------------------------------------------------------------------------------+; csr_address ; Input ; Info ; Stuck at GND ;; csr_read ; Input ; Info ; Stuck at GND ;; csr_write ; Input ; Info ; Stuck at GND ;; csr_readdata ; Output ; Info ; Explicitly unconnected ;; csr_writedata ; Input ; Info ; Stuck at GND ;; almost_full_data ; Output ; Info ; Explicitly unconnected ;; almost_empty_data ; Output ; Info ; Explicitly unconnected ;; in_startofpacket ; Input ; Info ; Stuck at GND ;; in_endofpacket ; Input ; Info ; Stuck at GND ;; out_startofpacket ; Output ; Info ; Explicitly unconnected ;; out_endofpacket ; Output ; Info ; Explicitly unconnected ;; in_empty ; Input ; Info ; Stuck at GND ;; out_empty ; Output ; Info ; Explicitly unconnected ;; in_error ; Input ; Info ; Stuck at GND ;; out_error ; Output ; Info ; Explicitly unconnected ;; in_channel ; Input ; Info ; Stuck at GND ;; out_channel ; Output ; Info ; Explicitly unconnected ;+-------------------+--------+----------+--------------------------------------------------------------------------------------------------------++----------------------------------------------------------------------------------------------------------------------------------------------+; Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rsp_fifo" ;+-------------------+--------+----------+------------------------------------------------------------------------------------------------------+; Port ; Type ; Severity ; Details ;+-------------------+--------+----------+------------------------------------------------------------------------------------------------------+; csr_address ; Input ; Info ; Stuck at GND ;; csr_read ; Input ; Info ; Stuck at GND ;; csr_write ; Input ; Info ; Stuck at GND ;; csr_readdata ; Output ; Info ; Explicitly unconnected ;; csr_writedata ; Input ; Info ; Stuck at GND ;; almost_full_data ; Output ; Info ; Explicitly unconnected ;; almost_empty_data ; Output ; Info ; Explicitly unconnected ;; in_empty ; Input ; Info ; Stuck at GND ;; out_empty ; Output ; Info ; Explicitly unconnected ;; in_error ; Input ; Info ; Stuck at GND ;; out_error ; Output ; Info ; Explicitly unconnected ;; in_channel ; Input ; Info ; Stuck at GND ;; out_channel ; Output ; Info ; Explicitly unconnected ;+-------------------+--------+----------+------------------------------------------------------------------------------------------------------++-----------------------------------------------------------------------------------------------------------------------------------------+; Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:clock_sel_s1_agent" ;+-----------------------+-------+----------+----------------------------------------------------------------------------------------------+; Port ; Type ; Severity ; Details ;+-----------------------+-------+----------+----------------------------------------------------------------------------------------------+; m0_response ; Input ; Info ; Stuck at GND ;; m0_writeresponsevalid ; Input ; Info ; Stuck at GND ;+-----------------------+-------+----------+----------------------------------------------------------------------------------------------++------------------------------------------------------------------------------------------------------------------------------------------------+; Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo" ;+-------------------+--------+----------+--------------------------------------------------------------------------------------------------------+; Port ; Type ; Severity ; Details ;+-------------------+--------+----------+--------------------------------------------------------------------------------------------------------+; csr_address ; Input ; Info ; Stuck at GND ;; csr_read ; Input ; Info ; Stuck at GND ;; csr_write ; Input ; Info ; Stuck at GND ;; csr_readdata ; Output ; Info ; Explicitly unconnected ;; csr_writedata ; Input ; Info ; Stuck at GND ;; almost_full_data ; Output ; Info ; Explicitly unconnected ;; almost_empty_data ; Output ; Info ; Explicitly unconnected ;; in_startofpacket ; Input ; Info ; Stuck at GND ;; in_endofpacket ; Input ; Info ; Stuck at GND ;; out_startofpacket ; Output ; Info ; Explicitly unconnected ;; out_endofpacket ; Output ; Info ; Explicitly unconnected ;; in_empty ; Input ; Info ; Stuck at GND ;; out_empty ; Output ; Info ; Explicitly unconnected ;; in_error ; Input ; Info ; Stuck at GND ;; out_error ; Output ; Info ; Explicitly unconnected ;; in_channel ; Input ; Info ; Stuck at GND ;; out_channel ; Output ; Info ; Explicitly unconnected ;+-------------------+--------+----------+--------------------------------------------------------------------------------------------------------++----------------------------------------------------------------------------------------------------------------------------------------------+; Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rsp_fifo" ;+-------------------+--------+----------+------------------------------------------------------------------------------------------------------+; Port ; Type ; Severity ; Details ;+-------------------+--------+----------+------------------------------------------------------------------------------------------------------+; csr_address ; Input ; Info ; Stuck at GND ;; csr_read ; Input ; Info ; Stuck at GND ;; csr_write ; Input ; Info ; Stuck at GND ;; csr_readdata ; Output ; Info ; Explicitly unconnected ;; csr_writedata ; Input ; Info ; Stuck at GND ;; almost_full_data ; Output ; Info ; Explicitly unconnected ;; almost_empty_data ; Output ; Info ; Explicitly unconnected ;; in_empty ; Input ; Info ; Stuck at GND ;; out_empty ; Output ; Info ; Explicitly unconnected ;; in_error ; Input ; Info ; Stuck at GND ;; out_error ; Output ; Info ; Explicitly unconnected ;; in_channel ; Input ; Info ; Stuck at GND ;; out_channel ; Output ; Info ; Explicitly unconnected ;+-------------------+--------+----------+------------------------------------------------------------------------------------------------------++-----------------------------------------------------------------------------------------------------------------------------------------+; Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:data_info_s1_agent" ;+-----------------------+-------+----------+----------------------------------------------------------------------------------------------+; Port ; Type ; Severity ; Details ;+-----------------------+-------+----------+----------------------------------------------------------------------------------------------+; m0_response ; Input ; Info ; Stuck at GND ;; m0_writeresponsevalid ; Input ; Info ; Stuck at GND ;+-----------------------+-------+----------+----------------------------------------------------------------------------------------------++--------------------------------------------------------------------------------------------------------------------------------------------------------+; Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rdata_fifo" ;+-------------------+--------+----------+----------------------------------------------------------------------------------------------------------------+; Port ; Type ; Severity ; Details ;+-------------------+--------+----------+----------------------------------------------------------------------------------------------------------------+; csr_address ; Input ; Info ; Stuck at GND ;; csr_read ; Input ; Info ; Stuck at GND ;; csr_write ; Input ; Info ; Stuck at GND ;; csr_readdata ; Output ; Info ; Explicitly unconnected ;; csr_writedata ; Input ; Info ; Stuck at GND ;; almost_full_data ; Output ; Info ; Explicitly unconnected ;; almost_empty_data ; Output ; Info ; Explicitly unconnected ;; in_startofpacket ; Input ; Info ; Stuck at GND ;; in_endofpacket ; Input ; Info ; Stuck at GND ;; out_startofpacket ; Output ; Info ; Explicitly unconnected ;; out_endofpacket ; Output ; Info ; Explicitly unconnected ;; in_empty ; Input ; Info ; Stuck at GND ;; out_empty ; Output ; Info ; Explicitly unconnected ;; in_error ; Input ; Info ; Stuck at GND ;; out_error ; Output ; Info ; Explicitly unconnected ;; in_channel ; Input ; Info ; Stuck at GND ;; out_channel ; Output ; Info ; Explicitly unconnected ;+-------------------+--------+----------+----------------------------------------------------------------------------------------------------------------++------------------------------------------------------------------------------------------------------------------------------------------------------+; Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rsp_fifo" ;+-------------------+--------+----------+--------------------------------------------------------------------------------------------------------------+; Port ; Type ; Severity ; Details ;+-------------------+--------+----------+--------------------------------------------------------------------------------------------------------------+; csr_address ; Input ; Info ; Stuck at GND ;; csr_read ; Input ; Info ; Stuck at GND ;; csr_write ; Input ; Info ; Stuck at GND ;; csr_readdata ; Output ; Info ; Explicitly unconnected ;; csr_writedata ; Input ; Info ; Stuck at GND ;; almost_full_data ; Output ; Info ; Explicitly unconnected ;; almost_empty_data ; Output ; Info ; Explicitly unconnected ;; in_empty ; Input ; Info ; Stuck at GND ;; out_empty ; Output ; Info ; Explicitly unconnected ;; in_error ; Input ; Info ; Stuck at GND ;; out_error ; Output ; Info ; Explicitly unconnected ;; in_channel ; Input ; Info ; Stuck at GND ;; out_channel ; Output ; Info ; Explicitly unconnected ;+-------------------+--------+----------+--------------------------------------------------------------------------------------------------------------++-------------------------------------------------------------------------------------------------------------------------------------------------+; Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_tx_ready_s1_agent" ;+-----------------------+-------+----------+------------------------------------------------------------------------------------------------------+; Port ; Type ; Severity ; Details ;+-----------------------+-------+----------+------------------------------------------------------------------------------------------------------+; m0_response ; Input ; Info ; Stuck at GND ;; m0_writeresponsevalid ; Input ; Info ; Stuck at GND ;+-----------------------+-------+----------+------------------------------------------------------------------------------------------------------++---------------------------------------------------------------------------------------------------------------------------------------------------------+; Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rdata_fifo" ;+-------------------+--------+----------+-----------------------------------------------------------------------------------------------------------------+; Port ; Type ; Severity ; Details ;+-------------------+--------+----------+-----------------------------------------------------------------------------------------------------------------+; csr_address ; Input ; Info ; Stuck at GND ;; csr_read ; Input ; Info ; Stuck at GND ;; csr_write ; Input ; Info ; Stuck at GND ;; csr_readdata ; Output ; Info ; Explicitly unconnected ;; csr_writedata ; Input ; Info ; Stuck at GND ;; almost_full_data ; Output ; Info ; Explicitly unconnected ;; almost_empty_data ; Output ; Info ; Explicitly unconnected ;; in_startofpacket ; Input ; Info ; Stuck at GND ;; in_endofpacket ; Input ; Info ; Stuck at GND ;; out_startofpacket ; Output ; Info ; Explicitly unconnected ;; out_endofpacket ; Output ; Info ; Explicitly unconnected ;; in_empty ; Input ; Info ; Stuck at GND ;; out_empty ; Output ; Info ; Explicitly unconnected ;; in_error ; Input ; Info ; Stuck at GND ;; out_error ; Output ; Info ; Explicitly unconnected ;; in_channel ; Input ; Info ; Stuck at GND ;; out_channel ; Output ; Info ; Explicitly unconnected ;+-------------------+--------+----------+-----------------------------------------------------------------------------------------------------------------++-------------------------------------------------------------------------------------------------------------------------------------------------------+; Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rsp_fifo" ;+-------------------+--------+----------+---------------------------------------------------------------------------------------------------------------+; Port ; Type ; Severity ; Details ;+-------------------+--------+----------+---------------------------------------------------------------------------------------------------------------+; csr_address ; Input ; Info ; Stuck at GND ;; csr_read ; Input ; Info ; Stuck at GND ;; csr_write ; Input ; Info ; Stuck at GND ;; csr_readdata ; Output ; Info ; Explicitly unconnected ;; csr_writedata ; Input ; Info ; Stuck at GND ;; almost_full_data ; Output ; Info ; Explicitly unconnected ;; almost_empty_data ; Output ; Info ; Explicitly unconnected ;; in_empty ; Input ; Info ; Stuck at GND ;; out_empty ; Output ; Info ; Explicitly unconnected ;; in_error ; Input ; Info ; Stuck at GND ;; out_error ; Output ; Info ; Explicitly unconnected ;; in_channel ; Input ; Info ; Stuck at GND ;; out_channel ; Output ; Info ; Explicitly unconnected ;+-------------------+--------+----------+---------------------------------------------------------------------------------------------------------------++--------------------------------------------------------------------------------------------------------------------------------------------------+; Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_tx_enable_s1_agent" ;+-----------------------+-------+----------+-------------------------------------------------------------------------------------------------------+; Port ; Type ; Severity ; Details ;+-----------------------+-------+----------+-------------------------------------------------------------------------------------------------------+; m0_response ; Input ; Info ; Stuck at GND ;; m0_writeresponsevalid ; Input ; Info ; Stuck at GND ;+-----------------------+-------+----------+-------------------------------------------------------------------------------------------------------++-------------------------------------------------------------------------------------------------------------------------------------------------------+; Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rdata_fifo" ;+-------------------+--------+----------+---------------------------------------------------------------------------------------------------------------+; Port ; Type ; Severity ; Details ;+-------------------+--------+----------+---------------------------------------------------------------------------------------------------------------+; csr_address ; Input ; Info ; Stuck at GND ;; csr_read ; Input ; Info ; Stuck at GND ;; csr_write ; Input ; Info ; Stuck at GND ;; csr_readdata ; Output ; Info ; Explicitly unconnected ;; csr_writedata ; Input ; Info ; Stuck at GND ;; almost_full_data ; Output ; Info ; Explicitly unconnected ;; almost_empty_data ; Output ; Info ; Explicitly unconnected ;; in_startofpacket ; Input ; Info ; Stuck at GND ;; in_endofpacket ; Input ; Info ; Stuck at GND ;; out_startofpacket ; Output ; Info ; Explicitly unconnected ;; out_endofpacket ; Output ; Info ; Explicitly unconnected ;; in_empty ; Input ; Info ; Stuck at GND ;; out_empty ; Output ; Info ; Explicitly unconnected ;; in_error ; Input ; Info ; Stuck at GND ;; out_error ; Output ; Info ; Explicitly unconnected ;; in_channel ; Input ; Info ; Stuck at GND ;; out_channel ; Output ; Info ; Explicitly unconnected ;+-------------------+--------+----------+---------------------------------------------------------------------------------------------------------------++-----------------------------------------------------------------------------------------------------------------------------------------------------+; Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rsp_fifo" ;+-------------------+--------+----------+-------------------------------------------------------------------------------------------------------------+; Port ; Type ; Severity ; Details ;+-------------------+--------+----------+-------------------------------------------------------------------------------------------------------------+; csr_address ; Input ; Info ; Stuck at GND ;; csr_read ; Input ; Info ; Stuck at GND ;; csr_write ; Input ; Info ; Stuck at GND ;; csr_readdata ; Output ; Info ; Explicitly unconnected ;; csr_writedata ; Input ; Info ; Stuck at GND ;; almost_full_data ; Output ; Info ; Explicitly unconnected ;; almost_empty_data ; Output ; Info ; Explicitly unconnected ;; in_empty ; Input ; Info ; Stuck at GND ;; out_empty ; Output ; Info ; Explicitly unconnected ;; in_error ; Input ; Info ; Stuck at GND ;; out_error ; Output ; Info ; Explicitly unconnected ;; in_channel ; Input ; Info ; Stuck at GND ;; out_channel ; Output ; Info ; Explicitly unconnected ;+-------------------+--------+----------+-------------------------------------------------------------------------------------------------------------++------------------------------------------------------------------------------------------------------------------------------------------------+; Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_tx_data_s1_agent" ;+-----------------------+-------+----------+-----------------------------------------------------------------------------------------------------+; Port ; Type ; Severity ; Details ;+-----------------------+-------+----------+-----------------------------------------------------------------------------------------------------+; m0_response ; Input ; Info ; Stuck at GND ;; m0_writeresponsevalid ; Input ; Info ; Stuck at GND ;+-----------------------+-------+----------+-----------------------------------------------------------------------------------------------------++-----------------------------------------------------------------------------------------------------------------------------------------------------------+; Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rdata_fifo" ;+-------------------+--------+----------+-------------------------------------------------------------------------------------------------------------------+; Port ; Type ; Severity ; Details ;+-------------------+--------+----------+-------------------------------------------------------------------------------------------------------------------+; csr_address ; Input ; Info ; Stuck at GND ;; csr_read ; Input ; Info ; Stuck at GND ;; csr_write ; Input ; Info ; Stuck at GND ;; csr_readdata ; Output ; Info ; Explicitly unconnected ;; csr_writedata ; Input ; Info ; Stuck at GND ;; almost_full_data ; Output ; Info ; Explicitly unconnected ;; almost_empty_data ; Output ; Info ; Explicitly unconnected ;; in_startofpacket ; Input ; Info ; Stuck at GND ;; in_endofpacket ; Input ; Info ; Stuck at GND ;; out_startofpacket ; Output ; Info ; Explicitly unconnected ;; out_endofpacket ; Output ; Info ; Explicitly unconnected ;; in_empty ; Input ; Info ; Stuck at GND ;; out_empty ; Output ; Info ; Explicitly unconnected ;; in_error ; Input ; Info ; Stuck at GND ;; out_error ; Output ; Info ; Explicitly unconnected ;; in_channel ; Input ; Info ; Stuck at GND ;; out_channel ; Output ; Info ; Explicitly unconnected ;+-------------------+--------+----------+-------------------------------------------------------------------------------------------------------------------++---------------------------------------------------------------------------------------------------------------------------------------------------------+; Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rsp_fifo" ;+-------------------+--------+----------+-----------------------------------------------------------------------------------------------------------------+; Port ; Type ; Severity ; Details ;+-------------------+--------+----------+-----------------------------------------------------------------------------------------------------------------+; csr_address ; Input ; Info ; Stuck at GND ;; csr_read ; Input ; Info ; Stuck at GND ;; csr_write ; Input ; Info ; Stuck at GND ;; csr_readdata ; Output ; Info ; Explicitly unconnected ;; csr_writedata ; Input ; Info ; Stuck at GND ;; almost_full_data ; Output ; Info ; Explicitly unconnected ;; almost_empty_data ; Output ; Info ; Explicitly unconnected ;; in_empty ; Input ; Info ; Stuck at GND ;; out_empty ; Output ; Info ; Explicitly unconnected ;; in_error ; Input ; Info ; Stuck at GND ;; out_error ; Output ; Info ; Explicitly unconnected ;; in_channel ; Input ; Info ; Stuck at GND ;; out_channel ; Output ; Info ; Explicitly unconnected ;+-------------------+--------+----------+-----------------------------------------------------------------------------------------------------------------++----------------------------------------------------------------------------------------------------------------------------------------------------+; Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fifo_empty_tx_status_s1_agent" ;+-----------------------+-------+----------+---------------------------------------------------------------------------------------------------------+; Port ; Type ; Severity ; Details ;+-----------------------+-------+----------+---------------------------------------------------------------------------------------------------------+; m0_response ; Input ; Info ; Stuck at GND ;; m0_writeresponsevalid ; Input ; Info ; Stuck at GND ;+-----------------------+-------+----------+---------------------------------------------------------------------------------------------------------++----------------------------------------------------------------------------------------------------------------------------------------------------------+; Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo" ;+-------------------+--------+----------+------------------------------------------------------------------------------------------------------------------+; Port ; Type ; Severity ; Details ;+-------------------+--------+----------+------------------------------------------------------------------------------------------------------------------+; csr_address ; Input ; Info ; Stuck at GND ;; csr_read ; Input ; Info ; Stuck at GND ;; csr_write ; Input ; Info ; Stuck at GND ;; csr_readdata ; Output ; Info ; Explicitly unconnected ;; csr_writedata ; Input ; Info ; Stuck at GND ;; almost_full_data ; Output ; Info ; Explicitly unconnected ;; almost_empty_data ; Output ; Info ; Explicitly unconnected ;; in_startofpacket ; Input ; Info ; Stuck at GND ;; in_endofpacket ; Input ; Info ; Stuck at GND ;; out_startofpacket ; Output ; Info ; Explicitly unconnected ;; out_endofpacket ; Output ; Info ; Explicitly unconnected ;; in_empty ; Input ; Info ; Stuck at GND ;; out_empty ; Output ; Info ; Explicitly unconnected ;; in_error ; Input ; Info ; Stuck at GND ;; out_error ; Output ; Info ; Explicitly unconnected ;; in_channel ; Input ; Info ; Stuck at GND ;; out_channel ; Output ; Info ; Explicitly unconnected ;+-------------------+--------+----------+------------------------------------------------------------------------------------------------------------------++--------------------------------------------------------------------------------------------------------------------------------------------------------+; Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rsp_fifo" ;+-------------------+--------+----------+----------------------------------------------------------------------------------------------------------------+; Port ; Type ; Severity ; Details ;+-------------------+--------+----------+----------------------------------------------------------------------------------------------------------------+; csr_address ; Input ; Info ; Stuck at GND ;; csr_read ; Input ; Info ; Stuck at GND ;; csr_write ; Input ; Info ; Stuck at GND ;; csr_readdata ; Output ; Info ; Explicitly unconnected ;; csr_writedata ; Input ; Info ; Stuck at GND ;; almost_full_data ; Output ; Info ; Explicitly unconnected ;; almost_empty_data ; Output ; Info ; Explicitly unconnected ;; in_empty ; Input ; Info ; Stuck at GND ;; out_empty ; Output ; Info ; Explicitly unconnected ;; in_error ; Input ; Info ; Stuck at GND ;; out_error ; Output ; Info ; Explicitly unconnected ;; in_channel ; Input ; Info ; Stuck at GND ;; out_channel ; Output ; Info ; Explicitly unconnected ;+-------------------+--------+----------+----------------------------------------------------------------------------------------------------------------++---------------------------------------------------------------------------------------------------------------------------------------------------+; Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fifo_full_tx_status_s1_agent" ;+-----------------------+-------+----------+--------------------------------------------------------------------------------------------------------+; Port ; Type ; Severity ; Details ;+-----------------------+-------+----------+--------------------------------------------------------------------------------------------------------+; m0_response ; Input ; Info ; Stuck at GND ;; m0_writeresponsevalid ; Input ; Info ; Stuck at GND ;+-----------------------+-------+----------+--------------------------------------------------------------------------------------------------------++--------------------------------------------------------------------------------------------------------------------------------------------------+; Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo" ;+-------------------+--------+----------+----------------------------------------------------------------------------------------------------------+; Port ; Type ; Severity ; Details ;+-------------------+--------+----------+----------------------------------------------------------------------------------------------------------+; csr_address ; Input ; Info ; Stuck at GND ;; csr_read ; Input ; Info ; Stuck at GND ;; csr_write ; Input ; Info ; Stuck at GND ;; csr_readdata ; Output ; Info ; Explicitly unconnected ;; csr_writedata ; Input ; Info ; Stuck at GND ;; almost_full_data ; Output ; Info ; Explicitly unconnected ;; almost_empty_data ; Output ; Info ; Explicitly unconnected ;; in_startofpacket ; Input ; Info ; Stuck at GND ;; in_endofpacket ; Input ; Info ; Stuck at GND ;; out_startofpacket ; Output ; Info ; Explicitly unconnected ;; out_endofpacket ; Output ; Info ; Explicitly unconnected ;; in_empty ; Input ; Info ; Stuck at GND ;; out_empty ; Output ; Info ; Explicitly unconnected ;; in_error ; Input ; Info ; Stuck at GND ;; out_error ; Output ; Info ; Explicitly unconnected ;; in_channel ; Input ; Info ; Stuck at GND ;; out_channel ; Output ; Info ; Explicitly unconnected ;+-------------------+--------+----------+----------------------------------------------------------------------------------------------------------++------------------------------------------------------------------------------------------------------------------------------------------------+; Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rsp_fifo" ;+-------------------+--------+----------+--------------------------------------------------------------------------------------------------------+; Port ; Type ; Severity ; Details ;+-------------------+--------+----------+--------------------------------------------------------------------------------------------------------+; csr_address ; Input ; Info ; Stuck at GND ;; csr_read ; Input ; Info ; Stuck at GND ;; csr_write ; Input ; Info ; Stuck at GND ;; csr_readdata ; Output ; Info ; Explicitly unconnected ;; csr_writedata ; Input ; Info ; Stuck at GND ;; almost_full_data ; Output ; Info ; Explicitly unconnected ;; almost_empty_data ; Output ; Info ; Explicitly unconnected ;; in_empty ; Input ; Info ; Stuck at GND ;; out_empty ; Output ; Info ; Explicitly unconnected ;; in_error ; Input ; Info ; Stuck at GND ;; out_error ; Output ; Info ; Explicitly unconnected ;; in_channel ; Input ; Info ; Stuck at GND ;; out_channel ; Output ; Info ; Explicitly unconnected ;+-------------------+--------+----------+--------------------------------------------------------------------------------------------------------++-------------------------------------------------------------------------------------------------------------------------------------------+; Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:write_en_tx_s1_agent" ;+-----------------------+-------+----------+------------------------------------------------------------------------------------------------+; Port ; Type ; Severity ; Details ;+-----------------------+-------+----------+------------------------------------------------------------------------------------------------+; m0_response ; Input ; Info ; Stuck at GND ;; m0_writeresponsevalid ; Input ; Info ; Stuck at GND ;+-----------------------+-------+----------+------------------------------------------------------------------------------------------------++---------------------------------------------------------------------------------------------------------------------------------------------------------+; Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rdata_fifo" ;+-------------------+--------+----------+-----------------------------------------------------------------------------------------------------------------+; Port ; Type ; Severity ; Details ;+-------------------+--------+----------+-----------------------------------------------------------------------------------------------------------------+; csr_address ; Input ; Info ; Stuck at GND ;; csr_read ; Input ; Info ; Stuck at GND ;; csr_write ; Input ; Info ; Stuck at GND ;; csr_readdata ; Output ; Info ; Explicitly unconnected ;; csr_writedata ; Input ; Info ; Stuck at GND ;; almost_full_data ; Output ; Info ; Explicitly unconnected ;; almost_empty_data ; Output ; Info ; Explicitly unconnected ;; in_startofpacket ; Input ; Info ; Stuck at GND ;; in_endofpacket ; Input ; Info ; Stuck at GND ;; out_startofpacket ; Output ; Info ; Explicitly unconnected ;; out_endofpacket ; Output ; Info ; Explicitly unconnected ;; in_empty ; Input ; Info ; Stuck at GND ;; out_empty ; Output ; Info ; Explicitly unconnected ;; in_error ; Input ; Info ; Stuck at GND ;; out_error ; Output ; Info ; Explicitly unconnected ;; in_channel ; Input ; Info ; Stuck at GND ;; out_channel ; Output ; Info ; Explicitly unconnected ;+-------------------+--------+----------+-----------------------------------------------------------------------------------------------------------------++-------------------------------------------------------------------------------------------------------------------------------------------------------+; Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rsp_fifo" ;+-------------------+--------+----------+---------------------------------------------------------------------------------------------------------------+; Port ; Type ; Severity ; Details ;+-------------------+--------+----------+---------------------------------------------------------------------------------------------------------------+; csr_address ; Input ; Info ; Stuck at GND ;; csr_read ; Input ; Info ; Stuck at GND ;; csr_write ; Input ; Info ; Stuck at GND ;; csr_readdata ; Output ; Info ; Explicitly unconnected ;; csr_writedata ; Input ; Info ; Stuck at GND ;; almost_full_data ; Output ; Info ; Explicitly unconnected ;; almost_empty_data ; Output ; Info ; Explicitly unconnected ;; in_empty ; Input ; Info ; Stuck at GND ;; out_empty ; Output ; Info ; Explicitly unconnected ;; in_error ; Input ; Info ; Stuck at GND ;; out_error ; Output ; Info ; Explicitly unconnected ;; in_channel ; Input ; Info ; Stuck at GND ;; out_channel ; Output ; Info ; Explicitly unconnected ;+-------------------+--------+----------+---------------------------------------------------------------------------------------------------------------++--------------------------------------------------------------------------------------------------------------------------------------------------+; Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:write_data_fifo_tx_s1_agent" ;+-----------------------+-------+----------+-------------------------------------------------------------------------------------------------------+; Port ; Type ; Severity ; Details ;+-----------------------+-------+----------+-------------------------------------------------------------------------------------------------------+; m0_response ; Input ; Info ; Stuck at GND ;; m0_writeresponsevalid ; Input ; Info ; Stuck at GND ;+-----------------------+-------+----------+-------------------------------------------------------------------------------------------------------++---------------------------------------------------------------------------------------------------------------------------------------------------+; Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo" ;+-------------------+--------+----------+-----------------------------------------------------------------------------------------------------------+; Port ; Type ; Severity ; Details ;+-------------------+--------+----------+-----------------------------------------------------------------------------------------------------------+; csr_address ; Input ; Info ; Stuck at GND ;; csr_read ; Input ; Info ; Stuck at GND ;; csr_write ; Input ; Info ; Stuck at GND ;; csr_readdata ; Output ; Info ; Explicitly unconnected ;; csr_writedata ; Input ; Info ; Stuck at GND ;; almost_full_data ; Output ; Info ; Explicitly unconnected ;; almost_empty_data ; Output ; Info ; Explicitly unconnected ;; in_startofpacket ; Input ; Info ; Stuck at GND ;; in_endofpacket ; Input ; Info ; Stuck at GND ;; out_startofpacket ; Output ; Info ; Explicitly unconnected ;; out_endofpacket ; Output ; Info ; Explicitly unconnected ;; in_empty ; Input ; Info ; Stuck at GND ;; out_empty ; Output ; Info ; Explicitly unconnected ;; in_error ; Input ; Info ; Stuck at GND ;; out_error ; Output ; Info ; Explicitly unconnected ;; in_channel ; Input ; Info ; Stuck at GND ;; out_channel ; Output ; Info ; Explicitly unconnected ;+-------------------+--------+----------+-----------------------------------------------------------------------------------------------------------++-------------------------------------------------------------------------------------------------------------------------------------------------+; Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rsp_fifo" ;+-------------------+--------+----------+---------------------------------------------------------------------------------------------------------+; Port ; Type ; Severity ; Details ;+-------------------+--------+----------+---------------------------------------------------------------------------------------------------------+; csr_address ; Input ; Info ; Stuck at GND ;; csr_read ; Input ; Info ; Stuck at GND ;; csr_write ; Input ; Info ; Stuck at GND ;; csr_readdata ; Output ; Info ; Explicitly unconnected ;; csr_writedata ; Input ; Info ; Stuck at GND ;; almost_full_data ; Output ; Info ; Explicitly unconnected ;; almost_empty_data ; Output ; Info ; Explicitly unconnected ;; in_empty ; Input ; Info ; Stuck at GND ;; out_empty ; Output ; Info ; Explicitly unconnected ;; in_error ; Input ; Info ; Stuck at GND ;; out_error ; Output ; Info ; Explicitly unconnected ;; in_channel ; Input ; Info ; Stuck at GND ;; out_channel ; Output ; Info ; Explicitly unconnected ;+-------------------+--------+----------+---------------------------------------------------------------------------------------------------------++--------------------------------------------------------------------------------------------------------------------------------------------+; Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:link_disable_s1_agent" ;+-----------------------+-------+----------+-------------------------------------------------------------------------------------------------+; Port ; Type ; Severity ; Details ;+-----------------------+-------+----------+-------------------------------------------------------------------------------------------------+; m0_response ; Input ; Info ; Stuck at GND ;; m0_writeresponsevalid ; Input ; Info ; Stuck at GND ;+-----------------------+-------+----------+-------------------------------------------------------------------------------------------------++-------------------------------------------------------------------------------------------------------------------------------------------------+; Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo" ;+-------------------+--------+----------+---------------------------------------------------------------------------------------------------------+; Port ; Type ; Severity ; Details ;+-------------------+--------+----------+---------------------------------------------------------------------------------------------------------+; csr_address ; Input ; Info ; Stuck at GND ;; csr_read ; Input ; Info ; Stuck at GND ;; csr_write ; Input ; Info ; Stuck at GND ;; csr_readdata ; Output ; Info ; Explicitly unconnected ;; csr_writedata ; Input ; Info ; Stuck at GND ;; almost_full_data ; Output ; Info ; Explicitly unconnected ;; almost_empty_data ; Output ; Info ; Explicitly unconnected ;; in_startofpacket ; Input ; Info ; Stuck at GND ;; in_endofpacket ; Input ; Info ; Stuck at GND ;; out_startofpacket ; Output ; Info ; Explicitly unconnected ;; out_endofpacket ; Output ; Info ; Explicitly unconnected ;; in_empty ; Input ; Info ; Stuck at GND ;; out_empty ; Output ; Info ; Explicitly unconnected ;; in_error ; Input ; Info ; Stuck at GND ;; out_error ; Output ; Info ; Explicitly unconnected ;; in_channel ; Input ; Info ; Stuck at GND ;; out_channel ; Output ; Info ; Explicitly unconnected ;+-------------------+--------+----------+---------------------------------------------------------------------------------------------------------++-----------------------------------------------------------------------------------------------------------------------------------------------+; Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rsp_fifo" ;+-------------------+--------+----------+-------------------------------------------------------------------------------------------------------+; Port ; Type ; Severity ; Details ;+-------------------+--------+----------+-------------------------------------------------------------------------------------------------------+; csr_address ; Input ; Info ; Stuck at GND ;; csr_read ; Input ; Info ; Stuck at GND ;; csr_write ; Input ; Info ; Stuck at GND ;; csr_readdata ; Output ; Info ; Explicitly unconnected ;; csr_writedata ; Input ; Info ; Stuck at GND ;; almost_full_data ; Output ; Info ; Explicitly unconnected ;; almost_empty_data ; Output ; Info ; Explicitly unconnected ;; in_empty ; Input ; Info ; Stuck at GND ;; out_empty ; Output ; Info ; Explicitly unconnected ;; in_error ; Input ; Info ; Stuck at GND ;; out_error ; Output ; Info ; Explicitly unconnected ;; in_channel ; Input ; Info ; Stuck at GND ;; out_channel ; Output ; Info ; Explicitly unconnected ;+-------------------+--------+----------+-------------------------------------------------------------------------------------------------------++------------------------------------------------------------------------------------------------------------------------------------------+; Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:auto_start_s1_agent" ;+-----------------------+-------+----------+-----------------------------------------------------------------------------------------------+; Port ; Type ; Severity ; Details ;+-----------------------+-------+----------+-----------------------------------------------------------------------------------------------+; m0_response ; Input ; Info ; Stuck at GND ;; m0_writeresponsevalid ; Input ; Info ; Stuck at GND ;+-----------------------+-------+----------+-----------------------------------------------------------------------------------------------++-------------------------------------------------------------------------------------------------------------------------------------------------+; Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo" ;+-------------------+--------+----------+---------------------------------------------------------------------------------------------------------+; Port ; Type ; Severity ; Details ;+-------------------+--------+----------+---------------------------------------------------------------------------------------------------------+; csr_address ; Input ; Info ; Stuck at GND ;; csr_read ; Input ; Info ; Stuck at GND ;; csr_write ; Input ; Info ; Stuck at GND ;; csr_readdata ; Output ; Info ; Explicitly unconnected ;; csr_writedata ; Input ; Info ; Stuck at GND ;; almost_full_data ; Output ; Info ; Explicitly unconnected ;; almost_empty_data ; Output ; Info ; Explicitly unconnected ;; in_startofpacket ; Input ; Info ; Stuck at GND ;; in_endofpacket ; Input ; Info ; Stuck at GND ;; out_startofpacket ; Output ; Info ; Explicitly unconnected ;; out_endofpacket ; Output ; Info ; Explicitly unconnected ;; in_empty ; Input ; Info ; Stuck at GND ;; out_empty ; Output ; Info ; Explicitly unconnected ;; in_error ; Input ; Info ; Stuck at GND ;; out_error ; Output ; Info ; Explicitly unconnected ;; in_channel ; Input ; Info ; Stuck at GND ;; out_channel ; Output ; Info ; Explicitly unconnected ;+-------------------+--------+----------+---------------------------------------------------------------------------------------------------------++-----------------------------------------------------------------------------------------------------------------------------------------------+; Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rsp_fifo" ;+-------------------+--------+----------+-------------------------------------------------------------------------------------------------------+; Port ; Type ; Severity ; Details ;+-------------------+--------+----------+-------------------------------------------------------------------------------------------------------+; csr_address ; Input ; Info ; Stuck at GND ;; csr_read ; Input ; Info ; Stuck at GND ;; csr_write ; Input ; Info ; Stuck at GND ;; csr_readdata ; Output ; Info ; Explicitly unconnected ;; csr_writedata ; Input ; Info ; Stuck at GND ;; almost_full_data ; Output ; Info ; Explicitly unconnected ;; almost_empty_data ; Output ; Info ; Explicitly unconnected ;; in_empty ; Input ; Info ; Stuck at GND ;; out_empty ; Output ; Info ; Explicitly unconnected ;; in_error ; Input ; Info ; Stuck at GND ;; out_error ; Output ; Info ; Explicitly unconnected ;; in_channel ; Input ; Info ; Stuck at GND ;; out_channel ; Output ; Info ; Explicitly unconnected ;+-------------------+--------+----------+-------------------------------------------------------------------------------------------------------++------------------------------------------------------------------------------------------------------------------------------------------+; Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:link_start_s1_agent" ;+-----------------------+-------+----------+-----------------------------------------------------------------------------------------------+; Port ; Type ; Severity ; Details ;+-----------------------+-------+----------+-----------------------------------------------------------------------------------------------+; m0_response ; Input ; Info ; Stuck at GND ;; m0_writeresponsevalid ; Input ; Info ; Stuck at GND ;+-----------------------+-------+----------+-----------------------------------------------------------------------------------------------++-----------------------------------------------------------------------------------------------------------------------------------------------------------+; Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo" ;+-------------------+--------+----------+-------------------------------------------------------------------------------------------------------------------+; Port ; Type ; Severity ; Details ;+-------------------+--------+----------+-------------------------------------------------------------------------------------------------------------------+; csr_address ; Input ; Info ; Stuck at GND ;; csr_read ; Input ; Info ; Stuck at GND ;; csr_write ; Input ; Info ; Stuck at GND ;; csr_readdata ; Output ; Info ; Explicitly unconnected ;; csr_writedata ; Input ; Info ; Stuck at GND ;; almost_full_data ; Output ; Info ; Explicitly unconnected ;; almost_empty_data ; Output ; Info ; Explicitly unconnected ;; in_startofpacket ; Input ; Info ; Stuck at GND ;; in_endofpacket ; Input ; Info ; Stuck at GND ;; out_startofpacket ; Output ; Info ; Explicitly unconnected ;; out_endofpacket ; Output ; Info ; Explicitly unconnected ;; in_empty ; Input ; Info ; Stuck at GND ;; out_empty ; Output ; Info ; Explicitly unconnected ;; in_error ; Input ; Info ; Stuck at GND ;; out_error ; Output ; Info ; Explicitly unconnected ;; in_channel ; Input ; Info ; Stuck at GND ;; out_channel ; Output ; Info ; Explicitly unconnected ;+-------------------+--------+----------+-------------------------------------------------------------------------------------------------------------------++---------------------------------------------------------------------------------------------------------------------------------------------------------+; Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rsp_fifo" ;+-------------------+--------+----------+-----------------------------------------------------------------------------------------------------------------+; Port ; Type ; Severity ; Details ;+-------------------+--------+----------+-----------------------------------------------------------------------------------------------------------------+; csr_address ; Input ; Info ; Stuck at GND ;; csr_read ; Input ; Info ; Stuck at GND ;; csr_write ; Input ; Info ; Stuck at GND ;; csr_readdata ; Output ; Info ; Explicitly unconnected ;; csr_writedata ; Input ; Info ; Stuck at GND ;; almost_full_data ; Output ; Info ; Explicitly unconnected ;; almost_empty_data ; Output ; Info ; Explicitly unconnected ;; in_empty ; Input ; Info ; Stuck at GND ;; out_empty ; Output ; Info ; Explicitly unconnected ;; in_error ; Input ; Info ; Stuck at GND ;; out_error ; Output ; Info ; Explicitly unconnected ;; in_channel ; Input ; Info ; Stuck at GND ;; out_channel ; Output ; Info ; Explicitly unconnected ;+-------------------+--------+----------+-----------------------------------------------------------------------------------------------------------------++----------------------------------------------------------------------------------------------------------------------------------------------------+; Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fifo_empty_rx_status_s1_agent" ;+-----------------------+-------+----------+---------------------------------------------------------------------------------------------------------+; Port ; Type ; Severity ; Details ;+-----------------------+-------+----------+---------------------------------------------------------------------------------------------------------+; m0_response ; Input ; Info ; Stuck at GND ;; m0_writeresponsevalid ; Input ; Info ; Stuck at GND ;+-----------------------+-------+----------+---------------------------------------------------------------------------------------------------------++----------------------------------------------------------------------------------------------------------------------------------------------------------+; Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo" ;+-------------------+--------+----------+------------------------------------------------------------------------------------------------------------------+; Port ; Type ; Severity ; Details ;+-------------------+--------+----------+------------------------------------------------------------------------------------------------------------------+; csr_address ; Input ; Info ; Stuck at GND ;; csr_read ; Input ; Info ; Stuck at GND ;; csr_write ; Input ; Info ; Stuck at GND ;; csr_readdata ; Output ; Info ; Explicitly unconnected ;; csr_writedata ; Input ; Info ; Stuck at GND ;; almost_full_data ; Output ; Info ; Explicitly unconnected ;; almost_empty_data ; Output ; Info ; Explicitly unconnected ;; in_startofpacket ; Input ; Info ; Stuck at GND ;; in_endofpacket ; Input ; Info ; Stuck at GND ;; out_startofpacket ; Output ; Info ; Explicitly unconnected ;; out_endofpacket ; Output ; Info ; Explicitly unconnected ;; in_empty ; Input ; Info ; Stuck at GND ;; out_empty ; Output ; Info ; Explicitly unconnected ;; in_error ; Input ; Info ; Stuck at GND ;; out_error ; Output ; Info ; Explicitly unconnected ;; in_channel ; Input ; Info ; Stuck at GND ;; out_channel ; Output ; Info ; Explicitly unconnected ;+-------------------+--------+----------+------------------------------------------------------------------------------------------------------------------++--------------------------------------------------------------------------------------------------------------------------------------------------------+; Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rsp_fifo" ;+-------------------+--------+----------+----------------------------------------------------------------------------------------------------------------+; Port ; Type ; Severity ; Details ;+-------------------+--------+----------+----------------------------------------------------------------------------------------------------------------+; csr_address ; Input ; Info ; Stuck at GND ;; csr_read ; Input ; Info ; Stuck at GND ;; csr_write ; Input ; Info ; Stuck at GND ;; csr_readdata ; Output ; Info ; Explicitly unconnected ;; csr_writedata ; Input ; Info ; Stuck at GND ;; almost_full_data ; Output ; Info ; Explicitly unconnected ;; almost_empty_data ; Output ; Info ; Explicitly unconnected ;; in_empty ; Input ; Info ; Stuck at GND ;; out_empty ; Output ; Info ; Explicitly unconnected ;; in_error ; Input ; Info ; Stuck at GND ;; out_error ; Output ; Info ; Explicitly unconnected ;; in_channel ; Input ; Info ; Stuck at GND ;; out_channel ; Output ; Info ; Explicitly unconnected ;+-------------------+--------+----------+----------------------------------------------------------------------------------------------------------------++---------------------------------------------------------------------------------------------------------------------------------------------------+; Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fifo_full_rx_status_s1_agent" ;+-----------------------+-------+----------+--------------------------------------------------------------------------------------------------------+; Port ; Type ; Severity ; Details ;+-----------------------+-------+----------+--------------------------------------------------------------------------------------------------------+; m0_response ; Input ; Info ; Stuck at GND ;; m0_writeresponsevalid ; Input ; Info ; Stuck at GND ;+-----------------------+-------+----------+--------------------------------------------------------------------------------------------------------++------------------------------------------------------------------------------------------------------------------------------------------------------+; Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo" ;+-------------------+--------+----------+--------------------------------------------------------------------------------------------------------------+; Port ; Type ; Severity ; Details ;+-------------------+--------+----------+--------------------------------------------------------------------------------------------------------------+; csr_address ; Input ; Info ; Stuck at GND ;; csr_read ; Input ; Info ; Stuck at GND ;; csr_write ; Input ; Info ; Stuck at GND ;; csr_readdata ; Output ; Info ; Explicitly unconnected ;; csr_writedata ; Input ; Info ; Stuck at GND ;; almost_full_data ; Output ; Info ; Explicitly unconnected ;; almost_empty_data ; Output ; Info ; Explicitly unconnected ;; in_startofpacket ; Input ; Info ; Stuck at GND ;; in_endofpacket ; Input ; Info ; Stuck at GND ;; out_startofpacket ; Output ; Info ; Explicitly unconnected ;; out_endofpacket ; Output ; Info ; Explicitly unconnected ;; in_empty ; Input ; Info ; Stuck at GND ;; out_empty ; Output ; Info ; Explicitly unconnected ;; in_error ; Input ; Info ; Stuck at GND ;; out_error ; Output ; Info ; Explicitly unconnected ;; in_channel ; Input ; Info ; Stuck at GND ;; out_channel ; Output ; Info ; Explicitly unconnected ;+-------------------+--------+----------+--------------------------------------------------------------------------------------------------------------++----------------------------------------------------------------------------------------------------------------------------------------------------+; Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rsp_fifo" ;+-------------------+--------+----------+------------------------------------------------------------------------------------------------------------+; Port ; Type ; Severity ; Details ;+-------------------+--------+----------+------------------------------------------------------------------------------------------------------------+; csr_address ; Input ; Info ; Stuck at GND ;; csr_read ; Input ; Info ; Stuck at GND ;; csr_write ; Input ; Info ; Stuck at GND ;; csr_readdata ; Output ; Info ; Explicitly unconnected ;; csr_writedata ; Input ; Info ; Stuck at GND ;; almost_full_data ; Output ; Info ; Explicitly unconnected ;; almost_empty_data ; Output ; Info ; Explicitly unconnected ;; in_empty ; Input ; Info ; Stuck at GND ;; out_empty ; Output ; Info ; Explicitly unconnected ;; in_error ; Input ; Info ; Stuck at GND ;; out_error ; Output ; Info ; Explicitly unconnected ;; in_channel ; Input ; Info ; Stuck at GND ;; out_channel ; Output ; Info ; Explicitly unconnected ;+-------------------+--------+----------+------------------------------------------------------------------------------------------------------------++-----------------------------------------------------------------------------------------------------------------------------------------------+; Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:data_read_en_rx_s1_agent" ;+-----------------------+-------+----------+----------------------------------------------------------------------------------------------------+; Port ; Type ; Severity ; Details ;+-----------------------+-------+----------+----------------------------------------------------------------------------------------------------+; m0_response ; Input ; Info ; Stuck at GND ;; m0_writeresponsevalid ; Input ; Info ; Stuck at GND ;+-----------------------+-------+----------+----------------------------------------------------------------------------------------------------++---------------------------------------------------------------------------------------------------------------------------------------------------+; Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo" ;+-------------------+--------+----------+-----------------------------------------------------------------------------------------------------------+; Port ; Type ; Severity ; Details ;+-------------------+--------+----------+-----------------------------------------------------------------------------------------------------------+; csr_address ; Input ; Info ; Stuck at GND ;; csr_read ; Input ; Info ; Stuck at GND ;; csr_write ; Input ; Info ; Stuck at GND ;; csr_readdata ; Output ; Info ; Explicitly unconnected ;; csr_writedata ; Input ; Info ; Stuck at GND ;; almost_full_data ; Output ; Info ; Explicitly unconnected ;; almost_empty_data ; Output ; Info ; Explicitly unconnected ;; in_startofpacket ; Input ; Info ; Stuck at GND ;; in_endofpacket ; Input ; Info ; Stuck at GND ;; out_startofpacket ; Output ; Info ; Explicitly unconnected ;; out_endofpacket ; Output ; Info ; Explicitly unconnected ;; in_empty ; Input ; Info ; Stuck at GND ;; out_empty ; Output ; Info ; Explicitly unconnected ;; in_error ; Input ; Info ; Stuck at GND ;; out_error ; Output ; Info ; Explicitly unconnected ;; in_channel ; Input ; Info ; Stuck at GND ;; out_channel ; Output ; Info ; Explicitly unconnected ;+-------------------+--------+----------+-----------------------------------------------------------------------------------------------------------++-------------------------------------------------------------------------------------------------------------------------------------------------+; Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rsp_fifo" ;+-------------------+--------+----------+---------------------------------------------------------------------------------------------------------+; Port ; Type ; Severity ; Details ;+-------------------+--------+----------+---------------------------------------------------------------------------------------------------------+; csr_address ; Input ; Info ; Stuck at GND ;; csr_read ; Input ; Info ; Stuck at GND ;; csr_write ; Input ; Info ; Stuck at GND ;; csr_readdata ; Output ; Info ; Explicitly unconnected ;; csr_writedata ; Input ; Info ; Stuck at GND ;; almost_full_data ; Output ; Info ; Explicitly unconnected ;; almost_empty_data ; Output ; Info ; Explicitly unconnected ;; in_empty ; Input ; Info ; Stuck at GND ;; out_empty ; Output ; Info ; Explicitly unconnected ;; in_error ; Input ; Info ; Stuck at GND ;; out_error ; Output ; Info ; Explicitly unconnected ;; in_channel ; Input ; Info ; Stuck at GND ;; out_channel ; Output ; Info ; Explicitly unconnected ;+-------------------+--------+----------+---------------------------------------------------------------------------------------------------------++--------------------------------------------------------------------------------------------------------------------------------------------+; Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:data_flag_rx_s1_agent" ;+-----------------------+-------+----------+-------------------------------------------------------------------------------------------------+; Port ; Type ; Severity ; Details ;+-----------------------+-------+----------+-------------------------------------------------------------------------------------------------+; m0_response ; Input ; Info ; Stuck at GND ;; m0_writeresponsevalid ; Input ; Info ; Stuck at GND ;+-----------------------+-------+----------+-------------------------------------------------------------------------------------------------++--------------------------------------------------------------------------------------------------------------------------------------------------------+; Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo" ;+-------------------+--------+----------+----------------------------------------------------------------------------------------------------------------+; Port ; Type ; Severity ; Details ;+-------------------+--------+----------+----------------------------------------------------------------------------------------------------------------+; csr_address ; Input ; Info ; Stuck at GND ;; csr_read ; Input ; Info ; Stuck at GND ;; csr_write ; Input ; Info ; Stuck at GND ;; csr_readdata ; Output ; Info ; Explicitly unconnected ;; csr_writedata ; Input ; Info ; Stuck at GND ;; almost_full_data ; Output ; Info ; Explicitly unconnected ;; almost_empty_data ; Output ; Info ; Explicitly unconnected ;; in_startofpacket ; Input ; Info ; Stuck at GND ;; in_endofpacket ; Input ; Info ; Stuck at GND ;; out_startofpacket ; Output ; Info ; Explicitly unconnected ;; out_endofpacket ; Output ; Info ; Explicitly unconnected ;; in_empty ; Input ; Info ; Stuck at GND ;; out_empty ; Output ; Info ; Explicitly unconnected ;; in_error ; Input ; Info ; Stuck at GND ;; out_error ; Output ; Info ; Explicitly unconnected ;; in_channel ; Input ; Info ; Stuck at GND ;; out_channel ; Output ; Info ; Explicitly unconnected ;+-------------------+--------+----------+----------------------------------------------------------------------------------------------------------------++------------------------------------------------------------------------------------------------------------------------------------------------------+; Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rsp_fifo" ;+-------------------+--------+----------+--------------------------------------------------------------------------------------------------------------+; Port ; Type ; Severity ; Details ;+-------------------+--------+----------+--------------------------------------------------------------------------------------------------------------+; csr_address ; Input ; Info ; Stuck at GND ;; csr_read ; Input ; Info ; Stuck at GND ;; csr_write ; Input ; Info ; Stuck at GND ;; csr_readdata ; Output ; Info ; Explicitly unconnected ;; csr_writedata ; Input ; Info ; Stuck at GND ;; almost_full_data ; Output ; Info ; Explicitly unconnected ;; almost_empty_data ; Output ; Info ; Explicitly unconnected ;; in_empty ; Input ; Info ; Stuck at GND ;; out_empty ; Output ; Info ; Explicitly unconnected ;; in_error ; Input ; Info ; Stuck at GND ;; out_error ; Output ; Info ; Explicitly unconnected ;; in_channel ; Input ; Info ; Stuck at GND ;; out_channel ; Output ; Info ; Explicitly unconnected ;+-------------------+--------+----------+--------------------------------------------------------------------------------------------------------------++-------------------------------------------------------------------------------------------------------------------------------------------------+; Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_ready_rx_s1_agent" ;+-----------------------+-------+----------+------------------------------------------------------------------------------------------------------+; Port ; Type ; Severity ; Details ;+-----------------------+-------+----------+------------------------------------------------------------------------------------------------------+; m0_response ; Input ; Info ; Stuck at GND ;; m0_writeresponsevalid ; Input ; Info ; Stuck at GND ;+-----------------------+-------+----------+------------------------------------------------------------------------------------------------------++--------------------------------------------------------------------------------------------------------------------------------------------------+; Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rdata_fifo" ;+-------------------+--------+----------+----------------------------------------------------------------------------------------------------------+; Port ; Type ; Severity ; Details ;+-------------------+--------+----------+----------------------------------------------------------------------------------------------------------+; csr_address ; Input ; Info ; Stuck at GND ;; csr_read ; Input ; Info ; Stuck at GND ;; csr_write ; Input ; Info ; Stuck at GND ;; csr_readdata ; Output ; Info ; Explicitly unconnected ;; csr_writedata ; Input ; Info ; Stuck at GND ;; almost_full_data ; Output ; Info ; Explicitly unconnected ;; almost_empty_data ; Output ; Info ; Explicitly unconnected ;; in_startofpacket ; Input ; Info ; Stuck at GND ;; in_endofpacket ; Input ; Info ; Stuck at GND ;; out_startofpacket ; Output ; Info ; Explicitly unconnected ;; out_endofpacket ; Output ; Info ; Explicitly unconnected ;; in_empty ; Input ; Info ; Stuck at GND ;; out_empty ; Output ; Info ; Explicitly unconnected ;; in_error ; Input ; Info ; Stuck at GND ;; out_error ; Output ; Info ; Explicitly unconnected ;; in_channel ; Input ; Info ; Stuck at GND ;; out_channel ; Output ; Info ; Explicitly unconnected ;+-------------------+--------+----------+----------------------------------------------------------------------------------------------------------++------------------------------------------------------------------------------------------------------------------------------------------------+; Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rsp_fifo" ;+-------------------+--------+----------+--------------------------------------------------------------------------------------------------------+; Port ; Type ; Severity ; Details ;+-------------------+--------+----------+--------------------------------------------------------------------------------------------------------+; csr_address ; Input ; Info ; Stuck at GND ;; csr_read ; Input ; Info ; Stuck at GND ;; csr_write ; Input ; Info ; Stuck at GND ;; csr_readdata ; Output ; Info ; Explicitly unconnected ;; csr_writedata ; Input ; Info ; Stuck at GND ;; almost_full_data ; Output ; Info ; Explicitly unconnected ;; almost_empty_data ; Output ; Info ; Explicitly unconnected ;; in_empty ; Input ; Info ; Stuck at GND ;; out_empty ; Output ; Info ; Explicitly unconnected ;; in_error ; Input ; Info ; Stuck at GND ;; out_error ; Output ; Info ; Explicitly unconnected ;; in_channel ; Input ; Info ; Stuck at GND ;; out_channel ; Output ; Info ; Explicitly unconnected ;+-------------------+--------+----------+--------------------------------------------------------------------------------------------------------++-------------------------------------------------------------------------------------------------------------------------------------------+; Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_rx_s1_agent" ;+-----------------------+-------+----------+------------------------------------------------------------------------------------------------+; Port ; Type ; Severity ; Details ;+-----------------------+-------+----------+------------------------------------------------------------------------------------------------+; m0_response ; Input ; Info ; Stuck at GND ;; m0_writeresponsevalid ; Input ; Info ; Stuck at GND ;+-----------------------+-------+----------+------------------------------------------------------------------------------------------------++---------------------------------------------------------------------------------------------------------------------------------------------------+; Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo" ;+-------------------+--------+----------+-----------------------------------------------------------------------------------------------------------+; Port ; Type ; Severity ; Details ;+-------------------+--------+----------+-----------------------------------------------------------------------------------------------------------+; csr_address ; Input ; Info ; Stuck at GND ;; csr_read ; Input ; Info ; Stuck at GND ;; csr_write ; Input ; Info ; Stuck at GND ;; csr_readdata ; Output ; Info ; Explicitly unconnected ;; csr_writedata ; Input ; Info ; Stuck at GND ;; almost_full_data ; Output ; Info ; Explicitly unconnected ;; almost_empty_data ; Output ; Info ; Explicitly unconnected ;; in_startofpacket ; Input ; Info ; Stuck at GND ;; in_endofpacket ; Input ; Info ; Stuck at GND ;; out_startofpacket ; Output ; Info ; Explicitly unconnected ;; out_endofpacket ; Output ; Info ; Explicitly unconnected ;; in_empty ; Input ; Info ; Stuck at GND ;; out_empty ; Output ; Info ; Explicitly unconnected ;; in_error ; Input ; Info ; Stuck at GND ;; out_error ; Output ; Info ; Explicitly unconnected ;; in_channel ; Input ; Info ; Stuck at GND ;; out_channel ; Output ; Info ; Explicitly unconnected ;+-------------------+--------+----------+-----------------------------------------------------------------------------------------------------------++-------------------------------------------------------------------------------------------------------------------------------------------------+; Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rsp_fifo" ;+-------------------+--------+----------+---------------------------------------------------------------------------------------------------------+; Port ; Type ; Severity ; Details ;+-------------------+--------+----------+---------------------------------------------------------------------------------------------------------+; csr_address ; Input ; Info ; Stuck at GND ;; csr_read ; Input ; Info ; Stuck at GND ;; csr_write ; Input ; Info ; Stuck at GND ;; csr_readdata ; Output ; Info ; Explicitly unconnected ;; csr_writedata ; Input ; Info ; Stuck at GND ;; almost_full_data ; Output ; Info ; Explicitly unconnected ;; almost_empty_data ; Output ; Info ; Explicitly unconnected ;; in_empty ; Input ; Info ; Stuck at GND ;; out_empty ; Output ; Info ; Explicitly unconnected ;; in_error ; Input ; Info ; Stuck at GND ;; out_error ; Output ; Info ; Explicitly unconnected ;; in_channel ; Input ; Info ; Stuck at GND ;; out_channel ; Output ; Info ; Explicitly unconnected ;+-------------------+--------+----------+---------------------------------------------------------------------------------------------------------++--------------------------------------------------------------------------------------------------------------------------------------------+; Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:led_pio_test_s1_agent" ;+-----------------------+-------+----------+-------------------------------------------------------------------------------------------------+; Port ; Type ; Severity ; Details ;+-----------------------+-------+----------+-------------------------------------------------------------------------------------------------+; m0_response ; Input ; Info ; Stuck at GND ;; m0_writeresponsevalid ; Input ; Info ; Stuck at GND ;+-----------------------+-------+----------+-------------------------------------------------------------------------------------------------++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_axi_master_ni:hps_0_h2f_axi_master_agent|altera_merlin_address_alignment:align_address_to_size" ;+------------------+--------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Port ; Type ; Severity ; Details ;+------------------+--------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------+; out_data[31..30] ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;+------------------+--------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------++---------------------------------------------------------------------------------------------------------------------------------------------------+; Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_axi_master_ni:hps_0_h2f_axi_master_agent" ;+----------+--------+----------+--------------------------------------------------------------------------------------------------------------------+; Port ; Type ; Severity ; Details ;+----------+--------+----------+--------------------------------------------------------------------------------------------------------------------+; awuser ; Input ; Info ; Stuck at GND ;; aruser ; Input ; Info ; Stuck at GND ;; awqos ; Input ; Info ; Stuck at GND ;; arqos ; Input ; Info ; Stuck at GND ;; awregion ; Input ; Info ; Stuck at GND ;; arregion ; Input ; Info ; Stuck at GND ;; wuser ; Input ; Info ; Stuck at GND ;; ruser ; Output ; Info ; Explicitly unconnected ;; buser ; Output ; Info ; Explicitly unconnected ;+----------+--------+----------+--------------------------------------------------------------------------------------------------------------------++---------------------------------------------------------------------------------------------------------------------------------------------------------+; Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:counter_rx_fifo_s1_translator" ;+------------------------+--------+----------+------------------------------------------------------------------------------------------------------------+; Port ; Type ; Severity ; Details ;+------------------------+--------+----------+------------------------------------------------------------------------------------------------------------+; av_write ; Output ; Info ; Explicitly unconnected ;; av_read ; Output ; Info ; Explicitly unconnected ;; av_writedata ; Output ; Info ; Explicitly unconnected ;; av_begintransfer ; Output ; Info ; Explicitly unconnected ;; av_beginbursttransfer ; Output ; Info ; Explicitly unconnected ;; av_burstcount ; Output ; Info ; Explicitly unconnected ;; av_byteenable ; Output ; Info ; Explicitly unconnected ;; av_readdatavalid ; Input ; Info ; Stuck at GND ;; av_waitrequest ; Input ; Info ; Stuck at GND ;; av_writebyteenable ; Output ; Info ; Explicitly unconnected ;; av_lock ; Output ; Info ; Explicitly unconnected ;; av_chipselect ; Output ; Info ; Explicitly unconnected ;; av_clken ; Output ; Info ; Explicitly unconnected ;; uav_clken ; Input ; Info ; Stuck at GND ;; av_debugaccess ; Output ; Info ; Explicitly unconnected ;; av_outputenable ; Output ; Info ; Explicitly unconnected ;; uav_response ; Output ; Info ; Explicitly unconnected ;; av_response ; Input ; Info ; Stuck at GND ;; uav_writeresponsevalid ; Output ; Info ; Explicitly unconnected ;; av_writeresponsevalid ; Input ; Info ; Stuck at GND ;+------------------------+--------+----------+------------------------------------------------------------------------------------------------------------++---------------------------------------------------------------------------------------------------------------------------------------------------------+; Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:counter_tx_fifo_s1_translator" ;+------------------------+--------+----------+------------------------------------------------------------------------------------------------------------+; Port ; Type ; Severity ; Details ;+------------------------+--------+----------+------------------------------------------------------------------------------------------------------------+; av_write ; Output ; Info ; Explicitly unconnected ;; av_read ; Output ; Info ; Explicitly unconnected ;; av_writedata ; Output ; Info ; Explicitly unconnected ;; av_begintransfer ; Output ; Info ; Explicitly unconnected ;; av_beginbursttransfer ; Output ; Info ; Explicitly unconnected ;; av_burstcount ; Output ; Info ; Explicitly unconnected ;; av_byteenable ; Output ; Info ; Explicitly unconnected ;; av_readdatavalid ; Input ; Info ; Stuck at GND ;; av_waitrequest ; Input ; Info ; Stuck at GND ;; av_writebyteenable ; Output ; Info ; Explicitly unconnected ;; av_lock ; Output ; Info ; Explicitly unconnected ;; av_chipselect ; Output ; Info ; Explicitly unconnected ;; av_clken ; Output ; Info ; Explicitly unconnected ;; uav_clken ; Input ; Info ; Stuck at GND ;; av_debugaccess ; Output ; Info ; Explicitly unconnected ;; av_outputenable ; Output ; Info ; Explicitly unconnected ;; uav_response ; Output ; Info ; Explicitly unconnected ;; av_response ; Input ; Info ; Stuck at GND ;; uav_writeresponsevalid ; Output ; Info ; Explicitly unconnected ;; av_writeresponsevalid ; Input ; Info ; Stuck at GND ;+------------------------+--------+----------+------------------------------------------------------------------------------------------------------------++--------------------------------------------------------------------------------------------------------------------------------------------------+; Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fsm_info_s1_translator" ;+------------------------+--------+----------+-----------------------------------------------------------------------------------------------------+; Port ; Type ; Severity ; Details ;+------------------------+--------+----------+-----------------------------------------------------------------------------------------------------+; av_write ; Output ; Info ; Explicitly unconnected ;; av_read ; Output ; Info ; Explicitly unconnected ;; av_writedata ; Output ; Info ; Explicitly unconnected ;; av_begintransfer ; Output ; Info ; Explicitly unconnected ;; av_beginbursttransfer ; Output ; Info ; Explicitly unconnected ;; av_burstcount ; Output ; Info ; Explicitly unconnected ;; av_byteenable ; Output ; Info ; Explicitly unconnected ;; av_readdatavalid ; Input ; Info ; Stuck at GND ;; av_waitrequest ; Input ; Info ; Stuck at GND ;; av_writebyteenable ; Output ; Info ; Explicitly unconnected ;; av_lock ; Output ; Info ; Explicitly unconnected ;; av_chipselect ; Output ; Info ; Explicitly unconnected ;; av_clken ; Output ; Info ; Explicitly unconnected ;; uav_clken ; Input ; Info ; Stuck at GND ;; av_debugaccess ; Output ; Info ; Explicitly unconnected ;; av_outputenable ; Output ; Info ; Explicitly unconnected ;; uav_response ; Output ; Info ; Explicitly unconnected ;; av_response ; Input ; Info ; Stuck at GND ;; uav_writeresponsevalid ; Output ; Info ; Explicitly unconnected ;; av_writeresponsevalid ; Input ; Info ; Stuck at GND ;+------------------------+--------+----------+-----------------------------------------------------------------------------------------------------++---------------------------------------------------------------------------------------------------------------------------------------------------+; Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:clock_sel_s1_translator" ;+------------------------+--------+----------+------------------------------------------------------------------------------------------------------+; Port ; Type ; Severity ; Details ;+------------------------+--------+----------+------------------------------------------------------------------------------------------------------+; av_read ; Output ; Info ; Explicitly unconnected ;; av_begintransfer ; Output ; Info ; Explicitly unconnected ;; av_beginbursttransfer ; Output ; Info ; Explicitly unconnected ;; av_burstcount ; Output ; Info ; Explicitly unconnected ;; av_byteenable ; Output ; Info ; Explicitly unconnected ;; av_readdatavalid ; Input ; Info ; Stuck at GND ;; av_waitrequest ; Input ; Info ; Stuck at GND ;; av_writebyteenable ; Output ; Info ; Explicitly unconnected ;; av_lock ; Output ; Info ; Explicitly unconnected ;; av_clken ; Output ; Info ; Explicitly unconnected ;; uav_clken ; Input ; Info ; Stuck at GND ;; av_debugaccess ; Output ; Info ; Explicitly unconnected ;; av_outputenable ; Output ; Info ; Explicitly unconnected ;; uav_response ; Output ; Info ; Explicitly unconnected ;; av_response ; Input ; Info ; Stuck at GND ;; uav_writeresponsevalid ; Output ; Info ; Explicitly unconnected ;; av_writeresponsevalid ; Input ; Info ; Stuck at GND ;+------------------------+--------+----------+------------------------------------------------------------------------------------------------------++---------------------------------------------------------------------------------------------------------------------------------------------------+; Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:data_info_s1_translator" ;+------------------------+--------+----------+------------------------------------------------------------------------------------------------------+; Port ; Type ; Severity ; Details ;+------------------------+--------+----------+------------------------------------------------------------------------------------------------------+; av_write ; Output ; Info ; Explicitly unconnected ;; av_read ; Output ; Info ; Explicitly unconnected ;; av_writedata ; Output ; Info ; Explicitly unconnected ;; av_begintransfer ; Output ; Info ; Explicitly unconnected ;; av_beginbursttransfer ; Output ; Info ; Explicitly unconnected ;; av_burstcount ; Output ; Info ; Explicitly unconnected ;; av_byteenable ; Output ; Info ; Explicitly unconnected ;; av_readdatavalid ; Input ; Info ; Stuck at GND ;; av_waitrequest ; Input ; Info ; Stuck at GND ;; av_writebyteenable ; Output ; Info ; Explicitly unconnected ;; av_lock ; Output ; Info ; Explicitly unconnected ;; av_chipselect ; Output ; Info ; Explicitly unconnected ;; av_clken ; Output ; Info ; Explicitly unconnected ;; uav_clken ; Input ; Info ; Stuck at GND ;; av_debugaccess ; Output ; Info ; Explicitly unconnected ;; av_outputenable ; Output ; Info ; Explicitly unconnected ;; uav_response ; Output ; Info ; Explicitly unconnected ;; av_response ; Input ; Info ; Stuck at GND ;; uav_writeresponsevalid ; Output ; Info ; Explicitly unconnected ;; av_writeresponsevalid ; Input ; Info ; Stuck at GND ;+------------------------+--------+----------+------------------------------------------------------------------------------------------------------++-----------------------------------------------------------------------------------------------------------------------------------------------------------+; Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_ready_s1_translator" ;+------------------------+--------+----------+--------------------------------------------------------------------------------------------------------------+; Port ; Type ; Severity ; Details ;+------------------------+--------+----------+--------------------------------------------------------------------------------------------------------------+; av_write ; Output ; Info ; Explicitly unconnected ;; av_read ; Output ; Info ; Explicitly unconnected ;; av_writedata ; Output ; Info ; Explicitly unconnected ;; av_begintransfer ; Output ; Info ; Explicitly unconnected ;; av_beginbursttransfer ; Output ; Info ; Explicitly unconnected ;; av_burstcount ; Output ; Info ; Explicitly unconnected ;; av_byteenable ; Output ; Info ; Explicitly unconnected ;; av_readdatavalid ; Input ; Info ; Stuck at GND ;; av_waitrequest ; Input ; Info ; Stuck at GND ;; av_writebyteenable ; Output ; Info ; Explicitly unconnected ;; av_lock ; Output ; Info ; Explicitly unconnected ;; av_chipselect ; Output ; Info ; Explicitly unconnected ;; av_clken ; Output ; Info ; Explicitly unconnected ;; uav_clken ; Input ; Info ; Stuck at GND ;; av_debugaccess ; Output ; Info ; Explicitly unconnected ;; av_outputenable ; Output ; Info ; Explicitly unconnected ;; uav_response ; Output ; Info ; Explicitly unconnected ;; av_response ; Input ; Info ; Stuck at GND ;; uav_writeresponsevalid ; Output ; Info ; Explicitly unconnected ;; av_writeresponsevalid ; Input ; Info ; Stuck at GND ;+------------------------+--------+----------+--------------------------------------------------------------------------------------------------------------++------------------------------------------------------------------------------------------------------------------------------------------------------------+; Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_enable_s1_translator" ;+------------------------+--------+----------+---------------------------------------------------------------------------------------------------------------+; Port ; Type ; Severity ; Details ;+------------------------+--------+----------+---------------------------------------------------------------------------------------------------------------+; av_read ; Output ; Info ; Explicitly unconnected ;; av_begintransfer ; Output ; Info ; Explicitly unconnected ;; av_beginbursttransfer ; Output ; Info ; Explicitly unconnected ;; av_burstcount ; Output ; Info ; Explicitly unconnected ;; av_byteenable ; Output ; Info ; Explicitly unconnected ;; av_readdatavalid ; Input ; Info ; Stuck at GND ;; av_waitrequest ; Input ; Info ; Stuck at GND ;; av_writebyteenable ; Output ; Info ; Explicitly unconnected ;; av_lock ; Output ; Info ; Explicitly unconnected ;; av_clken ; Output ; Info ; Explicitly unconnected ;; uav_clken ; Input ; Info ; Stuck at GND ;; av_debugaccess ; Output ; Info ; Explicitly unconnected ;; av_outputenable ; Output ; Info ; Explicitly unconnected ;; uav_response ; Output ; Info ; Explicitly unconnected ;; av_response ; Input ; Info ; Stuck at GND ;; uav_writeresponsevalid ; Output ; Info ; Explicitly unconnected ;; av_writeresponsevalid ; Input ; Info ; Stuck at GND ;+------------------------+--------+----------+---------------------------------------------------------------------------------------------------------------++----------------------------------------------------------------------------------------------------------------------------------------------------------+; Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_data_s1_translator" ;+------------------------+--------+----------+-------------------------------------------------------------------------------------------------------------+; Port ; Type ; Severity ; Details ;+------------------------+--------+----------+-------------------------------------------------------------------------------------------------------------+; av_read ; Output ; Info ; Explicitly unconnected ;; av_begintransfer ; Output ; Info ; Explicitly unconnected ;; av_beginbursttransfer ; Output ; Info ; Explicitly unconnected ;; av_burstcount ; Output ; Info ; Explicitly unconnected ;; av_byteenable ; Output ; Info ; Explicitly unconnected ;; av_readdatavalid ; Input ; Info ; Stuck at GND ;; av_waitrequest ; Input ; Info ; Stuck at GND ;; av_writebyteenable ; Output ; Info ; Explicitly unconnected ;; av_lock ; Output ; Info ; Explicitly unconnected ;; av_clken ; Output ; Info ; Explicitly unconnected ;; uav_clken ; Input ; Info ; Stuck at GND ;; av_debugaccess ; Output ; Info ; Explicitly unconnected ;; av_outputenable ; Output ; Info ; Explicitly unconnected ;; uav_response ; Output ; Info ; Explicitly unconnected ;; av_response ; Input ; Info ; Stuck at GND ;; uav_writeresponsevalid ; Output ; Info ; Explicitly unconnected ;; av_writeresponsevalid ; Input ; Info ; Stuck at GND ;+------------------------+--------+----------+-------------------------------------------------------------------------------------------------------------++--------------------------------------------------------------------------------------------------------------------------------------------------------------+; Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_empty_tx_status_s1_translator" ;+------------------------+--------+----------+-----------------------------------------------------------------------------------------------------------------+; Port ; Type ; Severity ; Details ;+------------------------+--------+----------+-----------------------------------------------------------------------------------------------------------------+; av_write ; Output ; Info ; Explicitly unconnected ;; av_read ; Output ; Info ; Explicitly unconnected ;; av_writedata ; Output ; Info ; Explicitly unconnected ;; av_begintransfer ; Output ; Info ; Explicitly unconnected ;; av_beginbursttransfer ; Output ; Info ; Explicitly unconnected ;; av_burstcount ; Output ; Info ; Explicitly unconnected ;; av_byteenable ; Output ; Info ; Explicitly unconnected ;; av_readdatavalid ; Input ; Info ; Stuck at GND ;; av_waitrequest ; Input ; Info ; Stuck at GND ;; av_writebyteenable ; Output ; Info ; Explicitly unconnected ;; av_lock ; Output ; Info ; Explicitly unconnected ;; av_chipselect ; Output ; Info ; Explicitly unconnected ;; av_clken ; Output ; Info ; Explicitly unconnected ;; uav_clken ; Input ; Info ; Stuck at GND ;; av_debugaccess ; Output ; Info ; Explicitly unconnected ;; av_outputenable ; Output ; Info ; Explicitly unconnected ;; uav_response ; Output ; Info ; Explicitly unconnected ;; av_response ; Input ; Info ; Stuck at GND ;; uav_writeresponsevalid ; Output ; Info ; Explicitly unconnected ;; av_writeresponsevalid ; Input ; Info ; Stuck at GND ;+------------------------+--------+----------+-----------------------------------------------------------------------------------------------------------------++-------------------------------------------------------------------------------------------------------------------------------------------------------------+; Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_full_tx_status_s1_translator" ;+------------------------+--------+----------+----------------------------------------------------------------------------------------------------------------+; Port ; Type ; Severity ; Details ;+------------------------+--------+----------+----------------------------------------------------------------------------------------------------------------+; av_write ; Output ; Info ; Explicitly unconnected ;; av_read ; Output ; Info ; Explicitly unconnected ;; av_writedata ; Output ; Info ; Explicitly unconnected ;; av_begintransfer ; Output ; Info ; Explicitly unconnected ;; av_beginbursttransfer ; Output ; Info ; Explicitly unconnected ;; av_burstcount ; Output ; Info ; Explicitly unconnected ;; av_byteenable ; Output ; Info ; Explicitly unconnected ;; av_readdatavalid ; Input ; Info ; Stuck at GND ;; av_waitrequest ; Input ; Info ; Stuck at GND ;; av_writebyteenable ; Output ; Info ; Explicitly unconnected ;; av_lock ; Output ; Info ; Explicitly unconnected ;; av_chipselect ; Output ; Info ; Explicitly unconnected ;; av_clken ; Output ; Info ; Explicitly unconnected ;; uav_clken ; Input ; Info ; Stuck at GND ;; av_debugaccess ; Output ; Info ; Explicitly unconnected ;; av_outputenable ; Output ; Info ; Explicitly unconnected ;; uav_response ; Output ; Info ; Explicitly unconnected ;; av_response ; Input ; Info ; Stuck at GND ;; uav_writeresponsevalid ; Output ; Info ; Explicitly unconnected ;; av_writeresponsevalid ; Input ; Info ; Stuck at GND ;+------------------------+--------+----------+----------------------------------------------------------------------------------------------------------------++-----------------------------------------------------------------------------------------------------------------------------------------------------+; Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:write_en_tx_s1_translator" ;+------------------------+--------+----------+--------------------------------------------------------------------------------------------------------+; Port ; Type ; Severity ; Details ;+------------------------+--------+----------+--------------------------------------------------------------------------------------------------------+; av_read ; Output ; Info ; Explicitly unconnected ;; av_begintransfer ; Output ; Info ; Explicitly unconnected ;; av_beginbursttransfer ; Output ; Info ; Explicitly unconnected ;; av_burstcount ; Output ; Info ; Explicitly unconnected ;; av_byteenable ; Output ; Info ; Explicitly unconnected ;; av_readdatavalid ; Input ; Info ; Stuck at GND ;; av_waitrequest ; Input ; Info ; Stuck at GND ;; av_writebyteenable ; Output ; Info ; Explicitly unconnected ;; av_lock ; Output ; Info ; Explicitly unconnected ;; av_clken ; Output ; Info ; Explicitly unconnected ;; uav_clken ; Input ; Info ; Stuck at GND ;; av_debugaccess ; Output ; Info ; Explicitly unconnected ;; av_outputenable ; Output ; Info ; Explicitly unconnected ;; uav_response ; Output ; Info ; Explicitly unconnected ;; av_response ; Input ; Info ; Stuck at GND ;; uav_writeresponsevalid ; Output ; Info ; Explicitly unconnected ;; av_writeresponsevalid ; Input ; Info ; Stuck at GND ;+------------------------+--------+----------+--------------------------------------------------------------------------------------------------------++------------------------------------------------------------------------------------------------------------------------------------------------------------+; Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:write_data_fifo_tx_s1_translator" ;+------------------------+--------+----------+---------------------------------------------------------------------------------------------------------------+; Port ; Type ; Severity ; Details ;+------------------------+--------+----------+---------------------------------------------------------------------------------------------------------------+; av_read ; Output ; Info ; Explicitly unconnected ;; av_begintransfer ; Output ; Info ; Explicitly unconnected ;; av_beginbursttransfer ; Output ; Info ; Explicitly unconnected ;; av_burstcount ; Output ; Info ; Explicitly unconnected ;; av_byteenable ; Output ; Info ; Explicitly unconnected ;; av_readdatavalid ; Input ; Info ; Stuck at GND ;; av_waitrequest ; Input ; Info ; Stuck at GND ;; av_writebyteenable ; Output ; Info ; Explicitly unconnected ;; av_lock ; Output ; Info ; Explicitly unconnected ;; av_clken ; Output ; Info ; Explicitly unconnected ;; uav_clken ; Input ; Info ; Stuck at GND ;; av_debugaccess ; Output ; Info ; Explicitly unconnected ;; av_outputenable ; Output ; Info ; Explicitly unconnected ;; uav_response ; Output ; Info ; Explicitly unconnected ;; av_response ; Input ; Info ; Stuck at GND ;; uav_writeresponsevalid ; Output ; Info ; Explicitly unconnected ;; av_writeresponsevalid ; Input ; Info ; Stuck at GND ;+------------------------+--------+----------+---------------------------------------------------------------------------------------------------------------++------------------------------------------------------------------------------------------------------------------------------------------------------+; Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:link_disable_s1_translator" ;+------------------------+--------+----------+---------------------------------------------------------------------------------------------------------+; Port ; Type ; Severity ; Details ;+------------------------+--------+----------+---------------------------------------------------------------------------------------------------------+; av_read ; Output ; Info ; Explicitly unconnected ;; av_begintransfer ; Output ; Info ; Explicitly unconnected ;; av_beginbursttransfer ; Output ; Info ; Explicitly unconnected ;; av_burstcount ; Output ; Info ; Explicitly unconnected ;; av_byteenable ; Output ; Info ; Explicitly unconnected ;; av_readdatavalid ; Input ; Info ; Stuck at GND ;; av_waitrequest ; Input ; Info ; Stuck at GND ;; av_writebyteenable ; Output ; Info ; Explicitly unconnected ;; av_lock ; Output ; Info ; Explicitly unconnected ;; av_clken ; Output ; Info ; Explicitly unconnected ;; uav_clken ; Input ; Info ; Stuck at GND ;; av_debugaccess ; Output ; Info ; Explicitly unconnected ;; av_outputenable ; Output ; Info ; Explicitly unconnected ;; uav_response ; Output ; Info ; Explicitly unconnected ;; av_response ; Input ; Info ; Stuck at GND ;; uav_writeresponsevalid ; Output ; Info ; Explicitly unconnected ;; av_writeresponsevalid ; Input ; Info ; Stuck at GND ;+------------------------+--------+----------+---------------------------------------------------------------------------------------------------------++----------------------------------------------------------------------------------------------------------------------------------------------------+; Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:auto_start_s1_translator" ;+------------------------+--------+----------+-------------------------------------------------------------------------------------------------------+; Port ; Type ; Severity ; Details ;+------------------------+--------+----------+-------------------------------------------------------------------------------------------------------+; av_read ; Output ; Info ; Explicitly unconnected ;; av_begintransfer ; Output ; Info ; Explicitly unconnected ;; av_beginbursttransfer ; Output ; Info ; Explicitly unconnected ;; av_burstcount ; Output ; Info ; Explicitly unconnected ;; av_byteenable ; Output ; Info ; Explicitly unconnected ;; av_readdatavalid ; Input ; Info ; Stuck at GND ;; av_waitrequest ; Input ; Info ; Stuck at GND ;; av_writebyteenable ; Output ; Info ; Explicitly unconnected ;; av_lock ; Output ; Info ; Explicitly unconnected ;; av_clken ; Output ; Info ; Explicitly unconnected ;; uav_clken ; Input ; Info ; Stuck at GND ;; av_debugaccess ; Output ; Info ; Explicitly unconnected ;; av_outputenable ; Output ; Info ; Explicitly unconnected ;; uav_response ; Output ; Info ; Explicitly unconnected ;; av_response ; Input ; Info ; Stuck at GND ;; uav_writeresponsevalid ; Output ; Info ; Explicitly unconnected ;; av_writeresponsevalid ; Input ; Info ; Stuck at GND ;+------------------------+--------+----------+-------------------------------------------------------------------------------------------------------++----------------------------------------------------------------------------------------------------------------------------------------------------+; Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:link_start_s1_translator" ;+------------------------+--------+----------+-------------------------------------------------------------------------------------------------------+; Port ; Type ; Severity ; Details ;+------------------------+--------+----------+-------------------------------------------------------------------------------------------------------+; av_read ; Output ; Info ; Explicitly unconnected ;; av_begintransfer ; Output ; Info ; Explicitly unconnected ;; av_beginbursttransfer ; Output ; Info ; Explicitly unconnected ;; av_burstcount ; Output ; Info ; Explicitly unconnected ;; av_byteenable ; Output ; Info ; Explicitly unconnected ;; av_readdatavalid ; Input ; Info ; Stuck at GND ;; av_waitrequest ; Input ; Info ; Stuck at GND ;; av_writebyteenable ; Output ; Info ; Explicitly unconnected ;; av_lock ; Output ; Info ; Explicitly unconnected ;; av_clken ; Output ; Info ; Explicitly unconnected ;; uav_clken ; Input ; Info ; Stuck at GND ;; av_debugaccess ; Output ; Info ; Explicitly unconnected ;; av_outputenable ; Output ; Info ; Explicitly unconnected ;; uav_response ; Output ; Info ; Explicitly unconnected ;; av_response ; Input ; Info ; Stuck at GND ;; uav_writeresponsevalid ; Output ; Info ; Explicitly unconnected ;; av_writeresponsevalid ; Input ; Info ; Stuck at GND ;+------------------------+--------+----------+-------------------------------------------------------------------------------------------------------++--------------------------------------------------------------------------------------------------------------------------------------------------------------+; Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_empty_rx_status_s1_translator" ;+------------------------+--------+----------+-----------------------------------------------------------------------------------------------------------------+; Port ; Type ; Severity ; Details ;+------------------------+--------+----------+-----------------------------------------------------------------------------------------------------------------+; av_write ; Output ; Info ; Explicitly unconnected ;; av_read ; Output ; Info ; Explicitly unconnected ;; av_writedata ; Output ; Info ; Explicitly unconnected ;; av_begintransfer ; Output ; Info ; Explicitly unconnected ;; av_beginbursttransfer ; Output ; Info ; Explicitly unconnected ;; av_burstcount ; Output ; Info ; Explicitly unconnected ;; av_byteenable ; Output ; Info ; Explicitly unconnected ;; av_readdatavalid ; Input ; Info ; Stuck at GND ;; av_waitrequest ; Input ; Info ; Stuck at GND ;; av_writebyteenable ; Output ; Info ; Explicitly unconnected ;; av_lock ; Output ; Info ; Explicitly unconnected ;; av_chipselect ; Output ; Info ; Explicitly unconnected ;; av_clken ; Output ; Info ; Explicitly unconnected ;; uav_clken ; Input ; Info ; Stuck at GND ;; av_debugaccess ; Output ; Info ; Explicitly unconnected ;; av_outputenable ; Output ; Info ; Explicitly unconnected ;; uav_response ; Output ; Info ; Explicitly unconnected ;; av_response ; Input ; Info ; Stuck at GND ;; uav_writeresponsevalid ; Output ; Info ; Explicitly unconnected ;; av_writeresponsevalid ; Input ; Info ; Stuck at GND ;+------------------------+--------+----------+-----------------------------------------------------------------------------------------------------------------++-------------------------------------------------------------------------------------------------------------------------------------------------------------+; Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_full_rx_status_s1_translator" ;+------------------------+--------+----------+----------------------------------------------------------------------------------------------------------------+; Port ; Type ; Severity ; Details ;+------------------------+--------+----------+----------------------------------------------------------------------------------------------------------------+; av_write ; Output ; Info ; Explicitly unconnected ;; av_read ; Output ; Info ; Explicitly unconnected ;; av_writedata ; Output ; Info ; Explicitly unconnected ;; av_begintransfer ; Output ; Info ; Explicitly unconnected ;; av_beginbursttransfer ; Output ; Info ; Explicitly unconnected ;; av_burstcount ; Output ; Info ; Explicitly unconnected ;; av_byteenable ; Output ; Info ; Explicitly unconnected ;; av_readdatavalid ; Input ; Info ; Stuck at GND ;; av_waitrequest ; Input ; Info ; Stuck at GND ;; av_writebyteenable ; Output ; Info ; Explicitly unconnected ;; av_lock ; Output ; Info ; Explicitly unconnected ;; av_chipselect ; Output ; Info ; Explicitly unconnected ;; av_clken ; Output ; Info ; Explicitly unconnected ;; uav_clken ; Input ; Info ; Stuck at GND ;; av_debugaccess ; Output ; Info ; Explicitly unconnected ;; av_outputenable ; Output ; Info ; Explicitly unconnected ;; uav_response ; Output ; Info ; Explicitly unconnected ;; av_response ; Input ; Info ; Stuck at GND ;; uav_writeresponsevalid ; Output ; Info ; Explicitly unconnected ;; av_writeresponsevalid ; Input ; Info ; Stuck at GND ;+------------------------+--------+----------+----------------------------------------------------------------------------------------------------------------++---------------------------------------------------------------------------------------------------------------------------------------------------------+; Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:data_read_en_rx_s1_translator" ;+------------------------+--------+----------+------------------------------------------------------------------------------------------------------------+; Port ; Type ; Severity ; Details ;+------------------------+--------+----------+------------------------------------------------------------------------------------------------------------+; av_read ; Output ; Info ; Explicitly unconnected ;; av_begintransfer ; Output ; Info ; Explicitly unconnected ;; av_beginbursttransfer ; Output ; Info ; Explicitly unconnected ;; av_burstcount ; Output ; Info ; Explicitly unconnected ;; av_byteenable ; Output ; Info ; Explicitly unconnected ;; av_readdatavalid ; Input ; Info ; Stuck at GND ;; av_waitrequest ; Input ; Info ; Stuck at GND ;; av_writebyteenable ; Output ; Info ; Explicitly unconnected ;; av_lock ; Output ; Info ; Explicitly unconnected ;; av_clken ; Output ; Info ; Explicitly unconnected ;; uav_clken ; Input ; Info ; Stuck at GND ;; av_debugaccess ; Output ; Info ; Explicitly unconnected ;; av_outputenable ; Output ; Info ; Explicitly unconnected ;; uav_response ; Output ; Info ; Explicitly unconnected ;; av_response ; Input ; Info ; Stuck at GND ;; uav_writeresponsevalid ; Output ; Info ; Explicitly unconnected ;; av_writeresponsevalid ; Input ; Info ; Stuck at GND ;+------------------------+--------+----------+------------------------------------------------------------------------------------------------------------++------------------------------------------------------------------------------------------------------------------------------------------------------+; Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:data_flag_rx_s1_translator" ;+------------------------+--------+----------+---------------------------------------------------------------------------------------------------------+; Port ; Type ; Severity ; Details ;+------------------------+--------+----------+---------------------------------------------------------------------------------------------------------+; av_write ; Output ; Info ; Explicitly unconnected ;; av_read ; Output ; Info ; Explicitly unconnected ;; av_writedata ; Output ; Info ; Explicitly unconnected ;; av_begintransfer ; Output ; Info ; Explicitly unconnected ;; av_beginbursttransfer ; Output ; Info ; Explicitly unconnected ;; av_burstcount ; Output ; Info ; Explicitly unconnected ;; av_byteenable ; Output ; Info ; Explicitly unconnected ;; av_readdatavalid ; Input ; Info ; Stuck at GND ;; av_waitrequest ; Input ; Info ; Stuck at GND ;; av_writebyteenable ; Output ; Info ; Explicitly unconnected ;; av_lock ; Output ; Info ; Explicitly unconnected ;; av_chipselect ; Output ; Info ; Explicitly unconnected ;; av_clken ; Output ; Info ; Explicitly unconnected ;; uav_clken ; Input ; Info ; Stuck at GND ;; av_debugaccess ; Output ; Info ; Explicitly unconnected ;; av_outputenable ; Output ; Info ; Explicitly unconnected ;; uav_response ; Output ; Info ; Explicitly unconnected ;; av_response ; Input ; Info ; Stuck at GND ;; uav_writeresponsevalid ; Output ; Info ; Explicitly unconnected ;; av_writeresponsevalid ; Input ; Info ; Stuck at GND ;+------------------------+--------+----------+---------------------------------------------------------------------------------------------------------++-----------------------------------------------------------------------------------------------------------------------------------------------------------+; Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_ready_rx_s1_translator" ;+------------------------+--------+----------+--------------------------------------------------------------------------------------------------------------+; Port ; Type ; Severity ; Details ;+------------------------+--------+----------+--------------------------------------------------------------------------------------------------------------+; av_write ; Output ; Info ; Explicitly unconnected ;; av_read ; Output ; Info ; Explicitly unconnected ;; av_writedata ; Output ; Info ; Explicitly unconnected ;; av_begintransfer ; Output ; Info ; Explicitly unconnected ;; av_beginbursttransfer ; Output ; Info ; Explicitly unconnected ;; av_burstcount ; Output ; Info ; Explicitly unconnected ;; av_byteenable ; Output ; Info ; Explicitly unconnected ;; av_readdatavalid ; Input ; Info ; Stuck at GND ;; av_waitrequest ; Input ; Info ; Stuck at GND ;; av_writebyteenable ; Output ; Info ; Explicitly unconnected ;; av_lock ; Output ; Info ; Explicitly unconnected ;; av_chipselect ; Output ; Info ; Explicitly unconnected ;; av_clken ; Output ; Info ; Explicitly unconnected ;; uav_clken ; Input ; Info ; Stuck at GND ;; av_debugaccess ; Output ; Info ; Explicitly unconnected ;; av_outputenable ; Output ; Info ; Explicitly unconnected ;; uav_response ; Output ; Info ; Explicitly unconnected ;; av_response ; Input ; Info ; Stuck at GND ;; uav_writeresponsevalid ; Output ; Info ; Explicitly unconnected ;; av_writeresponsevalid ; Input ; Info ; Stuck at GND ;+------------------------+--------+----------+--------------------------------------------------------------------------------------------------------------++-----------------------------------------------------------------------------------------------------------------------------------------------------+; Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_rx_s1_translator" ;+------------------------+--------+----------+--------------------------------------------------------------------------------------------------------+; Port ; Type ; Severity ; Details ;+------------------------+--------+----------+--------------------------------------------------------------------------------------------------------+; av_write ; Output ; Info ; Explicitly unconnected ;; av_read ; Output ; Info ; Explicitly unconnected ;; av_writedata ; Output ; Info ; Explicitly unconnected ;; av_begintransfer ; Output ; Info ; Explicitly unconnected ;; av_beginbursttransfer ; Output ; Info ; Explicitly unconnected ;; av_burstcount ; Output ; Info ; Explicitly unconnected ;; av_byteenable ; Output ; Info ; Explicitly unconnected ;; av_readdatavalid ; Input ; Info ; Stuck at GND ;; av_waitrequest ; Input ; Info ; Stuck at GND ;; av_writebyteenable ; Output ; Info ; Explicitly unconnected ;; av_lock ; Output ; Info ; Explicitly unconnected ;; av_chipselect ; Output ; Info ; Explicitly unconnected ;; av_clken ; Output ; Info ; Explicitly unconnected ;; uav_clken ; Input ; Info ; Stuck at GND ;; av_debugaccess ; Output ; Info ; Explicitly unconnected ;; av_outputenable ; Output ; Info ; Explicitly unconnected ;; uav_response ; Output ; Info ; Explicitly unconnected ;; av_response ; Input ; Info ; Stuck at GND ;; uav_writeresponsevalid ; Output ; Info ; Explicitly unconnected ;; av_writeresponsevalid ; Input ; Info ; Stuck at GND ;+------------------------+--------+----------+--------------------------------------------------------------------------------------------------------++------------------------------------------------------------------------------------------------------------------------------------------------------+; Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:led_pio_test_s1_translator" ;+------------------------+--------+----------+---------------------------------------------------------------------------------------------------------+; Port ; Type ; Severity ; Details ;+------------------------+--------+----------+---------------------------------------------------------------------------------------------------------+; av_read ; Output ; Info ; Explicitly unconnected ;; av_begintransfer ; Output ; Info ; Explicitly unconnected ;; av_beginbursttransfer ; Output ; Info ; Explicitly unconnected ;; av_burstcount ; Output ; Info ; Explicitly unconnected ;; av_byteenable ; Output ; Info ; Explicitly unconnected ;; av_readdatavalid ; Input ; Info ; Stuck at GND ;; av_waitrequest ; Input ; Info ; Stuck at GND ;; av_writebyteenable ; Output ; Info ; Explicitly unconnected ;; av_lock ; Output ; Info ; Explicitly unconnected ;; av_clken ; Output ; Info ; Explicitly unconnected ;; uav_clken ; Input ; Info ; Stuck at GND ;; av_debugaccess ; Output ; Info ; Explicitly unconnected ;; av_outputenable ; Output ; Info ; Explicitly unconnected ;; uav_response ; Output ; Info ; Explicitly unconnected ;; av_response ; Input ; Info ; Stuck at GND ;; uav_writeresponsevalid ; Output ; Info ; Explicitly unconnected ;; av_writeresponsevalid ; Input ; Info ; Stuck at GND ;+------------------------+--------+----------+---------------------------------------------------------------------------------------------------------++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i" ;+-------------------+--------+----------+----------------------------------------------------------------------------------------------------------------------------------------------+; Port ; Type ; Severity ; Details ;+-------------------+--------+----------+----------------------------------------------------------------------------------------------------------------------------------------------+; fboutclk ; Output ; Info ; Explicitly unconnected ;; fbclk ; Input ; Info ; Stuck at GND ;; phase_en ; Input ; Warning ; Declared by entity but not connected by instance. If a default value exists, it will be used. Otherwise, the port will be connected to GND. ;; updn ; Input ; Warning ; Declared by entity but not connected by instance. If a default value exists, it will be used. Otherwise, the port will be connected to GND. ;; num_phase_shifts ; Input ; Warning ; Declared by entity but not connected by instance. If a default value exists, it will be used. Otherwise, the port will be connected to GND. ;; scanclk ; Input ; Warning ; Declared by entity but not connected by instance. If a default value exists, it will be used. Otherwise, the port will be connected to GND. ;; cntsel ; Input ; Warning ; Declared by entity but not connected by instance. If a default value exists, it will be used. Otherwise, the port will be connected to GND. ;; reconfig_to_pll ; Input ; Warning ; Declared by entity but not connected by instance. If a default value exists, it will be used. Otherwise, the port will be connected to GND. ;; extswitch ; Input ; Warning ; Declared by entity but not connected by instance. If a default value exists, it will be used. Otherwise, the port will be connected to GND. ;; adjpllin ; Input ; Warning ; Declared by entity but not connected by instance. If a default value exists, it will be used. Otherwise, the port will be connected to GND. ;; cclk ; Input ; Warning ; Declared by entity but not connected by instance. If a default value exists, it will be used. Otherwise, the port will be connected to GND. ;; phase_done ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;; reconfig_from_pll ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;; activeclk ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;; clkbad ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;; phout ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;; lvds_clk ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;; loaden ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;; extclk_out ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;; cascade_out ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;; zdbfbclk ; Bidir ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;+-------------------+--------+----------+----------------------------------------------------------------------------------------------------------------------------------------------++--------------------------------------------------------------------+; Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_pll_0:pll_0" ;+---------+-------+----------+---------------------------------------+; Port ; Type ; Severity ; Details ;+---------+-------+----------+---------------------------------------+; refclk1 ; Input ; Info ; Explicitly unconnected ;+---------+-------+----------+---------------------------------------++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|altera_mem_if_hard_memory_controller_top_cyclonev:c0" ;+-------------------------+--------+----------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Port ; Type ; Severity ; Details ;+-------------------------+--------+----------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; local_init_done ; Output ; Info ; Explicitly unconnected ;; local_cal_success ; Output ; Info ; Explicitly unconnected ;; local_cal_fail ; Output ; Info ; Explicitly unconnected ;; afi_init_req ; Output ; Info ; Explicitly unconnected ;; afi_cal_req ; Output ; Info ; Explicitly unconnected ;; afi_seq_busy ; Input ; Info ; Explicitly unconnected ;; afi_ctl_refresh_done ; Output ; Info ; Explicitly unconnected ;; afi_ctl_long_idle ; Output ; Info ; Explicitly unconnected ;; mp_cmd_clk_0 ; Input ; Info ; Stuck at GND ;; mp_cmd_reset_n_0 ; Input ; Info ; Stuck at VCC ;; mp_cmd_clk_1 ; Input ; Info ; Stuck at GND ;; mp_cmd_reset_n_1 ; Input ; Info ; Stuck at VCC ;; mp_cmd_clk_2 ; Input ; Info ; Stuck at GND ;; mp_cmd_reset_n_2 ; Input ; Info ; Stuck at VCC ;; mp_cmd_clk_3 ; Input ; Info ; Stuck at GND ;; mp_cmd_reset_n_3 ; Input ; Info ; Stuck at VCC ;; mp_cmd_clk_4 ; Input ; Info ; Stuck at GND ;; mp_cmd_reset_n_4 ; Input ; Info ; Stuck at VCC ;; mp_cmd_clk_5 ; Input ; Info ; Stuck at GND ;; mp_cmd_reset_n_5 ; Input ; Info ; Stuck at VCC ;; mp_rfifo_clk_0 ; Input ; Info ; Stuck at GND ;; mp_rfifo_reset_n_0 ; Input ; Info ; Stuck at VCC ;; mp_wfifo_clk_0 ; Input ; Info ; Stuck at GND ;; mp_wfifo_reset_n_0 ; Input ; Info ; Stuck at VCC ;; mp_rfifo_clk_1 ; Input ; Info ; Stuck at GND ;; mp_rfifo_reset_n_1 ; Input ; Info ; Stuck at VCC ;; mp_wfifo_clk_1 ; Input ; Info ; Stuck at GND ;; mp_wfifo_reset_n_1 ; Input ; Info ; Stuck at VCC ;; mp_rfifo_clk_2 ; Input ; Info ; Stuck at GND ;; mp_rfifo_reset_n_2 ; Input ; Info ; Stuck at VCC ;; mp_wfifo_clk_2 ; Input ; Info ; Stuck at GND ;; mp_wfifo_reset_n_2 ; Input ; Info ; Stuck at VCC ;; mp_rfifo_clk_3 ; Input ; Info ; Stuck at GND ;; mp_rfifo_reset_n_3 ; Input ; Info ; Stuck at VCC ;; mp_wfifo_clk_3 ; Input ; Info ; Stuck at GND ;; mp_wfifo_reset_n_3 ; Input ; Info ; Stuck at VCC ;; csr_clk ; Input ; Info ; Stuck at GND ;; csr_reset_n ; Input ; Info ; Stuck at VCC ;; avl_ready_0 ; Output ; Info ; Explicitly unconnected ;; avl_burstbegin_0 ; Input ; Info ; Stuck at GND ;; avl_addr_0 ; Input ; Info ; Stuck at GND ;; avl_rdata_valid_0 ; Output ; Info ; Explicitly unconnected ;; avl_rdata_0 ; Output ; Info ; Explicitly unconnected ;; avl_wdata_0 ; Input ; Info ; Stuck at GND ;; avl_be_0 ; Input ; Info ; Stuck at GND ;; avl_read_req_0 ; Input ; Info ; Stuck at GND ;; avl_write_req_0 ; Input ; Info ; Stuck at GND ;; avl_size_0 ; Input ; Info ; Stuck at GND ;; avl_ready_1 ; Output ; Info ; Explicitly unconnected ;; avl_burstbegin_1 ; Input ; Info ; Stuck at GND ;; avl_addr_1 ; Input ; Info ; Stuck at GND ;; avl_rdata_valid_1 ; Output ; Info ; Explicitly unconnected ;; avl_rdata_1 ; Output ; Info ; Explicitly unconnected ;; avl_wdata_1 ; Input ; Info ; Stuck at GND ;; avl_be_1 ; Input ; Info ; Stuck at GND ;; avl_read_req_1 ; Input ; Info ; Stuck at GND ;; avl_write_req_1 ; Input ; Info ; Stuck at GND ;; avl_size_1 ; Input ; Info ; Stuck at GND ;; avl_ready_2 ; Output ; Info ; Explicitly unconnected ;; avl_burstbegin_2 ; Input ; Info ; Stuck at GND ;; avl_addr_2 ; Input ; Info ; Stuck at GND ;; avl_rdata_valid_2 ; Output ; Info ; Explicitly unconnected ;; avl_rdata_2 ; Output ; Info ; Explicitly unconnected ;; avl_wdata_2 ; Input ; Info ; Stuck at GND ;; avl_be_2 ; Input ; Info ; Stuck at GND ;; avl_read_req_2 ; Input ; Info ; Stuck at GND ;; avl_write_req_2 ; Input ; Info ; Stuck at GND ;; avl_size_2 ; Input ; Info ; Stuck at GND ;; avl_ready_3 ; Output ; Info ; Explicitly unconnected ;; avl_burstbegin_3 ; Input ; Info ; Stuck at GND ;; avl_addr_3 ; Input ; Info ; Stuck at GND ;; avl_rdata_valid_3 ; Output ; Info ; Explicitly unconnected ;; avl_rdata_3 ; Output ; Info ; Explicitly unconnected ;; avl_wdata_3 ; Input ; Info ; Stuck at GND ;; avl_be_3 ; Input ; Info ; Stuck at GND ;; avl_read_req_3 ; Input ; Info ; Stuck at GND ;; avl_write_req_3 ; Input ; Info ; Stuck at GND ;; avl_size_3 ; Input ; Info ; Stuck at GND ;; avl_ready_4 ; Output ; Info ; Explicitly unconnected ;; avl_burstbegin_4 ; Input ; Info ; Stuck at GND ;; avl_addr_4 ; Input ; Info ; Stuck at GND ;; avl_rdata_valid_4 ; Output ; Info ; Explicitly unconnected ;; avl_rdata_4 ; Output ; Info ; Explicitly unconnected ;; avl_wdata_4 ; Input ; Info ; Stuck at GND ;; avl_be_4 ; Input ; Info ; Stuck at GND ;; avl_read_req_4 ; Input ; Info ; Stuck at GND ;; avl_write_req_4 ; Input ; Info ; Stuck at GND ;; avl_size_4 ; Input ; Info ; Stuck at GND ;; avl_ready_5 ; Output ; Info ; Explicitly unconnected ;; avl_burstbegin_5 ; Input ; Info ; Stuck at GND ;; avl_addr_5 ; Input ; Info ; Stuck at GND ;; avl_rdata_valid_5 ; Output ; Info ; Explicitly unconnected ;; avl_rdata_5 ; Output ; Info ; Explicitly unconnected ;; avl_wdata_5 ; Input ; Info ; Stuck at GND ;; avl_be_5 ; Input ; Info ; Stuck at GND ;; avl_read_req_5 ; Input ; Info ; Stuck at GND ;; avl_write_req_5 ; Input ; Info ; Stuck at GND ;; avl_size_5 ; Input ; Info ; Stuck at GND ;; csr_write_req ; Input ; Info ; Stuck at GND ;; csr_read_req ; Input ; Info ; Stuck at GND ;; csr_waitrequest ; Output ; Info ; Explicitly unconnected ;; csr_addr ; Input ; Info ; Stuck at GND ;; csr_be ; Input ; Info ; Stuck at GND ;; csr_wdata ; Input ; Info ; Stuck at GND ;; csr_rdata ; Output ; Info ; Explicitly unconnected ;; csr_rdata_valid ; Output ; Info ; Explicitly unconnected ;; local_multicast ; Input ; Info ; Stuck at GND ;; local_refresh_req ; Input ; Info ; Stuck at GND ;; local_refresh_chip ; Input ; Info ; Stuck at GND ;; local_refresh_ack ; Output ; Info ; Explicitly unconnected ;; local_self_rfsh_req ; Input ; Info ; Stuck at GND ;; local_self_rfsh_chip ; Input ; Info ; Stuck at GND ;; local_self_rfsh_ack ; Output ; Info ; Explicitly unconnected ;; local_deep_powerdn_req ; Input ; Info ; Stuck at GND ;; local_deep_powerdn_chip ; Input ; Info ; Stuck at GND ;; local_deep_powerdn_ack ; Output ; Info ; Explicitly unconnected ;; local_powerdn_ack ; Output ; Info ; Explicitly unconnected ;; local_priority ; Input ; Info ; Stuck at GND ;; bonding_in_1 ; Input ; Info ; Stuck at GND ;; bonding_in_2 ; Input ; Info ; Stuck at GND ;; bonding_in_3 ; Input ; Info ; Stuck at GND ;; bonding_out_1 ; Output ; Info ; Explicitly unconnected ;; bonding_out_2 ; Output ; Info ; Explicitly unconnected ;; bonding_out_3 ; Output ; Info ; Explicitly unconnected ;; ctl_init_req ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;; local_sts_ctl_empty ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;+-------------------------+--------+----------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_altdqdqs:dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_acv_connect_to_hard_phy_cyclonev:altdq_dqs2_inst" ;+---------------------+--------+----------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Port ; Type ; Severity ; Details ;+---------------------+--------+----------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; dll_offsetdelay_in ; Input ; Warning ; Declared by entity but not connected by instance. If a default value exists, it will be used. Otherwise, the port will be connected to GND. ;; capture_strobe_in ; Input ; Warning ; Declared by entity but not connected by instance. If a default value exists, it will be used. Otherwise, the port will be connected to GND. ;; capture_strobe_n_in ; Input ; Warning ; Declared by entity but not connected by instance. If a default value exists, it will be used. Otherwise, the port will be connected to GND. ;; capture_strobe_ena ; Input ; Warning ; Declared by entity but not connected by instance. If a default value exists, it will be used. Otherwise, the port will be connected to GND. ;; output_strobe_out ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;; output_strobe_n_out ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;; dr_clock_in ; Input ; Warning ; Declared by entity but not connected by instance. If a default value exists, it will be used. Otherwise, the port will be connected to GND. ;; read_data_in ; Input ; Warning ; Declared by entity but not connected by instance. If a default value exists, it will be used. Otherwise, the port will be connected to GND. ;; write_data_out ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;+---------------------+--------+----------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_altdqdqs:dq_ddio[0].ubidir_dq_dqs" ;+--------------------+--------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Port ; Type ; Severity ; Details ;+--------------------+--------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; capture_strobe_out ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;+--------------------+--------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|hps_sdram_p0_generic_ddio:ureset_n_pad" ;+----------------+-------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Port ; Type ; Severity ; Details ;+----------------+-------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; halfratebypass ; Input ; Info ; Stuck at VCC ;+----------------+-------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|hps_sdram_p0_generic_ddio:ucmd_pad" ;+----------------+-------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Port ; Type ; Severity ; Details ;+----------------+-------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; halfratebypass ; Input ; Info ; Stuck at VCC ;+----------------+-------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|hps_sdram_p0_generic_ddio:ubank_pad" ;+----------------+-------+----------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Port ; Type ; Severity ; Details ;+----------------+-------+----------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; halfratebypass ; Input ; Info ; Stuck at VCC ;+----------------+-------+----------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|hps_sdram_p0_generic_ddio:uaddress_pad" ;+----------------+-------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Port ; Type ; Severity ; Details ;+----------------+-------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; halfratebypass ; Input ; Info ; Stuck at VCC ;+----------------+-------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|hps_sdram_p0_acv_ldc:address_gen[22].acv_ac_ldc" ;+---------+--------+----------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Port ; Type ; Severity ; Details ;+---------+--------+----------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; afi_clk ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;; avl_clk ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;; adc_clk ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;; hr_clk ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;+---------+--------+----------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|hps_sdram_p0_acv_ldc:address_gen[21].acv_ac_ldc" ;+---------+--------+----------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Port ; Type ; Severity ; Details ;+---------+--------+----------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; afi_clk ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;; avl_clk ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;; adc_clk ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;; hr_clk ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;+---------+--------+----------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|hps_sdram_p0_acv_ldc:address_gen[20].acv_ac_ldc" ;+---------+--------+----------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Port ; Type ; Severity ; Details ;+---------+--------+----------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; afi_clk ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;; avl_clk ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;; adc_clk ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;; hr_clk ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;+---------+--------+----------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|hps_sdram_p0_acv_ldc:address_gen[19].acv_ac_ldc" ;+---------+--------+----------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Port ; Type ; Severity ; Details ;+---------+--------+----------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; afi_clk ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;; avl_clk ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;; adc_clk ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;; hr_clk ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;+---------+--------+----------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|hps_sdram_p0_acv_ldc:address_gen[18].acv_ac_ldc" ;+---------+--------+----------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Port ; Type ; Severity ; Details ;+---------+--------+----------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; afi_clk ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;; avl_clk ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;; adc_clk ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;; hr_clk ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;+---------+--------+----------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|hps_sdram_p0_acv_ldc:address_gen[17].acv_ac_ldc" ;+---------+--------+----------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Port ; Type ; Severity ; Details ;+---------+--------+----------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; afi_clk ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;; avl_clk ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;; adc_clk ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;; hr_clk ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;+---------+--------+----------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|hps_sdram_p0_acv_ldc:address_gen[16].acv_ac_ldc" ;+---------+--------+----------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Port ; Type ; Severity ; Details ;+---------+--------+----------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; afi_clk ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;; avl_clk ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;; adc_clk ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;; hr_clk ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;+---------+--------+----------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|hps_sdram_p0_acv_ldc:address_gen[15].acv_ac_ldc" ;+---------+--------+----------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Port ; Type ; Severity ; Details ;+---------+--------+----------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; afi_clk ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;; avl_clk ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;; adc_clk ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;; hr_clk ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;+---------+--------+----------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|hps_sdram_p0_acv_ldc:address_gen[14].acv_ac_ldc" ;+---------+--------+----------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Port ; Type ; Severity ; Details ;+---------+--------+----------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; afi_clk ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;; avl_clk ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;; adc_clk ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;; hr_clk ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;+---------+--------+----------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|hps_sdram_p0_acv_ldc:address_gen[13].acv_ac_ldc" ;+---------+--------+----------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Port ; Type ; Severity ; Details ;+---------+--------+----------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; afi_clk ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;; avl_clk ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;; adc_clk ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;; hr_clk ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;+---------+--------+----------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|hps_sdram_p0_acv_ldc:address_gen[12].acv_ac_ldc" ;+---------+--------+----------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Port ; Type ; Severity ; Details ;+---------+--------+----------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; afi_clk ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;; avl_clk ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;; adc_clk ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;; hr_clk ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;+---------+--------+----------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|hps_sdram_p0_acv_ldc:address_gen[11].acv_ac_ldc" ;+---------+--------+----------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Port ; Type ; Severity ; Details ;+---------+--------+----------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; afi_clk ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;; avl_clk ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;; adc_clk ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;; hr_clk ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;+---------+--------+----------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|hps_sdram_p0_acv_ldc:address_gen[10].acv_ac_ldc" ;+---------+--------+----------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Port ; Type ; Severity ; Details ;+---------+--------+----------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; afi_clk ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;; avl_clk ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;; adc_clk ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;; hr_clk ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;+---------+--------+----------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|hps_sdram_p0_acv_ldc:address_gen[9].acv_ac_ldc" ;+---------+--------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Port ; Type ; Severity ; Details ;+---------+--------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; afi_clk ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;; avl_clk ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;; adc_clk ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;; hr_clk ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;+---------+--------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|hps_sdram_p0_acv_ldc:address_gen[8].acv_ac_ldc" ;+---------+--------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Port ; Type ; Severity ; Details ;+---------+--------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; afi_clk ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;; avl_clk ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;; adc_clk ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;; hr_clk ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;+---------+--------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|hps_sdram_p0_acv_ldc:address_gen[7].acv_ac_ldc" ;+---------+--------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Port ; Type ; Severity ; Details ;+---------+--------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; afi_clk ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;; avl_clk ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;; adc_clk ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;; hr_clk ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;+---------+--------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|hps_sdram_p0_acv_ldc:address_gen[6].acv_ac_ldc" ;+---------+--------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Port ; Type ; Severity ; Details ;+---------+--------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; afi_clk ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;; avl_clk ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;; adc_clk ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;; hr_clk ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;+---------+--------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|hps_sdram_p0_acv_ldc:address_gen[5].acv_ac_ldc" ;+---------+--------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Port ; Type ; Severity ; Details ;+---------+--------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; afi_clk ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;; avl_clk ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;; adc_clk ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;; hr_clk ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;+---------+--------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|hps_sdram_p0_acv_ldc:address_gen[4].acv_ac_ldc" ;+---------+--------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Port ; Type ; Severity ; Details ;+---------+--------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; afi_clk ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;; avl_clk ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;; adc_clk ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;; hr_clk ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;+---------+--------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|hps_sdram_p0_acv_ldc:address_gen[3].acv_ac_ldc" ;+---------+--------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Port ; Type ; Severity ; Details ;+---------+--------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; afi_clk ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;; avl_clk ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;; adc_clk ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;; hr_clk ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;+---------+--------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|hps_sdram_p0_acv_ldc:address_gen[2].acv_ac_ldc" ;+---------+--------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Port ; Type ; Severity ; Details ;+---------+--------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; afi_clk ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;; avl_clk ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;; adc_clk ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;; hr_clk ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;+---------+--------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|hps_sdram_p0_acv_ldc:address_gen[1].acv_ac_ldc" ;+---------+--------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Port ; Type ; Severity ; Details ;+---------+--------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; afi_clk ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;; avl_clk ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;; adc_clk ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;; hr_clk ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;+---------+--------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|hps_sdram_p0_acv_ldc:address_gen[0].acv_ac_ldc" ;+---------+--------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Port ; Type ; Severity ; Details ;+---------+--------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; afi_clk ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;; avl_clk ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;; adc_clk ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;; hr_clk ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;+---------+--------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads" ;+------------------+-------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Port ; Type ; Severity ; Details ;+------------------+-------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; phy_ddio_address ; Input ; Warning ; Input port expression (64 bits) is wider than the input port (52 bits) it drives. The 12 most-significant bit(s) in the expression will be dangling if they have no other fanouts. ;; phy_ddio_cs_n ; Input ; Warning ; Input port expression (8 bits) is wider than the input port (4 bits) it drives. The 4 most-significant bit(s) in the expression will be dangling if they have no other fanouts. ;; phy_ddio_cke ; Input ; Warning ; Input port expression (8 bits) is wider than the input port (4 bits) it drives. The 4 most-significant bit(s) in the expression will be dangling if they have no other fanouts. ;; phy_ddio_odt ; Input ; Warning ; Input port expression (8 bits) is wider than the input port (4 bits) it drives. The 4 most-significant bit(s) in the expression will be dangling if they have no other fanouts. ;+------------------+-------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads" ;+-----------------------------+-------+----------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Port ; Type ; Severity ; Details ;+-----------------------------+-------+----------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; phy_ddio_dmdout ; Input ; Warning ; Input port expression (20 bits) is smaller than the input port (25 bits) it drives. Extra input bit(s) "phy_ddio_dmdout[24..20]" will be connected to GND. ;; seq_read_latency_counter ; Input ; Warning ; Declared by entity but not connected by instance. If a default value exists, it will be used. Otherwise, the port will be connected to GND. ;; seq_read_increment_vfifo_fr ; Input ; Warning ; Declared by entity but not connected by instance. If a default value exists, it will be used. Otherwise, the port will be connected to GND. ;; seq_read_increment_vfifo_hr ; Input ; Warning ; Declared by entity but not connected by instance. If a default value exists, it will be used. Otherwise, the port will be connected to GND. ;+-----------------------------+-------+----------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_ldc:memphy_ldc" ;+--------+--------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Port ; Type ; Severity ; Details ;+--------+--------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; hr_clk ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;+--------+--------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0" ;+---------------------------+--------+----------+------------------------------------------------------------------------------------------------------------------------------------+; Port ; Type ; Severity ; Details ;+---------------------------+--------+----------+------------------------------------------------------------------------------------------------------------------------------------+; afi_reset_export_n ; Output ; Info ; Explicitly unconnected ;; avl_clk ; Output ; Info ; Explicitly unconnected ;; avl_reset_n ; Output ; Info ; Explicitly unconnected ;; scc_clk ; Output ; Info ; Explicitly unconnected ;; scc_reset_n ; Output ; Info ; Explicitly unconnected ;; avl_address ; Input ; Info ; Explicitly unconnected ;; avl_write ; Input ; Info ; Explicitly unconnected ;; avl_writedata ; Input ; Info ; Explicitly unconnected ;; avl_read ; Input ; Info ; Explicitly unconnected ;; avl_readdata ; Output ; Info ; Explicitly unconnected ;; avl_waitrequest ; Output ; Info ; Explicitly unconnected ;; scc_data ; Input ; Info ; Explicitly unconnected ;; scc_dqs_ena ; Input ; Info ; Explicitly unconnected ;; scc_dqs_io_ena ; Input ; Info ; Explicitly unconnected ;; scc_dq_ena ; Input ; Info ; Explicitly unconnected ;; scc_dm_ena ; Input ; Info ; Explicitly unconnected ;; capture_strobe_tracking ; Output ; Info ; Explicitly unconnected ;; scc_upd ; Input ; Info ; Explicitly unconnected ;; csr_soft_reset_req ; Input ; Info ; Stuck at GND ;; io_intaddrdout ; Input ; Info ; Stuck at GND ;; io_intbadout ; Input ; Info ; Stuck at GND ;; io_intcasndout ; Input ; Info ; Stuck at GND ;; io_intckdout ; Input ; Info ; Stuck at GND ;; io_intckedout ; Input ; Info ; Stuck at GND ;; io_intckndout ; Input ; Info ; Stuck at GND ;; io_intcsndout ; Input ; Info ; Stuck at GND ;; io_intdmdout ; Input ; Info ; Stuck at GND ;; io_intdqdin ; Output ; Info ; Explicitly unconnected ;; io_intdqdout ; Input ; Info ; Stuck at GND ;; io_intdqoe ; Input ; Info ; Stuck at GND ;; io_intdqsbdout ; Input ; Info ; Stuck at GND ;; io_intdqsboe ; Input ; Info ; Stuck at GND ;; io_intdqsdout ; Input ; Info ; Stuck at GND ;; io_intdqslogicdqsena ; Input ; Info ; Stuck at GND ;; io_intdqslogicfiforeset ; Input ; Info ; Stuck at GND ;; io_intdqslogicincrdataen ; Input ; Info ; Stuck at GND ;; io_intdqslogicincwrptr ; Input ; Info ; Stuck at GND ;; io_intdqslogicoct ; Input ; Info ; Stuck at GND ;; io_intdqslogicrdatavalid ; Output ; Info ; Explicitly unconnected ;; io_intdqslogicreadlatency ; Input ; Info ; Stuck at GND ;; io_intdqsoe ; Input ; Info ; Stuck at GND ;; io_intodtdout ; Input ; Info ; Stuck at GND ;; io_intrasndout ; Input ; Info ; Stuck at GND ;; io_intresetndout ; Input ; Info ; Stuck at GND ;; io_intwendout ; Input ; Info ; Stuck at GND ;; io_intafirlat ; Output ; Info ; Explicitly unconnected ;; io_intafiwlat ; Output ; Info ; Explicitly unconnected ;; phy_clk ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;; phy_reset_n ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;+---------------------------+--------+----------+------------------------------------------------------------------------------------------------------------------------------------++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst" ;+----------------+-------+----------+----------------------------------------------------------------------------------------------------------------------------------------------+; Port ; Type ; Severity ; Details ;+----------------+-------+----------+----------------------------------------------------------------------------------------------------------------------------------------------+; pll_ref_clk ; Input ; Warning ; Declared by entity but not connected by instance. If a default value exists, it will be used. Otherwise, the port will be connected to GND. ;; global_reset_n ; Input ; Warning ; Declared by entity but not connected by instance. If a default value exists, it will be used. Otherwise, the port will be connected to GND. ;; soft_reset_n ; Input ; Warning ; Declared by entity but not connected by instance. If a default value exists, it will be used. Otherwise, the port will be connected to GND. ;+----------------+-------+----------+----------------------------------------------------------------------------------------------------------------------------------------------++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Port Connectivity Checks: "ulight_fifo:u0" ;+--------------------+--------+----------+----------------------------------------------------------------------------------------------------------------------------------------------+; Port ; Type ; Severity ; Details ;+--------------------+--------+----------+----------------------------------------------------------------------------------------------------------------------------------------------+; memory_mem_a ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;; memory_mem_ba ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;; memory_mem_ck ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;; memory_mem_ck_n ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;; memory_mem_cke ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;; memory_mem_cs_n ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;; memory_mem_ras_n ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;; memory_mem_cas_n ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;; memory_mem_we_n ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;; memory_mem_reset_n ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;; memory_mem_dq ; Bidir ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;; memory_mem_dqs ; Bidir ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;; memory_mem_dqs_n ; Bidir ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;; memory_mem_odt ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;; memory_mem_dm ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;; memory_oct_rzqin ; Input ; Warning ; Declared by entity but not connected by instance. If a default value exists, it will be used. Otherwise, the port will be connected to GND. ;+--------------------+--------+----------+----------------------------------------------------------------------------------------------------------------------------------------------++-----------------------------------------------------+; Post-Synthesis Netlist Statistics for Top Partition ;+-------------------------------------+---------------+; Type ; Count ;+-------------------------------------+---------------+; arriav_ff ; 4628 ;; CLR ; 1150 ;; ENA CLR ; 3301 ;; plain ; 177 ;; arriav_hps_interface_boot_from_fpga ; 1 ;; arriav_hps_interface_clocks_resets ; 1 ;; arriav_hps_interface_dbg_apb ; 1 ;; arriav_hps_interface_fpga2hps ; 1 ;; arriav_hps_interface_fpga2sdram ; 1 ;; arriav_hps_interface_hps2fpga ; 1 ;; arriav_hps_interface_tpiu_trace ; 1 ;; arriav_lcell_comb ; 5407 ;; arith ; 219 ;; 1 data inputs ; 99 ;; 2 data inputs ; 89 ;; 3 data inputs ; 17 ;; 4 data inputs ; 13 ;; 5 data inputs ; 1 ;; extend ; 72 ;; 7 data inputs ; 72 ;; normal ; 5110 ;; 0 data inputs ; 1 ;; 1 data inputs ; 44 ;; 2 data inputs ; 483 ;; 3 data inputs ; 890 ;; 4 data inputs ; 1504 ;; 5 data inputs ; 906 ;; 6 data inputs ; 1282 ;; shared ; 6 ;; 2 data inputs ; 6 ;; boundary_port ; 15 ;; cyclonev_fractional_pll ; 1 ;; cyclonev_pll_output_counter ; 1 ;; cyclonev_pll_reconfig ; 1 ;; cyclonev_pll_refclk_select ; 1 ;; ; ;; Max LUT depth ; 7.00 ;; Average LUT depth ; 3.17 ;+-------------------------------------+---------------++----------------------------------------------------------------------------------------+; Post-Synthesis Netlist Statistics for Partition ulight_fifo_hps_0_hps_io_border:border ;+------------------------------------+---------------------------------------------------+; Type ; Count ;+------------------------------------+---------------------------------------------------+; arriav_clk_phase_select ; 29 ;; arriav_ddio_in ; 8 ;; arriav_ddio_oe ; 1 ;; arriav_ddio_out ; 114 ;; arriav_delay_chain ; 31 ;; arriav_dll ; 1 ;; arriav_dqs_config ; 1 ;; arriav_dqs_delay_chain ; 1 ;; arriav_dqs_enable_ctrl ; 1 ;; arriav_ff ; 9 ;; plain ; 9 ;; arriav_hps_sdram_pll ; 1 ;; arriav_io_config ; 10 ;; arriav_io_ibuf ; 9 ;; arriav_io_obuf ; 13 ;; arriav_ir_fifo_userdes ; 8 ;; arriav_lcell_comb ; 1 ;; normal ; 1 ;; 0 data inputs ; 1 ;; arriav_leveling_delay_chain ; 29 ;; arriav_lfifo ; 1 ;; arriav_mem_phy ; 1 ;; arriav_read_fifo_read_clock_select ; 8 ;; arriav_vfifo ; 1 ;; boundary_port ; 37 ;; cyclonev_hmc ; 1 ;; cyclonev_termination ; 1 ;; cyclonev_termination_logic ; 1 ;; stratixv_pseudo_diff_out ; 2 ;; ; ;; Max LUT depth ; 0.00 ;; Average LUT depth ; 0.00 ;+------------------------------------+---------------------------------------------------++-------------------------------------------------------+; Elapsed Time Per Partition ;+----------------------------------------+--------------+; Partition Name ; Elapsed Time ;+----------------------------------------+--------------+; Top ; 00:00:34 ;; ulight_fifo_hps_0_hps_io_border:border ; 00:00:01 ;+----------------------------------------+--------------++-------------------------------+; Analysis & Synthesis Messages ;+-------------------------------+Info: *******************************************************************Info: Running Quartus Prime Analysis & SynthesisInfo: Version 17.1.1 Internal Build 593 12/11/2017 SJ Lite EditionInfo: Processing started: Mon Feb 5 00:46:52 2018Info: Command: quartus_map --read_settings_files=on --write_settings_files=off spw_fifo_ulight -c spw_fifo_ulightInfo (16303): High Performance Effort optimization mode selected -- timing performance will be prioritized at the potential cost of increased compilation timeInfo (16304): Mode behavior is affected by advanced setting Fitter Effort (default for this mode is Standard Fit)Info (16304): Mode behavior is affected by advanced setting Physical Synthesis Effort Level (default for this mode is Normal)Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.Info (20030): Parallel compilation is enabled and will use 2 of the 2 processors detectedInfo (12021): Found 1 design units, including 1 entities, in source file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/tx_fsm_m.vInfo (12023): Found entity 1: tx_fsm_m File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/tx_fsm_m.v Line: 34Info (12021): Found 1 design units, including 1 entities, in source file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/tx_fct_send.vInfo (12023): Found entity 1: tx_fct_send File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/tx_fct_send.v Line: 33Info (12021): Found 1 design units, including 1 entities, in source file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/tx_fct_counter.vInfo (12023): Found entity 1: tx_fct_counter File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/tx_fct_counter.v Line: 33Info (12021): Found 1 design units, including 1 entities, in source file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/tx_data_send.vInfo (12023): Found entity 1: tx_data_send File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/tx_data_send.v Line: 33Warning (10890): Verilog HDL Attribute warning at rx_data_receive.v(64): overriding existing value for attribute "dont_replicate" File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/rx_data_receive.v Line: 64Info (12021): Found 1 design units, including 1 entities, in source file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/rx_data_receive.vInfo (12023): Found entity 1: rx_data_receive File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/rx_data_receive.v Line: 33Info (12021): Found 1 design units, including 1 entities, in source file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/rx_data_control_p.vInfo (12023): Found entity 1: rx_data_control_p File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/rx_data_control_p.v Line: 33Info (12021): Found 1 design units, including 1 entities, in source file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/rx_data_buffer_data_w.vInfo (12023): Found entity 1: rx_data_buffer_data_w File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/rx_data_buffer_data_w.v Line: 33Info (12021): Found 1 design units, including 1 entities, in source file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/rx_control_data_rdy.vInfo (12023): Found entity 1: rx_control_data_rdy File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/rx_control_data_rdy.v Line: 33Info (12021): Found 1 design units, including 1 entities, in source file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/rx_buffer_fsm.vInfo (12023): Found entity 1: rx_buffer_fsm File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/rx_buffer_fsm.v Line: 33Info (12021): Found 1 design units, including 1 entities, in source file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/mem_data.vInfo (12023): Found entity 1: mem_data File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/mem_data.v Line: 33Info (12021): Found 1 design units, including 1 entities, in source file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/counter_neg.vInfo (12023): Found entity 1: counter_neg File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/counter_neg.v Line: 33Info (12021): Found 1 design units, including 1 entities, in source file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/bitc_capture_control.vInfo (12023): Found entity 1: bit_capture_control File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/bitc_capture_control.v Line: 33Info (12021): Found 1 design units, including 1 entities, in source file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/bit_capture_data.vInfo (12023): Found entity 1: bit_capture_data File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/bit_capture_data.v Line: 33Info (12021): Found 1 design units, including 1 entities, in source file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/tx_spw.vInfo (12023): Found entity 1: TX_SPW File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/tx_spw.v Line: 36Info (12021): Found 1 design units, including 1 entities, in source file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/top_spw_ultra_light.vInfo (12023): Found entity 1: top_spw_ultra_light File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/top_spw_ultra_light.v Line: 36Info (12021): Found 1 design units, including 1 entities, in source file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/spw_ulight_con_top_x.vInfo (12023): Found entity 1: spw_ulight_con_top_x File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/spw_ulight_con_top_x.v Line: 36Info (12021): Found 1 design units, including 1 entities, in source file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/rx_spw.vInfo (12023): Found entity 1: RX_SPW File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/rx_spw.v Line: 36Info (12021): Found 1 design units, including 1 entities, in source file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/fsm_spw.vInfo (12023): Found entity 1: FSM_SPW File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/fsm_spw.v Line: 36Warning (10890): Verilog HDL Attribute warning at fifo_tx.v(43): overriding existing value for attribute "syn_noprune" File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/fifo_tx.v Line: 43Warning (10890): Verilog HDL Attribute warning at fifo_tx.v(44): overriding existing value for attribute "syn_noprune" File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/fifo_tx.v Line: 44Info (12021): Found 1 design units, including 1 entities, in source file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/fifo_tx.vInfo (12023): Found entity 1: fifo_tx File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/fifo_tx.v Line: 33Info (12021): Found 1 design units, including 1 entities, in source file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/fifo_rx.vInfo (12023): Found entity 1: fifo_rx File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/fifo_rx.v Line: 33Info (12021): Found 1 design units, including 1 entities, in source file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/DEBUG_VERILOG/debounce.vInfo (12023): Found entity 1: debounce_db File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/DEBUG_VERILOG/debounce.v Line: 33Info (12021): Found 1 design units, including 1 entities, in source file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/DEBUG_VERILOG/detector_tokens.vInfo (12023): Found entity 1: detector_tokens File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/DEBUG_VERILOG/detector_tokens.v Line: 33Info (12021): Found 1 design units, including 1 entities, in source file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/DEBUG_VERILOG/clock_reduce.vInfo (12023): Found entity 1: clock_reduce File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/DEBUG_VERILOG/clock_reduce.v Line: 34Info (12021): Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/ulight_fifo.vInfo (12023): Found entity 1: ulight_fifo File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/ulight_fifo.v Line: 6Info (12021): Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/altera_reset_controller.vInfo (12023): Found entity 1: altera_reset_controller File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_reset_controller.v Line: 42Info (12021): Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/altera_reset_synchronizer.vInfo (12023): Found entity 1: altera_reset_synchronizer File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_reset_synchronizer.v Line: 24Info (12021): Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0.vInfo (12023): Found entity 1: ulight_fifo_mm_interconnect_0 File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0.v Line: 9Info (12021): Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_avalon_st_adapter.vInfo (12023): Found entity 1: ulight_fifo_mm_interconnect_0_avalon_st_adapter File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_avalon_st_adapter.v Line: 9Info (12021): Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_avalon_st_adapter_error_adapter_0.svInfo (12023): Found entity 1: ulight_fifo_mm_interconnect_0_avalon_st_adapter_error_adapter_0 File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_avalon_st_adapter_error_adapter_0.sv Line: 66Info (12021): Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_rsp_mux.svInfo (12023): Found entity 1: ulight_fifo_mm_interconnect_0_rsp_mux File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_rsp_mux.sv Line: 51Info (12021): Found 2 design units, including 2 entities, in source file ulight_fifo/synthesis/submodules/altera_merlin_arbitrator.svInfo (12023): Found entity 1: altera_merlin_arbitrator File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_arbitrator.sv Line: 103Info (12023): Found entity 2: altera_merlin_arb_adder File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_arbitrator.sv Line: 228Info (12021): Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_rsp_demux.svInfo (12023): Found entity 1: ulight_fifo_mm_interconnect_0_rsp_demux File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_rsp_demux.sv Line: 43Info (12021): Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_cmd_mux.svInfo (12023): Found entity 1: ulight_fifo_mm_interconnect_0_cmd_mux File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_cmd_mux.sv Line: 51Info (12021): Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_cmd_demux.svInfo (12023): Found entity 1: ulight_fifo_mm_interconnect_0_cmd_demux File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_cmd_demux.sv Line: 43Info (12021): Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter.svInfo (12023): Found entity 1: altera_merlin_burst_adapter File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter.sv Line: 21Info (12021): Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_uncmpr.svInfo (12023): Found entity 1: altera_merlin_burst_adapter_uncompressed_only File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_uncmpr.sv Line: 39Info (12021): Found 5 design units, including 5 entities, in source file ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.svInfo (12023): Found entity 1: altera_merlin_burst_adapter_burstwrap_increment File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv Line: 40Info (12023): Found entity 2: altera_merlin_burst_adapter_adder File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv Line: 55Info (12023): Found entity 3: altera_merlin_burst_adapter_subtractor File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv Line: 77Info (12023): Found entity 4: altera_merlin_burst_adapter_min File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv Line: 98Info (12023): Found entity 5: altera_merlin_burst_adapter_13_1 File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv Line: 264Info (12021): Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_new.svInfo (12023): Found entity 1: altera_merlin_burst_adapter_new File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_new.sv Line: 25Info (12021): Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/altera_incr_burst_converter.svInfo (12023): Found entity 1: altera_incr_burst_converter File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_incr_burst_converter.sv Line: 28Info (12021): Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/altera_wrap_burst_converter.svInfo (12023): Found entity 1: altera_wrap_burst_converter File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_wrap_burst_converter.sv Line: 27Info (12021): Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/altera_default_burst_converter.svInfo (12023): Found entity 1: altera_default_burst_converter File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_default_burst_converter.sv Line: 30Info (12021): Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/altera_merlin_address_alignment.svInfo (12023): Found entity 1: altera_merlin_address_alignment File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_address_alignment.sv Line: 26Info (12021): Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/altera_avalon_st_pipeline_stage.svInfo (12023): Found entity 1: altera_avalon_st_pipeline_stage File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_avalon_st_pipeline_stage.sv Line: 22Info (12021): Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/altera_avalon_st_pipeline_base.vInfo (12023): Found entity 1: altera_avalon_st_pipeline_base File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_avalon_st_pipeline_base.v Line: 22Info (12021): Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/altera_merlin_traffic_limiter.svInfo (12023): Found entity 1: altera_merlin_traffic_limiter File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_traffic_limiter.sv Line: 49Info (12021): Found 2 design units, including 2 entities, in source file ulight_fifo/synthesis/submodules/altera_merlin_reorder_memory.svInfo (12023): Found entity 1: altera_merlin_reorder_memory File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_reorder_memory.sv Line: 28Info (12023): Found entity 2: memory_pointer_controller File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_reorder_memory.sv Line: 185Info (12021): Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/altera_avalon_sc_fifo.vInfo (12023): Found entity 1: altera_avalon_sc_fifo File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_avalon_sc_fifo.v Line: 21Info (12021): Found 2 design units, including 2 entities, in source file ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_router_002.svInfo (12023): Found entity 1: ulight_fifo_mm_interconnect_0_router_002_default_decode File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_router_002.sv Line: 45Info (12023): Found entity 2: ulight_fifo_mm_interconnect_0_router_002 File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_router_002.sv Line: 84Info (12021): Found 2 design units, including 2 entities, in source file ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_router.svInfo (12023): Found entity 1: ulight_fifo_mm_interconnect_0_router_default_decode File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_router.sv Line: 45Info (12023): Found entity 2: ulight_fifo_mm_interconnect_0_router File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_router.sv Line: 84Info (12021): Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/altera_merlin_slave_agent.svInfo (12023): Found entity 1: altera_merlin_slave_agent File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_slave_agent.sv Line: 34Info (12021): Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/altera_merlin_burst_uncompressor.svInfo (12023): Found entity 1: altera_merlin_burst_uncompressor File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_burst_uncompressor.sv Line: 40Info (12021): Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/altera_merlin_axi_master_ni.svInfo (12023): Found entity 1: altera_merlin_axi_master_ni File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_axi_master_ni.sv Line: 27Info (12021): Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/altera_merlin_slave_translator.svInfo (12023): Found entity 1: altera_merlin_slave_translator File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_slave_translator.sv Line: 35Info (12021): Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/ulight_fifo_write_data_fifo_tx.vInfo (12023): Found entity 1: ulight_fifo_write_data_fifo_tx File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_write_data_fifo_tx.v Line: 21Info (12021): Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/ulight_fifo_timecode_tx_data.vInfo (12023): Found entity 1: ulight_fifo_timecode_tx_data File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_timecode_tx_data.v Line: 21Info (12021): Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/ulight_fifo_timecode_rx.vInfo (12023): Found entity 1: ulight_fifo_timecode_rx File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_timecode_rx.v Line: 21Info (12021): Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/ulight_fifo_pll_0.vInfo (12023): Found entity 1: ulight_fifo_pll_0 File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_pll_0.v Line: 2Info (12021): Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/ulight_fifo_led_pio_test.vInfo (12023): Found entity 1: ulight_fifo_led_pio_test File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_led_pio_test.v Line: 21Info (12021): Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/ulight_fifo_hps_0.vInfo (12023): Found entity 1: ulight_fifo_hps_0 File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_hps_0.v Line: 9Info (12021): Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/ulight_fifo_hps_0_hps_io.vInfo (12023): Found entity 1: ulight_fifo_hps_0_hps_io File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_hps_0_hps_io.v Line: 9Info (12021): Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/hps_sdram.vInfo (12023): Found entity 1: hps_sdram File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram.v Line: 9Info (12021): Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/hps_sdram_pll.svInfo (12023): Found entity 1: hps_sdram_pll File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_pll.sv Line: 25Info (12021): Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/hps_sdram_p0_clock_pair_generator.vInfo (12023): Found entity 1: hps_sdram_p0_clock_pair_generator File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_clock_pair_generator.v Line: 28Info (12021): Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_addr_cmd_pads.vInfo (12023): Found entity 1: hps_sdram_p0_acv_hard_addr_cmd_pads File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_addr_cmd_pads.v Line: 17Info (12021): Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_memphy.vInfo (12023): Found entity 1: hps_sdram_p0_acv_hard_memphy File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_memphy.v Line: 21Info (12021): Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_ldc.vInfo (12023): Found entity 1: hps_sdram_p0_acv_ldc File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_ldc.v Line: 17Info (12021): Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_io_pads.vInfo (12023): Found entity 1: hps_sdram_p0_acv_hard_io_pads File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_io_pads.v Line: 17Info (12021): Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/hps_sdram_p0_generic_ddio.vInfo (12023): Found entity 1: hps_sdram_p0_generic_ddio File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_generic_ddio.v Line: 17Info (12021): Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/hps_sdram_p0_reset.vInfo (12023): Found entity 1: hps_sdram_p0_reset File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_reset.v Line: 18Info (12021): Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/hps_sdram_p0_reset_sync.vInfo (12023): Found entity 1: hps_sdram_p0_reset_sync File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_reset_sync.v Line: 17Info (12021): Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/hps_sdram_p0_phy_csr.svInfo (12023): Found entity 1: hps_sdram_p0_phy_csr File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_phy_csr.sv Line: 31Info (12021): Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/hps_sdram_p0_iss_probe.vInfo (12023): Found entity 1: hps_sdram_p0_iss_probe File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_iss_probe.v Line: 17Info (12021): Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/hps_sdram_p0.svInfo (12023): Found entity 1: hps_sdram_p0 File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0.sv Line: 18Info (12021): Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/hps_sdram_p0_altdqdqs.vInfo (12023): Found entity 1: hps_sdram_p0_altdqdqs File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_altdqdqs.v Line: 17Info (12021): Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/altdq_dqs2_acv_connect_to_hard_phy_cyclonev.svInfo (12023): Found entity 1: altdq_dqs2_acv_connect_to_hard_phy_cyclonev File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altdq_dqs2_acv_connect_to_hard_phy_cyclonev.sv Line: 19Info (12021): Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/altera_mem_if_hhp_qseq_synth_top.vInfo (12023): Found entity 1: altera_mem_if_hhp_qseq_synth_top File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_mem_if_hhp_qseq_synth_top.v Line: 15Info (12021): Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/altera_mem_if_hard_memory_controller_top_cyclonev.svInfo (12023): Found entity 1: altera_mem_if_hard_memory_controller_top_cyclonev File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_mem_if_hard_memory_controller_top_cyclonev.sv Line: 18Info (12021): Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/altera_mem_if_oct_cyclonev.svInfo (12023): Found entity 1: altera_mem_if_oct_cyclonev File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_mem_if_oct_cyclonev.sv Line: 23Info (12021): Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/altera_mem_if_dll_cyclonev.svInfo (12023): Found entity 1: altera_mem_if_dll_cyclonev File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_mem_if_dll_cyclonev.sv Line: 23Info (12021): Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/ulight_fifo_hps_0_hps_io_border.svInfo (12023): Found entity 1: ulight_fifo_hps_0_hps_io_border File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_hps_0_hps_io_border.sv Line: 14Info (12021): Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/ulight_fifo_hps_0_fpga_interfaces.svInfo (12023): Found entity 1: ulight_fifo_hps_0_fpga_interfaces File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_hps_0_fpga_interfaces.sv Line: 14Info (12021): Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/ulight_fifo_fifo_empty_rx_status.vInfo (12023): Found entity 1: ulight_fifo_fifo_empty_rx_status File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_fifo_empty_rx_status.v Line: 21Info (12021): Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/ulight_fifo_data_info.vInfo (12023): Found entity 1: ulight_fifo_data_info File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_data_info.v Line: 21Info (12021): Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/ulight_fifo_data_flag_rx.vInfo (12023): Found entity 1: ulight_fifo_data_flag_rx File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_data_flag_rx.v Line: 21Info (12021): Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/ulight_fifo_counter_rx_fifo.vInfo (12023): Found entity 1: ulight_fifo_counter_rx_fifo File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_counter_rx_fifo.v Line: 21Info (12021): Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/ulight_fifo_clock_sel.vInfo (12023): Found entity 1: ulight_fifo_clock_sel File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_clock_sel.v Line: 21Info (12021): Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/ulight_fifo_auto_start.vInfo (12023): Found entity 1: ulight_fifo_auto_start File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_auto_start.v Line: 21Info (12021): Found 1 design units, including 1 entities, in source file top_rtl/spw_fifo_ulight.vInfo (12023): Found entity 1: SPW_ULIGHT_FIFO File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/top_rtl/spw_fifo_ulight.v Line: 1Warning (10236): Verilog HDL Implicit Net warning at spw_fifo_ulight.v(99): created implicit net for "top_tx_ready_tick" File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/top_rtl/spw_fifo_ulight.v Line: 99Warning (10236): Verilog HDL Implicit Net warning at hps_sdram_pll.sv(168): created implicit net for "pll_dr_clk" File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_pll.sv Line: 168Info (12127): Elaborating entity "SPW_ULIGHT_FIFO" for the top level hierarchyWarning (10034): Output port "LED[6]" at spw_fifo_ulight.v(17) has no driver File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/top_rtl/spw_fifo_ulight.v Line: 17Info (12128): Elaborating entity "ulight_fifo" for hierarchy "ulight_fifo:u0" File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/top_rtl/spw_fifo_ulight.v Line: 105Info (12128): Elaborating entity "ulight_fifo_auto_start" for hierarchy "ulight_fifo:u0|ulight_fifo_auto_start:auto_start" File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/ulight_fifo.v Line: 174Info (12128): Elaborating entity "ulight_fifo_clock_sel" for hierarchy "ulight_fifo:u0|ulight_fifo_clock_sel:clock_sel" File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/ulight_fifo.v Line: 185Info (12128): Elaborating entity "ulight_fifo_counter_rx_fifo" for hierarchy "ulight_fifo:u0|ulight_fifo_counter_rx_fifo:counter_rx_fifo" File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/ulight_fifo.v Line: 193Info (12128): Elaborating entity "ulight_fifo_data_flag_rx" for hierarchy "ulight_fifo:u0|ulight_fifo_data_flag_rx:data_flag_rx" File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/ulight_fifo.v Line: 209Info (12128): Elaborating entity "ulight_fifo_data_info" for hierarchy "ulight_fifo:u0|ulight_fifo_data_info:data_info" File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/ulight_fifo.v Line: 217Info (12128): Elaborating entity "ulight_fifo_fifo_empty_rx_status" for hierarchy "ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_empty_rx_status" File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/ulight_fifo.v Line: 236Info (12128): Elaborating entity "ulight_fifo_hps_0" for hierarchy "ulight_fifo:u0|ulight_fifo_hps_0:hps_0" File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/ulight_fifo.v Line: 328Info (12128): Elaborating entity "ulight_fifo_hps_0_fpga_interfaces" for hierarchy "ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces" File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_hps_0.v Line: 134Info (12128): Elaborating entity "ulight_fifo_hps_0_hps_io" for hierarchy "ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io" File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_hps_0.v Line: 153Info (12128): Elaborating entity "ulight_fifo_hps_0_hps_io_border" for hierarchy "ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border" File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_hps_0_hps_io.v Line: 45Info (12128): Elaborating entity "hps_sdram" for hierarchy "ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst" File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_hps_0_hps_io_border.sv Line: 84Info (12128): Elaborating entity "hps_sdram_pll" for hierarchy "ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll" File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram.v Line: 105Warning (10036): Verilog HDL or VHDL warning at hps_sdram_pll.sv(168): object "pll_dr_clk" assigned a value but never read File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_pll.sv Line: 168Warning (10034): Output port "pll_locked" at hps_sdram_pll.sv(91) has no driver File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_pll.sv Line: 91Info (12128): Elaborating entity "hps_sdram_p0" for hierarchy "ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0" File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram.v Line: 230Info (10648): Verilog HDL Display System Task info at hps_sdram_p0.sv(405): Using Regular core emif simulation models File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0.sv Line: 405Info (12128): Elaborating entity "hps_sdram_p0_acv_hard_memphy" for hierarchy "ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy" File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0.sv Line: 573Warning (10858): Verilog HDL warning at hps_sdram_p0_acv_hard_memphy.v(420): object reset_n_seq_clk used but never assigned File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_memphy.v Line: 420Warning (10230): Verilog HDL assignment warning at hps_sdram_p0_acv_hard_memphy.v(557): truncated value with size 4 to match size of target (1) File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_memphy.v Line: 557Warning (10030): Net "reset_n_seq_clk" at hps_sdram_p0_acv_hard_memphy.v(420) has no driver or initial value, using a default initial value '0' File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_memphy.v Line: 420Warning (10034): Output port "ctl_reset_export_n" at hps_sdram_p0_acv_hard_memphy.v(222) has no driver File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_memphy.v Line: 222Info (12128): Elaborating entity "hps_sdram_p0_acv_ldc" for hierarchy "ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_ldc:memphy_ldc" File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_memphy.v Line: 554Warning (10036): Verilog HDL or VHDL warning at hps_sdram_p0_acv_ldc.v(45): object "phy_clk_dq" assigned a value but never read File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_ldc.v Line: 45Warning (10036): Verilog HDL or VHDL warning at hps_sdram_p0_acv_ldc.v(47): object "phy_clk_dqs_2x" assigned a value but never read File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_ldc.v Line: 47Info (12128): Elaborating entity "hps_sdram_p0_acv_hard_io_pads" for hierarchy "ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads" File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_memphy.v Line: 780Warning (10034): Output port "ddio_phy_dqdin[179..32]" at hps_sdram_p0_acv_hard_io_pads.v(191) has no driver File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_io_pads.v Line: 191Info (12128): Elaborating entity "hps_sdram_p0_acv_hard_addr_cmd_pads" for hierarchy "ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads" File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_io_pads.v Line: 244Info (12128): Elaborating entity "hps_sdram_p0_generic_ddio" for hierarchy "ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|hps_sdram_p0_generic_ddio:uaddress_pad" File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_addr_cmd_pads.v Line: 157Info (12128): Elaborating entity "hps_sdram_p0_generic_ddio" for hierarchy "ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|hps_sdram_p0_generic_ddio:ubank_pad" File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_addr_cmd_pads.v Line: 166Info (12128): Elaborating entity "hps_sdram_p0_generic_ddio" for hierarchy "ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|hps_sdram_p0_generic_ddio:ucmd_pad" File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_addr_cmd_pads.v Line: 189Info (12128): Elaborating entity "hps_sdram_p0_generic_ddio" for hierarchy "ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|hps_sdram_p0_generic_ddio:ureset_n_pad" File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_addr_cmd_pads.v Line: 198Info (12128): Elaborating entity "altddio_out" for hierarchy "ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|altddio_out:clock_gen[0].umem_ck_pad" File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_addr_cmd_pads.v Line: 317Info (12130): Elaborated megafunction instantiation "ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|altddio_out:clock_gen[0].umem_ck_pad" File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_addr_cmd_pads.v Line: 317Info (12133): Instantiated megafunction "ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|altddio_out:clock_gen[0].umem_ck_pad" with the following parameter: File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_addr_cmd_pads.v Line: 317Info (12134): Parameter "extend_oe_disable" = "UNUSED"Info (12134): Parameter "intended_device_family" = "Cyclone V"Info (12134): Parameter "invert_output" = "OFF"Info (12134): Parameter "lpm_hint" = "UNUSED"Info (12134): Parameter "lpm_type" = "altddio_out"Info (12134): Parameter "oe_reg" = "UNUSED"Info (12134): Parameter "power_up_high" = "OFF"Info (12134): Parameter "width" = "1"Info (12021): Found 1 design units, including 1 entities, in source file db/ddio_out_uqe.tdfInfo (12023): Found entity 1: ddio_out_uqe File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/db/ddio_out_uqe.tdf Line: 27Info (12128): Elaborating entity "ddio_out_uqe" for hierarchy "ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|altddio_out:clock_gen[0].umem_ck_pad|ddio_out_uqe:auto_generated" File: /home/felipe/intelFPGA_lite/17.1/quartus/libraries/megafunctions/altddio_out.tdf Line: 100Info (12128): Elaborating entity "hps_sdram_p0_clock_pair_generator" for hierarchy "ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|hps_sdram_p0_clock_pair_generator:clock_gen[0].uclk_generator" File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_addr_cmd_pads.v Line: 337Info (12128): Elaborating entity "hps_sdram_p0_altdqdqs" for hierarchy "ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_altdqdqs:dq_ddio[0].ubidir_dq_dqs" File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_io_pads.v Line: 317Info (12128): Elaborating entity "altdq_dqs2_acv_connect_to_hard_phy_cyclonev" for hierarchy "ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_altdqdqs:dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_acv_connect_to_hard_phy_cyclonev:altdq_dqs2_inst" File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_altdqdqs.v Line: 146Info (12128): Elaborating entity "altera_mem_if_hhp_qseq_synth_top" for hierarchy "ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|altera_mem_if_hhp_qseq_synth_top:seq" File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram.v Line: 238Info (12128): Elaborating entity "altera_mem_if_hard_memory_controller_top_cyclonev" for hierarchy "ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|altera_mem_if_hard_memory_controller_top_cyclonev:c0" File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram.v Line: 794Warning (10230): Verilog HDL assignment warning at altera_mem_if_hard_memory_controller_top_cyclonev.sv(1166): truncated value with size 320 to match size of target (1) File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_mem_if_hard_memory_controller_top_cyclonev.sv Line: 1166Warning (10230): Verilog HDL assignment warning at altera_mem_if_hard_memory_controller_top_cyclonev.sv(1167): truncated value with size 320 to match size of target (1) File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_mem_if_hard_memory_controller_top_cyclonev.sv Line: 1167Warning (10230): Verilog HDL assignment warning at altera_mem_if_hard_memory_controller_top_cyclonev.sv(1168): truncated value with size 320 to match size of target (1) File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_mem_if_hard_memory_controller_top_cyclonev.sv Line: 1168Warning (10230): Verilog HDL assignment warning at altera_mem_if_hard_memory_controller_top_cyclonev.sv(1169): truncated value with size 320 to match size of target (1) File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_mem_if_hard_memory_controller_top_cyclonev.sv Line: 1169Warning (10230): Verilog HDL assignment warning at altera_mem_if_hard_memory_controller_top_cyclonev.sv(1170): truncated value with size 320 to match size of target (1) File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_mem_if_hard_memory_controller_top_cyclonev.sv Line: 1170Warning (10230): Verilog HDL assignment warning at altera_mem_if_hard_memory_controller_top_cyclonev.sv(1171): truncated value with size 320 to match size of target (1) File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_mem_if_hard_memory_controller_top_cyclonev.sv Line: 1171Info (12128): Elaborating entity "altera_mem_if_oct_cyclonev" for hierarchy "ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|altera_mem_if_oct_cyclonev:oct" File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram.v Line: 802Info (12128): Elaborating entity "altera_mem_if_dll_cyclonev" for hierarchy "ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|altera_mem_if_dll_cyclonev:dll" File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram.v Line: 814Info (12128): Elaborating entity "ulight_fifo_led_pio_test" for hierarchy "ulight_fifo:u0|ulight_fifo_led_pio_test:led_pio_test" File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/ulight_fifo.v Line: 339Info (12128): Elaborating entity "ulight_fifo_pll_0" for hierarchy "ulight_fifo:u0|ulight_fifo_pll_0:pll_0" File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/ulight_fifo.v Line: 369Info (12128): Elaborating entity "altera_pll" for hierarchy "ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i" File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_pll_0.v Line: 241Warning (10034): Output port "lvds_clk" at altera_pll.v(319) has no driver File: /home/felipe/intelFPGA_lite/17.1/quartus/libraries/megafunctions/altera_pll.v Line: 319Warning (10034): Output port "loaden" at altera_pll.v(320) has no driver File: /home/felipe/intelFPGA_lite/17.1/quartus/libraries/megafunctions/altera_pll.v Line: 320Warning (10034): Output port "extclk_out" at altera_pll.v(321) has no driver File: /home/felipe/intelFPGA_lite/17.1/quartus/libraries/megafunctions/altera_pll.v Line: 321Info (10008): Verilog HDL or VHDL information: EDA Netlist Writer cannot regroup multidimensional array "wire_to_nowhere_64" into its busInfo (12130): Elaborated megafunction instantiation "ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i" File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_pll_0.v Line: 241Info (12133): Instantiated megafunction "ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i" with the following parameter: File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_pll_0.v Line: 241Info (12134): Parameter "fractional_vco_multiplier" = "false"Info (12134): Parameter "reference_clock_frequency" = "50.0 MHz"Info (12134): Parameter "pll_fractional_cout" = "32"Info (12134): Parameter "pll_dsm_out_sel" = "1st_order"Info (12134): Parameter "operation_mode" = "normal"Info (12134): Parameter "number_of_clocks" = "1"Info (12134): Parameter "output_clock_frequency0" = "400.000000 MHz"Info (12134): Parameter "phase_shift0" = "0 ps"Info (12134): Parameter "duty_cycle0" = "50"Info (12134): Parameter "output_clock_frequency1" = "0 MHz"Info (12134): Parameter "phase_shift1" = "0 ps"Info (12134): Parameter "duty_cycle1" = "50"Info (12134): Parameter "output_clock_frequency2" = "0 MHz"Info (12134): Parameter "phase_shift2" = "0 ps"Info (12134): Parameter "duty_cycle2" = "50"Info (12134): Parameter "output_clock_frequency3" = "0 MHz"Info (12134): Parameter "phase_shift3" = "0 ps"Info (12134): Parameter "duty_cycle3" = "50"Info (12134): Parameter "output_clock_frequency4" = "0 MHz"Info (12134): Parameter "phase_shift4" = "0 ps"Info (12134): Parameter "duty_cycle4" = "50"Info (12134): Parameter "output_clock_frequency5" = "0 MHz"Info (12134): Parameter "phase_shift5" = "0 ps"Info (12134): Parameter "duty_cycle5" = "50"Info (12134): Parameter "output_clock_frequency6" = "0 MHz"Info (12134): Parameter "phase_shift6" = "0 ps"Info (12134): Parameter "duty_cycle6" = "50"Info (12134): Parameter "output_clock_frequency7" = "0 MHz"Info (12134): Parameter "phase_shift7" = "0 ps"Info (12134): Parameter "duty_cycle7" = "50"Info (12134): Parameter "output_clock_frequency8" = "0 MHz"Info (12134): Parameter "phase_shift8" = "0 ps"Info (12134): Parameter "duty_cycle8" = "50"Info (12134): Parameter "output_clock_frequency9" = "0 MHz"Info (12134): Parameter "phase_shift9" = "0 ps"Info (12134): Parameter "duty_cycle9" = "50"Info (12134): Parameter "output_clock_frequency10" = "0 MHz"Info (12134): Parameter "phase_shift10" = "0 ps"Info (12134): Parameter "duty_cycle10" = "50"Info (12134): Parameter "output_clock_frequency11" = "0 MHz"Info (12134): Parameter "phase_shift11" = "0 ps"Info (12134): Parameter "duty_cycle11" = "50"Info (12134): Parameter "output_clock_frequency12" = "0 MHz"Info (12134): Parameter "phase_shift12" = "0 ps"Info (12134): Parameter "duty_cycle12" = "50"Info (12134): Parameter "output_clock_frequency13" = "0 MHz"Info (12134): Parameter "phase_shift13" = "0 ps"Info (12134): Parameter "duty_cycle13" = "50"Info (12134): Parameter "output_clock_frequency14" = "0 MHz"Info (12134): Parameter "phase_shift14" = "0 ps"Info (12134): Parameter "duty_cycle14" = "50"Info (12134): Parameter "output_clock_frequency15" = "0 MHz"Info (12134): Parameter "phase_shift15" = "0 ps"Info (12134): Parameter "duty_cycle15" = "50"Info (12134): Parameter "output_clock_frequency16" = "0 MHz"Info (12134): Parameter "phase_shift16" = "0 ps"Info (12134): Parameter "duty_cycle16" = "50"Info (12134): Parameter "output_clock_frequency17" = "0 MHz"Info (12134): Parameter "phase_shift17" = "0 ps"Info (12134): Parameter "duty_cycle17" = "50"Info (12134): Parameter "pll_type" = "Cyclone V"Info (12134): Parameter "pll_subtype" = "General"Info (12134): Parameter "m_cnt_hi_div" = "4"Info (12134): Parameter "m_cnt_lo_div" = "4"Info (12134): Parameter "n_cnt_hi_div" = "256"Info (12134): Parameter "n_cnt_lo_div" = "256"Info (12134): Parameter "m_cnt_bypass_en" = "false"Info (12134): Parameter "n_cnt_bypass_en" = "true"Info (12134): Parameter "m_cnt_odd_div_duty_en" = "false"Info (12134): Parameter "n_cnt_odd_div_duty_en" = "false"Info (12134): Parameter "c_cnt_hi_div0" = "256"Info (12134): Parameter "c_cnt_lo_div0" = "256"Info (12134): Parameter "c_cnt_prst0" = "1"Info (12134): Parameter "c_cnt_ph_mux_prst0" = "0"Info (12134): Parameter "c_cnt_in_src0" = "ph_mux_clk"Info (12134): Parameter "c_cnt_bypass_en0" = "true"Info (12134): Parameter "c_cnt_odd_div_duty_en0" = "false"Info (12134): Parameter "c_cnt_hi_div1" = "1"Info (12134): Parameter "c_cnt_lo_div1" = "1"Info (12134): Parameter "c_cnt_prst1" = "1"Info (12134): Parameter "c_cnt_ph_mux_prst1" = "0"Info (12134): Parameter "c_cnt_in_src1" = "ph_mux_clk"Info (12134): Parameter "c_cnt_bypass_en1" = "true"Info (12134): Parameter "c_cnt_odd_div_duty_en1" = "false"Info (12134): Parameter "c_cnt_hi_div2" = "1"Info (12134): Parameter "c_cnt_lo_div2" = "1"Info (12134): Parameter "c_cnt_prst2" = "1"Info (12134): Parameter "c_cnt_ph_mux_prst2" = "0"Info (12134): Parameter "c_cnt_in_src2" = "ph_mux_clk"Info (12134): Parameter "c_cnt_bypass_en2" = "true"Info (12134): Parameter "c_cnt_odd_div_duty_en2" = "false"Info (12134): Parameter "c_cnt_hi_div3" = "1"Info (12134): Parameter "c_cnt_lo_div3" = "1"Info (12134): Parameter "c_cnt_prst3" = "1"Info (12134): Parameter "c_cnt_ph_mux_prst3" = "0"Info (12134): Parameter "c_cnt_in_src3" = "ph_mux_clk"Info (12134): Parameter "c_cnt_bypass_en3" = "true"Info (12134): Parameter "c_cnt_odd_div_duty_en3" = "false"Info (12134): Parameter "c_cnt_hi_div4" = "1"Info (12134): Parameter "c_cnt_lo_div4" = "1"Info (12134): Parameter "c_cnt_prst4" = "1"Info (12134): Parameter "c_cnt_ph_mux_prst4" = "0"Info (12134): Parameter "c_cnt_in_src4" = "ph_mux_clk"Info (12134): Parameter "c_cnt_bypass_en4" = "true"Info (12134): Parameter "c_cnt_odd_div_duty_en4" = "false"Info (12134): Parameter "c_cnt_hi_div5" = "1"Info (12134): Parameter "c_cnt_lo_div5" = "1"Info (12134): Parameter "c_cnt_prst5" = "1"Info (12134): Parameter "c_cnt_ph_mux_prst5" = "0"Info (12134): Parameter "c_cnt_in_src5" = "ph_mux_clk"Info (12134): Parameter "c_cnt_bypass_en5" = "true"Info (12134): Parameter "c_cnt_odd_div_duty_en5" = "false"Info (12134): Parameter "c_cnt_hi_div6" = "1"Info (12134): Parameter "c_cnt_lo_div6" = "1"Info (12134): Parameter "c_cnt_prst6" = "1"Info (12134): Parameter "c_cnt_ph_mux_prst6" = "0"Info (12134): Parameter "c_cnt_in_src6" = "ph_mux_clk"Info (12134): Parameter "c_cnt_bypass_en6" = "true"Info (12134): Parameter "c_cnt_odd_div_duty_en6" = "false"Info (12134): Parameter "c_cnt_hi_div7" = "1"Info (12134): Parameter "c_cnt_lo_div7" = "1"Info (12134): Parameter "c_cnt_prst7" = "1"Info (12134): Parameter "c_cnt_ph_mux_prst7" = "0"Info (12134): Parameter "c_cnt_in_src7" = "ph_mux_clk"Info (12134): Parameter "c_cnt_bypass_en7" = "true"Info (12134): Parameter "c_cnt_odd_div_duty_en7" = "false"Info (12134): Parameter "c_cnt_hi_div8" = "1"Info (12134): Parameter "c_cnt_lo_div8" = "1"Info (12134): Parameter "c_cnt_prst8" = "1"Info (12134): Parameter "c_cnt_ph_mux_prst8" = "0"Info (12134): Parameter "c_cnt_in_src8" = "ph_mux_clk"Info (12134): Parameter "c_cnt_bypass_en8" = "true"Info (12134): Parameter "c_cnt_odd_div_duty_en8" = "false"Info (12134): Parameter "c_cnt_hi_div9" = "1"Info (12134): Parameter "c_cnt_lo_div9" = "1"Info (12134): Parameter "c_cnt_prst9" = "1"Info (12134): Parameter "c_cnt_ph_mux_prst9" = "0"Info (12134): Parameter "c_cnt_in_src9" = "ph_mux_clk"Info (12134): Parameter "c_cnt_bypass_en9" = "true"Info (12134): Parameter "c_cnt_odd_div_duty_en9" = "false"Info (12134): Parameter "c_cnt_hi_div10" = "1"Info (12134): Parameter "c_cnt_lo_div10" = "1"Info (12134): Parameter "c_cnt_prst10" = "1"Info (12134): Parameter "c_cnt_ph_mux_prst10" = "0"Info (12134): Parameter "c_cnt_in_src10" = "ph_mux_clk"Info (12134): Parameter "c_cnt_bypass_en10" = "true"Info (12134): Parameter "c_cnt_odd_div_duty_en10" = "false"Info (12134): Parameter "c_cnt_hi_div11" = "1"Info (12134): Parameter "c_cnt_lo_div11" = "1"Info (12134): Parameter "c_cnt_prst11" = "1"Info (12134): Parameter "c_cnt_ph_mux_prst11" = "0"Info (12134): Parameter "c_cnt_in_src11" = "ph_mux_clk"Info (12134): Parameter "c_cnt_bypass_en11" = "true"Info (12134): Parameter "c_cnt_odd_div_duty_en11" = "false"Info (12134): Parameter "c_cnt_hi_div12" = "1"Info (12134): Parameter "c_cnt_lo_div12" = "1"Info (12134): Parameter "c_cnt_prst12" = "1"Info (12134): Parameter "c_cnt_ph_mux_prst12" = "0"Info (12134): Parameter "c_cnt_in_src12" = "ph_mux_clk"Info (12134): Parameter "c_cnt_bypass_en12" = "true"Info (12134): Parameter "c_cnt_odd_div_duty_en12" = "false"Info (12134): Parameter "c_cnt_hi_div13" = "1"Info (12134): Parameter "c_cnt_lo_div13" = "1"Info (12134): Parameter "c_cnt_prst13" = "1"Info (12134): Parameter "c_cnt_ph_mux_prst13" = "0"Info (12134): Parameter "c_cnt_in_src13" = "ph_mux_clk"Info (12134): Parameter "c_cnt_bypass_en13" = "true"Info (12134): Parameter "c_cnt_odd_div_duty_en13" = "false"Info (12134): Parameter "c_cnt_hi_div14" = "1"Info (12134): Parameter "c_cnt_lo_div14" = "1"Info (12134): Parameter "c_cnt_prst14" = "1"Info (12134): Parameter "c_cnt_ph_mux_prst14" = "0"Info (12134): Parameter "c_cnt_in_src14" = "ph_mux_clk"Info (12134): Parameter "c_cnt_bypass_en14" = "true"Info (12134): Parameter "c_cnt_odd_div_duty_en14" = "false"Info (12134): Parameter "c_cnt_hi_div15" = "1"Info (12134): Parameter "c_cnt_lo_div15" = "1"Info (12134): Parameter "c_cnt_prst15" = "1"Info (12134): Parameter "c_cnt_ph_mux_prst15" = "0"Info (12134): Parameter "c_cnt_in_src15" = "ph_mux_clk"Info (12134): Parameter "c_cnt_bypass_en15" = "true"Info (12134): Parameter "c_cnt_odd_div_duty_en15" = "false"Info (12134): Parameter "c_cnt_hi_div16" = "1"Info (12134): Parameter "c_cnt_lo_div16" = "1"Info (12134): Parameter "c_cnt_prst16" = "1"Info (12134): Parameter "c_cnt_ph_mux_prst16" = "0"Info (12134): Parameter "c_cnt_in_src16" = "ph_mux_clk"Info (12134): Parameter "c_cnt_bypass_en16" = "true"Info (12134): Parameter "c_cnt_odd_div_duty_en16" = "false"Info (12134): Parameter "c_cnt_hi_div17" = "1"Info (12134): Parameter "c_cnt_lo_div17" = "1"Info (12134): Parameter "c_cnt_prst17" = "1"Info (12134): Parameter "c_cnt_ph_mux_prst17" = "0"Info (12134): Parameter "c_cnt_in_src17" = "ph_mux_clk"Info (12134): Parameter "c_cnt_bypass_en17" = "true"Info (12134): Parameter "c_cnt_odd_div_duty_en17" = "false"Info (12134): Parameter "pll_vco_div" = "2"Info (12134): Parameter "pll_cp_current" = "20"Info (12134): Parameter "pll_bwctrl" = "4000"Info (12134): Parameter "pll_output_clk_frequency" = "400.0 MHz"Info (12134): Parameter "pll_fractional_division" = "1"Info (12134): Parameter "mimic_fbclk_type" = "gclk"Info (12134): Parameter "pll_fbclk_mux_1" = "glb"Info (12134): Parameter "pll_fbclk_mux_2" = "fb_1"Info (12134): Parameter "pll_m_cnt_in_src" = "ph_mux_clk"Info (12134): Parameter "pll_slf_rst" = "false"Info (12134): Parameter "refclk1_frequency" = "100.0 MHz"Info (12134): Parameter "pll_clk_loss_sw_en" = "true"Info (12134): Parameter "pll_manu_clk_sw_en" = "false"Info (12134): Parameter "pll_auto_clk_sw_en" = "true"Info (12134): Parameter "pll_clkin_1_src" = "clk_1"Info (12134): Parameter "pll_clk_sw_dly" = "0"Info (12128): Elaborating entity "dps_extra_kick" for hierarchy "ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i|dps_extra_kick:dps_extra_inst" File: /home/felipe/intelFPGA_lite/17.1/quartus/libraries/megafunctions/altera_pll.v Line: 768Info (12131): Elaborated megafunction instantiation "ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i|dps_extra_kick:dps_extra_inst", which is child of megafunction instantiation "ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i" File: /home/felipe/intelFPGA_lite/17.1/quartus/libraries/megafunctions/altera_pll.v Line: 768Info (12128): Elaborating entity "dprio_init" for hierarchy "ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i|dprio_init:dprio_init_inst" File: /home/felipe/intelFPGA_lite/17.1/quartus/libraries/megafunctions/altera_pll.v Line: 783Info (12131): Elaborated megafunction instantiation "ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i|dprio_init:dprio_init_inst", which is child of megafunction instantiation "ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i" File: /home/felipe/intelFPGA_lite/17.1/quartus/libraries/megafunctions/altera_pll.v Line: 783Info (12128): Elaborating entity "altera_pll_dps_lcell_comb" for hierarchy "ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i|altera_pll_dps_lcell_comb:lcell_cntsel_int_0" File: /home/felipe/intelFPGA_lite/17.1/quartus/libraries/megafunctions/altera_pll.v Line: 1960Info (12131): Elaborated megafunction instantiation "ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i|altera_pll_dps_lcell_comb:lcell_cntsel_int_0", which is child of megafunction instantiation "ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i" File: /home/felipe/intelFPGA_lite/17.1/quartus/libraries/megafunctions/altera_pll.v Line: 1960Info (12128): Elaborating entity "altera_pll_dps_lcell_comb" for hierarchy "ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i|altera_pll_dps_lcell_comb:lcell_cntsel_int_1" File: /home/felipe/intelFPGA_lite/17.1/quartus/libraries/megafunctions/altera_pll.v Line: 1971Info (12131): Elaborated megafunction instantiation "ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i|altera_pll_dps_lcell_comb:lcell_cntsel_int_1", which is child of megafunction instantiation "ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i" File: /home/felipe/intelFPGA_lite/17.1/quartus/libraries/megafunctions/altera_pll.v Line: 1971Info (12128): Elaborating entity "altera_pll_dps_lcell_comb" for hierarchy "ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i|altera_pll_dps_lcell_comb:lcell_cntsel_int_2" File: /home/felipe/intelFPGA_lite/17.1/quartus/libraries/megafunctions/altera_pll.v Line: 1982Info (12131): Elaborated megafunction instantiation "ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i|altera_pll_dps_lcell_comb:lcell_cntsel_int_2", which is child of megafunction instantiation "ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i" File: /home/felipe/intelFPGA_lite/17.1/quartus/libraries/megafunctions/altera_pll.v Line: 1982Info (12128): Elaborating entity "altera_pll_dps_lcell_comb" for hierarchy "ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i|altera_pll_dps_lcell_comb:lcell_cntsel_int_3" File: /home/felipe/intelFPGA_lite/17.1/quartus/libraries/megafunctions/altera_pll.v Line: 1993Info (12131): Elaborated megafunction instantiation "ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i|altera_pll_dps_lcell_comb:lcell_cntsel_int_3", which is child of megafunction instantiation "ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i" File: /home/felipe/intelFPGA_lite/17.1/quartus/libraries/megafunctions/altera_pll.v Line: 1993Info (12128): Elaborating entity "altera_pll_dps_lcell_comb" for hierarchy "ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i|altera_pll_dps_lcell_comb:lcell_cntsel_int_4" File: /home/felipe/intelFPGA_lite/17.1/quartus/libraries/megafunctions/altera_pll.v Line: 2004Info (12131): Elaborated megafunction instantiation "ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i|altera_pll_dps_lcell_comb:lcell_cntsel_int_4", which is child of megafunction instantiation "ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i" File: /home/felipe/intelFPGA_lite/17.1/quartus/libraries/megafunctions/altera_pll.v Line: 2004Info (12128): Elaborating entity "altera_cyclonev_pll" for hierarchy "ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i|altera_cyclonev_pll:cyclonev_pll" File: /home/felipe/intelFPGA_lite/17.1/quartus/libraries/megafunctions/altera_pll.v Line: 2223Warning (10034): Output port "extclk" at altera_cyclonev_pll.v(631) has no driver File: /home/felipe/intelFPGA_lite/17.1/quartus/libraries/megafunctions/altera_cyclonev_pll.v Line: 631Warning (10034): Output port "clkout[0]" at altera_cyclonev_pll.v(636) has no driver File: /home/felipe/intelFPGA_lite/17.1/quartus/libraries/megafunctions/altera_cyclonev_pll.v Line: 636Warning (10034): Output port "loaden" at altera_cyclonev_pll.v(640) has no driver File: /home/felipe/intelFPGA_lite/17.1/quartus/libraries/megafunctions/altera_cyclonev_pll.v Line: 640Warning (10034): Output port "lvdsclk" at altera_cyclonev_pll.v(641) has no driver File: /home/felipe/intelFPGA_lite/17.1/quartus/libraries/megafunctions/altera_cyclonev_pll.v Line: 641Info (12131): Elaborated megafunction instantiation "ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i|altera_cyclonev_pll:cyclonev_pll", which is child of megafunction instantiation "ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i" File: /home/felipe/intelFPGA_lite/17.1/quartus/libraries/megafunctions/altera_pll.v Line: 2223Info (12128): Elaborating entity "altera_cyclonev_pll_base" for hierarchy "ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i|altera_cyclonev_pll:cyclonev_pll|altera_cyclonev_pll_base:fpll_0" File: /home/felipe/intelFPGA_lite/17.1/quartus/libraries/megafunctions/altera_cyclonev_pll.v Line: 1152Info (12131): Elaborated megafunction instantiation "ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i|altera_cyclonev_pll:cyclonev_pll|altera_cyclonev_pll_base:fpll_0", which is child of megafunction instantiation "ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i" File: /home/felipe/intelFPGA_lite/17.1/quartus/libraries/megafunctions/altera_cyclonev_pll.v Line: 1152Info (12128): Elaborating entity "ulight_fifo_timecode_rx" for hierarchy "ulight_fifo:u0|ulight_fifo_timecode_rx:timecode_rx" File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/ulight_fifo.v Line: 385Info (12128): Elaborating entity "ulight_fifo_timecode_tx_data" for hierarchy "ulight_fifo:u0|ulight_fifo_timecode_tx_data:timecode_tx_data" File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/ulight_fifo.v Line: 396Info (12128): Elaborating entity "ulight_fifo_write_data_fifo_tx" for hierarchy "ulight_fifo:u0|ulight_fifo_write_data_fifo_tx:write_data_fifo_tx" File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/ulight_fifo.v Line: 426Info (12128): Elaborating entity "ulight_fifo_mm_interconnect_0" for hierarchy "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0" File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/ulight_fifo.v Line: 553Info (12128): Elaborating entity "altera_merlin_slave_translator" for hierarchy "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:led_pio_test_s1_translator" File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0.v Line: 1962Info (12128): Elaborating entity "altera_merlin_axi_master_ni" for hierarchy "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_axi_master_ni:hps_0_h2f_axi_master_agent" File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0.v Line: 3434Info (12128): Elaborating entity "altera_merlin_address_alignment" for hierarchy "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_axi_master_ni:hps_0_h2f_axi_master_agent|altera_merlin_address_alignment:align_address_to_size" File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_axi_master_ni.sv Line: 485Info (12128): Elaborating entity "altera_merlin_slave_agent" for hierarchy "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:led_pio_test_s1_agent" File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0.v Line: 3518Info (12128): Elaborating entity "altera_merlin_burst_uncompressor" for hierarchy "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:led_pio_test_s1_agent|altera_merlin_burst_uncompressor:uncompressor" File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_slave_agent.sv Line: 608Info (12128): Elaborating entity "altera_avalon_sc_fifo" for hierarchy "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rsp_fifo" File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0.v Line: 3559Info (12128): Elaborating entity "altera_avalon_sc_fifo" for hierarchy "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo" File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0.v Line: 3600Info (12128): Elaborating entity "ulight_fifo_mm_interconnect_0_router" for hierarchy "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_router:router" File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0.v Line: 7102Info (12128): Elaborating entity "ulight_fifo_mm_interconnect_0_router_default_decode" for hierarchy "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_router:router|ulight_fifo_mm_interconnect_0_router_default_decode:the_default_decode" File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_router.sv Line: 205Info (12128): Elaborating entity "ulight_fifo_mm_interconnect_0_router_002" for hierarchy "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_router_002:router_002" File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0.v Line: 7134Info (12128): Elaborating entity "ulight_fifo_mm_interconnect_0_router_002_default_decode" for hierarchy "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_router_002:router_002|ulight_fifo_mm_interconnect_0_router_002_default_decode:the_default_decode" File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_router_002.sv Line: 181Info (12128): Elaborating entity "altera_merlin_traffic_limiter" for hierarchy "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_traffic_limiter:hps_0_h2f_axi_master_wr_limiter" File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0.v Line: 7520Info (12128): Elaborating entity "altera_merlin_burst_adapter" for hierarchy "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter" File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0.v Line: 7620Info (12128): Elaborating entity "altera_merlin_burst_adapter_13_1" for hierarchy "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter" File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter.sv Line: 181Info (12128): Elaborating entity "altera_merlin_address_alignment" for hierarchy "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size" File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv Line: 778Info (12128): Elaborating entity "altera_merlin_burst_adapter_burstwrap_increment" for hierarchy "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_burstwrap_increment:the_burstwrap_increment" File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv Line: 979Info (12128): Elaborating entity "altera_merlin_burst_adapter_min" for hierarchy "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min" File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv Line: 1004Info (12128): Elaborating entity "altera_merlin_burst_adapter_subtractor" for hierarchy "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ab_sub" File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv Line: 157Info (12128): Elaborating entity "altera_merlin_burst_adapter_adder" for hierarchy "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ab_sub|altera_merlin_burst_adapter_adder:subtract" File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv Line: 88Info (12128): Elaborating entity "ulight_fifo_mm_interconnect_0_cmd_demux" for hierarchy "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_demux:cmd_demux" File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0.v Line: 8813Info (12128): Elaborating entity "ulight_fifo_mm_interconnect_0_cmd_mux" for hierarchy "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux" File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0.v Line: 8979Info (12128): Elaborating entity "altera_merlin_arbitrator" for hierarchy "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux|altera_merlin_arbitrator:arb" File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_cmd_mux.sv Line: 287Info (12128): Elaborating entity "altera_merlin_arb_adder" for hierarchy "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder" File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_arbitrator.sv Line: 169Info (12128): Elaborating entity "ulight_fifo_mm_interconnect_0_rsp_demux" for hierarchy "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux" File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0.v Line: 9485Info (12128): Elaborating entity "ulight_fifo_mm_interconnect_0_rsp_mux" for hierarchy "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_mux:rsp_mux" File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0.v Line: 10111Info (12128): Elaborating entity "altera_merlin_arbitrator" for hierarchy "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_mux:rsp_mux|altera_merlin_arbitrator:arb" File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_rsp_mux.sv Line: 630Info (12128): Elaborating entity "altera_merlin_arb_adder" for hierarchy "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_mux:rsp_mux|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder" File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_arbitrator.sv Line: 169Info (12128): Elaborating entity "ulight_fifo_mm_interconnect_0_avalon_st_adapter" for hierarchy "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter" File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0.v Line: 10283Info (12128): Elaborating entity "ulight_fifo_mm_interconnect_0_avalon_st_adapter_error_adapter_0" for hierarchy "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter|ulight_fifo_mm_interconnect_0_avalon_st_adapter_error_adapter_0:error_adapter_0" File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_avalon_st_adapter.v Line: 200Info (12128): Elaborating entity "altera_reset_controller" for hierarchy "ulight_fifo:u0|altera_reset_controller:rst_controller" File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/ulight_fifo.v Line: 616Info (12128): Elaborating entity "altera_reset_synchronizer" for hierarchy "ulight_fifo:u0|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1" File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_reset_controller.v Line: 208Info (12128): Elaborating entity "altera_reset_synchronizer" for hierarchy "ulight_fifo:u0|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_req_sync_uq1" File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_reset_controller.v Line: 220Info (12128): Elaborating entity "spw_ulight_con_top_x" for hierarchy "spw_ulight_con_top_x:A_SPW_TOP" File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/top_rtl/spw_fifo_ulight.v Line: 148Info (12128): Elaborating entity "top_spw_ultra_light" for hierarchy "spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW" File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/spw_ulight_con_top_x.v Line: 136Info (12128): Elaborating entity "FSM_SPW" for hierarchy "spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM" File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/top_spw_ultra_light.v Line: 112Info (12128): Elaborating entity "RX_SPW" for hierarchy "spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX" File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/top_spw_ultra_light.v Line: 134Info (12128): Elaborating entity "rx_buffer_fsm" for hierarchy "spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|rx_buffer_fsm:buffer_fsm" File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/rx_spw.v Line: 176Info (12128): Elaborating entity "rx_data_buffer_data_w" for hierarchy "spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|rx_data_buffer_data_w:buffer_data_flag" File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/rx_spw.v Line: 191Info (12128): Elaborating entity "rx_control_data_rdy" for hierarchy "spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|rx_control_data_rdy:control_data_rdy" File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/rx_spw.v Line: 213Info (12128): Elaborating entity "rx_data_control_p" for hierarchy "spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|rx_data_control_p:data_control" File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/rx_spw.v Line: 250Info (12128): Elaborating entity "bit_capture_data" for hierarchy "spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|bit_capture_data:capture_d" File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/rx_spw.v Line: 270Info (12128): Elaborating entity "bit_capture_control" for hierarchy "spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|bit_capture_control:capture_c" File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/rx_spw.v Line: 283Info (12128): Elaborating entity "counter_neg" for hierarchy "spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|counter_neg:cnt_neg" File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/rx_spw.v Line: 291Info (10264): Verilog HDL Case Statement information at counter_neg.v(58): all case item expressions in this case statement are onehot File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/counter_neg.v Line: 58Info (12128): Elaborating entity "rx_data_receive" for hierarchy "spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|rx_data_receive:rx_dtarcv" File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/rx_spw.v Line: 325Info (12128): Elaborating entity "TX_SPW" for hierarchy "spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX" File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/top_spw_ultra_light.v Line: 157Info (12128): Elaborating entity "tx_fsm_m" for hierarchy "spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm" File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/tx_spw.v Line: 117Info (12128): Elaborating entity "tx_fct_counter" for hierarchy "spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_counter:tx_fct_cnt" File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/tx_fsm_m.v Line: 789Info (12128): Elaborating entity "tx_fct_send" for hierarchy "spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_send:tx_fct_snd" File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/tx_fsm_m.v Line: 797Info (12128): Elaborating entity "tx_data_send" for hierarchy "spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_data_send:tx_data_snd" File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/tx_spw.v Line: 142Info (12128): Elaborating entity "fifo_rx" for hierarchy "spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data" File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/spw_ulight_con_top_x.v Line: 151Info (12128): Elaborating entity "mem_data" for hierarchy "spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx" File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/fifo_rx.v Line: 415Info (12128): Elaborating entity "fifo_tx" for hierarchy "spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data" File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/spw_ulight_con_top_x.v Line: 165Info (12128): Elaborating entity "debounce_db" for hierarchy "debounce_db:db_system_spwulight_b" File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/top_rtl/spw_fifo_ulight.v Line: 155Info (12128): Elaborating entity "clock_reduce" for hierarchy "clock_reduce:R_400_to_2_5_10_100_200_300MHZ" File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/top_rtl/spw_fifo_ulight.v Line: 163Info (12128): Elaborating entity "detector_tokens" for hierarchy "detector_tokens:m_x" File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/top_rtl/spw_fifo_ulight.v Line: 170Warning (10036): Verilog HDL or VHDL warning at detector_tokens.v(87): object "control_r" assigned a value but never read File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/DEBUG_VERILOG/detector_tokens.v Line: 87Warning (10858): Verilog HDL warning at detector_tokens.v(88): object control_p_r used but never assigned File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/DEBUG_VERILOG/detector_tokens.v Line: 88Warning (10036): Verilog HDL or VHDL warning at detector_tokens.v(92): object "dta_timec" assigned a value but never read File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/DEBUG_VERILOG/detector_tokens.v Line: 92Warning (10858): Verilog HDL warning at detector_tokens.v(93): object dta_timec_p used but never assigned File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/DEBUG_VERILOG/detector_tokens.v Line: 93Warning (10036): Verilog HDL or VHDL warning at detector_tokens.v(104): object "ready_control" assigned a value but never read File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/DEBUG_VERILOG/detector_tokens.v Line: 104Warning (10036): Verilog HDL or VHDL warning at detector_tokens.v(105): object "ready_data" assigned a value but never read File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/DEBUG_VERILOG/detector_tokens.v Line: 105Warning (10030): Net "control_p_r" at detector_tokens.v(88) has no driver or initial value, using a default initial value '0' File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/DEBUG_VERILOG/detector_tokens.v Line: 88Warning (10030): Net "dta_timec_p[7..0]" at detector_tokens.v(93) has no driver or initial value, using a default initial value '0' File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/DEBUG_VERILOG/detector_tokens.v Line: 93Warning (12030): Port "extclk" on the entity instantiation of "cyclonev_pll" is connected to a signal of width 1. The formal width of the signal in the module is 2. The extra bits will be left dangling without any fan-out logic. File: /home/felipe/intelFPGA_lite/17.1/quartus/libraries/megafunctions/altera_pll.v Line: 2223Warning (14284): Synthesized away the following node(s):Warning (14285): Synthesized away the following LCELL buffer node(s):Warning (14320): Synthesized away node "ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i|cntsel_temp[4]" File: /home/felipe/intelFPGA_lite/17.1/quartus/libraries/megafunctions/altera_pll.v Line: 424Warning (14320): Synthesized away node "ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i|cntsel_temp[3]" File: /home/felipe/intelFPGA_lite/17.1/quartus/libraries/megafunctions/altera_pll.v Line: 424Warning (14320): Synthesized away node "ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i|cntsel_temp[2]" File: /home/felipe/intelFPGA_lite/17.1/quartus/libraries/megafunctions/altera_pll.v Line: 424Warning (14320): Synthesized away node "ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i|cntsel_temp[1]" File: /home/felipe/intelFPGA_lite/17.1/quartus/libraries/megafunctions/altera_pll.v Line: 424Warning (14320): Synthesized away node "ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i|cntsel_temp[0]" File: /home/felipe/intelFPGA_lite/17.1/quartus/libraries/megafunctions/altera_pll.v Line: 424Warning (14320): Synthesized away node "ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i|gnd" File: /home/felipe/intelFPGA_lite/17.1/quartus/libraries/megafunctions/altera_pll.v Line: 426Info (13014): Ignored 2 buffer(s)Info (13019): Ignored 2 SOFT buffer(s)Warning (12241): 32 hierarchies have connectivity warnings - see the Connectivity Checks report folderInfo (284007): State machine "|SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state" will be implemented as a safe state machine. File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv Line: 398Info (284007): State machine "|SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state" will be implemented as a safe state machine. File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv Line: 398Info (284007): State machine "|SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state" will be implemented as a safe state machine. File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv Line: 398Info (284007): State machine "|SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state" will be implemented as a safe state machine. File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv Line: 398Info (284007): State machine "|SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state" will be implemented as a safe state machine. File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv Line: 398Info (284007): State machine "|SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state" will be implemented as a safe state machine. File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv Line: 398Info (284007): State machine "|SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state" will be implemented as a safe state machine. File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv Line: 398Info (284007): State machine "|SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state" will be implemented as a safe state machine. File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv Line: 398Info (284007): State machine "|SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state" will be implemented as a safe state machine. File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv Line: 398Info (284007): State machine "|SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state" will be implemented as a safe state machine. File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv Line: 398Info (284007): State machine "|SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state" will be implemented as a safe state machine. File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv Line: 398Info (284007): State machine "|SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state" will be implemented as a safe state machine. File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv Line: 398Info (284007): State machine "|SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state" will be implemented as a safe state machine. File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv Line: 398Info (284007): State machine "|SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state" will be implemented as a safe state machine. File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv Line: 398Info (284007): State machine "|SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state" will be implemented as a safe state machine. File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv Line: 398Info (284007): State machine "|SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state" will be implemented as a safe state machine. File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv Line: 398Info (284007): State machine "|SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state" will be implemented as a safe state machine. File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv Line: 398Info (284007): State machine "|SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state" will be implemented as a safe state machine. File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv Line: 398Info (284007): State machine "|SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state" will be implemented as a safe state machine. File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv Line: 398Info (284007): State machine "|SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state" will be implemented as a safe state machine. File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv Line: 398Info (284007): State machine "|SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state" will be implemented as a safe state machine. File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv Line: 398Info (284007): State machine "|SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state" will be implemented as a safe state machine. File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv Line: 398Info (284007): State machine "|SPW_ULIGHT_FIFO|detector_tokens:m_x|state_data_process" will be implemented as a safe state machine. File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/DEBUG_VERILOG/detector_tokens.v Line: 51Info (284007): State machine "|SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|state_open_slot" will be implemented as a safe state machine. File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/fifo_rx.v Line: 60Info (284007): State machine "|SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|state_data_write" will be implemented as a safe state machine. File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/fifo_rx.v Line: 54Info (284007): State machine "|SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|state_data_read" will be implemented as a safe state machine. File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/fifo_rx.v Line: 57Info (284007): State machine "|SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i|dps_extra_kick:dps_extra_inst|dps_current_state" will be implemented as a safe state machine. File: /home/felipe/intelFPGA_lite/17.1/quartus/libraries/megafunctions/altera_pll.v Line: 2672Info (284007): State machine "|SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|state_data_read" will be implemented as a safe state machine. File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/fifo_tx.v Line: 52Info (284007): State machine "|SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|state_tx" will be implemented as a safe state machine. File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/tx_fsm_m.v Line: 92Info (284007): State machine "|SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_send:tx_fct_snd|state_fct_send" will be implemented as a safe state machine. File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/tx_fct_send.v Line: 45Info (284007): State machine "|SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_send:tx_fct_snd|state_fct_send_p" will be implemented as a safe state machine. File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/tx_fct_send.v Line: 48Info (284007): State machine "|SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_counter:tx_fct_cnt|state_fct_p" will be implemented as a safe state machine. File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/tx_fct_counter.v Line: 47Info (284007): State machine "|SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|state_data_write" will be implemented as a safe state machine. File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/fifo_tx.v Line: 49Info (284007): State machine "|SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_counter:tx_fct_cnt|state_fct_receive" will be implemented as a safe state machine. File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/tx_fct_counter.v Line: 44Info (284007): State machine "|SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|state_fsm" will be implemented as a safe state machine. File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/fsm_spw.v Line: 71Warning (13024): Output pins are stuck at VCC or GNDWarning (13410): Pin "LED[6]" is stuck at GND File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/top_rtl/spw_fifo_ulight.v Line: 17Info (286031): Timing-Driven Synthesis is running on partition "Top"Info (17049): 1382 registers lost all their fanouts during netlist optimizations.Info (286031): Timing-Driven Synthesis is running on partition "ulight_fifo_hps_0_hps_io_border:border"Info (144001): Generated suppressed messages file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/output_files/spw_fifo_ulight.map.smsgWarning (35014): Found 1 partition definition(s) having no effect on incremental compilationWarning (35015): Partition "ulight_fifo_hps_0_hps_io_border:border" has no effect on incremental compilationInfo (16010): Generating hard_block partition "hard_block:auto_generated_inst"Info (16011): Adding 15 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELLWarning (21074): Design contains 1 input pin(s) that do not drive logicWarning (15610): No output dependent on input pin "KEY[0]" File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/top_rtl/spw_fifo_ulight.v Line: 3Info (21057): Implemented 8595 device resources after synthesis - the final resource count might be differentInfo (21058): Implemented 5 input pinsInfo (21059): Implemented 10 output pinsInfo (21061): Implemented 8569 logic cellsInfo: Quartus Prime Analysis & Synthesis was successful. 0 errors, 53 warningsInfo: Peak virtual memory: 1310 megabytesInfo: Processing ended: Mon Feb 5 00:52:10 2018Info: Elapsed time: 00:05:18Info: Total CPU time (on all processors): 00:05:46+------------------------------------------+; Analysis & Synthesis Suppressed Messages ;+------------------------------------------+The suppressed messages can be found in /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/output_files/spw_fifo_ulight.map.smsg.