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[/] [spacewiresystemc/] [trunk/] [altera_work/] [spw_fifo_ulight/] [ulight_fifo/] [synthesis/] [submodules/] [hps_sdram.v] - Rev 40
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// hps_sdram.v // This file was auto-generated from altera_mem_if_hps_emif_hw.tcl. If you edit it your changes // will probably be lost. // // Generated using ACDS version 17.1 593 `timescale 1 ps / 1 ps module hps_sdram ( input wire pll_ref_clk, // pll_ref_clk.clk input wire global_reset_n, // global_reset.reset_n input wire soft_reset_n, // soft_reset.reset_n output wire [12:0] mem_a, // memory.mem_a output wire [2:0] mem_ba, // .mem_ba output wire [0:0] mem_ck, // .mem_ck output wire [0:0] mem_ck_n, // .mem_ck_n output wire [0:0] mem_cke, // .mem_cke output wire [0:0] mem_cs_n, // .mem_cs_n output wire [0:0] mem_dm, // .mem_dm output wire [0:0] mem_ras_n, // .mem_ras_n output wire [0:0] mem_cas_n, // .mem_cas_n output wire [0:0] mem_we_n, // .mem_we_n output wire mem_reset_n, // .mem_reset_n inout wire [7:0] mem_dq, // .mem_dq inout wire [0:0] mem_dqs, // .mem_dqs inout wire [0:0] mem_dqs_n, // .mem_dqs_n output wire [0:0] mem_odt, // .mem_odt input wire oct_rzqin // oct.rzqin ); wire pll_afi_clk_clk; // pll:afi_clk -> [c0:afi_clk, p0:afi_clk] wire pll_afi_half_clk_clk; // pll:afi_half_clk -> [c0:afi_half_clk, p0:afi_half_clk] wire [4:0] p0_afi_afi_rlat; // p0:afi_rlat -> c0:afi_rlat wire p0_afi_afi_cal_success; // p0:afi_cal_success -> c0:afi_cal_success wire [79:0] p0_afi_afi_rdata; // p0:afi_rdata -> c0:afi_rdata wire [3:0] p0_afi_afi_wlat; // p0:afi_wlat -> c0:afi_wlat wire p0_afi_afi_cal_fail; // p0:afi_cal_fail -> c0:afi_cal_fail wire [0:0] p0_afi_afi_rdata_valid; // p0:afi_rdata_valid -> c0:afi_rdata_valid wire p0_afi_reset_reset; // p0:afi_reset_n -> c0:afi_reset_n wire [4:0] c0_afi_afi_rdata_en_full; // c0:afi_rdata_en_full -> p0:afi_rdata_en_full wire [0:0] c0_afi_afi_rst_n; // c0:afi_rst_n -> p0:afi_rst_n wire [4:0] c0_afi_afi_dqs_burst; // c0:afi_dqs_burst -> p0:afi_dqs_burst wire [19:0] c0_afi_afi_addr; // c0:afi_addr -> p0:afi_addr wire [9:0] c0_afi_afi_dm; // c0:afi_dm -> p0:afi_dm wire [0:0] c0_afi_afi_mem_clk_disable; // c0:afi_mem_clk_disable -> p0:afi_mem_clk_disable wire [0:0] c0_afi_afi_we_n; // c0:afi_we_n -> p0:afi_we_n wire [4:0] c0_afi_afi_rdata_en; // c0:afi_rdata_en -> p0:afi_rdata_en wire [1:0] c0_afi_afi_odt; // c0:afi_odt -> p0:afi_odt wire [0:0] c0_afi_afi_ras_n; // c0:afi_ras_n -> p0:afi_ras_n wire [1:0] c0_afi_afi_cke; // c0:afi_cke -> p0:afi_cke wire [4:0] c0_afi_afi_wdata_valid; // c0:afi_wdata_valid -> p0:afi_wdata_valid wire [79:0] c0_afi_afi_wdata; // c0:afi_wdata -> p0:afi_wdata wire [2:0] c0_afi_afi_ba; // c0:afi_ba -> p0:afi_ba wire [0:0] c0_afi_afi_cas_n; // c0:afi_cas_n -> p0:afi_cas_n wire [1:0] c0_afi_afi_cs_n; // c0:afi_cs_n -> p0:afi_cs_n wire [7:0] c0_hard_phy_cfg_cfg_tmrd; // c0:cfg_tmrd -> p0:cfg_tmrd wire [23:0] c0_hard_phy_cfg_cfg_dramconfig; // c0:cfg_dramconfig -> p0:cfg_dramconfig wire [7:0] c0_hard_phy_cfg_cfg_rowaddrwidth; // c0:cfg_rowaddrwidth -> p0:cfg_rowaddrwidth wire [7:0] c0_hard_phy_cfg_cfg_devicewidth; // c0:cfg_devicewidth -> p0:cfg_devicewidth wire [15:0] c0_hard_phy_cfg_cfg_trefi; // c0:cfg_trefi -> p0:cfg_trefi wire [7:0] c0_hard_phy_cfg_cfg_tcl; // c0:cfg_tcl -> p0:cfg_tcl wire [7:0] c0_hard_phy_cfg_cfg_csaddrwidth; // c0:cfg_csaddrwidth -> p0:cfg_csaddrwidth wire [7:0] c0_hard_phy_cfg_cfg_coladdrwidth; // c0:cfg_coladdrwidth -> p0:cfg_coladdrwidth wire [7:0] c0_hard_phy_cfg_cfg_trfc; // c0:cfg_trfc -> p0:cfg_trfc wire [7:0] c0_hard_phy_cfg_cfg_addlat; // c0:cfg_addlat -> p0:cfg_addlat wire [7:0] c0_hard_phy_cfg_cfg_bankaddrwidth; // c0:cfg_bankaddrwidth -> p0:cfg_bankaddrwidth wire [7:0] c0_hard_phy_cfg_cfg_interfacewidth; // c0:cfg_interfacewidth -> p0:cfg_interfacewidth wire [7:0] c0_hard_phy_cfg_cfg_twr; // c0:cfg_twr -> p0:cfg_twr wire [7:0] c0_hard_phy_cfg_cfg_caswrlat; // c0:cfg_caswrlat -> p0:cfg_caswrlat wire p0_ctl_clk_clk; // p0:ctl_clk -> c0:ctl_clk wire p0_ctl_reset_reset; // p0:ctl_reset_n -> c0:ctl_reset_n wire p0_io_int_io_intaficalfail; // p0:io_intaficalfail -> c0:io_intaficalfail wire p0_io_int_io_intaficalsuccess; // p0:io_intaficalsuccess -> c0:io_intaficalsuccess wire [15:0] oct_oct_sharing_parallelterminationcontrol; // oct:parallelterminationcontrol -> p0:parallelterminationcontrol wire [15:0] oct_oct_sharing_seriesterminationcontrol; // oct:seriesterminationcontrol -> p0:seriesterminationcontrol wire pll_pll_sharing_pll_write_clk; // pll:pll_write_clk -> p0:pll_write_clk wire pll_pll_sharing_pll_avl_clk; // pll:pll_avl_clk -> p0:pll_avl_clk wire pll_pll_sharing_pll_write_clk_pre_phy_clk; // pll:pll_write_clk_pre_phy_clk -> p0:pll_write_clk_pre_phy_clk wire pll_pll_sharing_pll_addr_cmd_clk; // pll:pll_addr_cmd_clk -> p0:pll_addr_cmd_clk wire pll_pll_sharing_pll_config_clk; // pll:pll_config_clk -> p0:pll_config_clk wire pll_pll_sharing_pll_avl_phy_clk; // pll:pll_avl_phy_clk -> p0:pll_avl_phy_clk wire pll_pll_sharing_afi_phy_clk; // pll:afi_phy_clk -> p0:afi_phy_clk wire pll_pll_sharing_pll_mem_clk; // pll:pll_mem_clk -> p0:pll_mem_clk wire pll_pll_sharing_pll_locked; // pll:pll_locked -> p0:pll_locked wire pll_pll_sharing_pll_mem_phy_clk; // pll:pll_mem_phy_clk -> p0:pll_mem_phy_clk wire p0_dll_clk_clk; // p0:dll_clk -> dll:clk wire p0_dll_sharing_dll_pll_locked; // p0:dll_pll_locked -> dll:dll_pll_locked wire [6:0] dll_dll_sharing_dll_delayctrl; // dll:dll_delayctrl -> p0:dll_delayctrl hps_sdram_pll pll ( .global_reset_n (global_reset_n), // global_reset.reset_n .pll_ref_clk (pll_ref_clk), // pll_ref_clk.clk .afi_clk (pll_afi_clk_clk), // afi_clk.clk .afi_half_clk (pll_afi_half_clk_clk), // afi_half_clk.clk .pll_mem_clk (pll_pll_sharing_pll_mem_clk), // pll_sharing.pll_mem_clk .pll_write_clk (pll_pll_sharing_pll_write_clk), // .pll_write_clk .pll_locked (pll_pll_sharing_pll_locked), // .pll_locked .pll_write_clk_pre_phy_clk (pll_pll_sharing_pll_write_clk_pre_phy_clk), // .pll_write_clk_pre_phy_clk .pll_addr_cmd_clk (pll_pll_sharing_pll_addr_cmd_clk), // .pll_addr_cmd_clk .pll_avl_clk (pll_pll_sharing_pll_avl_clk), // .pll_avl_clk .pll_config_clk (pll_pll_sharing_pll_config_clk), // .pll_config_clk .pll_mem_phy_clk (pll_pll_sharing_pll_mem_phy_clk), // .pll_mem_phy_clk .afi_phy_clk (pll_pll_sharing_afi_phy_clk), // .afi_phy_clk .pll_avl_phy_clk (pll_pll_sharing_pll_avl_phy_clk) // .pll_avl_phy_clk ); hps_sdram_p0 p0 ( .global_reset_n (global_reset_n), // global_reset.reset_n .soft_reset_n (soft_reset_n), // soft_reset.reset_n .afi_reset_n (p0_afi_reset_reset), // afi_reset.reset_n .afi_reset_export_n (), // afi_reset_export.reset_n .ctl_reset_n (p0_ctl_reset_reset), // ctl_reset.reset_n .afi_clk (pll_afi_clk_clk), // afi_clk.clk .afi_half_clk (pll_afi_half_clk_clk), // afi_half_clk.clk .ctl_clk (p0_ctl_clk_clk), // ctl_clk.clk .avl_clk (), // avl_clk.clk .avl_reset_n (), // avl_reset.reset_n .scc_clk (), // scc_clk.clk .scc_reset_n (), // scc_reset.reset_n .avl_address (), // avl.address .avl_write (), // .write .avl_writedata (), // .writedata .avl_read (), // .read .avl_readdata (), // .readdata .avl_waitrequest (), // .waitrequest .dll_clk (p0_dll_clk_clk), // dll_clk.clk .afi_addr (c0_afi_afi_addr), // afi.afi_addr .afi_ba (c0_afi_afi_ba), // .afi_ba .afi_cke (c0_afi_afi_cke), // .afi_cke .afi_cs_n (c0_afi_afi_cs_n), // .afi_cs_n .afi_ras_n (c0_afi_afi_ras_n), // .afi_ras_n .afi_we_n (c0_afi_afi_we_n), // .afi_we_n .afi_cas_n (c0_afi_afi_cas_n), // .afi_cas_n .afi_rst_n (c0_afi_afi_rst_n), // .afi_rst_n .afi_odt (c0_afi_afi_odt), // .afi_odt .afi_dqs_burst (c0_afi_afi_dqs_burst), // .afi_dqs_burst .afi_wdata_valid (c0_afi_afi_wdata_valid), // .afi_wdata_valid .afi_wdata (c0_afi_afi_wdata), // .afi_wdata .afi_dm (c0_afi_afi_dm), // .afi_dm .afi_rdata (p0_afi_afi_rdata), // .afi_rdata .afi_rdata_en (c0_afi_afi_rdata_en), // .afi_rdata_en .afi_rdata_en_full (c0_afi_afi_rdata_en_full), // .afi_rdata_en_full .afi_rdata_valid (p0_afi_afi_rdata_valid), // .afi_rdata_valid .afi_wlat (p0_afi_afi_wlat), // .afi_wlat .afi_rlat (p0_afi_afi_rlat), // .afi_rlat .afi_cal_success (p0_afi_afi_cal_success), // .afi_cal_success .afi_cal_fail (p0_afi_afi_cal_fail), // .afi_cal_fail .scc_data (), // scc.scc_data .scc_dqs_ena (), // .scc_dqs_ena .scc_dqs_io_ena (), // .scc_dqs_io_ena .scc_dq_ena (), // .scc_dq_ena .scc_dm_ena (), // .scc_dm_ena .capture_strobe_tracking (), // .capture_strobe_tracking .scc_upd (), // .scc_upd .cfg_addlat (c0_hard_phy_cfg_cfg_addlat), // hard_phy_cfg.cfg_addlat .cfg_bankaddrwidth (c0_hard_phy_cfg_cfg_bankaddrwidth), // .cfg_bankaddrwidth .cfg_caswrlat (c0_hard_phy_cfg_cfg_caswrlat), // .cfg_caswrlat .cfg_coladdrwidth (c0_hard_phy_cfg_cfg_coladdrwidth), // .cfg_coladdrwidth .cfg_csaddrwidth (c0_hard_phy_cfg_cfg_csaddrwidth), // .cfg_csaddrwidth .cfg_devicewidth (c0_hard_phy_cfg_cfg_devicewidth), // .cfg_devicewidth .cfg_dramconfig (c0_hard_phy_cfg_cfg_dramconfig), // .cfg_dramconfig .cfg_interfacewidth (c0_hard_phy_cfg_cfg_interfacewidth), // .cfg_interfacewidth .cfg_rowaddrwidth (c0_hard_phy_cfg_cfg_rowaddrwidth), // .cfg_rowaddrwidth .cfg_tcl (c0_hard_phy_cfg_cfg_tcl), // .cfg_tcl .cfg_tmrd (c0_hard_phy_cfg_cfg_tmrd), // .cfg_tmrd .cfg_trefi (c0_hard_phy_cfg_cfg_trefi), // .cfg_trefi .cfg_trfc (c0_hard_phy_cfg_cfg_trfc), // .cfg_trfc .cfg_twr (c0_hard_phy_cfg_cfg_twr), // .cfg_twr .afi_mem_clk_disable (c0_afi_afi_mem_clk_disable), // afi_mem_clk_disable.afi_mem_clk_disable .pll_mem_clk (pll_pll_sharing_pll_mem_clk), // pll_sharing.pll_mem_clk .pll_write_clk (pll_pll_sharing_pll_write_clk), // .pll_write_clk .pll_locked (pll_pll_sharing_pll_locked), // .pll_locked .pll_write_clk_pre_phy_clk (pll_pll_sharing_pll_write_clk_pre_phy_clk), // .pll_write_clk_pre_phy_clk .pll_addr_cmd_clk (pll_pll_sharing_pll_addr_cmd_clk), // .pll_addr_cmd_clk .pll_avl_clk (pll_pll_sharing_pll_avl_clk), // .pll_avl_clk .pll_config_clk (pll_pll_sharing_pll_config_clk), // .pll_config_clk .pll_mem_phy_clk (pll_pll_sharing_pll_mem_phy_clk), // .pll_mem_phy_clk .afi_phy_clk (pll_pll_sharing_afi_phy_clk), // .afi_phy_clk .pll_avl_phy_clk (pll_pll_sharing_pll_avl_phy_clk), // .pll_avl_phy_clk .dll_pll_locked (p0_dll_sharing_dll_pll_locked), // dll_sharing.dll_pll_locked .dll_delayctrl (dll_dll_sharing_dll_delayctrl), // .dll_delayctrl .seriesterminationcontrol (oct_oct_sharing_seriesterminationcontrol), // oct_sharing.seriesterminationcontrol .parallelterminationcontrol (oct_oct_sharing_parallelterminationcontrol), // .parallelterminationcontrol .mem_a (mem_a), // memory.mem_a .mem_ba (mem_ba), // .mem_ba .mem_ck (mem_ck), // .mem_ck .mem_ck_n (mem_ck_n), // .mem_ck_n .mem_cke (mem_cke), // .mem_cke .mem_cs_n (mem_cs_n), // .mem_cs_n .mem_dm (mem_dm), // .mem_dm .mem_ras_n (mem_ras_n), // .mem_ras_n .mem_cas_n (mem_cas_n), // .mem_cas_n .mem_we_n (mem_we_n), // .mem_we_n .mem_reset_n (mem_reset_n), // .mem_reset_n .mem_dq (mem_dq), // .mem_dq .mem_dqs (mem_dqs), // .mem_dqs .mem_dqs_n (mem_dqs_n), // .mem_dqs_n .mem_odt (mem_odt), // .mem_odt .io_intaficalfail (p0_io_int_io_intaficalfail), // io_int.io_intaficalfail .io_intaficalsuccess (p0_io_int_io_intaficalsuccess), // .io_intaficalsuccess .csr_soft_reset_req (1'b0), // (terminated) .io_intaddrdout (64'b0000000000000000000000000000000000000000000000000000000000000000), // (terminated) .io_intbadout (12'b000000000000), // (terminated) .io_intcasndout (4'b0000), // (terminated) .io_intckdout (4'b0000), // (terminated) .io_intckedout (8'b00000000), // (terminated) .io_intckndout (4'b0000), // (terminated) .io_intcsndout (8'b00000000), // (terminated) .io_intdmdout (20'b00000000000000000000), // (terminated) .io_intdqdin (), // (terminated) .io_intdqdout (180'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000), // (terminated) .io_intdqoe (90'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000), // (terminated) .io_intdqsbdout (20'b00000000000000000000), // (terminated) .io_intdqsboe (10'b0000000000), // (terminated) .io_intdqsdout (20'b00000000000000000000), // (terminated) .io_intdqslogicdqsena (10'b0000000000), // (terminated) .io_intdqslogicfiforeset (5'b00000), // (terminated) .io_intdqslogicincrdataen (10'b0000000000), // (terminated) .io_intdqslogicincwrptr (10'b0000000000), // (terminated) .io_intdqslogicoct (10'b0000000000), // (terminated) .io_intdqslogicrdatavalid (), // (terminated) .io_intdqslogicreadlatency (25'b0000000000000000000000000), // (terminated) .io_intdqsoe (10'b0000000000), // (terminated) .io_intodtdout (8'b00000000), // (terminated) .io_intrasndout (4'b0000), // (terminated) .io_intresetndout (4'b0000), // (terminated) .io_intwendout (4'b0000), // (terminated) .io_intafirlat (), // (terminated) .io_intafiwlat () // (terminated) ); altera_mem_if_hhp_qseq_synth_top #( .MEM_IF_DM_WIDTH (1), .MEM_IF_DQS_WIDTH (1), .MEM_IF_CS_WIDTH (1), .MEM_IF_DQ_WIDTH (8) ) seq ( ); altera_mem_if_hard_memory_controller_top_cyclonev #( .MEM_IF_DQS_WIDTH (1), .MEM_IF_CS_WIDTH (1), .MEM_IF_CHIP_BITS (1), .MEM_IF_CLK_PAIR_COUNT (1), .CSR_ADDR_WIDTH (10), .CSR_DATA_WIDTH (8), .CSR_BE_WIDTH (1), .AVL_ADDR_WIDTH (22), .AVL_DATA_WIDTH (16), .AVL_SIZE_WIDTH (3), .AVL_DATA_WIDTH_PORT_0 (1), .AVL_ADDR_WIDTH_PORT_0 (1), .AVL_NUM_SYMBOLS_PORT_0 (1), .LSB_WFIFO_PORT_0 (5), .MSB_WFIFO_PORT_0 (5), .LSB_RFIFO_PORT_0 (5), .MSB_RFIFO_PORT_0 (5), .AVL_DATA_WIDTH_PORT_1 (1), .AVL_ADDR_WIDTH_PORT_1 (1), .AVL_NUM_SYMBOLS_PORT_1 (1), .LSB_WFIFO_PORT_1 (5), .MSB_WFIFO_PORT_1 (5), .LSB_RFIFO_PORT_1 (5), .MSB_RFIFO_PORT_1 (5), .AVL_DATA_WIDTH_PORT_2 (1), .AVL_ADDR_WIDTH_PORT_2 (1), .AVL_NUM_SYMBOLS_PORT_2 (1), .LSB_WFIFO_PORT_2 (5), .MSB_WFIFO_PORT_2 (5), .LSB_RFIFO_PORT_2 (5), .MSB_RFIFO_PORT_2 (5), .AVL_DATA_WIDTH_PORT_3 (1), .AVL_ADDR_WIDTH_PORT_3 (1), .AVL_NUM_SYMBOLS_PORT_3 (1), .LSB_WFIFO_PORT_3 (5), .MSB_WFIFO_PORT_3 (5), .LSB_RFIFO_PORT_3 (5), .MSB_RFIFO_PORT_3 (5), .AVL_DATA_WIDTH_PORT_4 (1), .AVL_ADDR_WIDTH_PORT_4 (1), .AVL_NUM_SYMBOLS_PORT_4 (1), .LSB_WFIFO_PORT_4 (5), .MSB_WFIFO_PORT_4 (5), .LSB_RFIFO_PORT_4 (5), .MSB_RFIFO_PORT_4 (5), .AVL_DATA_WIDTH_PORT_5 (1), .AVL_ADDR_WIDTH_PORT_5 (1), .AVL_NUM_SYMBOLS_PORT_5 (1), .LSB_WFIFO_PORT_5 (5), .MSB_WFIFO_PORT_5 (5), .LSB_RFIFO_PORT_5 (5), .MSB_RFIFO_PORT_5 (5), .ENUM_ATTR_COUNTER_ONE_RESET ("DISABLED"), .ENUM_ATTR_COUNTER_ZERO_RESET ("DISABLED"), .ENUM_ATTR_STATIC_CONFIG_VALID ("DISABLED"), .ENUM_AUTO_PCH_ENABLE_0 ("DISABLED"), .ENUM_AUTO_PCH_ENABLE_1 ("DISABLED"), .ENUM_AUTO_PCH_ENABLE_2 ("DISABLED"), .ENUM_AUTO_PCH_ENABLE_3 ("DISABLED"), .ENUM_AUTO_PCH_ENABLE_4 ("DISABLED"), .ENUM_AUTO_PCH_ENABLE_5 ("DISABLED"), .ENUM_CAL_REQ ("DISABLED"), .ENUM_CFG_BURST_LENGTH ("BL_8"), .ENUM_CFG_INTERFACE_WIDTH ("DWIDTH_8"), .ENUM_CFG_SELF_RFSH_EXIT_CYCLES ("SELF_RFSH_EXIT_CYCLES_512"), .ENUM_CFG_STARVE_LIMIT ("STARVE_LIMIT_10"), .ENUM_CFG_TYPE ("DDR3"), .ENUM_CLOCK_OFF_0 ("DISABLED"), .ENUM_CLOCK_OFF_1 ("DISABLED"), .ENUM_CLOCK_OFF_2 ("DISABLED"), .ENUM_CLOCK_OFF_3 ("DISABLED"), .ENUM_CLOCK_OFF_4 ("DISABLED"), .ENUM_CLOCK_OFF_5 ("DISABLED"), .ENUM_CLR_INTR ("NO_CLR_INTR"), .ENUM_CMD_PORT_IN_USE_0 ("FALSE"), .ENUM_CMD_PORT_IN_USE_1 ("FALSE"), .ENUM_CMD_PORT_IN_USE_2 ("FALSE"), .ENUM_CMD_PORT_IN_USE_3 ("FALSE"), .ENUM_CMD_PORT_IN_USE_4 ("FALSE"), .ENUM_CMD_PORT_IN_USE_5 ("FALSE"), .ENUM_CPORT0_RDY_ALMOST_FULL ("NOT_FULL"), .ENUM_CPORT0_RFIFO_MAP ("FIFO_0"), .ENUM_CPORT0_TYPE ("DISABLE"), .ENUM_CPORT0_WFIFO_MAP ("FIFO_0"), .ENUM_CPORT1_RDY_ALMOST_FULL ("NOT_FULL"), .ENUM_CPORT1_RFIFO_MAP ("FIFO_0"), .ENUM_CPORT1_TYPE ("DISABLE"), .ENUM_CPORT1_WFIFO_MAP ("FIFO_0"), .ENUM_CPORT2_RDY_ALMOST_FULL ("NOT_FULL"), .ENUM_CPORT2_RFIFO_MAP ("FIFO_0"), .ENUM_CPORT2_TYPE ("DISABLE"), .ENUM_CPORT2_WFIFO_MAP ("FIFO_0"), .ENUM_CPORT3_RDY_ALMOST_FULL ("NOT_FULL"), .ENUM_CPORT3_RFIFO_MAP ("FIFO_0"), .ENUM_CPORT3_TYPE ("DISABLE"), .ENUM_CPORT3_WFIFO_MAP ("FIFO_0"), .ENUM_CPORT4_RDY_ALMOST_FULL ("NOT_FULL"), .ENUM_CPORT4_RFIFO_MAP ("FIFO_0"), .ENUM_CPORT4_TYPE ("DISABLE"), .ENUM_CPORT4_WFIFO_MAP ("FIFO_0"), .ENUM_CPORT5_RDY_ALMOST_FULL ("NOT_FULL"), .ENUM_CPORT5_RFIFO_MAP ("FIFO_0"), .ENUM_CPORT5_TYPE ("DISABLE"), .ENUM_CPORT5_WFIFO_MAP ("FIFO_0"), .ENUM_CTL_ADDR_ORDER ("CHIP_ROW_BANK_COL"), .ENUM_CTL_ECC_ENABLED ("CTL_ECC_DISABLED"), .ENUM_CTL_ECC_RMW_ENABLED ("CTL_ECC_RMW_DISABLED"), .ENUM_CTL_REGDIMM_ENABLED ("REGDIMM_DISABLED"), .ENUM_CTL_USR_REFRESH ("CTL_USR_REFRESH_DISABLED"), .ENUM_CTRL_WIDTH ("DATA_WIDTH_16_BIT"), .ENUM_DELAY_BONDING ("BONDING_LATENCY_0"), .ENUM_DFX_BYPASS_ENABLE ("DFX_BYPASS_DISABLED"), .ENUM_DISABLE_MERGING ("MERGING_ENABLED"), .ENUM_ECC_DQ_WIDTH ("ECC_DQ_WIDTH_0"), .ENUM_ENABLE_ATPG ("DISABLED"), .ENUM_ENABLE_BONDING_0 ("DISABLED"), .ENUM_ENABLE_BONDING_1 ("DISABLED"), .ENUM_ENABLE_BONDING_2 ("DISABLED"), .ENUM_ENABLE_BONDING_3 ("DISABLED"), .ENUM_ENABLE_BONDING_4 ("DISABLED"), .ENUM_ENABLE_BONDING_5 ("DISABLED"), .ENUM_ENABLE_BONDING_WRAPBACK ("DISABLED"), .ENUM_ENABLE_DQS_TRACKING ("ENABLED"), .ENUM_ENABLE_ECC_CODE_OVERWRITES ("DISABLED"), .ENUM_ENABLE_FAST_EXIT_PPD ("DISABLED"), .ENUM_ENABLE_INTR ("DISABLED"), .ENUM_ENABLE_NO_DM ("DISABLED"), .ENUM_ENABLE_PIPELINEGLOBAL ("DISABLED"), .ENUM_GANGED_ARF ("DISABLED"), .ENUM_GEN_DBE ("GEN_DBE_DISABLED"), .ENUM_GEN_SBE ("GEN_SBE_DISABLED"), .ENUM_INC_SYNC ("FIFO_SET_2"), .ENUM_LOCAL_IF_CS_WIDTH ("ADDR_WIDTH_0"), .ENUM_MASK_CORR_DROPPED_INTR ("DISABLED"), .ENUM_MASK_DBE_INTR ("DISABLED"), .ENUM_MASK_SBE_INTR ("DISABLED"), .ENUM_MEM_IF_AL ("AL_0"), .ENUM_MEM_IF_BANKADDR_WIDTH ("ADDR_WIDTH_3"), .ENUM_MEM_IF_BURSTLENGTH ("MEM_IF_BURSTLENGTH_8"), .ENUM_MEM_IF_COLADDR_WIDTH ("ADDR_WIDTH_8"), .ENUM_MEM_IF_CS_PER_RANK ("MEM_IF_CS_PER_RANK_1"), .ENUM_MEM_IF_CS_WIDTH ("MEM_IF_CS_WIDTH_1"), .ENUM_MEM_IF_DQ_PER_CHIP ("MEM_IF_DQ_PER_CHIP_8"), .ENUM_MEM_IF_DQS_WIDTH ("DQS_WIDTH_1"), .ENUM_MEM_IF_DWIDTH ("MEM_IF_DWIDTH_8"), .ENUM_MEM_IF_MEMTYPE ("DDR3_SDRAM"), .ENUM_MEM_IF_ROWADDR_WIDTH ("ADDR_WIDTH_12"), .ENUM_MEM_IF_SPEEDBIN ("DDR3_800_5_5_5"), .ENUM_MEM_IF_TCCD ("TCCD_4"), .ENUM_MEM_IF_TCL ("TCL_7"), .ENUM_MEM_IF_TCWL ("TCWL_6"), .ENUM_MEM_IF_TFAW ("TFAW_12"), .ENUM_MEM_IF_TMRD ("TMRD_4"), .ENUM_MEM_IF_TRAS ("TRAS_13"), .ENUM_MEM_IF_TRC ("TRC_17"), .ENUM_MEM_IF_TRCD ("TRCD_5"), .ENUM_MEM_IF_TRP ("TRP_5"), .ENUM_MEM_IF_TRRD ("TRRD_3"), .ENUM_MEM_IF_TRTP ("TRTP_3"), .ENUM_MEM_IF_TWR ("TWR_5"), .ENUM_MEM_IF_TWTR ("TWTR_2"), .ENUM_MMR_CFG_MEM_BL ("MP_BL_8"), .ENUM_OUTPUT_REGD ("DISABLED"), .ENUM_PDN_EXIT_CYCLES ("SLOW_EXIT"), .ENUM_PORT0_WIDTH ("PORT_32_BIT"), .ENUM_PORT1_WIDTH ("PORT_32_BIT"), .ENUM_PORT2_WIDTH ("PORT_32_BIT"), .ENUM_PORT3_WIDTH ("PORT_32_BIT"), .ENUM_PORT4_WIDTH ("PORT_32_BIT"), .ENUM_PORT5_WIDTH ("PORT_32_BIT"), .ENUM_PRIORITY_0_0 ("WEIGHT_0"), .ENUM_PRIORITY_0_1 ("WEIGHT_0"), .ENUM_PRIORITY_0_2 ("WEIGHT_0"), .ENUM_PRIORITY_0_3 ("WEIGHT_0"), .ENUM_PRIORITY_0_4 ("WEIGHT_0"), .ENUM_PRIORITY_0_5 ("WEIGHT_0"), .ENUM_PRIORITY_1_0 ("WEIGHT_0"), .ENUM_PRIORITY_1_1 ("WEIGHT_0"), .ENUM_PRIORITY_1_2 ("WEIGHT_0"), .ENUM_PRIORITY_1_3 ("WEIGHT_0"), .ENUM_PRIORITY_1_4 ("WEIGHT_0"), .ENUM_PRIORITY_1_5 ("WEIGHT_0"), .ENUM_PRIORITY_2_0 ("WEIGHT_0"), .ENUM_PRIORITY_2_1 ("WEIGHT_0"), .ENUM_PRIORITY_2_2 ("WEIGHT_0"), .ENUM_PRIORITY_2_3 ("WEIGHT_0"), .ENUM_PRIORITY_2_4 ("WEIGHT_0"), .ENUM_PRIORITY_2_5 ("WEIGHT_0"), .ENUM_PRIORITY_3_0 ("WEIGHT_0"), .ENUM_PRIORITY_3_1 ("WEIGHT_0"), .ENUM_PRIORITY_3_2 ("WEIGHT_0"), .ENUM_PRIORITY_3_3 ("WEIGHT_0"), .ENUM_PRIORITY_3_4 ("WEIGHT_0"), .ENUM_PRIORITY_3_5 ("WEIGHT_0"), .ENUM_PRIORITY_4_0 ("WEIGHT_0"), .ENUM_PRIORITY_4_1 ("WEIGHT_0"), .ENUM_PRIORITY_4_2 ("WEIGHT_0"), .ENUM_PRIORITY_4_3 ("WEIGHT_0"), .ENUM_PRIORITY_4_4 ("WEIGHT_0"), .ENUM_PRIORITY_4_5 ("WEIGHT_0"), .ENUM_PRIORITY_5_0 ("WEIGHT_0"), .ENUM_PRIORITY_5_1 ("WEIGHT_0"), .ENUM_PRIORITY_5_2 ("WEIGHT_0"), .ENUM_PRIORITY_5_3 ("WEIGHT_0"), .ENUM_PRIORITY_5_4 ("WEIGHT_0"), .ENUM_PRIORITY_5_5 ("WEIGHT_0"), .ENUM_PRIORITY_6_0 ("WEIGHT_0"), .ENUM_PRIORITY_6_1 ("WEIGHT_0"), .ENUM_PRIORITY_6_2 ("WEIGHT_0"), .ENUM_PRIORITY_6_3 ("WEIGHT_0"), .ENUM_PRIORITY_6_4 ("WEIGHT_0"), .ENUM_PRIORITY_6_5 ("WEIGHT_0"), .ENUM_PRIORITY_7_0 ("WEIGHT_0"), .ENUM_PRIORITY_7_1 ("WEIGHT_0"), .ENUM_PRIORITY_7_2 ("WEIGHT_0"), .ENUM_PRIORITY_7_3 ("WEIGHT_0"), .ENUM_PRIORITY_7_4 ("WEIGHT_0"), .ENUM_PRIORITY_7_5 ("WEIGHT_0"), .ENUM_RCFG_STATIC_WEIGHT_0 ("WEIGHT_0"), .ENUM_RCFG_STATIC_WEIGHT_1 ("WEIGHT_0"), .ENUM_RCFG_STATIC_WEIGHT_2 ("WEIGHT_0"), .ENUM_RCFG_STATIC_WEIGHT_3 ("WEIGHT_0"), .ENUM_RCFG_STATIC_WEIGHT_4 ("WEIGHT_0"), .ENUM_RCFG_STATIC_WEIGHT_5 ("WEIGHT_0"), .ENUM_RCFG_USER_PRIORITY_0 ("PRIORITY_1"), .ENUM_RCFG_USER_PRIORITY_1 ("PRIORITY_1"), .ENUM_RCFG_USER_PRIORITY_2 ("PRIORITY_1"), .ENUM_RCFG_USER_PRIORITY_3 ("PRIORITY_1"), .ENUM_RCFG_USER_PRIORITY_4 ("PRIORITY_1"), .ENUM_RCFG_USER_PRIORITY_5 ("PRIORITY_1"), .ENUM_RD_DWIDTH_0 ("DWIDTH_0"), .ENUM_RD_DWIDTH_1 ("DWIDTH_0"), .ENUM_RD_DWIDTH_2 ("DWIDTH_0"), .ENUM_RD_DWIDTH_3 ("DWIDTH_0"), .ENUM_RD_DWIDTH_4 ("DWIDTH_0"), .ENUM_RD_DWIDTH_5 ("DWIDTH_0"), .ENUM_RD_FIFO_IN_USE_0 ("FALSE"), .ENUM_RD_FIFO_IN_USE_1 ("FALSE"), .ENUM_RD_FIFO_IN_USE_2 ("FALSE"), .ENUM_RD_FIFO_IN_USE_3 ("FALSE"), .ENUM_RD_PORT_INFO_0 ("USE_NO"), .ENUM_RD_PORT_INFO_1 ("USE_NO"), .ENUM_RD_PORT_INFO_2 ("USE_NO"), .ENUM_RD_PORT_INFO_3 ("USE_NO"), .ENUM_RD_PORT_INFO_4 ("USE_NO"), .ENUM_RD_PORT_INFO_5 ("USE_NO"), .ENUM_READ_ODT_CHIP ("ODT_DISABLED"), .ENUM_REORDER_DATA ("DATA_REORDERING"), .ENUM_RFIFO0_CPORT_MAP ("CMD_PORT_0"), .ENUM_RFIFO1_CPORT_MAP ("CMD_PORT_0"), .ENUM_RFIFO2_CPORT_MAP ("CMD_PORT_0"), .ENUM_RFIFO3_CPORT_MAP ("CMD_PORT_0"), .ENUM_SINGLE_READY_0 ("CONCATENATE_RDY"), .ENUM_SINGLE_READY_1 ("CONCATENATE_RDY"), .ENUM_SINGLE_READY_2 ("CONCATENATE_RDY"), .ENUM_SINGLE_READY_3 ("CONCATENATE_RDY"), .ENUM_STATIC_WEIGHT_0 ("WEIGHT_0"), .ENUM_STATIC_WEIGHT_1 ("WEIGHT_0"), .ENUM_STATIC_WEIGHT_2 ("WEIGHT_0"), .ENUM_STATIC_WEIGHT_3 ("WEIGHT_0"), .ENUM_STATIC_WEIGHT_4 ("WEIGHT_0"), .ENUM_STATIC_WEIGHT_5 ("WEIGHT_0"), .ENUM_SYNC_MODE_0 ("ASYNCHRONOUS"), .ENUM_SYNC_MODE_1 ("ASYNCHRONOUS"), .ENUM_SYNC_MODE_2 ("ASYNCHRONOUS"), .ENUM_SYNC_MODE_3 ("ASYNCHRONOUS"), .ENUM_SYNC_MODE_4 ("ASYNCHRONOUS"), .ENUM_SYNC_MODE_5 ("ASYNCHRONOUS"), .ENUM_TEST_MODE ("NORMAL_MODE"), .ENUM_THLD_JAR1_0 ("THRESHOLD_32"), .ENUM_THLD_JAR1_1 ("THRESHOLD_32"), .ENUM_THLD_JAR1_2 ("THRESHOLD_32"), .ENUM_THLD_JAR1_3 ("THRESHOLD_32"), .ENUM_THLD_JAR1_4 ("THRESHOLD_32"), .ENUM_THLD_JAR1_5 ("THRESHOLD_32"), .ENUM_THLD_JAR2_0 ("THRESHOLD_16"), .ENUM_THLD_JAR2_1 ("THRESHOLD_16"), .ENUM_THLD_JAR2_2 ("THRESHOLD_16"), .ENUM_THLD_JAR2_3 ("THRESHOLD_16"), .ENUM_THLD_JAR2_4 ("THRESHOLD_16"), .ENUM_THLD_JAR2_5 ("THRESHOLD_16"), .ENUM_USE_ALMOST_EMPTY_0 ("EMPTY"), .ENUM_USE_ALMOST_EMPTY_1 ("EMPTY"), .ENUM_USE_ALMOST_EMPTY_2 ("EMPTY"), .ENUM_USE_ALMOST_EMPTY_3 ("EMPTY"), .ENUM_USER_ECC_EN ("DISABLE"), .ENUM_USER_PRIORITY_0 ("PRIORITY_1"), .ENUM_USER_PRIORITY_1 ("PRIORITY_1"), .ENUM_USER_PRIORITY_2 ("PRIORITY_1"), .ENUM_USER_PRIORITY_3 ("PRIORITY_1"), .ENUM_USER_PRIORITY_4 ("PRIORITY_1"), .ENUM_USER_PRIORITY_5 ("PRIORITY_1"), .ENUM_WFIFO0_CPORT_MAP ("CMD_PORT_0"), .ENUM_WFIFO0_RDY_ALMOST_FULL ("NOT_FULL"), .ENUM_WFIFO1_CPORT_MAP ("CMD_PORT_0"), .ENUM_WFIFO1_RDY_ALMOST_FULL ("NOT_FULL"), .ENUM_WFIFO2_CPORT_MAP ("CMD_PORT_0"), .ENUM_WFIFO2_RDY_ALMOST_FULL ("NOT_FULL"), .ENUM_WFIFO3_CPORT_MAP ("CMD_PORT_0"), .ENUM_WFIFO3_RDY_ALMOST_FULL ("NOT_FULL"), .ENUM_WR_DWIDTH_0 ("DWIDTH_0"), .ENUM_WR_DWIDTH_1 ("DWIDTH_0"), .ENUM_WR_DWIDTH_2 ("DWIDTH_0"), .ENUM_WR_DWIDTH_3 ("DWIDTH_0"), .ENUM_WR_DWIDTH_4 ("DWIDTH_0"), .ENUM_WR_DWIDTH_5 ("DWIDTH_0"), .ENUM_WR_FIFO_IN_USE_0 ("FALSE"), .ENUM_WR_FIFO_IN_USE_1 ("FALSE"), .ENUM_WR_FIFO_IN_USE_2 ("FALSE"), .ENUM_WR_FIFO_IN_USE_3 ("FALSE"), .ENUM_WR_PORT_INFO_0 ("USE_NO"), .ENUM_WR_PORT_INFO_1 ("USE_NO"), .ENUM_WR_PORT_INFO_2 ("USE_NO"), .ENUM_WR_PORT_INFO_3 ("USE_NO"), .ENUM_WR_PORT_INFO_4 ("USE_NO"), .ENUM_WR_PORT_INFO_5 ("USE_NO"), .ENUM_WRITE_ODT_CHIP ("ODT_DISABLED"), .INTG_MEM_AUTO_PD_CYCLES (0), .INTG_CYC_TO_RLD_JARS_0 (1), .INTG_CYC_TO_RLD_JARS_1 (1), .INTG_CYC_TO_RLD_JARS_2 (1), .INTG_CYC_TO_RLD_JARS_3 (1), .INTG_CYC_TO_RLD_JARS_4 (1), .INTG_CYC_TO_RLD_JARS_5 (1), .INTG_EXTRA_CTL_CLK_ACT_TO_ACT (0), .INTG_EXTRA_CTL_CLK_ACT_TO_ACT_DIFF_BANK (0), .INTG_EXTRA_CTL_CLK_ACT_TO_PCH (0), .INTG_EXTRA_CTL_CLK_ACT_TO_RDWR (0), .INTG_EXTRA_CTL_CLK_ARF_PERIOD (0), .INTG_EXTRA_CTL_CLK_ARF_TO_VALID (0), .INTG_EXTRA_CTL_CLK_FOUR_ACT_TO_ACT (0), .INTG_EXTRA_CTL_CLK_PCH_ALL_TO_VALID (0), .INTG_EXTRA_CTL_CLK_PCH_TO_VALID (0), .INTG_EXTRA_CTL_CLK_PDN_PERIOD (0), .INTG_EXTRA_CTL_CLK_PDN_TO_VALID (0), .INTG_EXTRA_CTL_CLK_RD_AP_TO_VALID (0), .INTG_EXTRA_CTL_CLK_RD_TO_PCH (0), .INTG_EXTRA_CTL_CLK_RD_TO_RD (0), .INTG_EXTRA_CTL_CLK_RD_TO_RD_DIFF_CHIP (0), .INTG_EXTRA_CTL_CLK_RD_TO_WR (2), .INTG_EXTRA_CTL_CLK_RD_TO_WR_BC (2), .INTG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP (2), .INTG_EXTRA_CTL_CLK_SRF_TO_VALID (0), .INTG_EXTRA_CTL_CLK_SRF_TO_ZQ_CAL (0), .INTG_EXTRA_CTL_CLK_WR_AP_TO_VALID (0), .INTG_EXTRA_CTL_CLK_WR_TO_PCH (0), .INTG_EXTRA_CTL_CLK_WR_TO_RD (3), .INTG_EXTRA_CTL_CLK_WR_TO_RD_BC (3), .INTG_EXTRA_CTL_CLK_WR_TO_RD_DIFF_CHIP (3), .INTG_EXTRA_CTL_CLK_WR_TO_WR (0), .INTG_EXTRA_CTL_CLK_WR_TO_WR_DIFF_CHIP (0), .INTG_MEM_IF_TREFI (2101), .INTG_MEM_IF_TRFC (23), .INTG_RCFG_SUM_WT_PRIORITY_0 (0), .INTG_RCFG_SUM_WT_PRIORITY_1 (0), .INTG_RCFG_SUM_WT_PRIORITY_2 (0), .INTG_RCFG_SUM_WT_PRIORITY_3 (0), .INTG_RCFG_SUM_WT_PRIORITY_4 (0), .INTG_RCFG_SUM_WT_PRIORITY_5 (0), .INTG_RCFG_SUM_WT_PRIORITY_6 (0), .INTG_RCFG_SUM_WT_PRIORITY_7 (0), .INTG_SUM_WT_PRIORITY_0 (0), .INTG_SUM_WT_PRIORITY_1 (0), .INTG_SUM_WT_PRIORITY_2 (0), .INTG_SUM_WT_PRIORITY_3 (0), .INTG_SUM_WT_PRIORITY_4 (0), .INTG_SUM_WT_PRIORITY_5 (0), .INTG_SUM_WT_PRIORITY_6 (0), .INTG_SUM_WT_PRIORITY_7 (0), .INTG_POWER_SAVING_EXIT_CYCLES (5), .INTG_MEM_CLK_ENTRY_CYCLES (10), .ENUM_ENABLE_BURST_INTERRUPT ("DISABLED"), .ENUM_ENABLE_BURST_TERMINATE ("DISABLED"), .AFI_RATE_RATIO (1), .AFI_ADDR_WIDTH (13), .AFI_BANKADDR_WIDTH (3), .AFI_CONTROL_WIDTH (1), .AFI_CS_WIDTH (1), .AFI_DM_WIDTH (2), .AFI_DQ_WIDTH (16), .AFI_ODT_WIDTH (1), .AFI_WRITE_DQS_WIDTH (1), .AFI_RLAT_WIDTH (6), .AFI_WLAT_WIDTH (6), .HARD_PHY (1) ) c0 ( .afi_clk (pll_afi_clk_clk), // afi_clk.clk .afi_reset_n (p0_afi_reset_reset), // afi_reset.reset_n .ctl_reset_n (p0_ctl_reset_reset), // ctl_reset.reset_n .afi_half_clk (pll_afi_half_clk_clk), // afi_half_clk.clk .ctl_clk (p0_ctl_clk_clk), // ctl_clk.clk .local_init_done (), // status.local_init_done .local_cal_success (), // .local_cal_success .local_cal_fail (), // .local_cal_fail .afi_addr (c0_afi_afi_addr), // afi.afi_addr .afi_ba (c0_afi_afi_ba), // .afi_ba .afi_cke (c0_afi_afi_cke), // .afi_cke .afi_cs_n (c0_afi_afi_cs_n), // .afi_cs_n .afi_ras_n (c0_afi_afi_ras_n), // .afi_ras_n .afi_we_n (c0_afi_afi_we_n), // .afi_we_n .afi_cas_n (c0_afi_afi_cas_n), // .afi_cas_n .afi_rst_n (c0_afi_afi_rst_n), // .afi_rst_n .afi_odt (c0_afi_afi_odt), // .afi_odt .afi_mem_clk_disable (c0_afi_afi_mem_clk_disable), // .afi_mem_clk_disable .afi_init_req (), // .afi_init_req .afi_cal_req (), // .afi_cal_req .afi_seq_busy (), // .afi_seq_busy .afi_ctl_refresh_done (), // .afi_ctl_refresh_done .afi_ctl_long_idle (), // .afi_ctl_long_idle .afi_dqs_burst (c0_afi_afi_dqs_burst), // .afi_dqs_burst .afi_wdata_valid (c0_afi_afi_wdata_valid), // .afi_wdata_valid .afi_wdata (c0_afi_afi_wdata), // .afi_wdata .afi_dm (c0_afi_afi_dm), // .afi_dm .afi_rdata (p0_afi_afi_rdata), // .afi_rdata .afi_rdata_en (c0_afi_afi_rdata_en), // .afi_rdata_en .afi_rdata_en_full (c0_afi_afi_rdata_en_full), // .afi_rdata_en_full .afi_rdata_valid (p0_afi_afi_rdata_valid), // .afi_rdata_valid .afi_wlat (p0_afi_afi_wlat), // .afi_wlat .afi_rlat (p0_afi_afi_rlat), // .afi_rlat .afi_cal_success (p0_afi_afi_cal_success), // .afi_cal_success .afi_cal_fail (p0_afi_afi_cal_fail), // .afi_cal_fail .cfg_addlat (c0_hard_phy_cfg_cfg_addlat), // hard_phy_cfg.cfg_addlat .cfg_bankaddrwidth (c0_hard_phy_cfg_cfg_bankaddrwidth), // .cfg_bankaddrwidth .cfg_caswrlat (c0_hard_phy_cfg_cfg_caswrlat), // .cfg_caswrlat .cfg_coladdrwidth (c0_hard_phy_cfg_cfg_coladdrwidth), // .cfg_coladdrwidth .cfg_csaddrwidth (c0_hard_phy_cfg_cfg_csaddrwidth), // .cfg_csaddrwidth .cfg_devicewidth (c0_hard_phy_cfg_cfg_devicewidth), // .cfg_devicewidth .cfg_dramconfig (c0_hard_phy_cfg_cfg_dramconfig), // .cfg_dramconfig .cfg_interfacewidth (c0_hard_phy_cfg_cfg_interfacewidth), // .cfg_interfacewidth .cfg_rowaddrwidth (c0_hard_phy_cfg_cfg_rowaddrwidth), // .cfg_rowaddrwidth .cfg_tcl (c0_hard_phy_cfg_cfg_tcl), // .cfg_tcl .cfg_tmrd (c0_hard_phy_cfg_cfg_tmrd), // .cfg_tmrd .cfg_trefi (c0_hard_phy_cfg_cfg_trefi), // .cfg_trefi .cfg_trfc (c0_hard_phy_cfg_cfg_trfc), // .cfg_trfc .cfg_twr (c0_hard_phy_cfg_cfg_twr), // .cfg_twr .io_intaficalfail (p0_io_int_io_intaficalfail), // io_int.io_intaficalfail .io_intaficalsuccess (p0_io_int_io_intaficalsuccess), // .io_intaficalsuccess .mp_cmd_clk_0 (1'b0), // (terminated) .mp_cmd_reset_n_0 (1'b1), // (terminated) .mp_cmd_clk_1 (1'b0), // (terminated) .mp_cmd_reset_n_1 (1'b1), // (terminated) .mp_cmd_clk_2 (1'b0), // (terminated) .mp_cmd_reset_n_2 (1'b1), // (terminated) .mp_cmd_clk_3 (1'b0), // (terminated) .mp_cmd_reset_n_3 (1'b1), // (terminated) .mp_cmd_clk_4 (1'b0), // (terminated) .mp_cmd_reset_n_4 (1'b1), // (terminated) .mp_cmd_clk_5 (1'b0), // (terminated) .mp_cmd_reset_n_5 (1'b1), // (terminated) .mp_rfifo_clk_0 (1'b0), // (terminated) .mp_rfifo_reset_n_0 (1'b1), // (terminated) .mp_wfifo_clk_0 (1'b0), // (terminated) .mp_wfifo_reset_n_0 (1'b1), // (terminated) .mp_rfifo_clk_1 (1'b0), // (terminated) .mp_rfifo_reset_n_1 (1'b1), // (terminated) .mp_wfifo_clk_1 (1'b0), // (terminated) .mp_wfifo_reset_n_1 (1'b1), // (terminated) .mp_rfifo_clk_2 (1'b0), // (terminated) .mp_rfifo_reset_n_2 (1'b1), // (terminated) .mp_wfifo_clk_2 (1'b0), // (terminated) .mp_wfifo_reset_n_2 (1'b1), // (terminated) .mp_rfifo_clk_3 (1'b0), // (terminated) .mp_rfifo_reset_n_3 (1'b1), // (terminated) .mp_wfifo_clk_3 (1'b0), // (terminated) .mp_wfifo_reset_n_3 (1'b1), // (terminated) .csr_clk (1'b0), // (terminated) .csr_reset_n (1'b1), // (terminated) .avl_ready_0 (), // (terminated) .avl_burstbegin_0 (1'b0), // (terminated) .avl_addr_0 (1'b0), // (terminated) .avl_rdata_valid_0 (), // (terminated) .avl_rdata_0 (), // (terminated) .avl_wdata_0 (1'b0), // (terminated) .avl_be_0 (1'b0), // (terminated) .avl_read_req_0 (1'b0), // (terminated) .avl_write_req_0 (1'b0), // (terminated) .avl_size_0 (3'b000), // (terminated) .avl_ready_1 (), // (terminated) .avl_burstbegin_1 (1'b0), // (terminated) .avl_addr_1 (1'b0), // (terminated) .avl_rdata_valid_1 (), // (terminated) .avl_rdata_1 (), // (terminated) .avl_wdata_1 (1'b0), // (terminated) .avl_be_1 (1'b0), // (terminated) .avl_read_req_1 (1'b0), // (terminated) .avl_write_req_1 (1'b0), // (terminated) .avl_size_1 (3'b000), // (terminated) .avl_ready_2 (), // (terminated) .avl_burstbegin_2 (1'b0), // (terminated) .avl_addr_2 (1'b0), // (terminated) .avl_rdata_valid_2 (), // (terminated) .avl_rdata_2 (), // (terminated) .avl_wdata_2 (1'b0), // (terminated) .avl_be_2 (1'b0), // (terminated) .avl_read_req_2 (1'b0), // (terminated) .avl_write_req_2 (1'b0), // (terminated) .avl_size_2 (3'b000), // (terminated) .avl_ready_3 (), // (terminated) .avl_burstbegin_3 (1'b0), // (terminated) .avl_addr_3 (1'b0), // (terminated) .avl_rdata_valid_3 (), // (terminated) .avl_rdata_3 (), // (terminated) .avl_wdata_3 (1'b0), // (terminated) .avl_be_3 (1'b0), // (terminated) .avl_read_req_3 (1'b0), // (terminated) .avl_write_req_3 (1'b0), // (terminated) .avl_size_3 (3'b000), // (terminated) .avl_ready_4 (), // (terminated) .avl_burstbegin_4 (1'b0), // (terminated) .avl_addr_4 (1'b0), // (terminated) .avl_rdata_valid_4 (), // (terminated) .avl_rdata_4 (), // (terminated) .avl_wdata_4 (1'b0), // (terminated) .avl_be_4 (1'b0), // (terminated) .avl_read_req_4 (1'b0), // (terminated) .avl_write_req_4 (1'b0), // (terminated) .avl_size_4 (3'b000), // (terminated) .avl_ready_5 (), // (terminated) .avl_burstbegin_5 (1'b0), // (terminated) .avl_addr_5 (1'b0), // (terminated) .avl_rdata_valid_5 (), // (terminated) .avl_rdata_5 (), // (terminated) .avl_wdata_5 (1'b0), // (terminated) .avl_be_5 (1'b0), // (terminated) .avl_read_req_5 (1'b0), // (terminated) .avl_write_req_5 (1'b0), // (terminated) .avl_size_5 (3'b000), // (terminated) .csr_write_req (1'b0), // (terminated) .csr_read_req (1'b0), // (terminated) .csr_waitrequest (), // (terminated) .csr_addr (10'b0000000000), // (terminated) .csr_be (1'b0), // (terminated) .csr_wdata (8'b00000000), // (terminated) .csr_rdata (), // (terminated) .csr_rdata_valid (), // (terminated) .local_multicast (1'b0), // (terminated) .local_refresh_req (1'b0), // (terminated) .local_refresh_chip (1'b0), // (terminated) .local_refresh_ack (), // (terminated) .local_self_rfsh_req (1'b0), // (terminated) .local_self_rfsh_chip (1'b0), // (terminated) .local_self_rfsh_ack (), // (terminated) .local_deep_powerdn_req (1'b0), // (terminated) .local_deep_powerdn_chip (1'b0), // (terminated) .local_deep_powerdn_ack (), // (terminated) .local_powerdn_ack (), // (terminated) .local_priority (1'b0), // (terminated) .bonding_in_1 (4'b0000), // (terminated) .bonding_in_2 (6'b000000), // (terminated) .bonding_in_3 (6'b000000), // (terminated) .bonding_out_1 (), // (terminated) .bonding_out_2 (), // (terminated) .bonding_out_3 () // (terminated) ); altera_mem_if_oct_cyclonev #( .OCT_TERM_CONTROL_WIDTH (16) ) oct ( .oct_rzqin (oct_rzqin), // oct.rzqin .seriesterminationcontrol (oct_oct_sharing_seriesterminationcontrol), // oct_sharing.seriesterminationcontrol .parallelterminationcontrol (oct_oct_sharing_parallelterminationcontrol) // .parallelterminationcontrol ); altera_mem_if_dll_cyclonev #( .DLL_DELAY_CTRL_WIDTH (7), .DLL_OFFSET_CTRL_WIDTH (6), .DELAY_BUFFER_MODE ("HIGH"), .DELAY_CHAIN_LENGTH (8), .DLL_INPUT_FREQUENCY_PS_STR ("3333 ps") ) dll ( .clk (p0_dll_clk_clk), // clk.clk .dll_pll_locked (p0_dll_sharing_dll_pll_locked), // dll_sharing.dll_pll_locked .dll_delayctrl (dll_dll_sharing_dll_delayctrl) // .dll_delayctrl ); endmodule