Subversion Repositories spi2ram

module top_module ();
	reg clk=0;
 
    reg spi_sck,spi_cs,spi_mosi,spi_clk ;
 
    wire spi_miso; 
    wire[16:0] nvram_addr;
    wire nvram_en;
    wire nvram_g;									
    wire nvram_w;
 
    reg sys_clk;
    reg sys_rstn;
 
    parameter		clockperiod = 10;	
    parameter		clockperiod1 = 8;		
 
 
 
    initial 
    begin
        sys_rstn = 0;
        sys_clk = 0;
        #15
        sys_rstn = 1;
    end
 
    initial
    begin
        spi_sck = 1'b0;
        //repeat(1000) spi_sck = #(clockperiod/2)~spi_sck;
    end
 
 
 
	initial `probe_start;   // Start the timing diagram
 
	// A testbench
 
	initial begin
     #80;
	 spi_cs = 1'b0; 	
	 #20;spi_cs = 1'b1; 
        #20;  
        spi_cs = 1'b0; 	  
	  #20; 
        spi_cs = 1'b1; 
        #20;  
        spi_cs = 1'b0; 
        datasend(8'h02);
        datasend(8'h10);
        datasend(8'h33);
        datasend(8'haa);
        datasend(8'haa);
        datasend(8'haa);
	 spi_cs = 1'b1; 
	 #20; 
	 spi_cs = 1'b0; 
	 #20; 
	 spi_cs = 1'b1; 
 
	 $finish;            // Quit the simulation
	end
 
 
 
    task datasend(input [7:0] senddata);
        begin 
            #5; 
        spi_sck = 1'b0;
        spi_mosi = senddata[7];
        #5; 
            spi_sck = 1'b1;
        #5;  
            spi_sck = 1'b0;
            spi_mosi = senddata[6];
        #5;  
            spi_sck = 1'b1;
        #5;   
            spi_sck = 1'b0;
            spi_mosi = senddata[5];
        #5;
        spi_sck = 1'b1;
        #5;        
        spi_sck = 1'b0;
            spi_mosi = senddata[4];
        #5;
        spi_sck = 1'b1;
        #5;       
        spi_sck = 1'b0;
            spi_mosi = senddata[3];
        #5;
        spi_sck = 1'b1;
        #5;       
        spi_sck = 1'b0;
            spi_mosi = senddata[2];
        #5;
        spi_sck = 1'b1;
        #5;       
        spi_sck = 1'b0;
            spi_mosi = senddata[1];
        #5;
        spi_sck = 1'b1;
        #5;       
        spi_sck = 1'b0;
            spi_mosi = senddata[0];
        #5;
        spi_sck = 1'b1;
        #5;
        spi_sck = 1'b0; 
        #5;
 
        end
    endtask
    spi_slave_nvram spi_slave_nvram_sim	( 
    .sys_rstn(sys_rstn),
    .spi_sck(spi_sck),
    .spi_cs(spi_cs),
    .spi_mosi(spi_mosi),
    .spi_miso(spi_miso)
 
    );	
 
 
    `probe(spi_sck);        // Probe signal "clk"
    `probe(spi_mosi);        // Probe signal "clk" 
	`probe(sys_rstn);        // Probe signal "clk"
	`probe(spi_cs);        // Probe signal "clk"
    `probe(spi_miso);        // Probe signal "clk" 
 
endmodule
 
module spi_slave_nvram
(
input sys_clk,
input sys_rstn,
//spi interface
input spi_sck,
input spi_cs,
input spi_mosi,
output  spi_miso, 
//nvram interface 
    output reg   [7:0] nvram_dq ,
    output reg   [7:0] nvram_dq1, 
    output reg   [7:0] nvram_dq2 
 
);
 
    reg [7:0] rINBUF;
    reg [7:0] rOUTBUF;
    assign spi_miso = rOUTBUF[7];
    reg rCStart[1:0]; 
    reg [5:0] rCnt;
    wire sCnt8;
    assign sCnt8 = (~|(rCnt[2:0])) & (|rCnt[5:3]);
 
    reg rFlagData;
 
 
    always@(posedge spi_sck or posedge spi_cs )begin
        if(spi_cs)begin
            rINBUF <= 'b0;
            rCnt <= 'b0;
        end
        else
        begin 
               rINBUF <= {rINBUF[6:0], spi_mosi}; 
               rCnt <= rCnt + 1'b1;   
        end
    end
 
    reg [7:0] rCmd;
    always@( negedge spi_sck) begin
        if(sCnt8)begin
            case( rCnt[4:3])  
                2'b00: begin nvram_dq <= rINBUF;  rOUTBUF <= 8'hf1; end
                2'b01: begin nvram_dq1 <= rINBUF; rOUTBUF <= 8'haa; end
                2'b10: begin nvram_dq2 <= rINBUF; rOUTBUF <= 8'h80; end
                2'b11: begin nvram_dq <= rINBUF;  rOUTBUF <= 8'h22; end
            endcase
 
        end
        else begin
            rOUTBUF <= {rOUTBUF[6:0],1'b0}; 
        end 
    end
 
    `probe(rCnt);
 
    `probe(spi_sck);
    `probe(rINBUF);
    `probe(rOUTBUF);
    `probe(sCnt8);
    `probe(nvram_dq);
    `probe(nvram_dq1);
    `probe(nvram_dq2);
 
 
endmodule