Subversion Repositories ssram

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<b><font size=+2 face="Helvetica, Arial"
color=#bf0000>Project Name: SSRAM interface</font></b>
<p>
<font size=+1><b><u>Description</u></b></font>
<P>
The 'SSRAM interface core' is a collection of designs for easy integration of synchronous srams (ZBT srams) in your designs.<br>
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<font size=+1><b><u>Core Description</u></b></font>
<p>
Currently 2 designs have been implemented. ssram_conn and cs_ssram.<br>
The entity ssram_conn provides a standard interface to the ssram. It provides the pipeline correction and all IO structures needed for high speed bidirectional data transfers (including full FPGA IO-cell usage).<br>
The entity cs_ssram uses the standard interface to turn the ssram into a cycle shared memory. Because ZBTs feature zero bus latency there is no impact on throughput. Thus providing a low-cost alternative to dual-ported rams.<br>
<br>
The design uses attributes to preserve all tri-state enables. Standard compiler strategy is to optimize redundant logic resulting in a single output/tristate enable signal. For maximum performance all output enables have to be preserved. Xilinx and Altera devices (and others probably too) can use their high speed paths to the IO-blocks only if every IO-block has its own output-enable. For ASIC implementations it results in the lowest Tco and Tsu possible.<br>
The attributes used are for Leonardo Spectrum. Please tell me what attributes should be used for other compilers (like synplicity).
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<font size=+1><b><u>Implementations:</u></b></font>
<li>Standard interface for pipelined ZBTs</li>
<li>Dual ported memory using cycle shared ssram</li>
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<font size=+1><b><u>Current Status:</u></b></font>
<ul>
<li>Designs are available in VHDL from OpenCores CVS via <a href="http://www.opencores.org/cvsweb.shtml/">cvsweb</a> or via <a href="/cvsmodule.shtml">cvsget</a></li>
<li>ToDo: 
<ul>
<li>Modify the standard interface so it supports pipelined and flow-through ZBTs</li>
<li>Modify the standard interface for multi-compiler attributes.</li>
<li>Modify the cycle shared implementation so it can handle more than 2 sources (tri-ported, quad-ported etc. memories)</li>
</ul>
</li>
</ul>
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<font size=+1><b><u>Synthesis:</u></b></font>
<p>
Using the slowest Altera APEX20KE device 66MHz is possible.<br>
<p>
<font size=+1><b><u>Author & Maintainer(s):</u></b></font>
<ul><a href="mailto:rherveille@opencores.org_NOSPAM">Richard Herveille</a></ul>
<p><font size=+1><b><u>Mailing-list:</u></b></font>
<ul><a href=mailto:cores@opencores.org_NOSPAM>cores@opencores.org_NOSPAM</A></ul>
 
 
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