Subversion Repositories steelcore

[/] [vivado/] [steel-core.sim/] [sim_1/] [behav/] [xsim/] [elaborate.log] - Rev 11

Compare with Previous | Blame | View Log

Vivado Simulator 2019.2
Copyright 1986-1999, 2001-2019 Xilinx, Inc. All Rights Reserved.
Running: /home/rafa/Xilinx/Vivado/2019.2/bin/unwrapped/lnx64.o/xelab -wto b8561a63f69e41d98a2e12d383a11daf --incr --debug typical --relax --mt 8 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot tb_compliance_behav xil_defaultlib.tb_compliance xil_defaultlib.glbl -log elaborate.log 
Using 8 slave threads.
Starting static elaboration
Pass Through NonSizing Optimizer
Completed static elaboration
Starting simulation data flow analysis
Completed simulation data flow analysis
Time Resolution for simulation is 1ps
Compiling module xil_defaultlib.store_unit
Compiling module xil_defaultlib.decoder
Compiling module xil_defaultlib.imm_generator
Compiling module xil_defaultlib.branch_unit
Compiling module xil_defaultlib.integer_file
Compiling module xil_defaultlib.csr_file
Compiling module xil_defaultlib.machine_control
Compiling module xil_defaultlib.load_unit
Compiling module xil_defaultlib.alu
Compiling module xil_defaultlib.steel_top
Compiling module xil_defaultlib.tb_compliance
Compiling module xil_defaultlib.glbl
Built simulation snapshot tb_compliance_behav

Compare with Previous | Blame | View Log

powered by: WebSVN 2.1.0

© copyright 1999-2022, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.