Subversion Repositories systemverilog-uart16550

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# Copyright (C) 1991-2010 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions 
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# functions, and any output files from any of the foregoing 
# (including device programming or simulation files), and any 
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# to the terms and conditions of the Altera Program License 
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# without limitation, that your use is for the sole purpose of 
# programming logic devices manufactured by Altera and sold by 
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#
# Quartus II
# Version 9.1 Build 304 01/25/2010 Service Pack 1 SJ Web Edition
# Date created = 20:55:27  March 09, 2010
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
#               uart_top_assignment_defaults.qdf
#    If this file doesn't exist, see file:
#               assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
#    file is updated automatically by the Quartus II software
#    and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #


set_global_assignment -name FAMILY "Cyclone III"
set_global_assignment -name DEVICE AUTO
set_global_assignment -name TOP_LEVEL_ENTITY uart_top
set_global_assignment -name ORIGINAL_QUARTUS_VERSION "9.1 SP1"
set_global_assignment -name PROJECT_CREATION_TIME_DATE "20:55:27  MARCH 09, 2010"
set_global_assignment -name LAST_QUARTUS_VERSION "9.1 SP1"
set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim (Verilog)"
set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation
set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_blast_fpga
set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2005
set_global_assignment -name VERILOG_SHOW_LMF_MAPPING_MESSAGES OFF
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
set_global_assignment -name FMAX_REQUIREMENT "50 MHz"
set_global_assignment -name FMAX_REQUIREMENT "50 MHz" -section_id clk_sys
set_instance_assignment -name CLOCK_SETTINGS clk_sys -to clk_i
set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER OFF
set_global_assignment -name VERILOG_MACRO "SYN=<None>"
set_global_assignment -name SYSTEMVERILOG_FILE ../rtl/uart_16550_rll.sv
set_global_assignment -name SYSTEMVERILOG_FILE ../rtl/fifo_interface.sv
set_global_assignment -name SYSTEMVERILOG_FILE ../rtl/uart_package.sv
set_global_assignment -name SYSTEMVERILOG_FILE ../rtl/fifo_package.sv
set_global_assignment -name SYSTEMVERILOG_FILE ../rtl/uart_baud.sv
set_global_assignment -name SYSTEMVERILOG_FILE ../rtl/uart_noize_shaver.sv
set_global_assignment -name SYSTEMVERILOG_FILE ../bench/uart_top.sv
set_global_assignment -name SYSTEMVERILOG_FILE ../rtl/uart_transmitter.sv
set_global_assignment -name SYSTEMVERILOG_FILE ../rtl/uart_codec_state.sv
set_global_assignment -name SYSTEMVERILOG_FILE ../rtl/uart_fifo.sv
set_global_assignment -name SYSTEMVERILOG_FILE ../rtl/uart_interface.sv
set_global_assignment -name SYSTEMVERILOG_FILE ../rtl/uart_receiver.sv
set_global_assignment -name SYSTEMVERILOG_FILE ../rtl/uart_register.sv
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top