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[/] [t400/] [trunk/] [sw/] [verif/] [system/] [production_test/] [test.asm] - Rev 179
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;; *******************************************************************;; $Id: test.asm 179 2009-04-01 19:48:38Z arniml $;;;; Production test as proposed by;; "Testing of COP400 Familiy Devices";; National Semiconductor;; COP Note 7;; April 1991;;;; the cpu type is defined on asl's command lineorg 0x00; INSTRUCTION RESULT COMMENTSNOP ; NO CHANGE CHECK NOP & ALLOW TRANSIENT; CYCLE FOR MODEOGI 9 ; G(0 > 9) NOT FOR 410L/411LOGI 6 ; G(9 > 6) REVERSE ALL G STATESSTII 8 ; SET UP 0,0 FOR FUTURELBI 3, 13 ; B TO NEW POSITION (3, 13)OBD ; D(0 > 13) CHECK DCLRA ; MAKE SURE A = 0XABR ; 3 > A;0 > BrCAB ; MOVE 3 to BdOBD ; D(13 > 3) CHECK XABR CAB & D CHANGECLRA ; !AISC 2 ; !FORCE A > 2CAB ; 2 > BdOBD ; D(3 > 2) VERIFY 2 FROM A > BdSTII 7 ; 7 > 0,2 & Bd > 3OBD ; D(2 > 3) STII INCREMENTS BdCAB ; SEE THAT A STILL THE SAMEOMG ; G(6 > 7) OMB & RAM CHECKCLRACAB ; B(0,0)OMG ; G(7 > 8) TIE IN RAM, A & G OPERATIONSMB 0 ; SMB INST. CHECKOMG ; G(8 > 9) :SMB 1 ; :OMG ; G(9 > 11) :RMB 0 ; :RMB 3 ; :LD 0 ; :2 > A (modified AL)CAB ; A = 2 > BOMG ; G(11 > 7) OUTPUT M(0,2)LD 1 ; M(0,2) > A; B > 1,2XAD 0,0 ; A(7) < => M(0,0) 2AISC 15 ; AISC CHECK; A = 1LDD 0,0 ; CHECK SKIP OF 2 BYTE INST.X 0 ; STORE 1OMG ; G(7 > 1) VERIFYLD 0 ; COPY1,2 BACK TO AADT ; ADD TENXDS 0 ; LEAVE 11 IN 1,2;GO 1, 1 WITH 1XDS 0 ; LEAVE 1 IN 1,1;GO 1,0 W ?OBD ; D(2 > 0) CHECK Bd MOVEMENTSTII 5 ; 5 > 1,0;Bd TO 1,1CBA ; CHECK B > AAISC 3 ; AISC CHECK 4 >A; INSTRUCTION RESULT COMMENTSXDS 0 ; 1 > A; 4 > 1,1OMG ; G(1 > 5) FROM 1,0XDS 0 ; 5 > A; 1 > 1,0; Bd < 15 SKIPLDD 0,0 ; SKIPPED !OBD ; D(0 > 15)AISC 4 ; 9 > AX 0 ; 9 > 15OMG ; G(5 > 9)CLRACOMP ; ONES TO AXOR ; FLIP MEMORYXIS 0 ; 6 > 1,15; 9 > A; Bd > 1,0LDD 0,0 ; SKIPAISC 8 ; A > 1 (added AL)LDD 0,0 ; SKIP (added AL)SKELBI 1,2 ; SKIP 2 WORD LBI (NOT IN 410)OBD ; D(15 > 0) VERIFY WORDSKE ; 11 NOT = 9LBI 1,0 ; BACK TO 1,0SMB 2 ; :SKE ; :RMB 2 ; :SKE ; :CHECK BITSMB 3 ; :MANIPULATIONSSKE ; :LDD 0,0 ; :X 3 ; Bd > 2,0XAD 1,1 ; 9 > 1,1; 4 > AXIS 1 ; 4 > 2,0; Bd > 3,1ING ; INPUT G PORTX 0 ; STORE; INSTRUCTION RESULT COMMENTSCLRAASC ; CHECK ADD WITH CARRYSC ; CHECK SET CARRYSKC ; CHECK SKIP ON CARRYLDD 0,0X 0 ; STORE AOMG ; G = 9 NO CHANGECLRAASCX 0OMG ; G(9 > 10) CARRY ADDS ONE TO MEMORYCAMQ ; STORE A & M IN Q; 10,9XDS 0 ; 9 > 3,1; 10 > A; Bd > 3,0CQMA ; STORE 9 IN 3,0 (added AL)OMG ; G(10 > 9)LD 2 ; 9 > A; Bd > 1,0; INSTRUCTION RESULT COMMENTSOMG ; G(9 > 1)LD 3 ; 1 > A; Bd > 2,0OMG ; G(1 > 4) (result corrected AL)ADD ; ADD WITHOUT CARRYX 0 ; STORE 3 IN 2,0SCLDD 0,0 ; 7 > ACASC ; CHECK CASCSKCX 0 ; STORE 12OMG ; G(4 > 14) (prev and current result corrected AL)CLRA ; :AISC 3 ; :X 0 ; :SC ; :CHECKSKC ; :SKC/SCX 0 ; :OMG ; G(14 > 3) (prev result corrected AL)RC ; :SKC ; :CHECKX 0 ; :RCOMG ; G(3 > 14) :LBI 0,0 ; :CHECKLBI 1,15 ; ;SEQUENTIAL LBI'SLBI 2,7 ; ALSO SKIPPED (LBI 2,7 NOT IN 410)OMG ; G(14 > 7)CQMA ; LOAD CONSTANTS FROM QOMG ; G(7 > 9) CHECKX 0 ; :OMG ; G(9 > 10) :LEI 1XAS ; STORE A - > S (9)CLRAAISC 7 ; :SKGBZ 0 ; :X 0 ; :CHECKOMG ; :SKGBZ 1 ; :X 0 ; ;G BITOMG ; G (10 > 7) :SKGBZ 2 ; :X 0 ; :OMG ; G(7 > 10) :TESTSSKGBZ 3 ; :X 0 ; :OMG ; G(10 > 7) :; INSTRUCTION RESULT COMMENTSSKGZX 0 ; :CHECKOMG ; G(7 > 10) :OGI 0 ; G(10 > 0) :G TESTSKGZ ; :X 0 ; :OMG ; G(0 > 10) :SKMBZ 0X 0 ; CHECK MEMORY BIT TESTSOMG ; NO CHANGESKMBZ 1; INSTRUCTION RESULT COMMENTSX 0OMG ; G(10 > 7) NO SKIPSKMBZ 2X 0 ; WON'T SKIPOMG ; G(7 > 10)INIL ; SEE THAT L LATCHES RESETININ ; ASSUME G - > ISKEX 1 ; Br > 1OMG ; SHOULD BE EQUALINIL ; :X 0 ; :SKMBZ 3 ; :OBD ; D(15 > 0) :INIL TESTOGI 1 ; G(10 > 1) :(result added AL)LBI 3,11 ; :OGI 0 ; G(1 > 0) :(result added AL)NOP ; (NOP added AL)INIL ; :X 0 ; :SKMBZ 0 ; :OBD ; D(0 > 11) :NOPXAS ; :X 0 ; :XAS TESTOMG ; G(10 > 9) :; INSTRUCTION RESULT COMMENTSLBI 0,0 ; LOAD RAM WITHSTII 7 ; CONSTANTS USINGSTII 14 ; STIISTII 5STII 12STII 3STII 10STII 1STII 8STII 15STII 6STII 13STII 4STII 11STII 2STII 9STII 0LBI 1,0STII 7STII 14STII 5STII 12STII 3STII 10STII 1STII 8STII 15STII 6STII 13STII 4STII 11STII 2STII 9STII 0LBI 2,0STII 7STII 14STII 5STII 12STII 3STII 10STII 1STII 8STII 15STII 6STII 13; INSTRUCTION RESULT COMMENTSSTII 4STII 11; INSTRUCTION RESULT COMMENTSSTII 2STII 9STII 0LBI 3,0STII 7STII 14STII 5STII 12STII 3STII 10STII 1STII 8STII 15STII 6STII 13STII 4STII 11STII 2STII 9STII 0; INSTRUCTION RESULT COMMENTSLBI 0,0 ; CHECK FOR RAM DATAOMG ; OUTPUT DATALD 0 ; :XIS 0 ; :MOVE TO NEXT DIGITOMG ; OUTPUT DATALD 0 ; :XIS 0 ; :MOVE TO NEXT DIGITOMG ; OUTPUT DATALD 0 ; :XIS 0 ; :MOVE TO NEXT DIGITOMG ; OUTPUT DATALD 0 ; :XIS 0 ; :MOVE TO NEXT DIGITOMG ; OUTPUT DATALD 0 ; :XIS 0 ; :MOVE TO NEXT DIGITOMG ; OUTPUT DATALD 0 ; :XIS 0 ; :MOVE TO NEXT DIGITOMG ; OUTPUT DATALD 0 ; :XIS 0 ; :MOVE TO NEXT DIGITOMG ; OUTPUT DATALD 0 ; :XIS 0 ; :MOVE TO NEXT DIGITOMG ; OUTPUT DATALD 0 ; :XIS 0 ; :MOVE TO NEXT DIGITOMG ; OUTPUT DATALD 0 ; :XIS 0 ; :MOVE TO NEXT DIGITOMG ; OUTPUT DATALD 0 ; :XIS 0 ; :MOVE TO NEXT DIGITOMG ; OUTPUT DATALD 0 ; :XIS 0 ; :MOVE TO NEXT DIGITOMG ; OUTPUT DATALD 0 ; :XIS 0 ; :MOVE TO NEXT DIGITOMG ; OUTPUT DATALD 0 ; :XIS 0 ; :MOVE TO NEXT DIGITOMG ; OUTPUT DATALD 0 ; :XIS 0 ; :MOVE TO NEXT DIGITOMG ; OUTPUT DATALD 0 ; :XIS 0 ; :MOVE TO NEXT DIGITNOP; INSTRUCTION RESULT COMMENTSLBI 1,0 ; CHECK FOR RAM DATAOMG ; OUTPUT DATALD 0 ; :XIS 0 ; :MOVE TO NEXT DIGIT; INSTRUCTION RESULT COMMENTSOMG ; OUTPUT DATALD 0 ; :XIS 0 ; :MOVE TO NEXT DIGITOMG ; OUTPUT DATALD 0 ; :XIS 0 ; :MOVE TO NEXT DIGITOMG ; OUTPUT DATALD 0 ; :XIS 0 ; :MOVE TO NEXT DIGITOMG ; OUTPUT DATALD 0 ; :XIS 0 ; :MOVE TO NEXT DIGITOMG ; OUTPUT DATALD 0 ; :XIS 0 ; :MOVE TO NEXT DIGITOMG ; OUTPUT DATALD 0 ; :XIS 0 ; :MOVE TO NEXT DIGITOMG ; OUTPUT DATALD 0 ; :XIS 0 ; :MOVE TO NEXT DIGITOMG ; OUTPUT DATALD 0 ; :XIS 0 ; :MOVE TO NEXT DIGITOMG ; OUTPUT DATALD 0 ; :XIS 0 ; :MOVE TO NEXT DIGITOMG ; OUTPUT DATALD 0 ; :XIS 0 ; :MOVE TO NEXT DIGITOMG ; OUTPUT DATALD 0 ; :XIS 0 ; :MOVE TO NEXT DIGITOMG ; OUTPUT DATALD 0 ; :XIS 0 ; :MOVE TO NEXT DIGITOMG ; OUTPUT DATALD 0 ; :XIS 0 ; :MOVE TO NEXT DIGITOMG ; OUTPUT DATALD 0 ; :XIS 0 ; :MOVE TO NEXT DIGITOMG ; OUTPUT DATALD 0 ; :XIS 0 ; :MOVE TO NEXT DIGITNOP; INSTRUCTION RESULT COMMENTSLBI 2,0 ; CHECK FOR RAM DATAOMG ; OUTPUT DATALD 0 ; :XIS 0 ; :MOVE TO NEXT DIGITOMG ; OUTPUT DATALD 0 ; :XIS 0 ; :MOVE TO NEXT DIGITOMG ; OUTPUT DATALD 0 ; :XIS 0 ; :MOVE TO NEXT DIGITOMG ; OUTPUT DATALD 0 ; :XIS 0 ; :MOVE TO NEXT DIGITOMG ; OUTPUT DATALD 0 ; :XIS 0 ; :MOVE TO NEXT DIGITOMG ; OUTPUT DATALD 0 ; :XIS 0 ; :MOVE TO NEXT DIGITOMG ; OUTPUT DATALD 0 ; :XIS 0 ; :MOVE TO NEXT DIGITOMG ; OUTPUT DATALD 0 ; :XIS 0 ; :MOVE TO NEXT DIGITOMG ; OUTPUT DATALD 0 ; :XIS 0 ; :MOVE TO NEXT DIGITOMG ; OUTPUT DATALD 0 ; :XIS 0 ; :MOVE TO NEXT DIGIT; INSTRUCTION RESULT COMMENTSOMG ; OUTPUT DATALD 0 ; :XIS 0 ; :MOVE TO NEXT DIGITOMG ; OUTPUT DATALD 0 ; :XIS 0 ; :MOVE TO NEXT DIGITOMG ; OUTPUT DATALD 0 ; :XIS 0 ; :MOVE TO NEXT DIGITOMG ; OUTPUT DATALD 0 ; :XIS 0 ; :MOVE TO NEXT DIGITOMG ; OUTPUT DATALD 0 ; :XIS 0 ; :MOVE TO NEXT DIGITOMG ; OUTPUT DATALD 0 ; :XIS 0 ; :MOVE TO NEXT DIGITNOP; INSTRUCTION RESULT COMMENTSLBI 3,0 ; CHECK FOR RAM DATAOMG ; OUTPUT DATALD 0 ; :XIS 0 ; :MOVE TO NEXT DIGITOMG ; OUTPUT DATALD 0 ; :XIS 0 ; :MOVE TO NEXT DIGITOMG ; OUTPUT DATALD 0 ; :XIS 0 ; :MOVE TO NEXT DIGITOMG ; OUTPUT DATALD 0 ; :XIS 0 ; :MOVE TO NEXT DIGITOMG ; OUTPUT DATALD 0 ; :XIS 0 ; :MOVE TO NEXT DIGITOMG ; OUTPUT DATALD 0 ; :XIS 0 ; :MOVE TO NEXT DIGITOMG ; OUTPUT DATALD 0 ; :XIS 0 ; :MOVE TO NEXT DIGITOMG ; OUTPUT DATALD 0 ; :XIS 0 ; :MOVE TO NEXT DIGITOMG ; OUTPUT DATALD 0 ; :XIS 0 ; :MOVE TO NEXT DIGITOMG ; OUTPUT DATALD 0 ; :XIS 0 ; :MOVE TO NEXT DIGITOMG ; OUTPUT DATALD 0 ; :XIS 0 ; :MOVE TO NEXT DIGITOMG ; OUTPUT DATALD 0 ; :XIS 0 ; :MOVE TO NEXT DIGITOMG ; OUTPUT DATALD 0 ; :XIS 0 ; :MOVE TO NEXT DIGITOMG ; OUTPUT DATALD 0 ; :XIS 0 ; :MOVE TO NEXT DIGITOMG ; OUTPUT DATALD 0 ; :XIS 0 ; :MOVE TO NEXT DIGITOMG ; OUTPUT DATALD 0 ; :XIS 0 ; :MOVE TO NEXT DIGITNOPjmp .