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[/] [tcp_ip_core_w_dhcp/] [trunk/] [ipcore_dir/] [TCP_FIFO.vho] - Rev 2
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-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
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-- Xilinx products are not intended for use in life support appliances, --
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-- (c) Copyright 1995-2015 Xilinx, Inc. --
-- All rights reserved. --
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-- Generated from core with identifier: xilinx.com:ip:fifo_generator:9.2 --
-- --
-- The FIFO Generator is a parameterizable first-in/first-out memory --
-- queue generator. Use it to generate resource and performance --
-- optimized FIFOs with common or independent read/write clock domains, --
-- and optional fixed or programmable full and empty flags and --
-- handshaking signals. Choose from a selection of memory resource --
-- types for implementation. Optional Hamming code based error --
-- detection and correction as well as error injection capability for --
-- system test help to insure data integrity. FIFO width and depth are --
-- parameterizable, and for native interface FIFOs, asymmetric read and --
-- write port widths are also supported. --
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-- Interfaces:
-- AXI4Stream_MASTER_M_AXIS
-- AXI4Stream_SLAVE_S_AXIS
-- AXI4_MASTER_M_AXI
-- AXI4_SLAVE_S_AXI
-- AXI4Lite_MASTER_M_AXI
-- AXI4Lite_SLAVE_S_AXI
-- The following code must appear in the VHDL architecture header:
------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
COMPONENT TCP_FIFO
PORT (
clk : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
full : OUT STD_LOGIC;
almost_full : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
data_count : OUT STD_LOGIC_VECTOR(11 DOWNTO 0)
);
END COMPONENT;
-- COMP_TAG_END ------ End COMPONENT Declaration ------------
-- The following code must appear in the VHDL architecture
-- body. Substitute your own instance name and net names.
------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
your_instance_name : TCP_FIFO
PORT MAP (
clk => clk,
din => din,
wr_en => wr_en,
rd_en => rd_en,
dout => dout,
full => full,
almost_full => almost_full,
empty => empty,
data_count => data_count
);
-- INST_TAG_END ------ End INSTANTIATION Template ------------
-- You must compile the wrapper file TCP_FIFO.vhd when simulating
-- the core, TCP_FIFO. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".