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https://opencores.org/ocsvn/tcp_socket/tcp_socket/trunk
Subversion Repositories tcp_socket
[/] [tcp_socket/] [trunk/] [chips2/] [test_suite/] [interconnect.py] - Rev 2
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#!/usr/bin/env python from chips.api.api import * import sys my_chip = Chip("interconnect") wire = Wire(my_chip) Component("producer.c")(my_chip, outputs={"z":wire}) Component("consumer.c")(my_chip, inputs={"a":wire}) my_chip.generate_verilog() my_chip.generate_testbench()