Subversion Repositories tinyvliw8

-----------------------------------------------------------------
-- Project: Aeternitas
-- Author:  Oliver Stecklina <stecklina@ihp-microelectronics.com
-- Date:    18.07.2013 
-- File:    pcReg.vhd
-- Design:  AeternitasSWUR
-----------------------------------------------------------------
-- Description : Program counter register.
-----------------------------------------------------------------
-- $Log$
-----------------------------------------------------------------
 
library ieee;
-- library lib;
 
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
 
-- use lib.defines.all;
 
entity vliwProc_pcReg is
	port (
	   addrOut    : out std_logic_vector(10 downto 0);
	   -- addrOut    : out std_logic_addr;
 
		state      : in std_logic_vector(3 downto 0);
		stalled_n  : in std_logic;
 
		ioAddr     : in std_logic_vector(1 downto 0);
		ioIn       : in std_logic_vector(7 downto 0);
		ioOut      : out std_logic_vector(7 downto 0);
		ioInEn_n   : in std_logic;
		ioInWr_n   : in std_logic;
 
		pcLoad_n   : out std_logic;
 
		jmpIn      : in std_logic_vector(10 downto 0);
		jmpInEn_n  : in std_logic;
 
		irq        : in std_logic;
		irqAddr    : in std_logic_vector(1 downto 0);
 
		rst_n      : in std_logic
	);
end vliwProc_pcReg;
 
architecture behavior of vliwProc_pcReg is
 
component gendelay
	generic (n: integer := 1);
	port (
		a_in	: in	std_logic;
		a_out	: out	std_logic
	);
end component;
 
	signal pcReg_s : std_logic_vector(10 downto 0);
	signal pcIrq_s : std_logic_vector(10 downto 0);
	signal pcInt_s : std_logic_vector(10 downto 0);
	signal pcUp_s  : std_logic_vector(2 downto 0);
 
	signal pcRegUpd_s : std_logic;
	signal pcLoad_n_s : std_logic;
 
	signal state0_s  : std_logic;
	-- signal state1_s  : std_logic;
	signal state3_s  : std_logic;
 
	signal delayedState3_s : std_logic;
 
begin
 
	state3Delay_i: gendelay
		generic map (n => 4)
		port map (
			a_in	=> state(3),
			a_out	=> delayedState3_s
		);
 
	state0_s <= state(0);
	-- state1_s <= state(1);
	state3_s <= state(3);
 
	update_pcInt: process(rst_n, state0_s)
		variable cnt_v : unsigned (10 downto 0);
	begin
		if (rst_n = '0') then
			cnt_v := (others => '0');
		else
			if (state0_s'event and state0_s = '1') then
				cnt_v := unsigned(pcReg_s) + 1;
			end if;
		end if;
 
		pcInt_s <= std_logic_vector(cnt_v);
	end process;
 
--	update_pcOut: process(rst_n, state1_s)
--	begin
--		if (rst_n = '0') then
--			pcOut_s <= (others => '0');
--		else
--			if (state1_s'event and state1_s = '1') then
--				pcOut_s <= pcInt_s;
--			end if;
--		end if;
--	end process;
--	
	update_pcUp: process(rst_n, state3_s)
	begin
		if (rst_n = '0') then
			pcUp_s <= (others => '0');
		else
			if (state3_s'event and state3_s = '1') then
				if (ioInWr_n = '0' and ioAddr = "01") then
					pcUp_s <= ioIn(2 downto 0);
				end if;
			end if;
		end if;
	end process;
 
	update_pcReg: process(rst_n, pcRegUpd_s)
		variable pcReg_v : std_logic_vector(10 downto 0);
	begin
		if (rst_n = '0') then
			pcReg_s <= (others => '0');
			pcReg_v := (others => '0');
 
			pcLoad_n_s <= '1';
		else
			if (pcRegUpd_s'event and pcRegUpd_s = '1') then
				pcLoad_n_s <= '1';
 
				if (stalled_n = '1') then
					if (ioInWr_n = '0' and ioAddr = "00") then
						pcReg_v := pcUp_s & ioIn;
						pcLoad_n_s <= '0';
					elsif (jmpInEn_n = '0') then
						pcReg_v := jmpIn;
					else
						pcReg_v := pcInt_s;
					end if;
				end if;
 
				pcReg_s <= pcReg_v;
 
			end if;
		end if;
	end process;
 
	irq_Assign: process(rst_n, irq)
	begin
		if (rst_n = '0') then
			pcIrq_s <= (others => '0');
		else
			if (irq'event and irq = '1') then
				pcIrq_s <= pcReg_s;
			end if;
		end if;
	end process;
 
	pcLoad_n   <= pcLoad_n_s when rst_n = '1' and delayedState3_s = '1' else
	              '1';
	pcRegUpd_s <= state3_s when rst_n = '1' and stalled_n = '1' else
	              '1' when rst_n = '1' and irq = '1' else
				  '0';
 
	addrOut <= pcReg_s when irq = '0' else
	            "111111111" & irqAddr;
 
	ioOut <= pcInt_s(7 downto 0)            when (rst_n = '1' and ioInEn_n = '0' and ioAddr = "00") else
	         "00000" & pcInt_s(10 downto 8) when (rst_n = '1' and ioInEn_n = '0' and ioAddr = "01") else
			 pcIrq_s(7 downto 0)            when (rst_n = '1' and ioInEn_n = '0' and ioAddr = "10") else
	         "00000" & pcIrq_s(10 downto 8) when (rst_n = '1' and ioInEn_n = '0' and ioAddr = "11") else
				(others => '0');
 
end behavior;