Subversion Repositories uart2bus

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    <file xil_pn:name="../../rtl/baud_gen.v" xil_pn:type="FILE_VERILOG">
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      <association xil_pn:name="Implementation"/>
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    <file xil_pn:name="../../rtl/uart2bus_top.v" xil_pn:type="FILE_VERILOG">
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    <file xil_pn:name="../../rtl/uart_parser.v" xil_pn:type="FILE_VERILOG">
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    <file xil_pn:name="../../rtl/uart_rx.v" xil_pn:type="FILE_VERILOG">
      <association xil_pn:name="BehavioralSimulation"/>
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    <file xil_pn:name="../../rtl/uart_top.v" xil_pn:type="FILE_VERILOG">
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    <file xil_pn:name="../../rtl/uart_tx.v" xil_pn:type="FILE_VERILOG">
      <association xil_pn:name="BehavioralSimulation"/>
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    <file xil_pn:name="uart2bus_top.ucf" xil_pn:type="FILE_UCF"/>
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  <properties>
    <property xil_pn:name="Change Device Speed To" xil_pn:value="-3"/>
    <property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-3"/>
    <property xil_pn:name="Constraints Entry" xil_pn:value="Constraints Editor"/>
    <property xil_pn:name="Device" xil_pn:value="xc3s50"/>
    <property xil_pn:name="Device Family" xil_pn:value="Spartan3"/>
    <property xil_pn:name="Device Speed Grade/Select ABS Minimum" xil_pn:value="-3"/>
    <property xil_pn:name="Fitter Report Format" xil_pn:value="HTML"/>
    <property xil_pn:name="Implementation Top" xil_pn:value="Module|uart2bus_top"/>
    <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/uart2bus_top"/>
    <property xil_pn:name="PROP_DesignName" xil_pn:value="uart2bus"/>
    <property xil_pn:name="Package" xil_pn:value="pq208"/>
    <property xil_pn:name="Preferred Language" xil_pn:value="Verilog"/>
    <property xil_pn:name="Simulator" xil_pn:value="Modelsim-SE Mixed"/>
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    <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)"/>
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