Subversion Repositories uart6551

// ============================================================================
//        __
//   \\__/ o\    (C) 2005-2022  Robert Finch, Waterloo
//    \  __ /    All rights reserved.
//     \/_//     robfinch<remove>@finitron.ca
//       ||
//
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// ============================================================================
//
module uart6551BaudLUT(a, o);
parameter pClkFreq = 40;
parameter pCounterBits = 24;
input [4:0] a;
output reg [pCounterBits-1:0] o;

// table for a 50.000MHz reference clock
// value = 50,000,000 / (baud * 16)
always_comb
if (pClkFreq==40)
        case (a)        // synopsys full_case parallel_case
        5'd0:   o <= 0;
        5'd1:   o <= 24'd50000; // 50 baud
        5'd2:   o <= 24'd33333; // 75 baud
        5'd3:   o <= 24'd22744; // 109.92 baud
        5'd4:   o <= 24'd18576; // 134.58 baud
        5'd5:   o <= 24'd16667; // 150 baud
        5'd6:   o <= 24'd8333;  // 300 baud
        5'd7:   o <= 24'd4167;  // 600 baud
        5'd8:   o <= 24'd2083;  // 1200 baud
        5'd9:   o <= 24'd1389;  // 1800 baud
        5'd10:  o <= 24'd1042;  // 2400 baud
        5'd11:  o <= 24'd694;   // 3600 baud
        5'd12:  o <= 24'd521;   // 4800 baud
        5'd13:  o <= 24'd347;   // 7200 baud
        5'd14:  o <= 24'd260;   // 9600 baud
        5'd15:  o <= 24'd130;   // 19200 baud

        5'd16:  o <= 24'd65;    // 38400 baud
        5'd17:  o <= 24'd43;    // 57600 baud
        5'd18:  o <= 24'd22;    // 115200 baud
        5'd19:  o <= 24'd11;    // 230400 baud
        5'd20:  o <= 24'd5;     // 460800 baud
        5'd21:  o <= 24'd3;     // 921600 baud
        default:        o <= 24'd260;   // 9600 baud
        endcase
else if (pClkFreq==50)
        case (a)        // synopsys full_case parallel_case
        5'd0:   o <= 0;
        5'd1:   o <= 24'd62500; // 50 baud
        5'd2:   o <= 24'd41667; // 75 baud
        5'd3:   o <= 24'd28617; // 109.92 baud
        5'd4:   o <= 24'd23220; // 134.58 baud
        5'd5:   o <= 24'd20833; // 150 baud
        5'd6:   o <= 24'd10417; // 300 baud
        5'd7:   o <= 24'd5208;  // 600 baud
        5'd8:   o <= 24'd2604;  // 1200 baud
        5'd9:   o <= 24'd1736;  // 1800 baud
        5'd10:  o <= 24'd1302;  // 2400 baud
        5'd11:  o <= 24'd868;   // 3600 baud
        5'd12:  o <= 24'd651;   // 4800 baud
        5'd13:  o <= 24'd434;   // 7200 baud
        5'd14:  o <= 24'd326;   // 9600 baud
        5'd15:  o <= 24'd163;   // 19200 baud

        5'd16:  o <= 24'd81;    // 38400 baud
        5'd17:  o <= 24'd54;    // 57600 baud
        5'd18:  o <= 24'd27;    // 115200 baud
        5'd19:  o <= 24'd14;    // 230400 baud
        5'd20:  o <= 24'd7;     // 460800 baud
        5'd21:  o <= 24'd3;     // 921600 baud
        default:        o <= 24'd326;   // 9600 baud
        endcase
else if (pClkFreq==80)
        case (a)        // synopsys full_case parallel_case
        5'd0:   o <= 0;
        5'd1:   o <= 24'd100000;        // 50 baud
        5'd2:   o <= 24'd66667; // 75 baud
        5'd3:   o <= 24'd45488; // 109.92 baud
        5'd4:   o <= 24'd37153; // 134.58 baud
        5'd5:   o <= 24'd33333; // 150 baud
        5'd6:   o <= 24'd16667; // 300 baud
        5'd7:   o <= 24'd8333;  // 600 baud
        5'd8:   o <= 24'd4167;  // 1200 baud
        5'd9:   o <= 24'd2778;  // 1800 baud
        5'd10:  o <= 24'd2083;  // 2400 baud
        5'd11:  o <= 24'd1389;  // 3600 baud
        5'd12:  o <= 24'd1042;  // 4800 baud
        5'd13:  o <= 24'd694;   // 7200 baud
        5'd14:  o <= 24'd521;   // 9600 baud
        5'd15:  o <= 24'd260;   // 19200 baud

        5'd16:  o <= 24'd130;   // 38400 baud
        5'd17:  o <= 24'd87;    // 57600 baud
        5'd18:  o <= 24'd43;    // 115200 baud
        5'd19:  o <= 24'd22;    // 230400 baud
        5'd20:  o <= 24'd11;    // 460800 baud
        5'd21:  o <= 24'd5;     // 921600 baud
        default:        o <= 24'd521;   // 9600 baud
        endcase

endmodule