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<a href="_i_n_t_e_r_c_o_n___p2_p_8vhd.html">Go to the documentation of this file.</a><div class="fragment"><pre class="fragment"><a name="l00001"></a>00001
<a name="l00003"></a>00003
<a name="l00004"></a>00004 <span class="vhdlkeyword">library </span><span class="keywordflow">IEEE</span>;
<a name="l00005"></a>00005 <span class="vhdlkeyword">use </span>IEEE.STD_LOGIC_1164.<span class="vhdlkeyword">ALL</span>;
<a name="l00006"></a>00006
<a name="l00007"></a><a class="code" href="class_i_n_t_e_r_c_o_n___p2_p.html">00007</a> <span class="keywordflow">entity </span><a class="code" href="class_i_n_t_e_r_c_o_n___p2_p.html">INTERCON_P2P</a> <span class="vhdlkeyword">is</span>
<a name="l00008"></a>00008 <span class="vhdlkeyword">port</span> <span class="vhdlchar">(</span><span class="keyword"></span>
<a name="l00009"></a>00009 <span class="keyword"> -- External (non-WISHBONE) inputs</span>
<a name="l00010"></a>00010 <span class="vhdlchar">EXTCLK</span><span class="vhdlchar">:</span> <span class="vhdlkeyword">in</span> <span class="comment">std_logic</span>;
<a name="l00011"></a>00011 <span class="vhdlchar">EXTRST</span><span class="vhdlchar">:</span> <span class="vhdlkeyword">in</span> <span class="comment">std_logic</span>;<span class="keyword"></span>
<a name="l00012"></a>00012 <span class="keyword"> -- External signals <span class="vhdlkeyword">for</span> simulation purposes</span>
<a name="l00013"></a>00013 <span class="vhdlchar">byte_out</span><span class="vhdlchar">:</span> <span class="vhdlkeyword">out</span> <span class="comment">std_logic_vector</span><span class="vhdlchar">(</span><span class="vhdllogic"></span><span class="vhdllogic">7</span> <span class="vhdlkeyword">downto</span> <span class="vhdllogic"></span><span class="vhdllogic">0</span><span class="vhdlchar">)</span>;
<a name="l00014"></a>00014 <span class="vhdlchar">data_avaible</span> <span class="vhdlchar">:</span> <span class="vhdlkeyword">out</span> <span class="comment">std_logic</span>;
<a name="l00015"></a>00015 <span class="vhdlchar">tx</span><span class="vhdlchar">:</span> <span class="vhdlkeyword">out</span> <span class="comment">std_logic</span>;
<a name="l00016"></a>00016 <span class="vhdlchar">rx</span> <span class="vhdlchar">:</span> <span class="vhdlkeyword">in</span> <span class="comment">std_logic</span>
<a name="l00017"></a>00017 <span class="vhdlchar">)</span>;
<a name="l00018"></a>00018 <span class="vhdlkeyword">end</span> <span class="vhdlchar">INTERCON_P2P</span>;
<a name="l00019"></a>00019
<a name="l00022"></a><a class="code" href="class_i_n_t_e_r_c_o_n___p2_p_1_1_behavioral.html">00022</a> <span class="vhdlkeyword">architecture</span> Behavioral <span class="vhdlkeyword">of</span> <a class="code" href="class_i_n_t_e_r_c_o_n___p2_p.html">INTERCON_P2P</a> is
<a name="l00023"></a><a class="code" href="class_i_n_t_e_r_c_o_n___p2_p_1_1_behavioral.html#a99b85cc71dbbaa06e16f4d4351530462">00023</a> <span class="vhdlkeyword">component</span> <a class="code" href="class_s_y_c0001a.html">SYC0001a</a>
<a name="l00024"></a>00024 <span class="vhdlkeyword">port</span>(<span class="keyword"></span>
<a name="l00025"></a>00025 <span class="keyword"> -- WISHBONE Interface</span>
<a name="l00026"></a>00026 <a class="code" href="class_s_y_c0001a.html#a47194b29006cd455b0c9239f61a32662" title="Clock output.">CLK_O</a>: <span class="vhdlkeyword">out</span> <span class="comment">std_logic</span>;
<a name="l00027"></a>00027 <a class="code" href="class_s_y_c0001a.html#ad526bc5e7968a2200cff030cb9b1d23e" title="Reset output.">RST_O</a>: <span class="vhdlkeyword">out</span> <span class="comment">std_logic</span>; <span class="keyword"></span>
<a name="l00028"></a>00028 <span class="keyword"> -- NON-WISHBONE Signals</span>
<a name="l00029"></a>00029 <a class="code" href="class_s_y_c0001a.html#aec20dfafe328406fe05937923ffb3546" title="Clock input.">EXTCLK</a>: <span class="vhdlkeyword">in</span> <span class="comment">std_logic</span>;
<a name="l00030"></a>00030 <a class="code" href="class_s_y_c0001a.html#a5242034b20a8e2bd36922221b2791426" title="Reset input.">EXTRST</a>: <span class="vhdlkeyword">in</span> <span class="comment">std_logic</span>
<a name="l00031"></a>00031 );
<a name="l00032"></a>00032 <span class="vhdlkeyword">end</span> <span class="vhdlkeyword">component</span> <span class="vhdlchar"><a class="code" href="class_i_n_t_e_r_c_o_n___p2_p_1_1_behavioral.html#a99b85cc71dbbaa06e16f4d4351530462" title="Clock output.">SYC0001a</a></span>;
<a name="l00033"></a>00033
<a name="l00034"></a><a class="code" href="class_i_n_t_e_r_c_o_n___p2_p_1_1_behavioral.html#a3eba7772cc5be92821da2ebda4b73fae">00034</a> <span class="vhdlkeyword">component</span> <a class="code" href="class_s_e_r_i_a_l_m_a_s_t_e_r.html">SERIALMASTER</a> <span class="vhdlkeyword">is</span>
<a name="l00035"></a>00035 <span class="vhdlkeyword">port</span>(<span class="keyword"></span>
<a name="l00036"></a>00036 <span class="keyword"> -- WISHBONE Signals</span>
<a name="l00037"></a>00037 <a class="code" href="class_s_e_r_i_a_l_m_a_s_t_e_r.html#a69bf28b7e6429b3f3e35bee455901578" title="Ack input.">ACK_I</a>: <span class="vhdlkeyword">in</span> <span class="comment">std_logic</span>;
<a name="l00038"></a>00038 <a class="code" href="class_s_e_r_i_a_l_m_a_s_t_e_r.html#a2331d71c69b0b20c1901627667a01471" title="Address output.">ADR_O</a>: <span class="vhdlkeyword">out</span> <span class="comment">std_logic_vector</span>( <span class="vhdllogic"></span><span class="vhdllogic">1</span> <span class="vhdlkeyword">downto</span> <span class="vhdllogic"></span><span class="vhdllogic">0</span> );
<a name="l00039"></a>00039 <a class="code" href="class_s_e_r_i_a_l_m_a_s_t_e_r.html#a3582288d52a135a76a7de24d94b4dc68" title="Clock input.">CLK_I</a>: <span class="vhdlkeyword">in</span> <span class="comment">std_logic</span>;
<a name="l00040"></a>00040 <a class="code" href="class_s_e_r_i_a_l_m_a_s_t_e_r.html#af4b285f68ab4fa480bd6095c34ff5135" title="Cycle output.">CYC_O</a>: <span class="vhdlkeyword">out</span> <span class="comment">std_logic</span>;
<a name="l00041"></a>00041 <a class="code" href="class_s_e_r_i_a_l_m_a_s_t_e_r.html#ab94f6b71e9a7ec24dab537723d8345d2" title="Data input.">DAT_I</a>: <span class="vhdlkeyword">in</span> <span class="comment">std_logic_vector</span>( <span class="vhdllogic"></span><span class="vhdllogic">31</span> <span class="vhdlkeyword">downto</span> <span class="vhdllogic"></span><span class="vhdllogic">0</span> );
<a name="l00042"></a>00042 <a class="code" href="class_s_e_r_i_a_l_m_a_s_t_e_r.html#a6b78f3634fd733feea1e7504e6a4ddc4" title="Data output.">DAT_O</a>: <span class="vhdlkeyword">out</span> <span class="comment">std_logic_vector</span>( <span class="vhdllogic"></span><span class="vhdllogic">31</span> <span class="vhdlkeyword">downto</span> <span class="vhdllogic"></span><span class="vhdllogic">0</span> );
<a name="l00043"></a>00043 <a class="code" href="class_s_e_r_i_a_l_m_a_s_t_e_r.html#ae9849e01c32648d8e13000bd5fb9760f" title="Reset input.">RST_I</a>: <span class="vhdlkeyword">in</span> <span class="comment">std_logic</span>;
<a name="l00044"></a>00044 <a class="code" href="class_s_e_r_i_a_l_m_a_s_t_e_r.html#abd694a1729387db79033dcfd6bf320bc" title="Select output.">SEL_O</a>: <span class="vhdlkeyword">out</span> <span class="comment">std_logic</span>;
<a name="l00045"></a>00045 <a class="code" href="class_s_e_r_i_a_l_m_a_s_t_e_r.html#ac7ffa7be9c863895b0f1d1ec6e101169" title="Strobe output (Works like a chip select)">STB_O</a>: <span class="vhdlkeyword">out</span> <span class="comment">std_logic</span>;
<a name="l00046"></a>00046 <a class="code" href="class_s_e_r_i_a_l_m_a_s_t_e_r.html#a41e7e86f235d5f673607008142e1ecad" title="Write enable.">WE_O</a>: <span class="vhdlkeyword">out</span> <span class="comment">std_logic</span>;
<a name="l00047"></a>00047 <span class="keyword"></span>
<a name="l00048"></a>00048 <span class="keyword"> -- NON-WISHBONE Signals</span>
<a name="l00049"></a>00049 <a class="code" href="class_s_e_r_i_a_l_m_a_s_t_e_r.html#af163828b322f105b0c03724feea898ce" title="Signal byte received (Used to debug on the out leds)">byte_rec</a> : <span class="vhdlkeyword">out</span> <span class="comment">std_logic_vector</span>(<span class="vhdllogic"></span><span class="vhdllogic">7</span> <span class="vhdlkeyword">downto</span> <span class="vhdllogic"></span><span class="vhdllogic">0</span>)
<a name="l00050"></a>00050 );
<a name="l00051"></a>00051 <span class="vhdlkeyword">end</span> <span class="vhdlkeyword">component</span>;
<a name="l00052"></a>00052
<a name="l00053"></a><a class="code" href="class_i_n_t_e_r_c_o_n___p2_p_1_1_behavioral.html#abc849ae7612bb6c8206d5bb023aee9b7">00053</a> <span class="vhdlkeyword">component</span> <a class="code" href="classuart__wishbone__slave.html">uart_wishbone_slave</a> <span class="vhdlkeyword">is</span>
<a name="l00054"></a>00054 <span class="vhdlkeyword">Port</span> ( <a class="code" href="classuart__wishbone__slave.html#a4775682dc01dcbf48f20a731490ff2da" title="Reset Input.">RST_I</a> : <span class="vhdlkeyword">in</span> <span class="comment">STD_LOGIC</span>;
<a name="l00055"></a>00055 <a class="code" href="classuart__wishbone__slave.html#aa26da3641303aaf250c88cbdf3d8a1a3" title="Clock Input.">CLK_I</a> : <span class="vhdlkeyword">in</span> <span class="comment">STD_LOGIC</span>;
<a name="l00056"></a>00056 <a class="code" href="classuart__wishbone__slave.html#aca7516cbd7b6a93eac24e720fc01760c" title="Address input.">ADR_I0</a> : <span class="vhdlkeyword">in</span> <span class="comment">STD_LOGIC_VECTOR</span> (<span class="vhdllogic"></span><span class="vhdllogic">1</span> <span class="vhdlkeyword">downto</span> <span class="vhdllogic"></span><span class="vhdllogic">0</span>);
<a name="l00057"></a>00057 <a class="code" href="classuart__wishbone__slave.html#ad423901fb91ee750587d52bd9ddb2001" title="Data Input 0.">DAT_I0</a> : <span class="vhdlkeyword">in</span> <span class="comment">STD_LOGIC_VECTOR</span> (<span class="vhdllogic"></span><span class="vhdllogic">31</span> <span class="vhdlkeyword">downto</span> <span class="vhdllogic"></span><span class="vhdllogic">0</span>);
<a name="l00058"></a>00058 <a class="code" href="classuart__wishbone__slave.html#a5779ba7b1bb275d5e56907020420ca27" title="Data Output 0.">DAT_O0</a> : <span class="vhdlkeyword">out</span> <span class="comment">STD_LOGIC_VECTOR</span> (<span class="vhdllogic"></span><span class="vhdllogic">31</span> <span class="vhdlkeyword">downto</span> <span class="vhdllogic"></span><span class="vhdllogic">0</span>);
<a name="l00059"></a>00059 <a class="code" href="classuart__wishbone__slave.html#a32a749c5f0d113303c3de1fa917b8f56" title="Write enable input.">WE_I</a> : <span class="vhdlkeyword">in</span> <span class="comment">STD_LOGIC</span>;
<a name="l00060"></a>00060 <a class="code" href="classuart__wishbone__slave.html#af3bb8cfb2912c0d4ce792bd6c53d6a4c" title="Strobe input (Works like a chip select)">STB_I</a> : <span class="vhdlkeyword">in</span> <span class="comment">STD_LOGIC</span>;
<a name="l00061"></a>00061 <a class="code" href="classuart__wishbone__slave.html#aeec8b0022ebb92b40f746bf13cf7319c" title="Ack output.">ACK_O</a> : <span class="vhdlkeyword">out</span> <span class="comment">STD_LOGIC</span>;
<a name="l00062"></a>00062 <span class="keyword"></span>
<a name="l00063"></a>00063 <span class="keyword"> -- NON-WISHBONE Signals</span>
<a name="l00064"></a>00064 <a class="code" href="classuart__wishbone__slave.html#aafe347fe5fc89efa63d92386f60c5f50" title="Uart serial input.">serial_in</a> : <span class="vhdlkeyword">in</span> <span class="comment">std_logic</span>;
<a name="l00065"></a>00065 <a class="code" href="classuart__wishbone__slave.html#ad55ceaa2b85f0ff8d37ba499fc620a61" title="Flag to indicate data avaible.">data_Avaible</a> : <span class="vhdlkeyword">out</span> <span class="comment">std_logic</span>;
<a name="l00066"></a>00066 serial_out : <span class="vhdlkeyword">out</span> <span class="comment">std_logic</span>
<a name="l00067"></a>00067 );
<a name="l00068"></a>00068 <span class="vhdlkeyword">end</span> <span class="vhdlkeyword">component</span>;
<a name="l00069"></a>00069 <span class="vhdlkeyword">signal</span> <span class="vhdlchar">CLK</span> <span class="vhdlchar">:</span> <span class="comment">std_logic</span>;
<a name="l00070"></a>00070 <span class="vhdlkeyword">signal</span> <span class="vhdlchar">RST</span> <span class="vhdlchar">:</span> <span class="comment">std_logic</span>;
<a name="l00071"></a>00071 <span class="vhdlkeyword">signal</span> <span class="vhdlchar">ACK</span> <span class="vhdlchar">:</span> <span class="comment">std_logic</span>;
<a name="l00072"></a>00072 <span class="vhdlkeyword">signal</span> <span class="vhdlchar">WE</span> <span class="vhdlchar">:</span> <span class="comment">std_logic</span>;
<a name="l00073"></a>00073 <span class="vhdlkeyword">signal</span> <span class="vhdlchar">STB</span> <span class="vhdlchar">:</span> <span class="comment">std_logic</span>;
<a name="l00074"></a>00074 <span class="vhdlkeyword">signal</span> <span class="vhdlchar">ADR</span> <span class="vhdlchar">:</span> <span class="comment">std_logic_vector</span><span class="vhdlchar">(</span> <span class="vhdllogic"></span><span class="vhdllogic">1</span> <span class="vhdlkeyword">downto</span> <span class="vhdllogic"></span><span class="vhdllogic">0</span> <span class="vhdlchar">)</span>;
<a name="l00075"></a>00075 <span class="vhdlkeyword">signal</span> <span class="vhdlchar">dataI</span> <span class="vhdlchar">:</span> <span class="comment">std_logic_vector</span> <span class="vhdlchar">(</span><span class="vhdllogic"></span><span class="vhdllogic">31</span> <span class="vhdlkeyword">downto</span> <span class="vhdllogic"></span><span class="vhdllogic">0</span><span class="vhdlchar">)</span>;
<a name="l00076"></a>00076 <span class="vhdlkeyword">signal</span> <span class="vhdlchar">dataO</span> <span class="vhdlchar">:</span> <span class="comment">std_logic_vector</span> <span class="vhdlchar">(</span><span class="vhdllogic"></span><span class="vhdllogic">31</span> <span class="vhdlkeyword">downto</span> <span class="vhdllogic"></span><span class="vhdllogic">0</span><span class="vhdlchar">)</span>;
<a name="l00077"></a>00077 <span class="vhdlkeyword">begin</span>
<a name="l00079"></a>00079 <a class="code" href="dummy.html#addc89a1043fac3e419f545918b00304b" title="Instantiate SYC0001a.">uSysCon</a>: <span class="vhdlkeyword">component</span> <a class="code" href="class_s_y_c0001a.html">SYC0001a</a>
<a name="l00080"></a>00080 <span class="vhdlkeyword">port</span> <span class="vhdlkeyword">map</span>(
<a name="l00081"></a>00081 <a class="code" href="class_s_y_c0001a.html#a47194b29006cd455b0c9239f61a32662" title="Clock output.">CLK_O</a> => CLK,
<a name="l00082"></a>00082 <a class="code" href="class_s_y_c0001a.html#ad526bc5e7968a2200cff030cb9b1d23e" title="Reset output.">RST_O</a> => RST,
<a name="l00083"></a>00083 <a class="code" href="class_s_y_c0001a.html#aec20dfafe328406fe05937923ffb3546" title="Clock input.">EXTCLK</a> => EXTCLK ,
<a name="l00084"></a>00084 <a class="code" href="class_s_y_c0001a.html#a5242034b20a8e2bd36922221b2791426" title="Reset input.">EXTRST</a> => EXTRST
<a name="l00085"></a>00085 <span class="vhdlchar">)</span>;
<a name="l00086"></a>00086
<a name="l00088"></a>00088 <a class="code" href="dummy.html#a17d29dc89d37b4f2942037816f9095f9" title="Instantiate SERIALMASTER.">uMasterSerial</a> : <span class="vhdlkeyword">component</span> <a class="code" href="class_s_e_r_i_a_l_m_a_s_t_e_r.html">SERIALMASTER</a>
<a name="l00089"></a>00089 <span class="vhdlkeyword">port</span> <span class="vhdlkeyword">map</span>(
<a name="l00090"></a>00090 <a class="code" href="class_s_e_r_i_a_l_m_a_s_t_e_r.html#a69bf28b7e6429b3f3e35bee455901578" title="Ack input.">ACK_I</a> => ACK,
<a name="l00091"></a>00091 <a class="code" href="class_s_e_r_i_a_l_m_a_s_t_e_r.html#a2331d71c69b0b20c1901627667a01471" title="Address output.">ADR_O</a> => ADR,
<a name="l00092"></a>00092 <a class="code" href="class_s_e_r_i_a_l_m_a_s_t_e_r.html#a3582288d52a135a76a7de24d94b4dc68" title="Clock input.">CLK_I</a> => CLK,
<a name="l00093"></a>00093 <a class="code" href="class_s_e_r_i_a_l_m_a_s_t_e_r.html#af4b285f68ab4fa480bd6095c34ff5135" title="Cycle output.">CYC_O</a> => <span class="vhdlkeyword">open</span>,
<a name="l00094"></a>00094 <a class="code" href="class_s_e_r_i_a_l_m_a_s_t_e_r.html#ab94f6b71e9a7ec24dab537723d8345d2" title="Data input.">DAT_I</a> => dataI,
<a name="l00095"></a>00095 <a class="code" href="class_s_e_r_i_a_l_m_a_s_t_e_r.html#a6b78f3634fd733feea1e7504e6a4ddc4" title="Data output.">DAT_O</a> => dataO,
<a name="l00096"></a>00096 <a class="code" href="class_s_e_r_i_a_l_m_a_s_t_e_r.html#ae9849e01c32648d8e13000bd5fb9760f" title="Reset input.">RST_I</a> => RST,
<a name="l00097"></a>00097 <a class="code" href="class_s_e_r_i_a_l_m_a_s_t_e_r.html#abd694a1729387db79033dcfd6bf320bc" title="Select output.">SEL_O</a> => <span class="vhdlkeyword">open</span>,
<a name="l00098"></a>00098 <a class="code" href="class_s_e_r_i_a_l_m_a_s_t_e_r.html#ac7ffa7be9c863895b0f1d1ec6e101169" title="Strobe output (Works like a chip select)">STB_O</a> => STB,
<a name="l00099"></a>00099 <a class="code" href="class_s_e_r_i_a_l_m_a_s_t_e_r.html#af163828b322f105b0c03724feea898ce" title="Signal byte received (Used to debug on the out leds)">byte_rec</a> => byte_out ,
<a name="l00100"></a>00100 <a class="code" href="class_s_e_r_i_a_l_m_a_s_t_e_r.html#a41e7e86f235d5f673607008142e1ecad" title="Write enable.">WE_O</a> => WE
<a name="l00101"></a>00101 <span class="vhdlchar">)</span>;
<a name="l00102"></a>00102
<a name="l00104"></a>00104 <a class="code" href="dummy.html#a869bee07e49a71e28b889f35f114c40f" title="Instantiate uart_wishbone_slave.">uUartWishboneSlave</a>: <span class="vhdlkeyword">component</span> <a class="code" href="classuart__wishbone__slave.html">uart_wishbone_slave</a>
<a name="l00105"></a>00105 <span class="vhdlkeyword">port</span> <span class="vhdlkeyword">map</span>(
<a name="l00106"></a>00106 <a class="code" href="classuart__wishbone__slave.html#a4775682dc01dcbf48f20a731490ff2da" title="Reset Input.">RST_I</a> => RST,
<a name="l00107"></a>00107 <a class="code" href="classuart__wishbone__slave.html#aa26da3641303aaf250c88cbdf3d8a1a3" title="Clock Input.">CLK_I</a> => CLK,
<a name="l00108"></a>00108 <a class="code" href="classuart__wishbone__slave.html#aca7516cbd7b6a93eac24e720fc01760c" title="Address input.">ADR_I0</a> => ADR,
<a name="l00109"></a>00109 <a class="code" href="classuart__wishbone__slave.html#ad423901fb91ee750587d52bd9ddb2001" title="Data Input 0.">DAT_I0</a> => dataO,
<a name="l00110"></a>00110 <a class="code" href="classuart__wishbone__slave.html#a5779ba7b1bb275d5e56907020420ca27" title="Data Output 0.">DAT_O0</a> => dataI,
<a name="l00111"></a>00111 <a class="code" href="classuart__wishbone__slave.html#a32a749c5f0d113303c3de1fa917b8f56" title="Write enable input.">WE_I</a> => WE,
<a name="l00112"></a>00112 <a class="code" href="classuart__wishbone__slave.html#af3bb8cfb2912c0d4ce792bd6c53d6a4c" title="Strobe input (Works like a chip select)">STB_I</a> => STB,
<a name="l00113"></a>00113 <a class="code" href="classuart__wishbone__slave.html#aeec8b0022ebb92b40f746bf13cf7319c" title="Ack output.">ACK_O</a> => ACK,
<a name="l00114"></a>00114 <a class="code" href="classuart__wishbone__slave.html#aafe347fe5fc89efa63d92386f60c5f50" title="Uart serial input.">serial_in</a> => rx,
<a name="l00115"></a>00115 <a class="code" href="classuart__wishbone__slave.html#ad55ceaa2b85f0ff8d37ba499fc620a61" title="Flag to indicate data avaible.">data_Avaible</a> => <span class="vhdlkeyword">open</span>,
<a name="l00116"></a>00116 serial_out => tx
<a name="l00117"></a>00117 <span class="vhdlchar">)</span>;
<a name="l00118"></a>00118
<a name="l00119"></a>00119 <span class="vhdlkeyword">end</span> <span class="vhdlchar">Behavioral</span>;
<a name="l00120"></a>00120
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