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<a href="_s_e_r_i_a_l_m_a_s_t_e_r_8vhd.html">Go to the documentation of this file.</a><div class="fragment"><pre class="fragment"><a name="l00001"></a>00001
<a name="l00003"></a>00003 <span class="vhdlkeyword">library </span><span class="keywordflow">ieee</span>;
<a name="l00004"></a>00004 <span class="vhdlkeyword">USE </span>ieee.std_logic_1164.<span class="vhdlkeyword">ALL</span>;
<a name="l00005"></a>00005 <span class="vhdlkeyword">use </span>ieee.std_logic_unsigned.<span class="vhdlkeyword">all</span>;
<a name="l00006"></a>00006 <span class="vhdlkeyword">use </span>ieee.std_logic_arith.<span class="vhdlkeyword">all</span>;
<a name="l00007"></a>00007
<a name="l00009"></a><a class="code" href="class_s_e_r_i_a_l_m_a_s_t_e_r.html#ac442dca664056131bdaf5c92e4351e01">00009</a> <span class="vhdlkeyword">use </span>work.pkgDefinitions.<span class="vhdlkeyword">all</span>;
<a name="l00010"></a>00010
<a name="l00011"></a><a class="code" href="class_s_e_r_i_a_l_m_a_s_t_e_r.html">00011</a> <span class="keywordflow">entity </span><a class="code" href="class_s_e_r_i_a_l_m_a_s_t_e_r.html">SERIALMASTER</a> <span class="vhdlkeyword">is</span>
<a name="l00012"></a>00012 <span class="vhdlkeyword">port</span><span class="vhdlchar">(</span><span class="keyword"></span>
<a name="l00013"></a>00013 <span class="keyword"> -- WISHBONE Signals</span>
<a name="l00014"></a><a class="code" href="class_s_e_r_i_a_l_m_a_s_t_e_r.html#a69bf28b7e6429b3f3e35bee455901578">00014</a> <span class="vhdlchar"><a class="code" href="class_s_e_r_i_a_l_m_a_s_t_e_r.html#a69bf28b7e6429b3f3e35bee455901578" title="Ack input.">ACK_I</a></span><span class="vhdlchar">:</span> <span class="vhdlkeyword">in</span> <span class="comment">std_logic</span>;
<a name="l00015"></a><a class="code" href="class_s_e_r_i_a_l_m_a_s_t_e_r.html#a2331d71c69b0b20c1901627667a01471">00015</a> <span class="vhdlchar"><a class="code" href="class_s_e_r_i_a_l_m_a_s_t_e_r.html#a2331d71c69b0b20c1901627667a01471" title="Address output.">ADR_O</a></span><span class="vhdlchar">:</span> <span class="vhdlkeyword">out</span> <span class="comment">std_logic_vector</span><span class="vhdlchar">(</span> <span class="vhdllogic"></span><span class="vhdllogic">1</span> <span class="vhdlkeyword">downto</span> <span class="vhdllogic"></span><span class="vhdllogic">0</span> <span class="vhdlchar">)</span>;
<a name="l00016"></a><a class="code" href="class_s_e_r_i_a_l_m_a_s_t_e_r.html#a3582288d52a135a76a7de24d94b4dc68">00016</a> <span class="vhdlchar"><a class="code" href="class_s_e_r_i_a_l_m_a_s_t_e_r.html#a3582288d52a135a76a7de24d94b4dc68" title="Clock input.">CLK_I</a></span><span class="vhdlchar">:</span> <span class="vhdlkeyword">in</span> <span class="comment">std_logic</span>;
<a name="l00017"></a><a class="code" href="class_s_e_r_i_a_l_m_a_s_t_e_r.html#af4b285f68ab4fa480bd6095c34ff5135">00017</a> <span class="vhdlchar"><a class="code" href="class_s_e_r_i_a_l_m_a_s_t_e_r.html#af4b285f68ab4fa480bd6095c34ff5135" title="Cycle output.">CYC_O</a></span><span class="vhdlchar">:</span> <span class="vhdlkeyword">out</span> <span class="comment">std_logic</span>;
<a name="l00018"></a><a class="code" href="class_s_e_r_i_a_l_m_a_s_t_e_r.html#ab94f6b71e9a7ec24dab537723d8345d2">00018</a> <span class="vhdlchar"><a class="code" href="class_s_e_r_i_a_l_m_a_s_t_e_r.html#ab94f6b71e9a7ec24dab537723d8345d2" title="Data input.">DAT_I</a></span><span class="vhdlchar">:</span> <span class="vhdlkeyword">in</span> <span class="comment">std_logic_vector</span><span class="vhdlchar">(</span> <span class="vhdllogic"></span><span class="vhdllogic">31</span> <span class="vhdlkeyword">downto</span> <span class="vhdllogic"></span><span class="vhdllogic">0</span> <span class="vhdlchar">)</span>;
<a name="l00019"></a><a class="code" href="class_s_e_r_i_a_l_m_a_s_t_e_r.html#a6b78f3634fd733feea1e7504e6a4ddc4">00019</a> <span class="vhdlchar"><a class="code" href="class_s_e_r_i_a_l_m_a_s_t_e_r.html#a6b78f3634fd733feea1e7504e6a4ddc4" title="Data output.">DAT_O</a></span><span class="vhdlchar">:</span> <span class="vhdlkeyword">out</span> <span class="comment">std_logic_vector</span><span class="vhdlchar">(</span> <span class="vhdllogic"></span><span class="vhdllogic">31</span> <span class="vhdlkeyword">downto</span> <span class="vhdllogic"></span><span class="vhdllogic">0</span> <span class="vhdlchar">)</span>;
<a name="l00020"></a><a class="code" href="class_s_e_r_i_a_l_m_a_s_t_e_r.html#ae9849e01c32648d8e13000bd5fb9760f">00020</a> <span class="vhdlchar"><a class="code" href="class_s_e_r_i_a_l_m_a_s_t_e_r.html#ae9849e01c32648d8e13000bd5fb9760f" title="Reset input.">RST_I</a></span><span class="vhdlchar">:</span> <span class="vhdlkeyword">in</span> <span class="comment">std_logic</span>;
<a name="l00021"></a><a class="code" href="class_s_e_r_i_a_l_m_a_s_t_e_r.html#abd694a1729387db79033dcfd6bf320bc">00021</a> <span class="vhdlchar"><a class="code" href="class_s_e_r_i_a_l_m_a_s_t_e_r.html#abd694a1729387db79033dcfd6bf320bc" title="Select output.">SEL_O</a></span><span class="vhdlchar">:</span> <span class="vhdlkeyword">out</span> <span class="comment">std_logic</span>;
<a name="l00022"></a><a class="code" href="class_s_e_r_i_a_l_m_a_s_t_e_r.html#ac7ffa7be9c863895b0f1d1ec6e101169">00022</a> <span class="vhdlchar"><a class="code" href="class_s_e_r_i_a_l_m_a_s_t_e_r.html#ac7ffa7be9c863895b0f1d1ec6e101169" title="Strobe output (Works like a chip select)">STB_O</a></span><span class="vhdlchar">:</span> <span class="vhdlkeyword">out</span> <span class="comment">std_logic</span>;
<a name="l00023"></a><a class="code" href="class_s_e_r_i_a_l_m_a_s_t_e_r.html#a41e7e86f235d5f673607008142e1ecad">00023</a> <span class="vhdlchar"><a class="code" href="class_s_e_r_i_a_l_m_a_s_t_e_r.html#a41e7e86f235d5f673607008142e1ecad" title="Write enable.">WE_O</a></span><span class="vhdlchar">:</span> <span class="vhdlkeyword">out</span> <span class="comment">std_logic</span>;
<a name="l00024"></a>00024 <span class="keyword"></span>
<a name="l00025"></a>00025 <span class="keyword"> -- NON-WISHBONE Signals</span>
<a name="l00026"></a><a class="code" href="class_s_e_r_i_a_l_m_a_s_t_e_r.html#af163828b322f105b0c03724feea898ce">00026</a> <span class="vhdlchar"><a class="code" href="class_s_e_r_i_a_l_m_a_s_t_e_r.html#af163828b322f105b0c03724feea898ce" title="Signal byte received (Used to debug on the out leds)">byte_rec</a></span> <span class="vhdlchar">:</span> <span class="vhdlkeyword">out</span> <span class="comment">std_logic_vector</span><span class="vhdlchar">(</span><span class="vhdllogic"></span><span class="vhdllogic">7</span> <span class="vhdlkeyword">downto</span> <span class="vhdllogic"></span><span class="vhdllogic">0</span><span class="vhdlchar">)</span>
<a name="l00027"></a>00027 <span class="vhdlchar">)</span>;
<a name="l00028"></a>00028
<a name="l00029"></a>00029 <span class="vhdlkeyword">end</span> <span class="vhdlchar">SERIALMASTER</span>;
<a name="l00030"></a>00030
<a name="l00033"></a><a class="code" href="class_s_e_r_i_a_l_m_a_s_t_e_r_1_1_behavioral.html">00033</a> <span class="vhdlkeyword">architecture</span> Behavioral <span class="vhdlkeyword">of</span> <a class="code" href="class_s_e_r_i_a_l_m_a_s_t_e_r.html">SERIALMASTER</a> is
<a name="l00034"></a>00034 <span class="vhdlkeyword">signal</span> <span class="vhdlchar">masterSerialStates</span> <span class="vhdlchar">:</span> <span class="vhdlchar">testMaster</span>;
<a name="l00035"></a>00035 <span class="vhdlkeyword">signal</span> <span class="vhdlchar">byteIncome</span> <span class="vhdlchar">:</span> <span class="comment">std_logic_vector</span><span class="vhdlchar">(</span><span class="vhdllogic"></span><span class="vhdllogic">7</span> <span class="vhdlkeyword">downto</span> <span class="vhdllogic"></span><span class="vhdllogic">0</span><span class="vhdlchar">)</span>;
<a name="l00036"></a>00036 <span class="vhdlkeyword">begin</span>
<a name="l00037"></a>00037
<a name="l00038"></a>00038 <span class="vhdlkeyword">process</span> (<a class="code" href="class_s_e_r_i_a_l_m_a_s_t_e_r.html#a3582288d52a135a76a7de24d94b4dc68" title="Clock input.">CLK_I</a>)
<a name="l00039"></a>00039 <span class="vhdlkeyword">variable</span> <span class="vhdlchar">contWait</span> <span class="vhdlchar">:</span> <span class="comment">integer</span> <span class="vhdlkeyword">range</span> <span class="vhdllogic"></span><span class="vhdllogic">0</span> <span class="vhdlkeyword">to</span> <span class="vhdllogic"></span><span class="vhdllogic">50000000</span>;
<a name="l00040"></a>00040 <span class="vhdlkeyword">variable</span> <span class="vhdlchar">cycles2Wait</span> <span class="vhdlchar">:</span> <span class="comment">integer</span> <span class="vhdlkeyword">range</span> <span class="vhdllogic"></span><span class="vhdllogic">0</span> <span class="vhdlkeyword">to</span> <span class="vhdllogic"></span><span class="vhdllogic">50000000</span>;
<a name="l00041"></a>00041 <span class="vhdlkeyword">variable</span> <span class="vhdlchar">nextState</span><span class="vhdlchar">:</span> <span class="vhdlchar">testMaster</span>;
<a name="l00042"></a>00042 <span class="vhdlkeyword"> begin</span>
<a name="l00043"></a>00043 <span class="vhdlkeyword">if</span> <span class="vhdlchar">rising_edge</span><span class="vhdlchar">(</span><span class="vhdlchar"><a class="code" href="class_s_e_r_i_a_l_m_a_s_t_e_r.html#a3582288d52a135a76a7de24d94b4dc68" title="Clock input.">CLK_I</a></span><span class="vhdlchar">)</span> <span class="vhdlkeyword">then</span>
<a name="l00044"></a>00044 <span class="vhdlkeyword">if</span> <span class="vhdlchar"><a class="code" href="class_s_e_r_i_a_l_m_a_s_t_e_r.html#ae9849e01c32648d8e13000bd5fb9760f" title="Reset input.">RST_I</a></span> <span class="vhdlchar">=</span> <span class="vhdlchar">'</span><span class="vhdllogic"></span><span class="vhdllogic">1</span><span class="vhdlchar">'</span> <span class="vhdlkeyword">then</span>
<a name="l00045"></a>00045 <span class="vhdlchar">masterSerialStates</span> <span class="vhdlchar"><=</span> <span class="vhdlchar">idle</span>;
<a name="l00046"></a>00046 <span class="vhdlchar">nextState</span> <span class="vhdlchar">:=</span> <span class="vhdlchar">idle</span>;
<a name="l00047"></a>00047 <span class="vhdlchar">contWait</span> <span class="vhdlchar">:=</span> <span class="vhdllogic"></span><span class="vhdllogic">0</span>;
<a name="l00048"></a>00048 <span class="vhdlchar">cycles2Wait</span> <span class="vhdlchar">:=</span> <span class="vhdllogic"></span><span class="vhdllogic">25000000</span>;
<a name="l00049"></a>00049 <span class="vhdlchar">byteIncome</span> <span class="vhdlchar"><=</span> <span class="vhdlchar">conv_std_logic_vector</span><span class="vhdlchar">(</span><span class="vhdllogic"></span><span class="vhdllogic">64</span><span class="vhdlchar">,</span> <span class="vhdlchar">(</span><span class="vhdlchar">nBitsLarge</span><span class="vhdlchar">)</span><span class="vhdlchar">)</span>;<span class="keyword"> --Send the '@';</span>
<a name="l00050"></a>00050 <span class="vhdlkeyword">else</span>
<a name="l00051"></a>00051 <span class="vhdlkeyword">case</span> <span class="vhdlchar">masterSerialStates</span> <span class="vhdlkeyword">is</span>
<a name="l00052"></a>00052 <span class="vhdlkeyword">when</span> <span class="vhdlchar">idle</span> <span class="vhdlchar">=</span><span class="vhdlchar">></span>
<a name="l00053"></a>00053 <span class="vhdlchar">masterSerialStates</span> <span class="vhdlchar"><=</span> <span class="vhdlchar">config_clock</span>;
<a name="l00054"></a>00054 <span class="vhdlchar">nextState</span> <span class="vhdlchar">:=</span> <span class="vhdlchar">idle</span>;
<a name="l00055"></a>00055
<a name="l00056"></a>00056 <span class="vhdlkeyword">when</span> <span class="vhdlchar">config_clock</span> <span class="vhdlchar">=</span><span class="vhdlchar">></span>
<a name="l00057"></a>00057 <span class="vhdlchar">nextState</span> <span class="vhdlchar">:=</span> <span class="vhdlchar">config_baud</span>;
<a name="l00058"></a>00058 <span class="vhdlchar"><a class="code" href="class_s_e_r_i_a_l_m_a_s_t_e_r.html#a2331d71c69b0b20c1901627667a01471" title="Address output.">ADR_O</a></span> <span class="vhdlchar"><=</span> <span class="vhdllogic">"00"</span>;
<a name="l00059"></a>00059 <span class="vhdlchar"><a class="code" href="class_s_e_r_i_a_l_m_a_s_t_e_r.html#a41e7e86f235d5f673607008142e1ecad" title="Write enable.">WE_O</a></span> <span class="vhdlchar"><=</span> <span class="vhdlchar">'</span><span class="vhdllogic"></span><span class="vhdllogic">1</span><span class="vhdlchar">'</span>;
<a name="l00060"></a>00060 <span class="vhdlchar"><a class="code" href="class_s_e_r_i_a_l_m_a_s_t_e_r.html#ac7ffa7be9c863895b0f1d1ec6e101169" title="Strobe output (Works like a chip select)">STB_O</a></span> <span class="vhdlchar"><=</span> <span class="vhdlchar">'</span><span class="vhdllogic"></span><span class="vhdllogic">1</span><span class="vhdlchar">'</span>;
<a name="l00061"></a>00061 <span class="vhdlchar"><a class="code" href="class_s_e_r_i_a_l_m_a_s_t_e_r.html#a6b78f3634fd733feea1e7504e6a4ddc4" title="Data output.">DAT_O</a></span> <span class="vhdlchar"><=</span> <span class="vhdlchar">conv_std_logic_vector</span><span class="vhdlchar">(</span><span class="vhdllogic"></span><span class="vhdllogic">50000000</span><span class="vhdlchar">,</span> <span class="vhdlchar">(</span><span class="vhdlchar">nBitsLarge</span><span class="vhdlchar">)</span><span class="vhdlchar">)</span>;<span class="keyword"> -- 50Mhz</span>
<a name="l00062"></a>00062 <span class="vhdlkeyword">if</span> <span class="vhdlchar"><a class="code" href="class_s_e_r_i_a_l_m_a_s_t_e_r.html#a69bf28b7e6429b3f3e35bee455901578" title="Ack input.">ACK_I</a></span> <span class="vhdlchar">=</span> <span class="vhdlchar">'</span><span class="vhdllogic"></span><span class="vhdllogic">1</span><span class="vhdlchar">'</span> <span class="vhdlkeyword">then</span><span class="keyword"></span>
<a name="l00063"></a>00063 <span class="keyword"> -- Byte received <span class="vhdlkeyword">wait</span> some cycles <span class="vhdlkeyword">to</span> continue </span>
<a name="l00064"></a>00064 <span class="vhdlchar">masterSerialStates</span> <span class="vhdlchar"><=</span> <span class="vhdlchar">wait_cycles</span>;
<a name="l00065"></a>00065 <span class="vhdlchar"><a class="code" href="class_s_e_r_i_a_l_m_a_s_t_e_r.html#af163828b322f105b0c03724feea898ce" title="Signal byte received (Used to debug on the out leds)">byte_rec</a></span> <span class="vhdlchar"><=</span> <span class="vhdllogic">"00000001"</span>;
<a name="l00066"></a>00066 <span class="vhdlkeyword">end</span> <span class="vhdlkeyword">if</span>;
<a name="l00067"></a>00067
<a name="l00068"></a>00068 <span class="vhdlkeyword">when</span> <span class="vhdlchar">config_baud</span> <span class="vhdlchar">=</span><span class="vhdlchar">></span>
<a name="l00069"></a>00069 <span class="vhdlchar">nextState</span> <span class="vhdlchar">:=</span> <span class="vhdlchar">send_byte</span>;
<a name="l00070"></a>00070 <span class="vhdlchar"><a class="code" href="class_s_e_r_i_a_l_m_a_s_t_e_r.html#a2331d71c69b0b20c1901627667a01471" title="Address output.">ADR_O</a></span> <span class="vhdlchar"><=</span> <span class="vhdllogic">"01"</span>;
<a name="l00071"></a>00071 <span class="vhdlchar"><a class="code" href="class_s_e_r_i_a_l_m_a_s_t_e_r.html#a41e7e86f235d5f673607008142e1ecad" title="Write enable.">WE_O</a></span> <span class="vhdlchar"><=</span> <span class="vhdlchar">'</span><span class="vhdllogic"></span><span class="vhdllogic">1</span><span class="vhdlchar">'</span>;
<a name="l00072"></a>00072 <span class="vhdlchar"><a class="code" href="class_s_e_r_i_a_l_m_a_s_t_e_r.html#ac7ffa7be9c863895b0f1d1ec6e101169" title="Strobe output (Works like a chip select)">STB_O</a></span> <span class="vhdlchar"><=</span> <span class="vhdlchar">'</span><span class="vhdllogic"></span><span class="vhdllogic">1</span><span class="vhdlchar">'</span>;
<a name="l00073"></a>00073 <span class="vhdlchar"><a class="code" href="class_s_e_r_i_a_l_m_a_s_t_e_r.html#a6b78f3634fd733feea1e7504e6a4ddc4" title="Data output.">DAT_O</a></span> <span class="vhdlchar"><=</span> <span class="vhdlchar">conv_std_logic_vector</span><span class="vhdlchar">(</span><span class="vhdllogic"></span><span class="vhdllogic">115200</span><span class="vhdlchar">,</span> <span class="vhdlchar">(</span><span class="vhdlchar">nBitsLarge</span><span class="vhdlchar">)</span><span class="vhdlchar">)</span>;<span class="keyword"> --115200 bps</span>
<a name="l00074"></a>00074 <span class="vhdlkeyword">if</span> <span class="vhdlchar"><a class="code" href="class_s_e_r_i_a_l_m_a_s_t_e_r.html#a69bf28b7e6429b3f3e35bee455901578" title="Ack input.">ACK_I</a></span> <span class="vhdlchar">=</span> <span class="vhdlchar">'</span><span class="vhdllogic"></span><span class="vhdllogic">1</span><span class="vhdlchar">'</span> <span class="vhdlkeyword">then</span><span class="keyword"></span>
<a name="l00075"></a>00075 <span class="keyword"> -- Byte received <span class="vhdlkeyword">wait</span> some cycles <span class="vhdlkeyword">to</span> continue</span>
<a name="l00076"></a>00076 <span class="vhdlchar">masterSerialStates</span> <span class="vhdlchar"><=</span> <span class="vhdlchar">wait_cycles</span>;
<a name="l00077"></a>00077 <span class="vhdlchar"><a class="code" href="class_s_e_r_i_a_l_m_a_s_t_e_r.html#af163828b322f105b0c03724feea898ce" title="Signal byte received (Used to debug on the out leds)">byte_rec</a></span> <span class="vhdlchar"><=</span> <span class="vhdllogic">"00000010"</span>;
<a name="l00078"></a>00078 <span class="vhdlkeyword">end</span> <span class="vhdlkeyword">if</span>;
<a name="l00079"></a>00079
<a name="l00080"></a>00080 <span class="vhdlkeyword">when</span> <span class="vhdlchar">send_byte</span> <span class="vhdlchar">=</span><span class="vhdlchar">></span>
<a name="l00081"></a>00081 <span class="vhdlchar">nextState</span> <span class="vhdlchar">:=</span> <span class="vhdlchar">receive_byte</span>;
<a name="l00082"></a>00082 <span class="vhdlchar"><a class="code" href="class_s_e_r_i_a_l_m_a_s_t_e_r.html#a2331d71c69b0b20c1901627667a01471" title="Address output.">ADR_O</a></span> <span class="vhdlchar"><=</span> <span class="vhdllogic">"10"</span>;
<a name="l00083"></a>00083 <span class="vhdlchar"><a class="code" href="class_s_e_r_i_a_l_m_a_s_t_e_r.html#a41e7e86f235d5f673607008142e1ecad" title="Write enable.">WE_O</a></span> <span class="vhdlchar"><=</span> <span class="vhdlchar">'</span><span class="vhdllogic"></span><span class="vhdllogic">1</span><span class="vhdlchar">'</span>;
<a name="l00084"></a>00084 <span class="vhdlchar"><a class="code" href="class_s_e_r_i_a_l_m_a_s_t_e_r.html#ac7ffa7be9c863895b0f1d1ec6e101169" title="Strobe output (Works like a chip select)">STB_O</a></span> <span class="vhdlchar"><=</span> <span class="vhdlchar">'</span><span class="vhdllogic"></span><span class="vhdllogic">1</span><span class="vhdlchar">'</span>;<span class="keyword"></span>
<a name="l00085"></a>00085 <span class="keyword"> --DAT_O <= conv_std_logic_vector(</span><span class="vhdllogic">64</span>, (nBitsLarge)); --Send the '@'
<a name="l00086"></a>00086 <span class="vhdlchar"><a class="code" href="class_s_e_r_i_a_l_m_a_s_t_e_r.html#a6b78f3634fd733feea1e7504e6a4ddc4" title="Data output.">DAT_O</a></span> <span class="vhdlchar"><=</span> <span class="vhdlchar">conv_std_logic_vector</span><span class="vhdlchar">(</span><span class="vhdllogic"></span><span class="vhdllogic">0</span><span class="vhdlchar">,</span> <span class="vhdlchar">(</span><span class="vhdlchar">nBitsLarge</span><span class="vhdlchar">-</span><span class="vhdllogic"></span><span class="vhdllogic">8</span><span class="vhdlchar">)</span><span class="vhdlchar">)</span> <span class="vhdlchar">&</span> <span class="vhdlchar">byteIncome</span>;<span class="keyword"> --Send the '@'</span>
<a name="l00087"></a>00087 <span class="vhdlkeyword">if</span> <span class="vhdlchar"><a class="code" href="class_s_e_r_i_a_l_m_a_s_t_e_r.html#a69bf28b7e6429b3f3e35bee455901578" title="Ack input.">ACK_I</a></span> <span class="vhdlchar">=</span> <span class="vhdlchar">'</span><span class="vhdllogic"></span><span class="vhdllogic">1</span><span class="vhdlchar">'</span> <span class="vhdlkeyword">then</span><span class="keyword"></span>
<a name="l00088"></a>00088 <span class="keyword"> -- Byte received <span class="vhdlkeyword">wait</span> some cycles <span class="vhdlkeyword">to</span> continue</span>
<a name="l00089"></a>00089 <span class="vhdlchar">masterSerialStates</span> <span class="vhdlchar"><=</span> <span class="vhdlchar">wait_cycles</span>;
<a name="l00090"></a>00090 <span class="vhdlchar">cycles2Wait</span> <span class="vhdlchar">:=</span> <span class="vhdllogic"></span><span class="vhdllogic">7000000</span>;
<a name="l00091"></a>00091 <span class="vhdlkeyword">end</span> <span class="vhdlkeyword">if</span>;
<a name="l00092"></a>00092
<a name="l00093"></a>00093 <span class="vhdlkeyword">when</span> <span class="vhdlchar">receive_byte</span> <span class="vhdlchar">=</span><span class="vhdlchar">></span>
<a name="l00094"></a>00094 <span class="vhdlchar">nextState</span> <span class="vhdlchar">:=</span> <span class="vhdlchar">send_byte</span>;
<a name="l00095"></a>00095 <span class="vhdlchar"><a class="code" href="class_s_e_r_i_a_l_m_a_s_t_e_r.html#a2331d71c69b0b20c1901627667a01471" title="Address output.">ADR_O</a></span> <span class="vhdlchar"><=</span> <span class="vhdllogic">"11"</span>;
<a name="l00096"></a>00096 <span class="vhdlchar"><a class="code" href="class_s_e_r_i_a_l_m_a_s_t_e_r.html#a41e7e86f235d5f673607008142e1ecad" title="Write enable.">WE_O</a></span> <span class="vhdlchar"><=</span> <span class="vhdlchar">'</span><span class="vhdllogic"></span><span class="vhdllogic">0</span><span class="vhdlchar">'</span>;
<a name="l00097"></a>00097 <span class="vhdlchar"><a class="code" href="class_s_e_r_i_a_l_m_a_s_t_e_r.html#ac7ffa7be9c863895b0f1d1ec6e101169" title="Strobe output (Works like a chip select)">STB_O</a></span> <span class="vhdlchar"><=</span> <span class="vhdlchar">'</span><span class="vhdllogic"></span><span class="vhdllogic">1</span><span class="vhdlchar">'</span>;
<a name="l00098"></a>00098 <span class="vhdlkeyword">if</span> <span class="vhdlchar"><a class="code" href="class_s_e_r_i_a_l_m_a_s_t_e_r.html#a69bf28b7e6429b3f3e35bee455901578" title="Ack input.">ACK_I</a></span> <span class="vhdlchar">=</span> <span class="vhdlchar">'</span><span class="vhdllogic"></span><span class="vhdllogic">1</span><span class="vhdlchar">'</span> <span class="vhdlkeyword">then</span><span class="keyword"></span>
<a name="l00099"></a>00099 <span class="keyword"> -- Byte received <span class="vhdlkeyword">wait</span> some cycles <span class="vhdlkeyword">to</span> continue</span>
<a name="l00100"></a>00100 <span class="vhdlchar">masterSerialStates</span> <span class="vhdlchar"><=</span> <span class="vhdlchar">wait_cycles</span>;
<a name="l00101"></a>00101 <span class="vhdlchar"><a class="code" href="class_s_e_r_i_a_l_m_a_s_t_e_r.html#af163828b322f105b0c03724feea898ce" title="Signal byte received (Used to debug on the out leds)">byte_rec</a></span> <span class="vhdlchar"><=</span> <span class="vhdlchar"><a class="code" href="class_s_e_r_i_a_l_m_a_s_t_e_r.html#ab94f6b71e9a7ec24dab537723d8345d2" title="Data input.">DAT_I</a></span><span class="vhdlchar">(</span><span class="vhdllogic"></span><span class="vhdllogic">7</span> <span class="vhdlkeyword">downto</span> <span class="vhdllogic"></span><span class="vhdllogic">0</span><span class="vhdlchar">)</span>;
<a name="l00102"></a>00102 <span class="vhdlchar">byteIncome</span> <span class="vhdlchar"><=</span> <span class="vhdlchar"><a class="code" href="class_s_e_r_i_a_l_m_a_s_t_e_r.html#ab94f6b71e9a7ec24dab537723d8345d2" title="Data input.">DAT_I</a></span><span class="vhdlchar">(</span><span class="vhdllogic"></span><span class="vhdllogic">7</span> <span class="vhdlkeyword">downto</span> <span class="vhdllogic"></span><span class="vhdllogic">0</span><span class="vhdlchar">)</span>;
<a name="l00103"></a>00103 <span class="vhdlchar">cycles2Wait</span> <span class="vhdlchar">:=</span> <span class="vhdllogic"></span><span class="vhdllogic">7000000</span>;
<a name="l00104"></a>00104 <span class="vhdlkeyword">end</span> <span class="vhdlkeyword">if</span>;
<a name="l00105"></a>00105
<a name="l00106"></a>00106 <span class="vhdlkeyword">when</span> <span class="vhdlchar">wait_cycles</span> <span class="vhdlchar">=</span><span class="vhdlchar">></span><span class="keyword"></span>
<a name="l00107"></a>00107 <span class="keyword"> -- <span class="vhdlkeyword">wait</span> some cycles </span>
<a name="l00108"></a>00108 <span class="vhdlkeyword">if</span> <span class="vhdlchar">contWait</span> <span class="vhdlchar"><</span> <span class="vhdlchar">cycles2Wait</span> <span class="vhdlkeyword">then</span>
<a name="l00109"></a>00109 <span class="vhdlchar">contWait</span> <span class="vhdlchar">:=</span> <span class="vhdlchar">contWait</span> <span class="vhdlchar">+</span> <span class="vhdllogic"></span><span class="vhdllogic">1</span>;
<a name="l00110"></a>00110 <span class="vhdlchar"><a class="code" href="class_s_e_r_i_a_l_m_a_s_t_e_r.html#ac7ffa7be9c863895b0f1d1ec6e101169" title="Strobe output (Works like a chip select)">STB_O</a></span> <span class="vhdlchar"><=</span> <span class="vhdlchar">'</span><span class="vhdllogic"></span><span class="vhdllogic">0</span><span class="vhdlchar">'</span>;
<a name="l00111"></a>00111 <span class="vhdlkeyword">else</span>
<a name="l00112"></a>00112 <span class="vhdlchar">contWait</span> <span class="vhdlchar">:=</span> <span class="vhdllogic"></span><span class="vhdllogic">0</span>;
<a name="l00113"></a>00113 <span class="vhdlchar">masterSerialStates</span> <span class="vhdlchar"><=</span> <span class="vhdlchar">nextState</span>;
<a name="l00114"></a>00114 <span class="vhdlkeyword">end</span> <span class="vhdlkeyword">if</span>;
<a name="l00115"></a>00115 <span class="vhdlkeyword">end</span> <span class="vhdlkeyword">case</span>;
<a name="l00116"></a>00116 <span class="vhdlkeyword">end</span> <span class="vhdlkeyword">if</span>;
<a name="l00117"></a>00117 <span class="vhdlkeyword">end</span> <span class="vhdlkeyword">if</span>;
<a name="l00118"></a>00118 <span class="vhdlkeyword">end</span> <span class="vhdlkeyword">process</span>;
<a name="l00119"></a>00119
<a name="l00120"></a>00120
<a name="l00121"></a>00121 <span class="vhdlkeyword">end</span> <span class="vhdlchar">Behavioral</span>;
<a name="l00122"></a>00122
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