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\section{behavior Architecture Reference} \label{classtest_uart__wishbone__slave_1_1behavior}\index{behavior@{behavior}} \\* \\* \subsection*{Processes} \begin{DoxyCompactItemize} \item {\bf C\-L\-K\-\_\-\-I\-\_\-process}{\bfseries ( )}\label{classtest_uart__wishbone__slave_1_1behavior_ae6956df8a9f0a3de7db54c4ad6fe3299} \item {\bf stim\-\_\-proc}{\bfseries ( )}\label{classtest_uart__wishbone__slave_1_1behavior_ad2efa6785cff833c341e27596b21aeb5} \end{DoxyCompactItemize} \subsection*{Components} \begin{DoxyCompactItemize} \item {\bf uart\-\_\-wishbone\-\_\-slave} {\bfseries } \begin{DoxyCompactList}\small\item\em Reset Input. \end{DoxyCompactList}\end{DoxyCompactItemize} \subsection*{Constants} \begin{DoxyCompactItemize} \item {\bf C\-L\-K\-\_\-\-I\-\_\-period} {\bfseries time \-:= 20 ns } \label{classtest_uart__wishbone__slave_1_1behavior_aaba2bb0049306c18f246a63f6bc9c712} \end{DoxyCompactItemize} \subsection*{Signals} \begin{DoxyCompactItemize} \item {\bf R\-S\-T\-\_\-\-I} {\bfseries std\-\_\-logic \-:= ' 0 ' } \label{classtest_uart__wishbone__slave_1_1behavior_a6ee791bdb5df4ccca9dd8a946696dd8a} \begin{DoxyCompactList}\small\item\em Signal to connect with U\-U\-T. \end{DoxyCompactList}\item {\bf C\-L\-K\-\_\-\-I} {\bfseries std\-\_\-logic \-:= ' 0 ' } \label{classtest_uart__wishbone__slave_1_1behavior_a4c7b3772ac2a67a7c972f606d2cc4ec7} \begin{DoxyCompactList}\small\item\em Signal to connect with U\-U\-T. \end{DoxyCompactList}\item {\bf A\-D\-R\-\_\-\-I0} {\bfseries std\-\_\-logic\-\_\-vector ( 1 downto 0 ) \-:= ( others = $>$ ' 0 ' ) } \label{classtest_uart__wishbone__slave_1_1behavior_a7a6abb7d1c91a8dfcf6ab3d0bf78a3ae} \begin{DoxyCompactList}\small\item\em Signal to connect with U\-U\-T. \end{DoxyCompactList}\item {\bf D\-A\-T\-\_\-\-I0} {\bfseries std\-\_\-logic\-\_\-vector ( 31 downto 0 ) \-:= ( others = $>$ ' 0 ' ) } \label{classtest_uart__wishbone__slave_1_1behavior_a4b087814632daf135cbc38c252bbaf77} \begin{DoxyCompactList}\small\item\em Signal to connect with U\-U\-T. \end{DoxyCompactList}\item {\bf W\-E\-\_\-\-I} {\bfseries std\-\_\-logic \-:= ' 0 ' } \label{classtest_uart__wishbone__slave_1_1behavior_a7c70578f707dad097203747f4870b498} \item {\bf S\-T\-B\-\_\-\-I} {\bfseries std\-\_\-logic \-:= ' 0 ' } \label{classtest_uart__wishbone__slave_1_1behavior_a861b1f4580110b89b3be07a9a2b29bf7} \item {\bf serial\-\_\-in} {\bfseries std\-\_\-logic \-:= ' 0 ' } \label{classtest_uart__wishbone__slave_1_1behavior_a15d41e2405387248c782af0ee1e11517} \item {\bf D\-A\-T\-\_\-\-O0} {\bfseries std\-\_\-logic\-\_\-vector ( 31 downto 0 ) } \label{classtest_uart__wishbone__slave_1_1behavior_aa444d95093cb5f8197bb92d21da1f43a} \begin{DoxyCompactList}\small\item\em Signal to connect with U\-U\-T. \end{DoxyCompactList}\item {\bf A\-C\-K\-\_\-\-O} {\bfseries std\-\_\-logic } \label{classtest_uart__wishbone__slave_1_1behavior_a21f50c72e4e45c54ea44e014934312d4} \begin{DoxyCompactList}\small\item\em Signal to connect with U\-U\-T. \end{DoxyCompactList}\item {\bf serial\-\_\-out} {\bfseries std\-\_\-logic } \label{classtest_uart__wishbone__slave_1_1behavior_a30dda061cfa67e7c4d84ec0f5d1cb295} \begin{DoxyCompactList}\small\item\em Signal to connect with U\-U\-T. \end{DoxyCompactList}\item {\bf data\-\_\-\-Avaible} {\bfseries std\-\_\-logic } \label{classtest_uart__wishbone__slave_1_1behavior_a051f773441045ed070bde8d6139dd817} \begin{DoxyCompactList}\small\item\em Signal to connect with U\-U\-T. \end{DoxyCompactList}\end{DoxyCompactItemize} \subsection{Detailed Description} Definition at line 13 of file test\-Uart\-\_\-wishbone\-\_\-slave.\-vhd. \subsection{Member Data Documentation} \index{test\-Uart\-\_\-wishbone\-\_\-slave\-::behavior@{test\-Uart\-\_\-wishbone\-\_\-slave\-::behavior}!uart\-\_\-wishbone\-\_\-slave@{uart\-\_\-wishbone\-\_\-slave}} \index{uart\-\_\-wishbone\-\_\-slave@{uart\-\_\-wishbone\-\_\-slave}!testUart_wishbone_slave::behavior@{test\-Uart\-\_\-wishbone\-\_\-slave\-::behavior}} \subsubsection[{uart\-\_\-wishbone\-\_\-slave}]{\setlength{\rightskip}{0pt plus 5cm}{\bf uart\-\_\-wishbone\-\_\-slave} {\bfseries } \hspace{0.3cm}{\ttfamily [Component]}}\label{classtest_uart__wishbone__slave_1_1behavior_a5c22d67786c8d4257bb37aa2efb6f261} Reset Input. Clock Input Address input Data Input 0 Data Output 0 Write enable input Strobe input (Works like a chip select) Ack output Uart serial input Flag to indicate data avaible Definition at line 17 of file test\-Uart\-\_\-wishbone\-\_\-slave.\-vhd. The documentation for this class was generated from the following files\-:\begin{DoxyCompactItemize} \item E\-:/uart\-\_\-block/hdl/ise\-Project/test\-Uart\-\_\-wishbone\-\_\-slave.\-vhd\end{DoxyCompactItemize}