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\section{Behavioral Architecture Reference}
\label{classuart__wishbone__slave_1_1_behavioral}\index{Behavioral@{Behavioral}}
Top \doxyref{uart\-\_\-wishbone\-\_\-slave}{p.}{classuart__wishbone__slave} architecture.
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\subsection*{Components}
\begin{DoxyCompactItemize}
\item
{\bf uart\-\_\-control} {\bfseries }
\begin{DoxyCompactList}\small\item\em Global reset. \end{DoxyCompactList}\item
{\bf uart\-\_\-communication\-\_\-blocks} {\bfseries }
\begin{DoxyCompactList}\small\item\em Global reset. \end{DoxyCompactList}\end{DoxyCompactItemize}
\subsection*{Signals}
\begin{DoxyCompactItemize}
\item
{\bf baud\-\_\-wait} {\bfseries std\-\_\-logic\-\_\-vector ( ( n\-Bits\-Large -\/ 1 ) downto 0 ) } \label{classuart__wishbone__slave_1_1_behavioral_a02e6fc94d95d5dd4100e3116031c017d}
\item
{\bf tx\-\_\-data\-\_\-sent} {\bfseries std\-\_\-logic } \label{classuart__wishbone__slave_1_1_behavioral_a5e38b2036bfceaed6dd35ffe5106eb68}
\item
{\bf tx\-\_\-start} {\bfseries std\-\_\-logic } \label{classuart__wishbone__slave_1_1_behavioral_a55e879368f17fd77652395947f70a9fb}
\item
{\bf rst\-\_\-comm\-\_\-blocks} {\bfseries std\-\_\-logic } \label{classuart__wishbone__slave_1_1_behavioral_ac46b40649bbe9f0e9aa3b226b3d26bb6}
\item
{\bf rx\-\_\-data\-\_\-ready} {\bfseries std\-\_\-logic } \label{classuart__wishbone__slave_1_1_behavioral_a3c51937788e20277886cbe0d74d31e3c}
\item
{\bf data\-\_\-byte\-\_\-tx} {\bfseries std\-\_\-logic\-\_\-vector ( 7 downto 0 ) } \label{classuart__wishbone__slave_1_1_behavioral_aadcbdfcb50dfbf081d01dde343bfd15b}
\item
{\bf data\-\_\-byte\-\_\-rx} {\bfseries std\-\_\-logic\-\_\-vector ( 7 downto 0 ) } \label{classuart__wishbone__slave_1_1_behavioral_a7789228178d32293559434619171f1d6}
\end{DoxyCompactItemize}
\subsection{Detailed Description}
Top \doxyref{uart\-\_\-wishbone\-\_\-slave}{p.}{classuart__wishbone__slave} architecture.
Connect the control unit and the communication blocks
Definition at line 29 of file uart\-\_\-wishbone\-\_\-slave.\-vhd.
\subsection{Member Data Documentation}
\index{uart\-\_\-wishbone\-\_\-slave\-::\-Behavioral@{uart\-\_\-wishbone\-\_\-slave\-::\-Behavioral}!uart\-\_\-control@{uart\-\_\-control}}
\index{uart\-\_\-control@{uart\-\_\-control}!uart_wishbone_slave::Behavioral@{uart\-\_\-wishbone\-\_\-slave\-::\-Behavioral}}
\subsubsection[{uart\-\_\-control}]{\setlength{\rightskip}{0pt plus 5cm}{\bf uart\-\_\-control} {\bfseries } \hspace{0.3cm}{\ttfamily [Component]}}\label{classuart__wishbone__slave_1_1_behavioral_af10b00731d230bdd4222dc8e41e55ef0}
Global reset.
Global clock Write enable Register address Start (Strobe) Done (A\-C\-K) Data Input (Wishbone) Data output (Wishbone) Signal to control the baud rate frequency 1 Byte to be send to \doxyref{serial\-\_\-transmitter}{p.}{classserial__transmitter} 1 Byte to be received by \doxyref{serial\-\_\-receiver}{p.}{classserial__receiver} Signal comming from \doxyref{serial\-\_\-transmitter}{p.}{classserial__transmitter} Signal to start sending serial data... Reset Communication blocks
Definition at line 30 of file uart\-\_\-wishbone\-\_\-slave.\-vhd.
\index{uart\-\_\-wishbone\-\_\-slave\-::\-Behavioral@{uart\-\_\-wishbone\-\_\-slave\-::\-Behavioral}!uart\-\_\-communication\-\_\-blocks@{uart\-\_\-communication\-\_\-blocks}}
\index{uart\-\_\-communication\-\_\-blocks@{uart\-\_\-communication\-\_\-blocks}!uart_wishbone_slave::Behavioral@{uart\-\_\-wishbone\-\_\-slave\-::\-Behavioral}}
\subsubsection[{uart\-\_\-communication\-\_\-blocks}]{\setlength{\rightskip}{0pt plus 5cm}{\bf uart\-\_\-communication\-\_\-blocks} {\bfseries } \hspace{0.3cm}{\ttfamily [Component]}}\label{classuart__wishbone__slave_1_1_behavioral_abe1057034c94a40f3d4c739676dea66c}
Global reset.
Global clock Number of cycles to wait in order to generate desired baud Byte to transmit Byte to receive Indicate that byte has been sent Indicate that we got a byte Uart serial out Uart serial in Initiate transmission
Definition at line 48 of file uart\-\_\-wishbone\-\_\-slave.\-vhd.
The documentation for this class was generated from the following file\-:\begin{DoxyCompactItemize}
\item
E\-:/uart\-\_\-block/hdl/ise\-Project/{\bf uart\-\_\-wishbone\-\_\-slave.\-vhd}\end{DoxyCompactItemize}