URL
https://opencores.org/ocsvn/usb_fpga_2_14/usb_fpga_2_14/trunk
Subversion Repositories usb_fpga_2_14
[/] [usb_fpga_2_14/] [trunk/] [examples/] [memfifo/] [fpga-2.01b/] [memfifo.ucf] - Rev 2
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# IFCLK
NET "IFCLK" TNM_NET = "IFCLK";
TIMESPEC "TS_IFCLK" = PERIOD "IFCLK" 20 ns HIGH 50 %;
NET "IFCLK" LOC = "T8" | IOSTANDARD = LVCMOS33 ;
NET "reset" LOC = "R3" | IOSTANDARD = LVCMOS33 ; # PA7/FLAGD/SLCS#
# GPIO
NET "gpio_clk" LOC = "N12" | IOSTANDARD = LVCMOS33 ; # PC1/GPIFADR1
NET "gpio_dir" LOC = "P12" | IOSTANDARD = LVCMOS33 ; # PC2/GPIFADR2
NET "gpio_dat" LOC = "N5" | IOSTANDARD = LVCMOS33 | PULLUP; # PC3/GPIFADR3
NET "sw8" LOC = "L14" | IOSTANDARD = LVCMOS33 | PULLUP ; # B11 / L14~IO_L47P_FWE_B_M1DQ0_1
# led1
NET "led1<0>" LOC = "R16" | IOSTANDARD = LVCMOS33 | DRIVE = 12 ; # A6 / R16~IO_L49N_M1DQ11_1
NET "led1<1>" LOC = "R15" | IOSTANDARD = LVCMOS33 | DRIVE = 12 ; # B6 / R15~IO_L49P_M1DQ10_1
NET "led1<2>" LOC = "P16" | IOSTANDARD = LVCMOS33 | DRIVE = 12 ; # A7 / P16~IO_L48N_M1DQ9_1
NET "led1<3>" LOC = "P15" | IOSTANDARD = LVCMOS33 | DRIVE = 12 ; # B7 / P15~IO_L48P_HDC_M1DQ8_1
NET "led1<4>" LOC = "N16" | IOSTANDARD = LVCMOS33 | DRIVE = 12 ; # A8 / N16~IO_L45N_A0_M1LDQSN_1
NET "led1<5>" LOC = "N14" | IOSTANDARD = LVCMOS33 | DRIVE = 12 ; # B8 / N14~IO_L45P_A1_M1LDQS_1
NET "led1<6>" LOC = "M16" | IOSTANDARD = LVCMOS33 | DRIVE = 12 ; # A9 / M16~IO_L46N_FOE_B_M1DQ3_1
NET "led1<7>" LOC = "M15" | IOSTANDARD = LVCMOS33 | DRIVE = 12 ; # B9 / M15~IO_L46P_FCS_B_M1DQ2_1
NET "led1<8>" LOC = "L13" | IOSTANDARD = LVCMOS33 | DRIVE = 12 ; # A10 / L13~IO_L53N_VREF_1
NET "led1<9>" LOC = "L12" | IOSTANDARD = LVCMOS33 | DRIVE = 12 ; # B10 / L12~IO_L53P_1
NET "FD<0>" LOC = "T9" | IOSTANDARD = LVCMOS33 ; # PB0/FD0
NET "FD<1>" LOC = "R9" | IOSTANDARD = LVCMOS33 ; # PB1/FD1
NET "FD<2>" LOC = "P9" | IOSTANDARD = LVCMOS33 ; # PB2/FD2
NET "FD<3>" LOC = "N9" | IOSTANDARD = LVCMOS33 ; # PB3/FD3
NET "FD<4>" LOC = "M10" | IOSTANDARD = LVCMOS33 ; # PB4/FD4
NET "FD<5>" LOC = "P11" | IOSTANDARD = LVCMOS33 ; # PB5/FD5
NET "FD<6>" LOC = "M11" | IOSTANDARD = LVCMOS33 ; # PB6/FD6
NET "FD<7>" LOC = "M12" | IOSTANDARD = LVCMOS33 ; # PB7/FD7
NET "FD<8>" LOC = "P8" | IOSTANDARD = LVCMOS33 ; # PD0/FD8
NET "FD<9>" LOC = "M7" | IOSTANDARD = LVCMOS33 ; # PD1/FD9
NET "FD<10>" LOC = "P7" | IOSTANDARD = LVCMOS33 ; # PD2/FD10
NET "FD<11>" LOC = "R7" | IOSTANDARD = LVCMOS33 ; # PD3/FD11
NET "FD<12>" LOC = "M6" | IOSTANDARD = LVCMOS33 ; # PD4/FD12
NET "FD<13>" LOC = "N6" | IOSTANDARD = LVCMOS33 ; # PD5/FD13
NET "FD<14>" LOC = "P6" | IOSTANDARD = LVCMOS33 ; # PD6/FD14
NET "FD<15>" LOC = "T6" | IOSTANDARD = LVCMOS33 ; # PD7/FD15
NET "SLRD" LOC = "T4" | IOSTANDARD = LVCMOS33 ; # RDY0/SLRD
NET "SLWR" LOC = "P4" | IOSTANDARD = LVCMOS33 ; # RDY1/SLWR
NET "FLAGA" LOC = "L10" | IOSTANDARD = LVCMOS33 ; # CTL0/FLAGA
NET "FLAGB" LOC = "M9" | IOSTANDARD = LVCMOS33 ; # CTL1/FLAGB
NET "SLOE" LOC = "B10" | IOSTANDARD = LVCMOS33 | DRIVE = 12 ; # PA2
NET "FIFOADDR0" LOC = "T11" | IOSTANDARD = LVCMOS33 | DRIVE = 12 ; # PA4
NET "FIFOADDR1" LOC = "N11" | IOSTANDARD = LVCMOS33 | DRIVE = 12 ; # PA5
NET "PKTEND" LOC = "T5" | IOSTANDARD = LVCMOS33 | DRIVE = 12 ; # PA6