Subversion Repositories usb_fpga_2_14

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<!-- IMPORTANT: This is an internal file that has been generated
     by the Xilinx ISE software.  Any direct editing or
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     behavior or data corruption.  It is strongly advised that
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<messages>
<msg type="info" file="sim" num="172" delta="old" >Generating IP...
</msg>

<msg type="info" file="sim" num="993" delta="old" >The selected IP does not support an ASY schematic symbol.
</msg>

<msg type="info" file="sim" num="949" delta="old" >Finished generation of ASY schematic symbol.
</msg>

<msg type="warning" file="sim" num="0" delta="new" ><arg fmt="%s" index="1">The chosen IP does not support an SYM schematic symbol.</arg>
</msg>

<msg type="warning" file="coreutil" num="0" delta="new" >WARNING: de_DE.ISO-8859-1 is not supported as a language.  Using usenglish.
INFO:HDLCompiler:1845 - Analyzing Verilog file
   &quot;/drv_s2/usb-fpga/ztex/examples/usb-fpga-2.04/2.04b/memfifo/fpga/ipcore_dir/t
   mp/_cg/mem0/user_design/rtl/infrastructure.v&quot; into library work
INFO:ProjectMgmt - Parsing design hierarchy completed successfully.
Adding /drv_s2/usb-fpga/ztex/examples/usb-fpga-2.04/2.04b/memfifo/fpga/ipcore_dir/tmp/_cg/mem0/user_design/rtl/mcb_controller/iodrp_controller.v -view all -origin_type created
INFO:HDLCompiler:1845 - Analyzing Verilog file
   &quot;/drv_s2/usb-fpga/ztex/examples/usb-fpga-2.04/2.04b/memfifo/fpga/ipcore_dir/t
   mp/_cg/mem0/user_design/rtl/mcb_controller/iodrp_controller.v&quot; into library
   work
</msg>

<msg type="info" file="sim" num="948" delta="old" >Finished FLIST file generation.
</msg>

</messages>