Subversion Repositories usb_fpga_2_14

INFO:sim:172 - Generating IP...
Applying current project options...
Finished applying current project options.
Customizing IP...
Finished Customizing.
Resolving generic values...
Finished resolving generic values.
INFO:sim:993 - The selected IP does not support an ASY schematic symbol.
INFO:sim:949 - Finished generation of ASY schematic symbol.
WARNING:sim - The chosen IP does not support an SYM schematic symbol.
Generating metadata file...
Generating ISE project...
XCO file found: mem0.xco
XMDF file found: mem0_xmdf.tcl
Adding
/drv_s2/usb-fpga/ztex/examples/usb-fpga-2.04/2.04b/memfifo/fpga/ipcore_dir/tmp/_
cg/mem0/user_design/rtl/infrastructure.v -view all -origin_type created
WARNING:coreutil - WARNING: de_DE.ISO-8859-1 is not supported as a language. 
   Using usenglish.
   INFO:HDLCompiler:1845 - Analyzing Verilog file
   "/drv_s2/usb-fpga/ztex/examples/usb-fpga-2.04/2.04b/memfifo/fpga/ipcore_dir/t
      mp/_cg/mem0/user_design/rtl/infrastructure.v" into library work
   INFO:ProjectMgmt - Parsing design hierarchy completed successfully.
   Adding
   /drv_s2/usb-fpga/ztex/examples/usb-fpga-2.04/2.04b/memfifo/fpga/ipcore_dir/tm
   p/_cg/mem0/user_design/rtl/mcb_controller/iodrp_controller.v -view all
   -origin_type created
   INFO:HDLCompiler:1845 - Analyzing Verilog file
   "/drv_s2/usb-fpga/ztex/examples/usb-fpga-2.04/2.04b/memfifo/fpga/ipcore_dir/t
      mp/_cg/mem0/user_design/rtl/mcb_controller/iodrp_controller.v" into
   library
      work
INFO:ProjectMgmt - Parsing design hierarchy completed successfully.
Adding
/drv_s2/usb-fpga/ztex/examples/usb-fpga-2.04/2.04b/memfifo/fpga/ipcore_dir/tmp/_
cg/mem0/user_design/rtl/mcb_controller/iodrp_mcb_controller.v -view all
-origin_type created
INFO:HDLCompiler:1845 - Analyzing Verilog file
   "/drv_s2/usb-fpga/ztex/examples/usb-fpga-2.04/2.04b/memfifo/fpga/ipcore_dir/t
   mp/_cg/mem0/user_design/rtl/mcb_controller/iodrp_mcb_controller.v" into
   library work
INFO:ProjectMgmt - Parsing design hierarchy completed successfully.
Adding
/drv_s2/usb-fpga/ztex/examples/usb-fpga-2.04/2.04b/memfifo/fpga/ipcore_dir/tmp/_
cg/mem0/user_design/rtl/mcb_controller/mcb_raw_wrapper.v -view all -origin_type
created
INFO:HDLCompiler:1845 - Analyzing Verilog file
   "/drv_s2/usb-fpga/ztex/examples/usb-fpga-2.04/2.04b/memfifo/fpga/ipcore_dir/t
   mp/_cg/mem0/user_design/rtl/mcb_controller/mcb_raw_wrapper.v" into library
   work
INFO:ProjectMgmt - Parsing design hierarchy completed successfully.
Adding
/drv_s2/usb-fpga/ztex/examples/usb-fpga-2.04/2.04b/memfifo/fpga/ipcore_dir/tmp/_
cg/mem0/user_design/rtl/mcb_controller/mcb_soft_calibration.v -view all
-origin_type created
INFO:HDLCompiler:1845 - Analyzing Verilog file
   "/drv_s2/usb-fpga/ztex/examples/usb-fpga-2.04/2.04b/memfifo/fpga/ipcore_dir/t
   mp/_cg/mem0/user_design/rtl/mcb_controller/mcb_soft_calibration.v" into
   library work
INFO:ProjectMgmt - Parsing design hierarchy completed successfully.
Adding
/drv_s2/usb-fpga/ztex/examples/usb-fpga-2.04/2.04b/memfifo/fpga/ipcore_dir/tmp/_
cg/mem0/user_design/rtl/mcb_controller/mcb_soft_calibration_top.v -view all
-origin_type created
INFO:HDLCompiler:1845 - Analyzing Verilog file
   "/drv_s2/usb-fpga/ztex/examples/usb-fpga-2.04/2.04b/memfifo/fpga/ipcore_dir/t
   mp/_cg/mem0/user_design/rtl/mcb_controller/mcb_soft_calibration_top.v" into
   library work
INFO:ProjectMgmt - Parsing design hierarchy completed successfully.
Adding
/drv_s2/usb-fpga/ztex/examples/usb-fpga-2.04/2.04b/memfifo/fpga/ipcore_dir/tmp/_
cg/mem0/user_design/rtl/mcb_controller/mcb_ui_top.v -view all -origin_type
created
INFO:HDLCompiler:1845 - Analyzing Verilog file
   "/drv_s2/usb-fpga/ztex/examples/usb-fpga-2.04/2.04b/memfifo/fpga/ipcore_dir/t
   mp/_cg/mem0/user_design/rtl/mcb_controller/mcb_ui_top.v" into library work
INFO:ProjectMgmt - Parsing design hierarchy completed successfully.
Adding
/drv_s2/usb-fpga/ztex/examples/usb-fpga-2.04/2.04b/memfifo/fpga/ipcore_dir/tmp/_
cg/mem0/user_design/rtl/mem0.v -view all -origin_type created
INFO:HDLCompiler:1845 - Analyzing Verilog file
   "/drv_s2/usb-fpga/ztex/examples/usb-fpga-2.04/2.04b/memfifo/fpga/ipcore_dir/t
   mp/_cg/mem0/user_design/rtl/mem0.v" into library work
INFO:ProjectMgmt - Parsing design hierarchy completed successfully.
Adding
/drv_s2/usb-fpga/ztex/examples/usb-fpga-2.04/2.04b/memfifo/fpga/ipcore_dir/tmp/_
cg/mem0/user_design/rtl/memc_wrapper.v -view all -origin_type created
INFO:HDLCompiler:1845 - Analyzing Verilog file
   "/drv_s2/usb-fpga/ztex/examples/usb-fpga-2.04/2.04b/memfifo/fpga/ipcore_dir/t
   mp/_cg/mem0/user_design/rtl/memc_wrapper.v" into library work
INFO:ProjectMgmt - Parsing design hierarchy completed successfully.
Adding
/drv_s2/usb-fpga/ztex/examples/usb-fpga-2.04/2.04b/memfifo/fpga/ipcore_dir/tmp/_
cg/mem0/user_design/par/mem0.ucf -view all -origin_type created
INFO:TclTasksC:2116 - The automatic calculation of top has been turned-off.
   Please set the new top explicitly by running the "project set top" command.
   To re-calculate the new top automatically, set the "Auto Implementation Top"
   property to true.
Top level has been set to "/mem0"
Generating FLIST file...
INFO:sim:948 - Finished FLIST file generation.
Generating README file...
Launching README viewer...
Moving files to output directory...
Finished moving files to output directory
Wrote CGP file for project 'mem0'.