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[/] [usb_fpga_2_14/] [trunk/] [examples/] [memfifo/] [fpga-2.04b/] [ipcore_dir/] [mem0/] [example_design/] [par/] [example_top.ucf] - Rev 2
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################################################################################ Xilinx, Inc. 2006 www.xilinx.com## Do. Mai 22 14:50:41 2014## Generated by MIG Version 3.92################################################################################ File name : example_top.ucf#### Details : Constraints file## FPGA family: spartan6## FPGA: xc6slx16-ftg256## Speedgrade: -2## Design Entry: VERILOG## Design: with Test bench## DCM Used: Enable## No.Of Memory Controllers: 1########################################################################################################################################################### VCC AUX VOLTAGE############################################################################CONFIG VCCAUX=2.5; # Valid values are 2.5 and 3.3############################################################################# DDR2 requires the MCB to operate in Extended performance mode with higher Vccint# specification to achieve maximum frequency. Therefore, the following CONFIG constraint# follows the corresponding GUI option setting. However, DDR3 can operate at higher# frequencies with any Vcciint value by operating MCB in extended mode. Please do not# remove/edit the below constraint to avoid false errors.############################################################################CONFIG MCB_PERFORMANCE= STANDARD;################################################################################### Timing Ignore constraints for paths crossing the clock domain##################################################################################NET "memc?_wrapper_inst/mcb_ui_top_inst/mcb_raw_wrapper_inst/selfrefresh_mcb_mode" TIG;NET "c?_pll_lock" TIG;INST "memc?_wrapper_inst/mcb_ui_top_inst/mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DONE_SOFTANDHARD_CAL*" TIG;#Please uncomment the below TIG if used in a design which enables self-refresh mode#NET "memc?_wrapper_inst/mcb_ui_top_inst/mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/SELFREFRESH_MCB_REQ" TIG;############################################################################## Memory Controller 3## Memory Device: DDR_SDRAM->MT46V32M16XX-5B-IT## Frequency: 200 MHz## Time Period: 5000 ps## Supported Part Numbers: MT46V32M16BN-5B-IT######################################################################################################################################################### All the IO resources in an IO tile which contains DQSP/UDQSP are used# irrespective of a single-ended or differential DQS design. Any signal that# is connected to the free pin of the same IO tile in a single-ended design# will be unrouted. Hence, the IOB cannot used as general pupose IO.############################################################################CONFIG PROHIBIT = N1,H1;############################################################################## Clock constraints############################################################################NET "memc3_infrastructure_inst/sys_clk_ibufg" TNM_NET = "SYS_CLK3";TIMESPEC "TS_SYS_CLK3" = PERIOD "SYS_CLK3" 5 ns HIGH 50 %;########################################################################################################################################################## I/O TERMINATION############################################################################NET "mcb3_dram_dq[*]" IN_TERM = NONE;NET "mcb3_dram_dqs" IN_TERM = NONE;NET "mcb3_dram_udqs" IN_TERM = NONE;############################################################################# Status Signals############################################################################NET "error" IOSTANDARD = LVCMOS18 ;NET "calib_done" IOSTANDARD = LVCMOS18 ;NET "calib_done" LOC = "B5" ;NET "error" LOC = "A5" ;############################################################################# I/O STANDARDS############################################################################NET "mcb3_dram_dq[*]" IOSTANDARD = SSTL2_II ;NET "mcb3_dram_a[*]" IOSTANDARD = SSTL2_II ;NET "mcb3_dram_ba[*]" IOSTANDARD = SSTL2_II ;NET "mcb3_dram_dqs" IOSTANDARD = SSTL2_II ;NET "mcb3_dram_udqs" IOSTANDARD = SSTL2_II ;NET "mcb3_dram_ck" IOSTANDARD = DIFF_SSTL2_II ;NET "mcb3_dram_ck_n" IOSTANDARD = DIFF_SSTL2_II ;NET "mcb3_dram_cke" IOSTANDARD = SSTL2_II ;NET "mcb3_dram_ras_n" IOSTANDARD = SSTL2_II ;NET "mcb3_dram_cas_n" IOSTANDARD = SSTL2_II ;NET "mcb3_dram_we_n" IOSTANDARD = SSTL2_II ;NET "mcb3_dram_dm" IOSTANDARD = SSTL2_II ;NET "mcb3_dram_udm" IOSTANDARD = SSTL2_II ;NET "mcb3_rzq" IOSTANDARD = SSTL2_II ;NET "c3_sys_clk" IOSTANDARD = LVCMOS25 ;NET "c3_sys_rst_i" IOSTANDARD = LVCMOS25 ;############################################################################# MCB 3# Pin Location Constraints for Clock, Masks, Address, and Controls############################################################################NET "mcb3_dram_a[0]" LOC = "K5" ;NET "mcb3_dram_a[10]" LOC = "G6" ;NET "mcb3_dram_a[11]" LOC = "E3" ;NET "mcb3_dram_a[12]" LOC = "F3" ;NET "mcb3_dram_a[1]" LOC = "K6" ;NET "mcb3_dram_a[2]" LOC = "D1" ;NET "mcb3_dram_a[3]" LOC = "L4" ;NET "mcb3_dram_a[4]" LOC = "G5" ;NET "mcb3_dram_a[5]" LOC = "H4" ;NET "mcb3_dram_a[6]" LOC = "H3" ;NET "mcb3_dram_a[7]" LOC = "D3" ;NET "mcb3_dram_a[8]" LOC = "B2" ;NET "mcb3_dram_a[9]" LOC = "A2" ;NET "mcb3_dram_ba[0]" LOC = "C3" ;NET "mcb3_dram_ba[1]" LOC = "C2" ;NET "mcb3_dram_cas_n" LOC = "H5" ;NET "mcb3_dram_ck" LOC = "E2" ;NET "mcb3_dram_ck_n" LOC = "E1" ;NET "mcb3_dram_cke" LOC = "F4" ;NET "mcb3_dram_dm" LOC = "J4" ;NET "mcb3_dram_dq[0]" LOC = "K2" ;NET "mcb3_dram_dq[10]" LOC = "M2" ;NET "mcb3_dram_dq[11]" LOC = "M1" ;NET "mcb3_dram_dq[12]" LOC = "P2" ;NET "mcb3_dram_dq[13]" LOC = "P1" ;NET "mcb3_dram_dq[14]" LOC = "R2" ;NET "mcb3_dram_dq[15]" LOC = "R1" ;NET "mcb3_dram_dq[1]" LOC = "K1" ;NET "mcb3_dram_dq[2]" LOC = "J3" ;NET "mcb3_dram_dq[3]" LOC = "J1" ;NET "mcb3_dram_dq[4]" LOC = "F2" ;NET "mcb3_dram_dq[5]" LOC = "F1" ;NET "mcb3_dram_dq[6]" LOC = "G3" ;NET "mcb3_dram_dq[7]" LOC = "G1" ;NET "mcb3_dram_dq[8]" LOC = "L3" ;NET "mcb3_dram_dq[9]" LOC = "L1" ;NET "mcb3_dram_dqs" LOC = "H2" ;NET "mcb3_dram_ras_n" LOC = "J6" ;NET "c3_sys_clk" LOC = "M9" ;NET "c3_sys_rst_i" LOC = "P6" ;NET "mcb3_dram_udm" LOC = "K3" ;NET "mcb3_dram_udqs" LOC = "N3" ;NET "mcb3_dram_we_n" LOC = "C1" ;###################################################################################RZQ is required for all MCB designs. Do not move the location ##of this pin for ES devices.For production devices, RZQ can be moved to any ##valid package pin within the MCB bank.For designs using Calibrated Input Termination, ##a 2R resistor should be connected between RZQand ground, where R is the desired##input termination value. Otherwise, RZQ should be left as a no-connect (NC) pin.###################################################################################NET "mcb3_rzq" LOC = "M4" ;