Subversion Repositories usb_fpga_2_14

#!/bin/csh -f
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# ****************************************************************************
#   ____  ____
#  /   /\/   /
# /___/  \  /    Vendor                : Xilinx
# \   \   \/     Version               : 3.92
#  \   \         Application           : MIG
#  /   /         Filename              : timing_sim.bat
# /___/   /\     Date Last Modified    : $Date: 2011/06/02 07:17:01 $
# \   \  /  \    Date Created          : Fri Feb 06 2009
#  \___\/\___\
#
# Device            : Spartan-6
# Design Name       : DDR/DDR2/DDR3/LPDDR
# Purpose           : Batch file to generate simulation netlist file.
# Reference         :
# Revision History  :
# ****************************************************************************
 
echo Simulation Tool: TIMING SIMULATION
cd ../../par
./ise_flow.bat
echo Netlist Generated
cd ../sim/timing
echo done