Subversion Repositories usb_fpga_2_14

MIG: 20:56:23 : xml_input_file: mig_a.prj
MIG: 20:56:23 : Absolute path of xml_input_file: /drv_s2/usb-fpga/ztex/examples/memfifo/fpga-2.18/memfifo.srcs/sources_1/ip/mig_7series_0/mig_a.prj
MIG: 20:56:23 : xml_input_file: mig_a.prj
MIG: 20:56:23 : Absolute path of xml_input_file: /drv_s2/usb-fpga/ztex/examples/memfifo/fpga-2.18/memfifo.srcs/sources_1/ip/mig_7series_0/mig_a.prj
MIG: 20:56:24 : xml_input_file: mig_a.prj
MIG: 20:56:24 : Absolute path of xml_input_file: mig_a.prj
MIG: 20:56:24 : xml_input_file: mig_a.prj
MIG: 20:56:24 : Absolute path of xml_input_file: mig_a.prj
MIG: 20:56:24 : xml_input_file: /drv_s2/usb-fpga/ztex/examples/memfifo/fpga-2.18/memfifo.srcs/sources_1/ip/mig_7series_0/mig_a.prj
MIG: 20:56:24 : Absolute path of xml_input_file: /drv_s2/usb-fpga/ztex/examples/memfifo/fpga-2.18/memfifo.srcs/sources_1/ip/mig_7series_0/mig_a.prj
MIG: 20:56:24 : xml_input_file: /drv_s2/usb-fpga/ztex/examples/memfifo/fpga-2.18/memfifo.srcs/sources_1/ip/mig_7series_0/mig_a.prj
MIG: 20:56:24 : Absolute path of xml_input_file: /drv_s2/usb-fpga/ztex/examples/memfifo/fpga-2.18/memfifo.srcs/sources_1/ip/mig_7series_0/mig_a.prj
MIG: 20:56:24 : In updateAllModelParams
MIG: 20:56:24 : IGN:     <ModuleName>mig_7series_0</ModuleName> <==>     <ModuleName>mig_7series_0</ModuleName> 
MIG: 20:56:24 : IGN:         <InputClkFreq></InputClkFreq> <==>         <InputClkFreq>400</InputClkFreq> 
MIG: 20:56:24 : XGUI hdlLanguage: Verilog
MIG: 20:56:24 : xgui vivado_mode: xpg_pa
MIG: 20:56:24 : xgui hdlLanguage: Verilog -- hdlExt: v
MIG: 20:56:24 : Reading /drv_s2/usb-fpga/ztex/examples/memfifo/fpga-2.18/memfifo.srcs/sources_1/ip/mig_7series_0/mig_7series_0/user_design/rtl/mig_7series_0_mig.v ...
MIG: 20:56:25 : 
MIG: 20:56:25 : Inside fn mem: DDR3
MIG: 20:56:25 : QDRII+ Inside fn ui: 100000000
MIG: 20:56:25 : cntrl:  memtype: DDR3
MIG: 20:56:25 : 
MIG: 20:56:25 :  MMCM_VCO single ctrl param_name: MMCM_VCO --  possibleMaxVcoVal: 800 
MIG: 20:56:25 : 
MIG: 20:56:25 : 
MIG: 20:56:25 : 
MIG: 20:56:25 : 
MIG: 20:56:25 :  polarity_value: 1
MIG: 20:56:25 : 
MIG: 20:56:25 : 
MIG: 20:56:25 : cntrl:  memtype: DDR3
MIG: 20:56:26 : 
MIG: 20:56:26 :  Valid Param: DDR3_BANK_WIDTH ==> 3
MIG: 20:56:26 : 
MIG: 20:56:26 :  Valid Param: DDR3_CK_WIDTH ==> 1
MIG: 20:56:26 :  Invalid Param: DDR3_COL_WIDTH ==> 10
MIG: 20:56:26 : 
MIG: 20:56:26 :  Valid Param: DDR3_CS_WIDTH ==> 1
MIG: 20:56:26 : 
MIG: 20:56:26 :  Valid Param: DDR3_nCS_PER_RANK ==> 1
MIG: 20:56:26 : 
MIG: 20:56:26 :  Valid Param: DDR3_CKE_WIDTH ==> 1
MIG: 20:56:26 :  Invalid Param: DDR3_DATA_BUF_ADDR_WIDTH ==> 5
MIG: 20:56:26 :  Invalid Param: DDR3_DQ_CNT_WIDTH ==> 4
MIG: 20:56:26 :  Invalid Param: DDR3_DQ_PER_DM ==> 8
MIG: 20:56:26 : 
MIG: 20:56:26 :  Valid Param: DDR3_DM_WIDTH ==> 2
MIG: 20:56:26 : 
MIG: 20:56:26 :  Valid Param: DDR3_DQ_WIDTH ==> 16
MIG: 20:56:26 : 
MIG: 20:56:26 :  Valid Param: DDR3_DQS_WIDTH ==> 2
MIG: 20:56:26 : 
MIG: 20:56:26 :  Valid Param: DDR3_DQS_CNT_WIDTH ==> 1
MIG: 20:56:26 :  Invalid Param: DDR3_DRAM_WIDTH ==> 8
MIG: 20:56:26 : 
MIG: 20:56:26 :  Valid Param: ECC ==> OFF
MIG: 20:56:26 : 
MIG: 20:56:26 :  Valid Param: DDR3_DATA_WIDTH ==> 16
MIG: 20:56:26 :  Invalid Param: ECC_TEST ==> "OFF"
MIG: 20:56:26 :  Invalid Param: DDR3_PAYLOAD_WIDTH ==> (ECC_TEST == "OFF") ? DATA_WIDTH : DQ_WIDTH
MIG: 20:56:26 :  Invalid Param: DDR3_MEM_ADDR_ORDER ==> "BANK_ROW_COLUMN"
MIG: 20:56:26 :  Invalid Param: DDR3_nBANK_MACHS ==> 4
MIG: 20:56:26 :  Invalid Param: DDR3_RANKS ==> 1
MIG: 20:56:26 : 
MIG: 20:56:26 :  Valid Param: DDR3_ODT_WIDTH ==> 1
MIG: 20:56:26 : 
MIG: 20:56:26 :  Valid Param: DDR3_ROW_WIDTH ==> 14
MIG: 20:56:26 : 
MIG: 20:56:26 :  Valid Param: DDR3_ADDR_WIDTH ==> 28
MIG: 20:56:26 : 
MIG: 20:56:26 :  Valid Param: DDR3_USE_CS_PORT ==> 0
MIG: 20:56:26 : 
MIG: 20:56:26 :  Valid Param: DDR3_USE_DM_PORT ==> 1
MIG: 20:56:26 : 
MIG: 20:56:26 :  Valid Param: DDR3_USE_ODT_PORT ==> 1
MIG: 20:56:26 :  Invalid Param: DDR3_IS_CLK_SHARED ==> "FALSE"
MIG: 20:56:26 :  Invalid Param: DDR3_PHY_CONTROL_MASTER_BANK ==> 0
MIG: 20:56:26 :  Invalid Param: DDR3_MEM_DENSITY ==> "2Gb"
MIG: 20:56:26 :  Invalid Param: DDR3_MEM_SPEEDGRADE ==> "125"
MIG: 20:56:26 :  Invalid Param: DDR3_MEM_DEVICE_WIDTH ==> 16
MIG: 20:56:26 :  Invalid Param: DDR3_AL ==> "0"
MIG: 20:56:26 :  Invalid Param: DDR3_nAL ==> 0
MIG: 20:56:26 :  Invalid Param: DDR3_BURST_MODE ==> "8"
MIG: 20:56:26 :  Invalid Param: DDR3_BURST_TYPE ==> "SEQ"
MIG: 20:56:26 :  Invalid Param: DDR3_CL ==> 6
MIG: 20:56:26 :  Invalid Param: DDR3_CWL ==> 5
MIG: 20:56:26 :  Invalid Param: DDR3_OUTPUT_DRV ==> "HIGH"
MIG: 20:56:26 :  Invalid Param: DDR3_RTT_NOM ==> "40"
MIG: 20:56:26 :  Invalid Param: DDR3_RTT_WR ==> "OFF"
MIG: 20:56:26 :  Invalid Param: DDR3_ADDR_CMD_MODE ==> "1T"
MIG: 20:56:26 : 
MIG: 20:56:26 :  Valid Param: DDR3_REG_CTRL ==> OFF
MIG: 20:56:26 :  Invalid Param: DDR3_CA_MIRROR ==> "OFF"
MIG: 20:56:26 :  Invalid Param: DDR3_VDD_OP_VOLT ==> "150"
MIG: 20:56:26 :  Invalid Param: DDR3_CLKIN_PERIOD ==> 2500
MIG: 20:56:26 :  Invalid Param: DDR3_CLKFBOUT_MULT ==> 2
MIG: 20:56:26 :  Invalid Param: DDR3_DIVCLK_DIVIDE ==> 1
MIG: 20:56:26 :  Invalid Param: DDR3_CLKOUT0_PHASE ==> 337.5
MIG: 20:56:26 :  Invalid Param: DDR3_CLKOUT0_DIVIDE ==> 2
MIG: 20:56:26 :  Invalid Param: DDR3_CLKOUT1_DIVIDE ==> 2
MIG: 20:56:26 :  Invalid Param: DDR3_CLKOUT2_DIVIDE ==> 32
MIG: 20:56:26 :  Invalid Param: DDR3_CLKOUT3_DIVIDE ==> 8
MIG: 20:56:26 :  Invalid Param: DDR3_MMCM_VCO ==> 800
MIG: 20:56:26 :  Invalid Param: DDR3_MMCM_MULT_F ==> 8
MIG: 20:56:26 :  Invalid Param: DDR3_MMCM_DIVCLK_DIVIDE ==> 1
MIG: 20:56:26 :  Invalid Param: DDR3_tCKE ==> 5000
MIG: 20:56:26 :  Invalid Param: DDR3_tFAW ==> 40000
MIG: 20:56:26 :  Invalid Param: DDR3_tPRDI ==> 1_000_000
MIG: 20:56:26 :  Invalid Param: DDR3_tRAS ==> 35000
MIG: 20:56:26 :  Invalid Param: DDR3_tRCD ==> 13750
MIG: 20:56:26 :  Invalid Param: DDR3_tREFI ==> 7800000
MIG: 20:56:26 :  Invalid Param: DDR3_tRFC ==> 160000
MIG: 20:56:26 :  Invalid Param: DDR3_tRP ==> 13750
MIG: 20:56:26 :  Invalid Param: DDR3_tRRD ==> 7500
MIG: 20:56:26 :  Invalid Param: DDR3_tRTP ==> 7500
MIG: 20:56:26 :  Invalid Param: DDR3_tWTR ==> 7500
MIG: 20:56:26 :  Invalid Param: DDR3_tZQI ==> 128_000_000
MIG: 20:56:26 :  Invalid Param: DDR3_tZQCS ==> 64
MIG: 20:56:26 :  Invalid Param: DDR3_SIM_BYPASS_INIT_CAL ==> "OFF"
MIG: 20:56:26 :  Invalid Param: DDR3_SIMULATION ==> "FALSE"
MIG: 20:56:26 :  Invalid Param: DDR3_BYTE_LANES_B0 ==> 4'b1111
MIG: 20:56:26 :  Invalid Param: DDR3_BYTE_LANES_B1 ==> 4'b0000
MIG: 20:56:26 :  Invalid Param: DDR3_BYTE_LANES_B2 ==> 4'b0000
MIG: 20:56:26 :  Invalid Param: DDR3_BYTE_LANES_B3 ==> 4'b0000
MIG: 20:56:26 :  Invalid Param: DDR3_BYTE_LANES_B4 ==> 4'b0000
MIG: 20:56:26 :  Invalid Param: DDR3_DATA_CTL_B0 ==> 4'b0011
MIG: 20:56:26 :  Invalid Param: DDR3_DATA_CTL_B1 ==> 4'b0000
MIG: 20:56:26 :  Invalid Param: DDR3_DATA_CTL_B2 ==> 4'b0000
MIG: 20:56:26 :  Invalid Param: DDR3_DATA_CTL_B3 ==> 4'b0000
MIG: 20:56:26 :  Invalid Param: DDR3_DATA_CTL_B4 ==> 4'b0000
MIG: 20:56:26 :  Invalid Param: DDR3_PHY_0_BITLANES ==> 48'hFFF_CFF_3DF_2FF
MIG: 20:56:26 :  Invalid Param: DDR3_PHY_1_BITLANES ==> 48'h000_000_000_000
MIG: 20:56:26 :  Invalid Param: DDR3_PHY_2_BITLANES ==> 48'h000_000_000_000
MIG: 20:56:26 :  Invalid Param: DDR3_CK_BYTE_MAP ==> 144'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_02
MIG: 20:56:26 :  Invalid Param: DDR3_ADDR_MAP ==> 192'h000_000_037_025_03A_024_035_03B_039_027_031_026_023_034_036_038
MIG: 20:56:26 :  Invalid Param: DDR3_BANK_MAP ==> 36'h033_02A_032
MIG: 20:56:26 :  Invalid Param: DDR3_CAS_MAP ==> 12'h020
MIG: 20:56:26 :  Invalid Param: DDR3_CKE_ODT_BYTE_MAP ==> 8'h00
MIG: 20:56:26 :  Invalid Param: DDR3_CKE_MAP ==> 96'h000_000_000_000_000_000_000_02B
MIG: 20:56:26 :  Invalid Param: DDR3_ODT_MAP ==> 96'h000_000_000_000_000_000_000_030
MIG: 20:56:26 :  Invalid Param: DDR3_CS_MAP ==> 120'h000_000_000_000_000_000_000_000_000_000
MIG: 20:56:26 :  Invalid Param: DDR3_PARITY_MAP ==> 12'h000
MIG: 20:56:26 :  Invalid Param: DDR3_RAS_MAP ==> 12'h021
MIG: 20:56:26 :  Invalid Param: DDR3_WE_MAP ==> 12'h022
MIG: 20:56:26 :  Invalid Param: DDR3_DQS_BYTE_MAP ==> 144'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_01
MIG: 20:56:26 :  Invalid Param: DDR3_DATA0_MAP ==> 96'h016_018_014_019_010_017_011_013
MIG: 20:56:26 :  Invalid Param: DDR3_DATA1_MAP ==> 96'h003_002_005_004_001_006_000_007
MIG: 20:56:26 :  Invalid Param: DDR3_DATA2_MAP ==> 96'h000_000_000_000_000_000_000_000
MIG: 20:56:26 :  Invalid Param: DDR3_DATA3_MAP ==> 96'h000_000_000_000_000_000_000_000
MIG: 20:56:26 :  Invalid Param: DDR3_DATA4_MAP ==> 96'h000_000_000_000_000_000_000_000
MIG: 20:56:26 :  Invalid Param: DDR3_DATA5_MAP ==> 96'h000_000_000_000_000_000_000_000
MIG: 20:56:26 :  Invalid Param: DDR3_DATA6_MAP ==> 96'h000_000_000_000_000_000_000_000
MIG: 20:56:26 :  Invalid Param: DDR3_DATA7_MAP ==> 96'h000_000_000_000_000_000_000_000
MIG: 20:56:26 :  Invalid Param: DDR3_DATA8_MAP ==> 96'h000_000_000_000_000_000_000_000
MIG: 20:56:26 :  Invalid Param: DDR3_DATA9_MAP ==> 96'h000_000_000_000_000_000_000_000
MIG: 20:56:26 :  Invalid Param: DDR3_DATA10_MAP ==> 96'h000_000_000_000_000_000_000_000
MIG: 20:56:26 :  Invalid Param: DDR3_DATA11_MAP ==> 96'h000_000_000_000_000_000_000_000
MIG: 20:56:26 :  Invalid Param: DDR3_DATA12_MAP ==> 96'h000_000_000_000_000_000_000_000
MIG: 20:56:26 :  Invalid Param: DDR3_DATA13_MAP ==> 96'h000_000_000_000_000_000_000_000
MIG: 20:56:26 :  Invalid Param: DDR3_DATA14_MAP ==> 96'h000_000_000_000_000_000_000_000
MIG: 20:56:26 :  Invalid Param: DDR3_DATA15_MAP ==> 96'h000_000_000_000_000_000_000_000
MIG: 20:56:26 :  Invalid Param: DDR3_DATA16_MAP ==> 96'h000_000_000_000_000_000_000_000
MIG: 20:56:26 :  Invalid Param: DDR3_DATA17_MAP ==> 96'h000_000_000_000_000_000_000_000
MIG: 20:56:26 :  Invalid Param: DDR3_MASK0_MAP ==> 108'h000_000_000_000_000_000_000_009_012
MIG: 20:56:26 :  Invalid Param: DDR3_MASK1_MAP ==> 108'h000_000_000_000_000_000_000_000_000
MIG: 20:56:26 :  Invalid Param: DDR3_SLOT_0_CONFIG ==> 8'b0000_0001
MIG: 20:56:26 :  Invalid Param: DDR3_SLOT_1_CONFIG ==> 8'b0000_0000
MIG: 20:56:26 :  Invalid Param: DDR3_IBUF_LPWR_MODE ==> "OFF"
MIG: 20:56:26 :  Invalid Param: DDR3_DATA_IO_IDLE_PWRDWN ==> "ON"
MIG: 20:56:26 :  Invalid Param: DDR3_BANK_TYPE ==> "HR_IO"
MIG: 20:56:26 :  Invalid Param: DDR3_DATA_IO_PRIM_TYPE ==> "HR_LP"
MIG: 20:56:26 :  Invalid Param: DDR3_CKE_ODT_AUX ==> "FALSE"
MIG: 20:56:26 :  Invalid Param: DDR3_USER_REFRESH ==> "OFF"
MIG: 20:56:26 :  Invalid Param: DDR3_WRLVL ==> "ON"
MIG: 20:56:26 :  Invalid Param: DDR3_ORDERING ==> "NORM"
MIG: 20:56:26 :  Invalid Param: DDR3_CALIB_ROW_ADD ==> 16'h0000
MIG: 20:56:26 :  Invalid Param: DDR3_CALIB_COL_ADD ==> 12'h000
MIG: 20:56:26 :  Invalid Param: DDR3_CALIB_BA_ADD ==> 3'h0
MIG: 20:56:26 :  Invalid Param: DDR3_TCQ ==> 100
MIG: 20:56:26 :  Invalid Param: DDR3_IDELAY_ADJ ==> "OFF"
MIG: 20:56:26 :  Invalid Param: DDR3_FINE_PER_BIT ==> "OFF"
MIG: 20:56:26 :  Invalid Param: DDR3_CENTER_COMP_MODE ==> "OFF"
MIG: 20:56:26 :  Invalid Param: DDR3_PI_VAL_ADJ ==> "OFF"
MIG: 20:56:26 :  Invalid Param: DDR3_IODELAY_GRP0 ==> "MIG_7SERIES_0_IODELAY_MIG0"
MIG: 20:56:26 :  Invalid Param: DDR3_IODELAY_GRP1 ==> "MIG_7SERIES_0_IODELAY_MIG1"
MIG: 20:56:26 :  Invalid Param: DDR3_SYSCLK_TYPE ==> "NO_BUFFER"
MIG: 20:56:26 :  Invalid Param: DDR3_REFCLK_TYPE ==> "NO_BUFFER"
MIG: 20:56:26 :  Invalid Param: DDR3_SYS_RST_PORT ==> "FALSE"
MIG: 20:56:26 :  Invalid Param: DDR3_FPGA_SPEED_GRADE ==> 1
MIG: 20:56:26 :  Invalid Param: DDR3_CMD_PIPE_PLUS1 ==> "ON"
MIG: 20:56:26 :  Invalid Param: DDR3_DRAM_TYPE ==> "DDR3"
MIG: 20:56:26 :  Invalid Param: DDR3_CAL_WIDTH ==> "HALF"
MIG: 20:56:26 :  Invalid Param: DDR3_STARVE_LIMIT ==> 2
MIG: 20:56:26 :  Invalid Param: DDR3_REF_CLK_MMCM_IODELAY_CTRL ==> "FALSE"
MIG: 20:56:26 :  Invalid Param: DDR3_REFCLK_FREQ ==> 200.0
MIG: 20:56:26 :  Invalid Param: DDR3_DIFF_TERM_REFCLK ==> "TRUE"
MIG: 20:56:26 :  Invalid Param: DDR3_tCK ==> 2500
MIG: 20:56:26 : 
MIG: 20:56:26 :  Valid Param: DDR3_nCK_PER_CLK ==> 4
MIG: 20:56:26 :  Invalid Param: DDR3_DIFF_TERM_SYSCLK ==> "TRUE"
MIG: 20:56:26 : 
MIG: 20:56:26 :  Valid Param: DDR3_DEBUG_PORT ==> OFF
MIG: 20:56:26 : 
MIG: 20:56:26 :  Invalid Param: DDR3_TEMP_MON_CONTROL ==> "EXTERNAL"
MIG: 20:56:26 :  Invalid Param: DDR3_RST_ACT_LOW ==> 1
MIG: 20:56:26 : 
MIG: 20:56:26 : 
MIG: 20:56:26 : 
MIG: 20:56:26 : Same Interface
MIG: 21:38:28 : xml_input_file: mig_a.prj
MIG: 21:38:28 : Absolute path of xml_input_file: /drv_s2/usb-fpga/ztex/examples/memfifo/fpga-2.18/memfifo.srcs/sources_1/ip/mig_7series_0/mig_a.prj
MIG: 21:38:28 : xml_input_file: mig_a.prj
MIG: 21:38:28 : Absolute path of xml_input_file: /drv_s2/usb-fpga/ztex/examples/memfifo/fpga-2.18/memfifo.srcs/sources_1/ip/mig_7series_0/mig_a.prj
MIG: 21:38:28 : In updateAllModelParams
MIG: 21:38:28 : ################# RUNNING MIG BATCH ###################
MIG: 21:38:28 : Writing IN file for 'mig_7series_0'...compDirPath: /drv_s2/xilinx/Vivado/2014.4/data/ip/xilinx/mig_7series_v2_3... instDirPath: /drv_s2/usb-fpga/ztex/examples/memfifo/fpga-2.18/memfifo.srcs/sources_1/ip/mig_7series_0
MIG: 21:38:28 : synp_flow:  -- synthesis_mode: Other
MIG: 21:38:28 : outputDirectory: /drv_s2/usb-fpga/ztex/examples/memfifo/fpga-2.18/memfifo.srcs/sources_1/ip/mig_7series_0/_tmp/
MIG: 21:38:28 : vivado_mode: xpg_pa
MIG: 21:38:28 :  locked false  
MIG: 21:38:28 : HDL Language: Verilog
MIG: 21:38:28 : compInfo: true
MIG: 21:38:28 : Vivado Options xc7a200t fbg484 -2
MIG: 21:38:28 : 1: xc7a35t 2: csg324 3: -1
MIG: 21:38:28 : relative mig path: coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/lin/mig
MIG: 21:38:28 : xilinx_path: /drv_s2/xilinx/Vivado/2014.4/ids_lite/ISE
MIG: 21:38:28 : I am in catch area
MIG: 21:38:28 : Running /drv_s2/xilinx/Vivado/2014.4/ids_lite/ISE/coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/lin/mig -cg_exc_inp /drv_s2/usb-fpga/ztex/examples/memfifo/fpga-2.18/memfifo.srcs/sources_1/ip/mig_7series_0/xil_txt.in -cg_exc_out /drv_s2/usb-fpga/ztex/examples/memfifo/fpga-2.18/memfifo.srcs/sources_1/ip/mig_7series_0/xil_txt.out ... 
MIG: 21:38:42 : XML_INPUT_FILE: /drv_s2/usb-fpga/ztex/examples/memfifo/fpga-2.18/memfifo.srcs/sources_1/ip/mig_7series_0/mig_a.prj
MIG: 21:38:42 : Component_Name: mig_7series_0
MIG: 21:38:46 : ################# RUNNING MIG BATCH ###################
MIG: 21:38:46 : Writing IN file for 'mig_7series_0'...compDirPath: /drv_s2/xilinx/Vivado/2014.4/data/ip/xilinx/mig_7series_v2_3... instDirPath: /drv_s2/usb-fpga/ztex/examples/memfifo/fpga-2.18/memfifo.srcs/sources_1/ip/mig_7series_0
MIG: 21:38:46 : synp_flow:  -- synthesis_mode: Other
MIG: 21:38:46 : outputDirectory: /drv_s2/usb-fpga/ztex/examples/memfifo/fpga-2.18/memfifo.srcs/sources_1/ip/mig_7series_0/_tmp/
MIG: 21:38:46 : vivado_mode: xpg_pa
MIG: 21:38:46 :  locked false  
MIG: 21:38:46 : HDL Language: Verilog
MIG: 21:38:46 : compInfo: false
MIG: 21:38:46 : Vivado Options xc7a200t fbg484 -2
MIG: 21:38:46 : 1: xc7a35t 2: csg324 3: -1
MIG: 21:38:46 : relative mig path: coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/lin/mig
MIG: 21:38:46 : xilinx_path: /drv_s2/xilinx/Vivado/2014.4/ids_lite/ISE
MIG: 21:38:46 : I am in catch area
MIG: 21:38:46 : Running /drv_s2/xilinx/Vivado/2014.4/ids_lite/ISE/coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/lin/mig -cg_exc_inp /drv_s2/usb-fpga/ztex/examples/memfifo/fpga-2.18/memfifo.srcs/sources_1/ip/mig_7series_0/xil_txt.in -cg_exc_out /drv_s2/usb-fpga/ztex/examples/memfifo/fpga-2.18/memfifo.srcs/sources_1/ip/mig_7series_0/xil_txt.out ... 
MIG: 21:39:05 : XML_INPUT_FILE: /drv_s2/usb-fpga/ztex/examples/memfifo/fpga-2.18/memfifo.srcs/sources_1/ip/mig_7series_0/mig_a.prj
MIG: 21:39:05 : Component_Name: mig_7series_0
MIG: 21:39:19 : xml_input_file: mig_a.prj
MIG: 21:39:19 : Absolute path of xml_input_file: mig_a.prj
MIG: 21:39:19 : xml_input_file: mig_a.prj
MIG: 21:39:19 : Absolute path of xml_input_file: mig_a.prj
MIG: 21:39:19 : xml_input_file: /drv_s2/usb-fpga/ztex/examples/memfifo/fpga-2.18/memfifo.srcs/sources_1/ip/mig_7series_0/mig_a.prj
MIG: 21:39:19 : Absolute path of xml_input_file: /drv_s2/usb-fpga/ztex/examples/memfifo/fpga-2.18/memfifo.srcs/sources_1/ip/mig_7series_0/mig_a.prj
MIG: 21:39:19 : xml_input_file: /drv_s2/usb-fpga/ztex/examples/memfifo/fpga-2.18/memfifo.srcs/sources_1/ip/mig_7series_0/mig_a.prj
MIG: 21:39:19 : Absolute path of xml_input_file: /drv_s2/usb-fpga/ztex/examples/memfifo/fpga-2.18/memfifo.srcs/sources_1/ip/mig_7series_0/mig_a.prj
MIG: 21:39:19 : In updateAllModelParams
MIG: 21:39:19 : ################# RUNNING MIG BATCH ###################
MIG: 21:39:19 : Writing IN file for 'mig_7series_0'...compDirPath: /drv_s2/xilinx/Vivado/2014.4/data/ip/xilinx/mig_7series_v2_3... instDirPath: /drv_s2/usb-fpga/ztex/examples/memfifo/fpga-2.18/memfifo.srcs/sources_1/ip/mig_7series_0
MIG: 21:39:19 : synp_flow:  -- synthesis_mode: Other
MIG: 21:39:19 : outputDirectory: /drv_s2/usb-fpga/ztex/examples/memfifo/fpga-2.18/memfifo.srcs/sources_1/ip/mig_7series_0/_tmp/
MIG: 21:39:19 : vivado_mode: xpg_pa
MIG: 21:39:19 :  locked false  
MIG: 21:39:19 : HDL Language: Verilog
MIG: 21:39:19 : compInfo: true
MIG: 21:39:19 : Vivado Options xc7a200t fbg484 -2
MIG: 21:39:19 : 1: xc7a35t 2: csg324 3: -1
MIG: 21:39:19 : relative mig path: coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/lin/mig
MIG: 21:39:19 : xilinx_path: /drv_s2/xilinx/Vivado/2014.4/ids_lite/ISE
MIG: 21:39:19 : I am in catch area
MIG: 21:39:19 : Running /drv_s2/xilinx/Vivado/2014.4/ids_lite/ISE/coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/lin/mig -cg_exc_inp /drv_s2/usb-fpga/ztex/examples/memfifo/fpga-2.18/memfifo.srcs/sources_1/ip/mig_7series_0/xil_txt.in -cg_exc_out /drv_s2/usb-fpga/ztex/examples/memfifo/fpga-2.18/memfifo.srcs/sources_1/ip/mig_7series_0/xil_txt.out ... 
MIG: 21:39:34 : XML_INPUT_FILE: /drv_s2/usb-fpga/ztex/examples/memfifo/fpga-2.18/memfifo.srcs/sources_1/ip/mig_7series_0/mig_a.prj
MIG: 21:39:34 : Component_Name: mig_7series_0
MIG: 21:39:38 : Running customizer.xit
MIG: 21:39:38 : ################# RUNNING MIG INTERACTIVE ###################
MIG: 21:39:38 : Writing IN file for 'mig_7series_0'...compDirPath: /drv_s2/xilinx/Vivado/2014.4/data/ip/xilinx/mig_7series_v2_3... instDirPath: /home/stefan/.Xil/Vivado-24505-ws2/coregen/mig_7series_0
MIG: 21:39:38 : synp_flow:  -- synthesis_mode: Other
MIG: 21:39:38 : outputDirectory: /home/stefan/.Xil/Vivado-24505-ws2/coregen/mig_7series_0/_tmp/
MIG: 21:39:38 : vivado_mode: xpg_pa
MIG: 21:39:38 :  locked false  
MIG: 21:39:38 : HDL Language: Verilog
MIG: 21:39:38 : compInfo: false
MIG: 21:39:38 : Vivado Options xc7a200t fbg484 -2
MIG: 21:39:38 : 1: xc7a35t 2: csg324 3: -1
MIG: 21:39:38 : relative mig path: coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/lin/mig
MIG: 21:39:38 : xilinx_path: /drv_s2/xilinx/Vivado/2014.4/ids_lite/ISE
MIG: 21:39:38 : I am in catch area
MIG: 21:39:38 : Running /drv_s2/xilinx/Vivado/2014.4/ids_lite/ISE/coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/lin/mig -cg_exc_inp /home/stefan/.Xil/Vivado-24505-ws2/coregen/mig_7series_0/xil_txt.in -cg_exc_out /home/stefan/.Xil/Vivado-24505-ws2/coregen/mig_7series_0/xil_txt.out ... 
MIG: 21:41:00 : Prasad before: xmlPropertyPrj -- mig_a.prj
MIG: 21:41:00 : Prasad After: xmlPropertyPrj -- mig_b.prj
MIG: 21:41:00 : XML_INPUT_FILE: /home/stefan/.Xil/Vivado-24505-ws2/coregen/mig_7series_0/mig_b.prj
MIG: 21:41:00 : Component_Name: mig_7series_0
MIG: 21:41:00 : Moving mig_7series_0.veo ...
MIG: 21:41:00 : Moving mig_7series_0 ...
MIG: 21:41:00 : Moving mig_7series_0_xmdf.tcl ...
MIG: 21:41:00 : Moving log.txt ...
MIG: 21:41:00 : Sending back 0
MIG: 21:41:02 : xml_input_file: mig_b.prj
MIG: 21:41:02 : Absolute path of xml_input_file: /drv_s2/usb-fpga/ztex/examples/memfifo/fpga-2.18/memfifo.srcs/sources_1/ip/mig_7series_0/mig_b.prj
MIG: 21:41:02 : xml_input_file: mig_b.prj
MIG: 21:41:02 : Absolute path of xml_input_file: /drv_s2/usb-fpga/ztex/examples/memfifo/fpga-2.18/memfifo.srcs/sources_1/ip/mig_7series_0/mig_b.prj
MIG: 21:41:02 : In updateAllModelParams
MIG: 21:41:02 : IGN:     <ModuleName>mig_7series_0</ModuleName> <==>     <ModuleName>mig_7series_0</ModuleName> 
MIG: 21:41:02 : IGN:         <InputClkFreq></InputClkFreq> <==>         <InputClkFreq></InputClkFreq> 
MIG: 21:41:02 : XGUI hdlLanguage: Verilog
MIG: 21:41:02 : xgui vivado_mode: xpg_pa
MIG: 21:41:02 : xgui hdlLanguage: Verilog -- hdlExt: v
MIG: 21:41:02 : Reading /drv_s2/usb-fpga/ztex/examples/memfifo/fpga-2.18/memfifo.srcs/sources_1/ip/mig_7series_0/mig_7series_0/user_design/rtl/mig_7series_0_mig.v ...
MIG: 21:41:03 : 1
MIG: 21:41:03 : Inside fn mem: DDR3
MIG: 21:41:03 : QDRII+ Inside fn ui: 100000000
MIG: 21:41:03 : cntrl:  memtype: DDR3
MIG: 21:41:03 : 800
MIG: 21:41:03 :  MMCM_VCO single ctrl param_name: MMCM_VCO --  possibleMaxVcoVal: 800 
MIG: 21:41:03 : 
MIG: 21:41:03 : 
MIG: 21:41:03 : 100000000
MIG: 21:41:03 : 
MIG: 21:41:03 :  polarity_value: 1
MIG: 21:41:03 : 
MIG: 21:41:03 : EXTERNAL
MIG: 21:41:03 : cntrl:  memtype: DDR3
MIG: 21:41:03 : 
MIG: 21:41:03 :  Valid Param: DDR3_BANK_WIDTH ==> 3
MIG: 21:41:03 : 
MIG: 21:41:03 :  Valid Param: DDR3_CK_WIDTH ==> 1
MIG: 21:41:03 :  Invalid Param: DDR3_COL_WIDTH ==> 10
MIG: 21:41:03 : 
MIG: 21:41:03 :  Valid Param: DDR3_CS_WIDTH ==> 1
MIG: 21:41:03 : 
MIG: 21:41:03 :  Valid Param: DDR3_nCS_PER_RANK ==> 1
MIG: 21:41:03 : 
MIG: 21:41:03 :  Valid Param: DDR3_CKE_WIDTH ==> 1
MIG: 21:41:03 :  Invalid Param: DDR3_DATA_BUF_ADDR_WIDTH ==> 5
MIG: 21:41:03 :  Invalid Param: DDR3_DQ_CNT_WIDTH ==> 4
MIG: 21:41:03 :  Invalid Param: DDR3_DQ_PER_DM ==> 8
MIG: 21:41:03 : 2
MIG: 21:41:03 :  Valid Param: DDR3_DM_WIDTH ==> 2
MIG: 21:41:03 : 16
MIG: 21:41:03 :  Valid Param: DDR3_DQ_WIDTH ==> 16
MIG: 21:41:03 : 2
MIG: 21:41:03 :  Valid Param: DDR3_DQS_WIDTH ==> 2
MIG: 21:41:03 : 
MIG: 21:41:03 :  Valid Param: DDR3_DQS_CNT_WIDTH ==> 1
MIG: 21:41:03 :  Invalid Param: DDR3_DRAM_WIDTH ==> 8
MIG: 21:41:03 : 
MIG: 21:41:03 :  Valid Param: ECC ==> OFF
MIG: 21:41:03 : 16
MIG: 21:41:03 :  Valid Param: DDR3_DATA_WIDTH ==> 16
MIG: 21:41:03 :  Invalid Param: ECC_TEST ==> "OFF"
MIG: 21:41:03 :  Invalid Param: DDR3_PAYLOAD_WIDTH ==> (ECC_TEST == "OFF") ? DATA_WIDTH : DQ_WIDTH
MIG: 21:41:03 :  Invalid Param: DDR3_MEM_ADDR_ORDER ==> "BANK_ROW_COLUMN"
MIG: 21:41:03 :  Invalid Param: DDR3_nBANK_MACHS ==> 4
MIG: 21:41:03 :  Invalid Param: DDR3_RANKS ==> 1
MIG: 21:41:03 : 
MIG: 21:41:03 :  Valid Param: DDR3_ODT_WIDTH ==> 1
MIG: 21:41:03 : 
MIG: 21:41:03 :  Valid Param: DDR3_ROW_WIDTH ==> 14
MIG: 21:41:03 : 28
MIG: 21:41:03 :  Valid Param: DDR3_ADDR_WIDTH ==> 28
MIG: 21:41:03 : 0
MIG: 21:41:03 :  Valid Param: DDR3_USE_CS_PORT ==> 0
MIG: 21:41:03 : 
MIG: 21:41:03 :  Valid Param: DDR3_USE_DM_PORT ==> 1
MIG: 21:41:03 : 
MIG: 21:41:03 :  Valid Param: DDR3_USE_ODT_PORT ==> 1
MIG: 21:41:03 :  Invalid Param: DDR3_IS_CLK_SHARED ==> "FALSE"
MIG: 21:41:03 :  Invalid Param: DDR3_PHY_CONTROL_MASTER_BANK ==> 0
MIG: 21:41:03 :  Invalid Param: DDR3_MEM_DENSITY ==> "2Gb"
MIG: 21:41:03 :  Invalid Param: DDR3_MEM_SPEEDGRADE ==> "125"
MIG: 21:41:03 :  Invalid Param: DDR3_MEM_DEVICE_WIDTH ==> 16
MIG: 21:41:03 :  Invalid Param: DDR3_AL ==> "0"
MIG: 21:41:03 :  Invalid Param: DDR3_nAL ==> 0
MIG: 21:41:03 :  Invalid Param: DDR3_BURST_MODE ==> "8"
MIG: 21:41:03 :  Invalid Param: DDR3_BURST_TYPE ==> "SEQ"
MIG: 21:41:03 :  Invalid Param: DDR3_CL ==> 6
MIG: 21:41:03 :  Invalid Param: DDR3_CWL ==> 5
MIG: 21:41:03 :  Invalid Param: DDR3_OUTPUT_DRV ==> "HIGH"
MIG: 21:41:03 :  Invalid Param: DDR3_RTT_NOM ==> "40"
MIG: 21:41:03 :  Invalid Param: DDR3_RTT_WR ==> "OFF"
MIG: 21:41:03 :  Invalid Param: DDR3_ADDR_CMD_MODE ==> "1T"
MIG: 21:41:03 : 
MIG: 21:41:03 :  Valid Param: DDR3_REG_CTRL ==> OFF
MIG: 21:41:03 :  Invalid Param: DDR3_CA_MIRROR ==> "OFF"
MIG: 21:41:03 :  Invalid Param: DDR3_VDD_OP_VOLT ==> "150"
MIG: 21:41:03 :  Invalid Param: DDR3_CLKIN_PERIOD ==> -2147483647
MIG: 21:41:03 :  Invalid Param: DDR3_CLKFBOUT_MULT ==> 0
MIG: 21:41:03 :  Invalid Param: DDR3_DIVCLK_DIVIDE ==> 0
MIG: 21:41:03 :  Invalid Param: DDR3_CLKOUT0_PHASE ==> 337.5
MIG: 21:41:03 :  Invalid Param: DDR3_CLKOUT0_DIVIDE ==> 0
MIG: 21:41:03 :  Invalid Param: DDR3_CLKOUT1_DIVIDE ==> 0
MIG: 21:41:03 :  Invalid Param: DDR3_CLKOUT2_DIVIDE ==> 0
MIG: 21:41:03 :  Invalid Param: DDR3_CLKOUT3_DIVIDE ==> 0
MIG: 21:41:03 :  Invalid Param: DDR3_MMCM_VCO ==> 800
MIG: 21:41:03 :  Invalid Param: DDR3_MMCM_MULT_F ==> 8
MIG: 21:41:03 :  Invalid Param: DDR3_MMCM_DIVCLK_DIVIDE ==> 1
MIG: 21:41:03 :  Invalid Param: DDR3_tCKE ==> 5000
MIG: 21:41:03 :  Invalid Param: DDR3_tFAW ==> 40000
MIG: 21:41:03 :  Invalid Param: DDR3_tPRDI ==> 1_000_000
MIG: 21:41:03 :  Invalid Param: DDR3_tRAS ==> 35000
MIG: 21:41:03 :  Invalid Param: DDR3_tRCD ==> 13750
MIG: 21:41:03 :  Invalid Param: DDR3_tREFI ==> 7800000
MIG: 21:41:03 :  Invalid Param: DDR3_tRFC ==> 160000
MIG: 21:41:03 :  Invalid Param: DDR3_tRP ==> 13750
MIG: 21:41:03 :  Invalid Param: DDR3_tRRD ==> 7500
MIG: 21:41:03 :  Invalid Param: DDR3_tRTP ==> 7500
MIG: 21:41:03 :  Invalid Param: DDR3_tWTR ==> 7500
MIG: 21:41:03 :  Invalid Param: DDR3_tZQI ==> 128_000_000
MIG: 21:41:03 :  Invalid Param: DDR3_tZQCS ==> 64
MIG: 21:41:03 :  Invalid Param: DDR3_SIM_BYPASS_INIT_CAL ==> "OFF"
MIG: 21:41:03 :  Invalid Param: DDR3_SIMULATION ==> "FALSE"
MIG: 21:41:03 :  Invalid Param: DDR3_BYTE_LANES_B0 ==> 4'b1111
MIG: 21:41:03 :  Invalid Param: DDR3_BYTE_LANES_B1 ==> 4'b0000
MIG: 21:41:03 :  Invalid Param: DDR3_BYTE_LANES_B2 ==> 4'b0000
MIG: 21:41:03 :  Invalid Param: DDR3_BYTE_LANES_B3 ==> 4'b0000
MIG: 21:41:03 :  Invalid Param: DDR3_BYTE_LANES_B4 ==> 4'b0000
MIG: 21:41:03 :  Invalid Param: DDR3_DATA_CTL_B0 ==> 4'b0011
MIG: 21:41:03 :  Invalid Param: DDR3_DATA_CTL_B1 ==> 4'b0000
MIG: 21:41:03 :  Invalid Param: DDR3_DATA_CTL_B2 ==> 4'b0000
MIG: 21:41:03 :  Invalid Param: DDR3_DATA_CTL_B3 ==> 4'b0000
MIG: 21:41:03 :  Invalid Param: DDR3_DATA_CTL_B4 ==> 4'b0000
MIG: 21:41:03 :  Invalid Param: DDR3_PHY_0_BITLANES ==> 48'hFFF_FFC_3FE_2FF
MIG: 21:41:03 :  Invalid Param: DDR3_PHY_1_BITLANES ==> 48'h000_000_000_000
MIG: 21:41:03 :  Invalid Param: DDR3_PHY_2_BITLANES ==> 48'h000_000_000_000
MIG: 21:41:03 :  Invalid Param: DDR3_CK_BYTE_MAP ==> 144'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_02
MIG: 21:41:03 :  Invalid Param: DDR3_ADDR_MAP ==> 192'h000_000_027_031_035_032_026_039_025_038_024_037_02B_03B_034_03A
MIG: 21:41:03 :  Invalid Param: DDR3_BANK_MAP ==> 36'h029_033_02A
MIG: 21:41:03 :  Invalid Param: DDR3_CAS_MAP ==> 12'h023
MIG: 21:41:03 :  Invalid Param: DDR3_CKE_ODT_BYTE_MAP ==> 8'h00
MIG: 21:41:03 :  Invalid Param: DDR3_CKE_MAP ==> 96'h000_000_000_000_000_000_000_036
MIG: 21:41:03 :  Invalid Param: DDR3_ODT_MAP ==> 96'h000_000_000_000_000_000_000_030
MIG: 21:41:03 :  Invalid Param: DDR3_CS_MAP ==> 120'h000_000_000_000_000_000_000_000_000_000
MIG: 21:41:03 :  Invalid Param: DDR3_PARITY_MAP ==> 12'h000
MIG: 21:41:03 :  Invalid Param: DDR3_RAS_MAP ==> 12'h022
MIG: 21:41:03 :  Invalid Param: DDR3_WE_MAP ==> 12'h028
MIG: 21:41:03 :  Invalid Param: DDR3_DQS_BYTE_MAP ==> 144'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_01
MIG: 21:41:03 :  Invalid Param: DDR3_DATA0_MAP ==> 96'h019_012_017_013_011_014_018_015
MIG: 21:41:03 :  Invalid Param: DDR3_DATA1_MAP ==> 96'h004_000_007_005_006_001_002_003
MIG: 21:41:03 :  Invalid Param: DDR3_DATA2_MAP ==> 96'h000_000_000_000_000_000_000_000
MIG: 21:41:03 :  Invalid Param: DDR3_DATA3_MAP ==> 96'h000_000_000_000_000_000_000_000
MIG: 21:41:03 :  Invalid Param: DDR3_DATA4_MAP ==> 96'h000_000_000_000_000_000_000_000
MIG: 21:41:03 :  Invalid Param: DDR3_DATA5_MAP ==> 96'h000_000_000_000_000_000_000_000
MIG: 21:41:03 :  Invalid Param: DDR3_DATA6_MAP ==> 96'h000_000_000_000_000_000_000_000
MIG: 21:41:03 :  Invalid Param: DDR3_DATA7_MAP ==> 96'h000_000_000_000_000_000_000_000
MIG: 21:41:03 :  Invalid Param: DDR3_DATA8_MAP ==> 96'h000_000_000_000_000_000_000_000
MIG: 21:41:03 :  Invalid Param: DDR3_DATA9_MAP ==> 96'h000_000_000_000_000_000_000_000
MIG: 21:41:03 :  Invalid Param: DDR3_DATA10_MAP ==> 96'h000_000_000_000_000_000_000_000
MIG: 21:41:03 :  Invalid Param: DDR3_DATA11_MAP ==> 96'h000_000_000_000_000_000_000_000
MIG: 21:41:03 :  Invalid Param: DDR3_DATA12_MAP ==> 96'h000_000_000_000_000_000_000_000
MIG: 21:41:03 :  Invalid Param: DDR3_DATA13_MAP ==> 96'h000_000_000_000_000_000_000_000
MIG: 21:41:03 :  Invalid Param: DDR3_DATA14_MAP ==> 96'h000_000_000_000_000_000_000_000
MIG: 21:41:03 :  Invalid Param: DDR3_DATA15_MAP ==> 96'h000_000_000_000_000_000_000_000
MIG: 21:41:03 :  Invalid Param: DDR3_DATA16_MAP ==> 96'h000_000_000_000_000_000_000_000
MIG: 21:41:03 :  Invalid Param: DDR3_DATA17_MAP ==> 96'h000_000_000_000_000_000_000_000
MIG: 21:41:03 :  Invalid Param: DDR3_MASK0_MAP ==> 108'h000_000_000_000_000_000_000_009_016
MIG: 21:41:03 :  Invalid Param: DDR3_MASK1_MAP ==> 108'h000_000_000_000_000_000_000_000_000
MIG: 21:41:03 :  Invalid Param: DDR3_SLOT_0_CONFIG ==> 8'b0000_0001
MIG: 21:41:03 :  Invalid Param: DDR3_SLOT_1_CONFIG ==> 8'b0000_0000
MIG: 21:41:03 :  Invalid Param: DDR3_IBUF_LPWR_MODE ==> "OFF"
MIG: 21:41:03 :  Invalid Param: DDR3_DATA_IO_IDLE_PWRDWN ==> "ON"
MIG: 21:41:03 :  Invalid Param: DDR3_BANK_TYPE ==> "HR_IO"
MIG: 21:41:03 :  Invalid Param: DDR3_DATA_IO_PRIM_TYPE ==> "HR_LP"
MIG: 21:41:03 :  Invalid Param: DDR3_CKE_ODT_AUX ==> "FALSE"
MIG: 21:41:03 :  Invalid Param: DDR3_USER_REFRESH ==> "OFF"
MIG: 21:41:03 :  Invalid Param: DDR3_WRLVL ==> "ON"
MIG: 21:41:03 :  Invalid Param: DDR3_ORDERING ==> "NORM"
MIG: 21:41:03 :  Invalid Param: DDR3_CALIB_ROW_ADD ==> 16'h0000
MIG: 21:41:03 :  Invalid Param: DDR3_CALIB_COL_ADD ==> 12'h000
MIG: 21:41:03 :  Invalid Param: DDR3_CALIB_BA_ADD ==> 3'h0
MIG: 21:41:03 :  Invalid Param: DDR3_TCQ ==> 100
MIG: 21:41:03 :  Invalid Param: DDR3_IDELAY_ADJ ==> "OFF"
MIG: 21:41:03 :  Invalid Param: DDR3_FINE_PER_BIT ==> "OFF"
MIG: 21:41:03 :  Invalid Param: DDR3_CENTER_COMP_MODE ==> "OFF"
MIG: 21:41:03 :  Invalid Param: DDR3_PI_VAL_ADJ ==> "OFF"
MIG: 21:41:03 :  Invalid Param: DDR3_IODELAY_GRP0 ==> "MIG_7SERIES_0_IODELAY_MIG0"
MIG: 21:41:03 :  Invalid Param: DDR3_IODELAY_GRP1 ==> "MIG_7SERIES_0_IODELAY_MIG1"
MIG: 21:41:03 :  Invalid Param: DDR3_SYSCLK_TYPE ==> "NO_BUFFER"
MIG: 21:41:03 :  Invalid Param: DDR3_REFCLK_TYPE ==> "NO_BUFFER"
MIG: 21:41:03 :  Invalid Param: DDR3_SYS_RST_PORT ==> "FALSE"
MIG: 21:41:03 :  Invalid Param: DDR3_FPGA_SPEED_GRADE ==> 2
MIG: 21:41:03 :  Invalid Param: DDR3_CMD_PIPE_PLUS1 ==> "ON"
MIG: 21:41:03 :  Invalid Param: DDR3_DRAM_TYPE ==> "DDR3"
MIG: 21:41:03 :  Invalid Param: DDR3_CAL_WIDTH ==> "HALF"
MIG: 21:41:03 :  Invalid Param: DDR3_STARVE_LIMIT ==> 2
MIG: 21:41:03 :  Invalid Param: DDR3_REF_CLK_MMCM_IODELAY_CTRL ==> "FALSE"
MIG: 21:41:03 :  Invalid Param: DDR3_REFCLK_FREQ ==> 200.0
MIG: 21:41:03 :  Invalid Param: DDR3_DIFF_TERM_REFCLK ==> "TRUE"
MIG: 21:41:03 :  Invalid Param: DDR3_tCK ==> 2500
MIG: 21:41:03 : 4
MIG: 21:41:03 :  Valid Param: DDR3_nCK_PER_CLK ==> 4
MIG: 21:41:03 :  Invalid Param: DDR3_DIFF_TERM_SYSCLK ==> "TRUE"
MIG: 21:41:03 : 
MIG: 21:41:03 :  Valid Param: DDR3_DEBUG_PORT ==> OFF
MIG: 21:41:03 : 
MIG: 21:41:03 :  Invalid Param: DDR3_TEMP_MON_CONTROL ==> "EXTERNAL"
MIG: 21:41:03 :  Invalid Param: DDR3_RST_ACT_LOW ==> 1
MIG: 21:41:03 : NOBUF
MIG: 21:41:03 : NOBUF
MIG: 21:41:03 : 
MIG: 21:41:03 : Same Interface
MIG: 21:41:39 : Running synthesis.xit
MIG: 21:41:39 : IGN:     <ModuleName>mig_7series_0</ModuleName> <==>     <ModuleName>mig_7series_0</ModuleName> 
MIG: 21:41:39 : IGN:         <InputClkFreq></InputClkFreq> <==>         <InputClkFreq></InputClkFreq> 
MIG: 21:41:39 : Running vlog_synth_rpr.xit
MIG: 21:41:39 : IGN:     <ModuleName>mig_7series_0</ModuleName> <==>     <ModuleName>mig_7series_0</ModuleName> 
MIG: 21:41:39 : IGN:         <InputClkFreq></InputClkFreq> <==>         <InputClkFreq></InputClkFreq> 
MIG: 21:41:39 : Running simulation.xit
MIG: 21:41:39 : IGN:     <ModuleName>mig_7series_0</ModuleName> <==>     <ModuleName>mig_7series_0</ModuleName> 
MIG: 21:41:39 : IGN:         <InputClkFreq></InputClkFreq> <==>         <InputClkFreq></InputClkFreq> 
MIG: 21:41:39 : Running vlog_sim_rpr.xit .. PRASAD DBG1
MIG: 21:41:39 : IGN:     <ModuleName>mig_7series_0</ModuleName> <==>     <ModuleName>mig_7series_0</ModuleName> 
MIG: 21:41:39 : IGN:         <InputClkFreq></InputClkFreq> <==>         <InputClkFreq></InputClkFreq> 
MIG: 21:41:39 : Running implementation.xit
MIG: 21:41:39 : IGN:     <ModuleName>mig_7series_0</ModuleName> <==>     <ModuleName>mig_7series_0</ModuleName> 
MIG: 21:41:39 : IGN:         <InputClkFreq></InputClkFreq> <==>         <InputClkFreq></InputClkFreq> 
MIG: 21:42:57 : xml_input_file: mig_b.prj
MIG: 21:42:58 : Absolute path of xml_input_file: mig_b.prj
MIG: 21:42:58 : xml_input_file: mig_b.prj
MIG: 21:42:58 : Absolute path of xml_input_file: mig_b.prj
MIG: 21:42:58 : xml_input_file: /drv_s2/usb-fpga/ztex/examples/memfifo/fpga-2.18/memfifo.srcs/sources_1/ip/mig_7series_0/mig_b.prj
MIG: 21:42:58 : Absolute path of xml_input_file: /drv_s2/usb-fpga/ztex/examples/memfifo/fpga-2.18/memfifo.srcs/sources_1/ip/mig_7series_0/mig_b.prj
MIG: 21:42:58 : xml_input_file: /drv_s2/usb-fpga/ztex/examples/memfifo/fpga-2.18/memfifo.srcs/sources_1/ip/mig_7series_0/mig_b.prj
MIG: 21:42:58 : Absolute path of xml_input_file: /drv_s2/usb-fpga/ztex/examples/memfifo/fpga-2.18/memfifo.srcs/sources_1/ip/mig_7series_0/mig_b.prj
MIG: 21:42:58 : In updateAllModelParams
MIG: 21:42:58 : IGN:     <ModuleName>mig_7series_0</ModuleName> <==>     <ModuleName>mig_7series_0</ModuleName> 
MIG: 21:42:58 : IGN:         <InputClkFreq></InputClkFreq> <==>         <InputClkFreq></InputClkFreq> 
MIG: 21:42:58 : XGUI hdlLanguage: Verilog
MIG: 21:42:58 : xgui vivado_mode: xpg_pa
MIG: 21:42:58 : xgui hdlLanguage: Verilog -- hdlExt: v
MIG: 21:42:58 : Reading /drv_s2/usb-fpga/ztex/examples/memfifo/fpga-2.18/memfifo.srcs/sources_1/ip/mig_7series_0/mig_7series_0/user_design/rtl/mig_7series_0_mig.v ...
MIG: 21:42:59 : 
MIG: 21:42:59 : Inside fn mem: DDR3
MIG: 21:42:59 : QDRII+ Inside fn ui: 100000000
MIG: 21:42:59 : cntrl:  memtype: DDR3
MIG: 21:42:59 : 
MIG: 21:42:59 :  MMCM_VCO single ctrl param_name: MMCM_VCO --  possibleMaxVcoVal: 800 
MIG: 21:42:59 : 
MIG: 21:42:59 : 
MIG: 21:42:59 : 
MIG: 21:42:59 : 
MIG: 21:42:59 :  polarity_value: 1
MIG: 21:42:59 : 
MIG: 21:42:59 : 
MIG: 21:42:59 : cntrl:  memtype: DDR3
MIG: 21:42:59 : 
MIG: 21:42:59 :  Valid Param: DDR3_BANK_WIDTH ==> 3
MIG: 21:42:59 : 
MIG: 21:42:59 :  Valid Param: DDR3_CK_WIDTH ==> 1
MIG: 21:42:59 :  Invalid Param: DDR3_COL_WIDTH ==> 10
MIG: 21:42:59 : 
MIG: 21:42:59 :  Valid Param: DDR3_CS_WIDTH ==> 1
MIG: 21:42:59 : 
MIG: 21:42:59 :  Valid Param: DDR3_nCS_PER_RANK ==> 1
MIG: 21:42:59 : 
MIG: 21:42:59 :  Valid Param: DDR3_CKE_WIDTH ==> 1
MIG: 21:42:59 :  Invalid Param: DDR3_DATA_BUF_ADDR_WIDTH ==> 5
MIG: 21:42:59 :  Invalid Param: DDR3_DQ_CNT_WIDTH ==> 4
MIG: 21:42:59 :  Invalid Param: DDR3_DQ_PER_DM ==> 8
MIG: 21:42:59 : 
MIG: 21:42:59 :  Valid Param: DDR3_DM_WIDTH ==> 2
MIG: 21:42:59 : 
MIG: 21:42:59 :  Valid Param: DDR3_DQ_WIDTH ==> 16
MIG: 21:42:59 : 
MIG: 21:42:59 :  Valid Param: DDR3_DQS_WIDTH ==> 2
MIG: 21:42:59 : 
MIG: 21:42:59 :  Valid Param: DDR3_DQS_CNT_WIDTH ==> 1
MIG: 21:42:59 :  Invalid Param: DDR3_DRAM_WIDTH ==> 8
MIG: 21:42:59 : 
MIG: 21:42:59 :  Valid Param: ECC ==> OFF
MIG: 21:42:59 : 
MIG: 21:42:59 :  Valid Param: DDR3_DATA_WIDTH ==> 16
MIG: 21:42:59 :  Invalid Param: ECC_TEST ==> "OFF"
MIG: 21:42:59 :  Invalid Param: DDR3_PAYLOAD_WIDTH ==> (ECC_TEST == "OFF") ? DATA_WIDTH : DQ_WIDTH
MIG: 21:42:59 :  Invalid Param: DDR3_MEM_ADDR_ORDER ==> "BANK_ROW_COLUMN"
MIG: 21:42:59 :  Invalid Param: DDR3_nBANK_MACHS ==> 4
MIG: 21:42:59 :  Invalid Param: DDR3_RANKS ==> 1
MIG: 21:42:59 : 
MIG: 21:42:59 :  Valid Param: DDR3_ODT_WIDTH ==> 1
MIG: 21:42:59 : 
MIG: 21:42:59 :  Valid Param: DDR3_ROW_WIDTH ==> 14
MIG: 21:42:59 : 
MIG: 21:42:59 :  Valid Param: DDR3_ADDR_WIDTH ==> 28
MIG: 21:42:59 : 
MIG: 21:42:59 :  Valid Param: DDR3_USE_CS_PORT ==> 0
MIG: 21:42:59 : 
MIG: 21:42:59 :  Valid Param: DDR3_USE_DM_PORT ==> 1
MIG: 21:42:59 : 
MIG: 21:42:59 :  Valid Param: DDR3_USE_ODT_PORT ==> 1
MIG: 21:42:59 :  Invalid Param: DDR3_IS_CLK_SHARED ==> "FALSE"
MIG: 21:42:59 :  Invalid Param: DDR3_PHY_CONTROL_MASTER_BANK ==> 0
MIG: 21:42:59 :  Invalid Param: DDR3_MEM_DENSITY ==> "2Gb"
MIG: 21:42:59 :  Invalid Param: DDR3_MEM_SPEEDGRADE ==> "125"
MIG: 21:42:59 :  Invalid Param: DDR3_MEM_DEVICE_WIDTH ==> 16
MIG: 21:42:59 :  Invalid Param: DDR3_AL ==> "0"
MIG: 21:42:59 :  Invalid Param: DDR3_nAL ==> 0
MIG: 21:42:59 :  Invalid Param: DDR3_BURST_MODE ==> "8"
MIG: 21:42:59 :  Invalid Param: DDR3_BURST_TYPE ==> "SEQ"
MIG: 21:42:59 :  Invalid Param: DDR3_CL ==> 6
MIG: 21:42:59 :  Invalid Param: DDR3_CWL ==> 5
MIG: 21:42:59 :  Invalid Param: DDR3_OUTPUT_DRV ==> "HIGH"
MIG: 21:42:59 :  Invalid Param: DDR3_RTT_NOM ==> "40"
MIG: 21:42:59 :  Invalid Param: DDR3_RTT_WR ==> "OFF"
MIG: 21:42:59 :  Invalid Param: DDR3_ADDR_CMD_MODE ==> "1T"
MIG: 21:42:59 : 
MIG: 21:42:59 :  Valid Param: DDR3_REG_CTRL ==> OFF
MIG: 21:42:59 :  Invalid Param: DDR3_CA_MIRROR ==> "OFF"
MIG: 21:42:59 :  Invalid Param: DDR3_VDD_OP_VOLT ==> "150"
MIG: 21:42:59 :  Invalid Param: DDR3_CLKIN_PERIOD ==> -2147483647
MIG: 21:42:59 :  Invalid Param: DDR3_CLKFBOUT_MULT ==> 0
MIG: 21:42:59 :  Invalid Param: DDR3_DIVCLK_DIVIDE ==> 0
MIG: 21:42:59 :  Invalid Param: DDR3_CLKOUT0_PHASE ==> 337.5
MIG: 21:42:59 :  Invalid Param: DDR3_CLKOUT0_DIVIDE ==> 0
MIG: 21:42:59 :  Invalid Param: DDR3_CLKOUT1_DIVIDE ==> 0
MIG: 21:42:59 :  Invalid Param: DDR3_CLKOUT2_DIVIDE ==> 0
MIG: 21:42:59 :  Invalid Param: DDR3_CLKOUT3_DIVIDE ==> 0
MIG: 21:42:59 :  Invalid Param: DDR3_MMCM_VCO ==> 800
MIG: 21:42:59 :  Invalid Param: DDR3_MMCM_MULT_F ==> 8
MIG: 21:42:59 :  Invalid Param: DDR3_MMCM_DIVCLK_DIVIDE ==> 1
MIG: 21:42:59 :  Invalid Param: DDR3_tCKE ==> 5000
MIG: 21:42:59 :  Invalid Param: DDR3_tFAW ==> 40000
MIG: 21:42:59 :  Invalid Param: DDR3_tPRDI ==> 1_000_000
MIG: 21:42:59 :  Invalid Param: DDR3_tRAS ==> 35000
MIG: 21:42:59 :  Invalid Param: DDR3_tRCD ==> 13750
MIG: 21:42:59 :  Invalid Param: DDR3_tREFI ==> 7800000
MIG: 21:42:59 :  Invalid Param: DDR3_tRFC ==> 160000
MIG: 21:42:59 :  Invalid Param: DDR3_tRP ==> 13750
MIG: 21:42:59 :  Invalid Param: DDR3_tRRD ==> 7500
MIG: 21:42:59 :  Invalid Param: DDR3_tRTP ==> 7500
MIG: 21:42:59 :  Invalid Param: DDR3_tWTR ==> 7500
MIG: 21:42:59 :  Invalid Param: DDR3_tZQI ==> 128_000_000
MIG: 21:42:59 :  Invalid Param: DDR3_tZQCS ==> 64
MIG: 21:42:59 :  Invalid Param: DDR3_SIM_BYPASS_INIT_CAL ==> "OFF"
MIG: 21:42:59 :  Invalid Param: DDR3_SIMULATION ==> "FALSE"
MIG: 21:42:59 :  Invalid Param: DDR3_BYTE_LANES_B0 ==> 4'b1111
MIG: 21:42:59 :  Invalid Param: DDR3_BYTE_LANES_B1 ==> 4'b0000
MIG: 21:42:59 :  Invalid Param: DDR3_BYTE_LANES_B2 ==> 4'b0000
MIG: 21:42:59 :  Invalid Param: DDR3_BYTE_LANES_B3 ==> 4'b0000
MIG: 21:42:59 :  Invalid Param: DDR3_BYTE_LANES_B4 ==> 4'b0000
MIG: 21:42:59 :  Invalid Param: DDR3_DATA_CTL_B0 ==> 4'b0011
MIG: 21:42:59 :  Invalid Param: DDR3_DATA_CTL_B1 ==> 4'b0000
MIG: 21:42:59 :  Invalid Param: DDR3_DATA_CTL_B2 ==> 4'b0000
MIG: 21:42:59 :  Invalid Param: DDR3_DATA_CTL_B3 ==> 4'b0000
MIG: 21:42:59 :  Invalid Param: DDR3_DATA_CTL_B4 ==> 4'b0000
MIG: 21:42:59 :  Invalid Param: DDR3_PHY_0_BITLANES ==> 48'hFFF_FFC_3FE_2FF
MIG: 21:42:59 :  Invalid Param: DDR3_PHY_1_BITLANES ==> 48'h000_000_000_000
MIG: 21:42:59 :  Invalid Param: DDR3_PHY_2_BITLANES ==> 48'h000_000_000_000
MIG: 21:42:59 :  Invalid Param: DDR3_CK_BYTE_MAP ==> 144'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_02
MIG: 21:42:59 :  Invalid Param: DDR3_ADDR_MAP ==> 192'h000_000_027_031_035_032_026_039_025_038_024_037_02B_03B_034_03A
MIG: 21:42:59 :  Invalid Param: DDR3_BANK_MAP ==> 36'h029_033_02A
MIG: 21:42:59 :  Invalid Param: DDR3_CAS_MAP ==> 12'h023
MIG: 21:42:59 :  Invalid Param: DDR3_CKE_ODT_BYTE_MAP ==> 8'h00
MIG: 21:42:59 :  Invalid Param: DDR3_CKE_MAP ==> 96'h000_000_000_000_000_000_000_036
MIG: 21:42:59 :  Invalid Param: DDR3_ODT_MAP ==> 96'h000_000_000_000_000_000_000_030
MIG: 21:42:59 :  Invalid Param: DDR3_CS_MAP ==> 120'h000_000_000_000_000_000_000_000_000_000
MIG: 21:42:59 :  Invalid Param: DDR3_PARITY_MAP ==> 12'h000
MIG: 21:42:59 :  Invalid Param: DDR3_RAS_MAP ==> 12'h022
MIG: 21:42:59 :  Invalid Param: DDR3_WE_MAP ==> 12'h028
MIG: 21:42:59 :  Invalid Param: DDR3_DQS_BYTE_MAP ==> 144'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_01
MIG: 21:42:59 :  Invalid Param: DDR3_DATA0_MAP ==> 96'h019_012_017_013_011_014_018_015
MIG: 21:42:59 :  Invalid Param: DDR3_DATA1_MAP ==> 96'h004_000_007_005_006_001_002_003
MIG: 21:42:59 :  Invalid Param: DDR3_DATA2_MAP ==> 96'h000_000_000_000_000_000_000_000
MIG: 21:42:59 :  Invalid Param: DDR3_DATA3_MAP ==> 96'h000_000_000_000_000_000_000_000
MIG: 21:42:59 :  Invalid Param: DDR3_DATA4_MAP ==> 96'h000_000_000_000_000_000_000_000
MIG: 21:42:59 :  Invalid Param: DDR3_DATA5_MAP ==> 96'h000_000_000_000_000_000_000_000
MIG: 21:42:59 :  Invalid Param: DDR3_DATA6_MAP ==> 96'h000_000_000_000_000_000_000_000
MIG: 21:42:59 :  Invalid Param: DDR3_DATA7_MAP ==> 96'h000_000_000_000_000_000_000_000
MIG: 21:42:59 :  Invalid Param: DDR3_DATA8_MAP ==> 96'h000_000_000_000_000_000_000_000
MIG: 21:42:59 :  Invalid Param: DDR3_DATA9_MAP ==> 96'h000_000_000_000_000_000_000_000
MIG: 21:42:59 :  Invalid Param: DDR3_DATA10_MAP ==> 96'h000_000_000_000_000_000_000_000
MIG: 21:42:59 :  Invalid Param: DDR3_DATA11_MAP ==> 96'h000_000_000_000_000_000_000_000
MIG: 21:42:59 :  Invalid Param: DDR3_DATA12_MAP ==> 96'h000_000_000_000_000_000_000_000
MIG: 21:42:59 :  Invalid Param: DDR3_DATA13_MAP ==> 96'h000_000_000_000_000_000_000_000
MIG: 21:42:59 :  Invalid Param: DDR3_DATA14_MAP ==> 96'h000_000_000_000_000_000_000_000
MIG: 21:42:59 :  Invalid Param: DDR3_DATA15_MAP ==> 96'h000_000_000_000_000_000_000_000
MIG: 21:42:59 :  Invalid Param: DDR3_DATA16_MAP ==> 96'h000_000_000_000_000_000_000_000
MIG: 21:42:59 :  Invalid Param: DDR3_DATA17_MAP ==> 96'h000_000_000_000_000_000_000_000
MIG: 21:42:59 :  Invalid Param: DDR3_MASK0_MAP ==> 108'h000_000_000_000_000_000_000_009_016
MIG: 21:42:59 :  Invalid Param: DDR3_MASK1_MAP ==> 108'h000_000_000_000_000_000_000_000_000
MIG: 21:42:59 :  Invalid Param: DDR3_SLOT_0_CONFIG ==> 8'b0000_0001
MIG: 21:42:59 :  Invalid Param: DDR3_SLOT_1_CONFIG ==> 8'b0000_0000
MIG: 21:42:59 :  Invalid Param: DDR3_IBUF_LPWR_MODE ==> "OFF"
MIG: 21:42:59 :  Invalid Param: DDR3_DATA_IO_IDLE_PWRDWN ==> "ON"
MIG: 21:42:59 :  Invalid Param: DDR3_BANK_TYPE ==> "HR_IO"
MIG: 21:42:59 :  Invalid Param: DDR3_DATA_IO_PRIM_TYPE ==> "HR_LP"
MIG: 21:42:59 :  Invalid Param: DDR3_CKE_ODT_AUX ==> "FALSE"
MIG: 21:42:59 :  Invalid Param: DDR3_USER_REFRESH ==> "OFF"
MIG: 21:42:59 :  Invalid Param: DDR3_WRLVL ==> "ON"
MIG: 21:42:59 :  Invalid Param: DDR3_ORDERING ==> "NORM"
MIG: 21:42:59 :  Invalid Param: DDR3_CALIB_ROW_ADD ==> 16'h0000
MIG: 21:42:59 :  Invalid Param: DDR3_CALIB_COL_ADD ==> 12'h000
MIG: 21:42:59 :  Invalid Param: DDR3_CALIB_BA_ADD ==> 3'h0
MIG: 21:42:59 :  Invalid Param: DDR3_TCQ ==> 100
MIG: 21:42:59 :  Invalid Param: DDR3_IDELAY_ADJ ==> "OFF"
MIG: 21:42:59 :  Invalid Param: DDR3_FINE_PER_BIT ==> "OFF"
MIG: 21:42:59 :  Invalid Param: DDR3_CENTER_COMP_MODE ==> "OFF"
MIG: 21:42:59 :  Invalid Param: DDR3_PI_VAL_ADJ ==> "OFF"
MIG: 21:42:59 :  Invalid Param: DDR3_IODELAY_GRP0 ==> "MIG_7SERIES_0_IODELAY_MIG0"
MIG: 21:42:59 :  Invalid Param: DDR3_IODELAY_GRP1 ==> "MIG_7SERIES_0_IODELAY_MIG1"
MIG: 21:42:59 :  Invalid Param: DDR3_SYSCLK_TYPE ==> "NO_BUFFER"
MIG: 21:42:59 :  Invalid Param: DDR3_REFCLK_TYPE ==> "NO_BUFFER"
MIG: 21:42:59 :  Invalid Param: DDR3_SYS_RST_PORT ==> "FALSE"
MIG: 21:42:59 :  Invalid Param: DDR3_FPGA_SPEED_GRADE ==> 2
MIG: 21:42:59 :  Invalid Param: DDR3_CMD_PIPE_PLUS1 ==> "ON"
MIG: 21:42:59 :  Invalid Param: DDR3_DRAM_TYPE ==> "DDR3"
MIG: 21:42:59 :  Invalid Param: DDR3_CAL_WIDTH ==> "HALF"
MIG: 21:42:59 :  Invalid Param: DDR3_STARVE_LIMIT ==> 2
MIG: 21:42:59 :  Invalid Param: DDR3_REF_CLK_MMCM_IODELAY_CTRL ==> "FALSE"
MIG: 21:42:59 :  Invalid Param: DDR3_REFCLK_FREQ ==> 200.0
MIG: 21:42:59 :  Invalid Param: DDR3_DIFF_TERM_REFCLK ==> "TRUE"
MIG: 21:42:59 :  Invalid Param: DDR3_tCK ==> 2500
MIG: 21:42:59 : 
MIG: 21:42:59 :  Valid Param: DDR3_nCK_PER_CLK ==> 4
MIG: 21:42:59 :  Invalid Param: DDR3_DIFF_TERM_SYSCLK ==> "TRUE"
MIG: 21:42:59 : 
MIG: 21:42:59 :  Valid Param: DDR3_DEBUG_PORT ==> OFF
MIG: 21:42:59 : 
MIG: 21:42:59 :  Invalid Param: DDR3_TEMP_MON_CONTROL ==> "EXTERNAL"
MIG: 21:42:59 :  Invalid Param: DDR3_RST_ACT_LOW ==> 1
MIG: 21:42:59 : 
MIG: 21:42:59 : 
MIG: 21:42:59 : 
MIG: 21:42:59 : Same Interface
MIG: 21:43:04 : Running customizer.xit
MIG: 21:43:04 : ################# RUNNING MIG INTERACTIVE ###################
MIG: 21:43:04 : Writing IN file for 'mig_7series_0'...compDirPath: /drv_s2/xilinx/Vivado/2014.4/data/ip/xilinx/mig_7series_v2_3... instDirPath: /home/stefan/.Xil/Vivado-24505-ws2/coregen/mig_7series_0
MIG: 21:43:04 : synp_flow:  -- synthesis_mode: Other
MIG: 21:43:04 : outputDirectory: /home/stefan/.Xil/Vivado-24505-ws2/coregen/mig_7series_0/_tmp/
MIG: 21:43:04 : vivado_mode: xpg_pa
MIG: 21:43:04 :  locked false  
MIG: 21:43:04 : HDL Language: Verilog
MIG: 21:43:04 : compInfo: false
MIG: 21:43:04 : Vivado Options xc7a200t fbg484 -2
MIG: 21:43:04 : 1: xc7a200t 2: fbg484 3: -2
MIG: 21:43:04 : relative mig path: coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/lin/mig
MIG: 21:43:04 : xilinx_path: /drv_s2/xilinx/Vivado/2014.4/ids_lite/ISE
MIG: 21:43:04 : I am in catch area
MIG: 21:43:04 : Running /drv_s2/xilinx/Vivado/2014.4/ids_lite/ISE/coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/lin/mig -cg_exc_inp /home/stefan/.Xil/Vivado-24505-ws2/coregen/mig_7series_0/xil_txt.in -cg_exc_out /home/stefan/.Xil/Vivado-24505-ws2/coregen/mig_7series_0/xil_txt.out ... 
MIG: 21:44:20 : Prasad before: xmlPropertyPrj -- mig_b.prj
MIG: 21:44:20 : Prasad After: xmlPropertyPrj -- mig_a.prj
MIG: 21:44:20 : XML_INPUT_FILE: /home/stefan/.Xil/Vivado-24505-ws2/coregen/mig_7series_0/mig_a.prj
MIG: 21:44:20 : Component_Name: mig_7series_0
MIG: 21:44:20 : Moving mig_7series_0.veo ...
MIG: 21:44:20 : Moving mig_7series_0 ...
MIG: 21:44:20 : Moving mig_7series_0_xmdf.tcl ...
MIG: 21:44:20 : Moving log.txt ...
MIG: 21:44:20 : Sending back 0
MIG: 21:44:22 : xml_input_file: mig_a.prj
MIG: 21:44:22 : Absolute path of xml_input_file: /drv_s2/usb-fpga/ztex/examples/memfifo/fpga-2.18/memfifo.srcs/sources_1/ip/mig_7series_0/mig_a.prj
MIG: 21:44:22 : xml_input_file: mig_a.prj
MIG: 21:44:22 : Absolute path of xml_input_file: /drv_s2/usb-fpga/ztex/examples/memfifo/fpga-2.18/memfifo.srcs/sources_1/ip/mig_7series_0/mig_a.prj
MIG: 21:44:22 : In updateAllModelParams
MIG: 21:44:22 : IGN:     <ModuleName>mig_7series_0</ModuleName> <==>     <ModuleName>mig_7series_0</ModuleName> 
MIG: 21:44:22 : IGN:         <InputClkFreq></InputClkFreq> <==>         <InputClkFreq></InputClkFreq> 
MIG: 21:44:22 : XGUI hdlLanguage: Verilog
MIG: 21:44:22 : xgui vivado_mode: xpg_pa
MIG: 21:44:22 : xgui hdlLanguage: Verilog -- hdlExt: v
MIG: 21:44:22 : Reading /drv_s2/usb-fpga/ztex/examples/memfifo/fpga-2.18/memfifo.srcs/sources_1/ip/mig_7series_0/mig_7series_0/user_design/rtl/mig_7series_0_mig.v ...
MIG: 21:44:23 : 
MIG: 21:44:23 : Inside fn mem: DDR3
MIG: 21:44:23 : QDRII+ Inside fn ui: 100000000
MIG: 21:44:23 : cntrl:  memtype: DDR3
MIG: 21:44:23 : 
MIG: 21:44:23 :  MMCM_VCO single ctrl param_name: MMCM_VCO --  possibleMaxVcoVal: 800 
MIG: 21:44:23 : 
MIG: 21:44:23 : 
MIG: 21:44:23 : 
MIG: 21:44:23 : 
MIG: 21:44:23 :  polarity_value: 1
MIG: 21:44:23 : 
MIG: 21:44:23 : 
MIG: 21:44:23 : cntrl:  memtype: DDR3
MIG: 21:44:23 : 
MIG: 21:44:23 :  Valid Param: DDR3_BANK_WIDTH ==> 3
MIG: 21:44:23 : 
MIG: 21:44:23 :  Valid Param: DDR3_CK_WIDTH ==> 1
MIG: 21:44:23 :  Invalid Param: DDR3_COL_WIDTH ==> 10
MIG: 21:44:23 : 
MIG: 21:44:23 :  Valid Param: DDR3_CS_WIDTH ==> 1
MIG: 21:44:23 : 
MIG: 21:44:23 :  Valid Param: DDR3_nCS_PER_RANK ==> 1
MIG: 21:44:23 : 
MIG: 21:44:23 :  Valid Param: DDR3_CKE_WIDTH ==> 1
MIG: 21:44:23 :  Invalid Param: DDR3_DATA_BUF_ADDR_WIDTH ==> 5
MIG: 21:44:23 :  Invalid Param: DDR3_DQ_CNT_WIDTH ==> 4
MIG: 21:44:23 :  Invalid Param: DDR3_DQ_PER_DM ==> 8
MIG: 21:44:23 : 
MIG: 21:44:23 :  Valid Param: DDR3_DM_WIDTH ==> 2
MIG: 21:44:23 : 
MIG: 21:44:23 :  Valid Param: DDR3_DQ_WIDTH ==> 16
MIG: 21:44:23 : 
MIG: 21:44:23 :  Valid Param: DDR3_DQS_WIDTH ==> 2
MIG: 21:44:23 : 
MIG: 21:44:23 :  Valid Param: DDR3_DQS_CNT_WIDTH ==> 1
MIG: 21:44:23 :  Invalid Param: DDR3_DRAM_WIDTH ==> 8
MIG: 21:44:23 : 
MIG: 21:44:23 :  Valid Param: ECC ==> OFF
MIG: 21:44:23 : 
MIG: 21:44:23 :  Valid Param: DDR3_DATA_WIDTH ==> 16
MIG: 21:44:23 :  Invalid Param: ECC_TEST ==> "OFF"
MIG: 21:44:23 :  Invalid Param: DDR3_PAYLOAD_WIDTH ==> (ECC_TEST == "OFF") ? DATA_WIDTH : DQ_WIDTH
MIG: 21:44:23 :  Invalid Param: DDR3_MEM_ADDR_ORDER ==> "BANK_ROW_COLUMN"
MIG: 21:44:23 :  Invalid Param: DDR3_nBANK_MACHS ==> 4
MIG: 21:44:23 :  Invalid Param: DDR3_RANKS ==> 1
MIG: 21:44:23 : 
MIG: 21:44:23 :  Valid Param: DDR3_ODT_WIDTH ==> 1
MIG: 21:44:23 : 
MIG: 21:44:23 :  Valid Param: DDR3_ROW_WIDTH ==> 14
MIG: 21:44:23 : 
MIG: 21:44:23 :  Valid Param: DDR3_ADDR_WIDTH ==> 28
MIG: 21:44:23 : 
MIG: 21:44:23 :  Valid Param: DDR3_USE_CS_PORT ==> 0
MIG: 21:44:23 : 
MIG: 21:44:23 :  Valid Param: DDR3_USE_DM_PORT ==> 1
MIG: 21:44:23 : 
MIG: 21:44:23 :  Valid Param: DDR3_USE_ODT_PORT ==> 1
MIG: 21:44:23 :  Invalid Param: DDR3_IS_CLK_SHARED ==> "FALSE"
MIG: 21:44:23 :  Invalid Param: DDR3_PHY_CONTROL_MASTER_BANK ==> 0
MIG: 21:44:23 :  Invalid Param: DDR3_MEM_DENSITY ==> "2Gb"
MIG: 21:44:23 :  Invalid Param: DDR3_MEM_SPEEDGRADE ==> "125"
MIG: 21:44:23 :  Invalid Param: DDR3_MEM_DEVICE_WIDTH ==> 16
MIG: 21:44:23 :  Invalid Param: DDR3_AL ==> "0"
MIG: 21:44:23 :  Invalid Param: DDR3_nAL ==> 0
MIG: 21:44:23 :  Invalid Param: DDR3_BURST_MODE ==> "8"
MIG: 21:44:23 :  Invalid Param: DDR3_BURST_TYPE ==> "SEQ"
MIG: 21:44:23 :  Invalid Param: DDR3_CL ==> 6
MIG: 21:44:23 :  Invalid Param: DDR3_CWL ==> 5
MIG: 21:44:23 :  Invalid Param: DDR3_OUTPUT_DRV ==> "HIGH"
MIG: 21:44:23 :  Invalid Param: DDR3_RTT_NOM ==> "40"
MIG: 21:44:23 :  Invalid Param: DDR3_RTT_WR ==> "OFF"
MIG: 21:44:23 :  Invalid Param: DDR3_ADDR_CMD_MODE ==> "1T"
MIG: 21:44:23 : 
MIG: 21:44:23 :  Valid Param: DDR3_REG_CTRL ==> OFF
MIG: 21:44:23 :  Invalid Param: DDR3_CA_MIRROR ==> "OFF"
MIG: 21:44:23 :  Invalid Param: DDR3_VDD_OP_VOLT ==> "150"
MIG: 21:44:23 :  Invalid Param: DDR3_CLKIN_PERIOD ==> -2147483647
MIG: 21:44:23 :  Invalid Param: DDR3_CLKFBOUT_MULT ==> 0
MIG: 21:44:23 :  Invalid Param: DDR3_DIVCLK_DIVIDE ==> 0
MIG: 21:44:23 :  Invalid Param: DDR3_CLKOUT0_PHASE ==> 337.5
MIG: 21:44:23 :  Invalid Param: DDR3_CLKOUT0_DIVIDE ==> 0
MIG: 21:44:23 :  Invalid Param: DDR3_CLKOUT1_DIVIDE ==> 0
MIG: 21:44:23 :  Invalid Param: DDR3_CLKOUT2_DIVIDE ==> 0
MIG: 21:44:23 :  Invalid Param: DDR3_CLKOUT3_DIVIDE ==> 0
MIG: 21:44:23 :  Invalid Param: DDR3_MMCM_VCO ==> 800
MIG: 21:44:23 :  Invalid Param: DDR3_MMCM_MULT_F ==> 8
MIG: 21:44:23 :  Invalid Param: DDR3_MMCM_DIVCLK_DIVIDE ==> 1
MIG: 21:44:23 :  Invalid Param: DDR3_tCKE ==> 5000
MIG: 21:44:23 :  Invalid Param: DDR3_tFAW ==> 40000
MIG: 21:44:23 :  Invalid Param: DDR3_tPRDI ==> 1_000_000
MIG: 21:44:23 :  Invalid Param: DDR3_tRAS ==> 35000
MIG: 21:44:23 :  Invalid Param: DDR3_tRCD ==> 13750
MIG: 21:44:23 :  Invalid Param: DDR3_tREFI ==> 7800000
MIG: 21:44:23 :  Invalid Param: DDR3_tRFC ==> 160000
MIG: 21:44:23 :  Invalid Param: DDR3_tRP ==> 13750
MIG: 21:44:23 :  Invalid Param: DDR3_tRRD ==> 7500
MIG: 21:44:23 :  Invalid Param: DDR3_tRTP ==> 7500
MIG: 21:44:23 :  Invalid Param: DDR3_tWTR ==> 7500
MIG: 21:44:23 :  Invalid Param: DDR3_tZQI ==> 128_000_000
MIG: 21:44:23 :  Invalid Param: DDR3_tZQCS ==> 64
MIG: 21:44:23 :  Invalid Param: DDR3_SIM_BYPASS_INIT_CAL ==> "OFF"
MIG: 21:44:23 :  Invalid Param: DDR3_SIMULATION ==> "FALSE"
MIG: 21:44:23 :  Invalid Param: DDR3_BYTE_LANES_B0 ==> 4'b1111
MIG: 21:44:23 :  Invalid Param: DDR3_BYTE_LANES_B1 ==> 4'b0000
MIG: 21:44:23 :  Invalid Param: DDR3_BYTE_LANES_B2 ==> 4'b0000
MIG: 21:44:23 :  Invalid Param: DDR3_BYTE_LANES_B3 ==> 4'b0000
MIG: 21:44:23 :  Invalid Param: DDR3_BYTE_LANES_B4 ==> 4'b0000
MIG: 21:44:23 :  Invalid Param: DDR3_DATA_CTL_B0 ==> 4'b0011
MIG: 21:44:23 :  Invalid Param: DDR3_DATA_CTL_B1 ==> 4'b0000
MIG: 21:44:23 :  Invalid Param: DDR3_DATA_CTL_B2 ==> 4'b0000
MIG: 21:44:23 :  Invalid Param: DDR3_DATA_CTL_B3 ==> 4'b0000
MIG: 21:44:23 :  Invalid Param: DDR3_DATA_CTL_B4 ==> 4'b0000
MIG: 21:44:23 :  Invalid Param: DDR3_PHY_0_BITLANES ==> 48'hFFF_FFC_3FE_2FF
MIG: 21:44:23 :  Invalid Param: DDR3_PHY_1_BITLANES ==> 48'h000_000_000_000
MIG: 21:44:23 :  Invalid Param: DDR3_PHY_2_BITLANES ==> 48'h000_000_000_000
MIG: 21:44:23 :  Invalid Param: DDR3_CK_BYTE_MAP ==> 144'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_02
MIG: 21:44:23 :  Invalid Param: DDR3_ADDR_MAP ==> 192'h000_000_027_031_035_032_026_039_025_038_024_037_02B_03B_034_03A
MIG: 21:44:23 :  Invalid Param: DDR3_BANK_MAP ==> 36'h029_033_02A
MIG: 21:44:23 :  Invalid Param: DDR3_CAS_MAP ==> 12'h023
MIG: 21:44:23 :  Invalid Param: DDR3_CKE_ODT_BYTE_MAP ==> 8'h00
MIG: 21:44:23 :  Invalid Param: DDR3_CKE_MAP ==> 96'h000_000_000_000_000_000_000_036
MIG: 21:44:23 :  Invalid Param: DDR3_ODT_MAP ==> 96'h000_000_000_000_000_000_000_030
MIG: 21:44:23 :  Invalid Param: DDR3_CS_MAP ==> 120'h000_000_000_000_000_000_000_000_000_000
MIG: 21:44:23 :  Invalid Param: DDR3_PARITY_MAP ==> 12'h000
MIG: 21:44:23 :  Invalid Param: DDR3_RAS_MAP ==> 12'h022
MIG: 21:44:23 :  Invalid Param: DDR3_WE_MAP ==> 12'h028
MIG: 21:44:23 :  Invalid Param: DDR3_DQS_BYTE_MAP ==> 144'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_01
MIG: 21:44:23 :  Invalid Param: DDR3_DATA0_MAP ==> 96'h019_012_017_013_011_014_018_015
MIG: 21:44:23 :  Invalid Param: DDR3_DATA1_MAP ==> 96'h004_000_007_005_006_001_002_003
MIG: 21:44:23 :  Invalid Param: DDR3_DATA2_MAP ==> 96'h000_000_000_000_000_000_000_000
MIG: 21:44:23 :  Invalid Param: DDR3_DATA3_MAP ==> 96'h000_000_000_000_000_000_000_000
MIG: 21:44:23 :  Invalid Param: DDR3_DATA4_MAP ==> 96'h000_000_000_000_000_000_000_000
MIG: 21:44:23 :  Invalid Param: DDR3_DATA5_MAP ==> 96'h000_000_000_000_000_000_000_000
MIG: 21:44:23 :  Invalid Param: DDR3_DATA6_MAP ==> 96'h000_000_000_000_000_000_000_000
MIG: 21:44:23 :  Invalid Param: DDR3_DATA7_MAP ==> 96'h000_000_000_000_000_000_000_000
MIG: 21:44:23 :  Invalid Param: DDR3_DATA8_MAP ==> 96'h000_000_000_000_000_000_000_000
MIG: 21:44:23 :  Invalid Param: DDR3_DATA9_MAP ==> 96'h000_000_000_000_000_000_000_000
MIG: 21:44:23 :  Invalid Param: DDR3_DATA10_MAP ==> 96'h000_000_000_000_000_000_000_000
MIG: 21:44:23 :  Invalid Param: DDR3_DATA11_MAP ==> 96'h000_000_000_000_000_000_000_000
MIG: 21:44:23 :  Invalid Param: DDR3_DATA12_MAP ==> 96'h000_000_000_000_000_000_000_000
MIG: 21:44:23 :  Invalid Param: DDR3_DATA13_MAP ==> 96'h000_000_000_000_000_000_000_000
MIG: 21:44:23 :  Invalid Param: DDR3_DATA14_MAP ==> 96'h000_000_000_000_000_000_000_000
MIG: 21:44:23 :  Invalid Param: DDR3_DATA15_MAP ==> 96'h000_000_000_000_000_000_000_000
MIG: 21:44:23 :  Invalid Param: DDR3_DATA16_MAP ==> 96'h000_000_000_000_000_000_000_000
MIG: 21:44:23 :  Invalid Param: DDR3_DATA17_MAP ==> 96'h000_000_000_000_000_000_000_000
MIG: 21:44:23 :  Invalid Param: DDR3_MASK0_MAP ==> 108'h000_000_000_000_000_000_000_009_016
MIG: 21:44:23 :  Invalid Param: DDR3_MASK1_MAP ==> 108'h000_000_000_000_000_000_000_000_000
MIG: 21:44:23 :  Invalid Param: DDR3_SLOT_0_CONFIG ==> 8'b0000_0001
MIG: 21:44:23 :  Invalid Param: DDR3_SLOT_1_CONFIG ==> 8'b0000_0000
MIG: 21:44:23 :  Invalid Param: DDR3_IBUF_LPWR_MODE ==> "OFF"
MIG: 21:44:23 :  Invalid Param: DDR3_DATA_IO_IDLE_PWRDWN ==> "ON"
MIG: 21:44:23 :  Invalid Param: DDR3_BANK_TYPE ==> "HR_IO"
MIG: 21:44:23 :  Invalid Param: DDR3_DATA_IO_PRIM_TYPE ==> "HR_LP"
MIG: 21:44:23 :  Invalid Param: DDR3_CKE_ODT_AUX ==> "FALSE"
MIG: 21:44:23 :  Invalid Param: DDR3_USER_REFRESH ==> "OFF"
MIG: 21:44:23 :  Invalid Param: DDR3_WRLVL ==> "ON"
MIG: 21:44:23 :  Invalid Param: DDR3_ORDERING ==> "NORM"
MIG: 21:44:23 :  Invalid Param: DDR3_CALIB_ROW_ADD ==> 16'h0000
MIG: 21:44:23 :  Invalid Param: DDR3_CALIB_COL_ADD ==> 12'h000
MIG: 21:44:23 :  Invalid Param: DDR3_CALIB_BA_ADD ==> 3'h0
MIG: 21:44:23 :  Invalid Param: DDR3_TCQ ==> 100
MIG: 21:44:23 :  Invalid Param: DDR3_IDELAY_ADJ ==> "OFF"
MIG: 21:44:23 :  Invalid Param: DDR3_FINE_PER_BIT ==> "OFF"
MIG: 21:44:23 :  Invalid Param: DDR3_CENTER_COMP_MODE ==> "OFF"
MIG: 21:44:23 :  Invalid Param: DDR3_PI_VAL_ADJ ==> "OFF"
MIG: 21:44:23 :  Invalid Param: DDR3_IODELAY_GRP0 ==> "MIG_7SERIES_0_IODELAY_MIG0"
MIG: 21:44:23 :  Invalid Param: DDR3_IODELAY_GRP1 ==> "MIG_7SERIES_0_IODELAY_MIG1"
MIG: 21:44:23 :  Invalid Param: DDR3_SYSCLK_TYPE ==> "NO_BUFFER"
MIG: 21:44:23 :  Invalid Param: DDR3_REFCLK_TYPE ==> "NO_BUFFER"
MIG: 21:44:23 :  Invalid Param: DDR3_SYS_RST_PORT ==> "FALSE"
MIG: 21:44:23 :  Invalid Param: DDR3_FPGA_SPEED_GRADE ==> 2
MIG: 21:44:23 :  Invalid Param: DDR3_CMD_PIPE_PLUS1 ==> "ON"
MIG: 21:44:23 :  Invalid Param: DDR3_DRAM_TYPE ==> "DDR3"
MIG: 21:44:23 :  Invalid Param: DDR3_CAL_WIDTH ==> "HALF"
MIG: 21:44:23 :  Invalid Param: DDR3_STARVE_LIMIT ==> 2
MIG: 21:44:23 :  Invalid Param: DDR3_REF_CLK_MMCM_IODELAY_CTRL ==> "FALSE"
MIG: 21:44:23 :  Invalid Param: DDR3_REFCLK_FREQ ==> 200.0
MIG: 21:44:23 :  Invalid Param: DDR3_DIFF_TERM_REFCLK ==> "TRUE"
MIG: 21:44:23 :  Invalid Param: DDR3_tCK ==> 2500
MIG: 21:44:23 : 
MIG: 21:44:23 :  Valid Param: DDR3_nCK_PER_CLK ==> 4
MIG: 21:44:23 :  Invalid Param: DDR3_DIFF_TERM_SYSCLK ==> "TRUE"
MIG: 21:44:23 : 
MIG: 21:44:23 :  Valid Param: DDR3_DEBUG_PORT ==> OFF
MIG: 21:44:23 : 
MIG: 21:44:23 :  Invalid Param: DDR3_TEMP_MON_CONTROL ==> "EXTERNAL"
MIG: 21:44:23 :  Invalid Param: DDR3_RST_ACT_LOW ==> 1
MIG: 21:44:23 : 
MIG: 21:44:23 : 
MIG: 21:44:23 : 
MIG: 21:44:23 : Same Interface
MIG: 21:44:27 : ################# RUNNING MIG BATCH ###################
MIG: 21:44:27 : Writing IN file for 'mig_7series_0'...compDirPath: /drv_s2/xilinx/Vivado/2014.4/data/ip/xilinx/mig_7series_v2_3... instDirPath: /drv_s2/usb-fpga/ztex/examples/memfifo/fpga-2.18/memfifo.srcs/sources_1/ip/mig_7series_0
MIG: 21:44:27 : synp_flow:  -- synthesis_mode: Other
MIG: 21:44:27 : outputDirectory: /drv_s2/usb-fpga/ztex/examples/memfifo/fpga-2.18/memfifo.srcs/sources_1/ip/mig_7series_0/_tmp/
MIG: 21:44:27 : vivado_mode: xpg_pa
MIG: 21:44:27 :  locked false  
MIG: 21:44:27 : HDL Language: Verilog
MIG: 21:44:27 : compInfo: false
MIG: 21:44:27 : Vivado Options xc7a200t fbg484 -2
MIG: 21:44:27 : 1: xc7a200t 2: fbg484 3: -2
MIG: 21:44:27 : relative mig path: coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/lin/mig
MIG: 21:44:27 : xilinx_path: /drv_s2/xilinx/Vivado/2014.4/ids_lite/ISE
MIG: 21:44:27 : I am in catch area
MIG: 21:44:27 : Running /drv_s2/xilinx/Vivado/2014.4/ids_lite/ISE/coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/lin/mig -cg_exc_inp /drv_s2/usb-fpga/ztex/examples/memfifo/fpga-2.18/memfifo.srcs/sources_1/ip/mig_7series_0/xil_txt.in -cg_exc_out /drv_s2/usb-fpga/ztex/examples/memfifo/fpga-2.18/memfifo.srcs/sources_1/ip/mig_7series_0/xil_txt.out ... 
MIG: 21:44:44 : XML_INPUT_FILE: /drv_s2/usb-fpga/ztex/examples/memfifo/fpga-2.18/memfifo.srcs/sources_1/ip/mig_7series_0/mig_a.prj
MIG: 21:44:44 : Component_Name: mig_7series_0
MIG: 21:44:44 : Moving mig_7series_0_xmdf.tcl ...
MIG: 21:44:44 : Moving mig_7series_0 ...
MIG: 21:44:44 : Moving mig_7series_0.veo ...
MIG: 21:44:44 : Moving log.txt ...
MIG: 21:45:59 : Running synthesis.xit
MIG: 21:45:59 : ################# RUNNING MIG BATCH ###################
MIG: 21:45:59 : Writing IN file for 'mig_7series_0'...compDirPath: /drv_s2/xilinx/Vivado/2014.4/data/ip/xilinx/mig_7series_v2_3... instDirPath: /drv_s2/usb-fpga/ztex/examples/memfifo/fpga-2.18/memfifo.srcs/sources_1/ip/mig_7series_0
MIG: 21:45:59 : synp_flow:  -- synthesis_mode: Other
MIG: 21:45:59 : outputDirectory: /drv_s2/usb-fpga/ztex/examples/memfifo/fpga-2.18/memfifo.srcs/sources_1/ip/mig_7series_0/_tmp/
MIG: 21:45:59 : vivado_mode: xpg_pa
MIG: 21:45:59 :  locked false  
MIG: 21:45:59 : HDL Language: Verilog
MIG: 21:45:59 : compInfo: false
MIG: 21:45:59 : Vivado Options xc7a200t fbg484 -2
MIG: 21:45:59 : 1: xc7a200t 2: fbg484 3: -2
MIG: 21:45:59 : relative mig path: coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/lin/mig
MIG: 21:45:59 : xilinx_path: /drv_s2/xilinx/Vivado/2014.4/ids_lite/ISE
MIG: 21:45:59 : I am in catch area
MIG: 21:45:59 : Running /drv_s2/xilinx/Vivado/2014.4/ids_lite/ISE/coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/lin/mig -cg_exc_inp /drv_s2/usb-fpga/ztex/examples/memfifo/fpga-2.18/memfifo.srcs/sources_1/ip/mig_7series_0/xil_txt.in -cg_exc_out /drv_s2/usb-fpga/ztex/examples/memfifo/fpga-2.18/memfifo.srcs/sources_1/ip/mig_7series_0/xil_txt.out ... 
MIG: 21:46:17 : XML_INPUT_FILE: /drv_s2/usb-fpga/ztex/examples/memfifo/fpga-2.18/memfifo.srcs/sources_1/ip/mig_7series_0/mig_a.prj
MIG: 21:46:17 : Component_Name: mig_7series_0
MIG: 21:46:17 : Moving mig_7series_0_xmdf.tcl ...
MIG: 21:46:17 : Moving mig_7series_0 ...
MIG: 21:46:17 : Moving mig_7series_0.veo ...
MIG: 21:46:17 : Running vlog_synth_rpr.xit
MIG: 21:46:17 : IGN:     <ModuleName>mig_7series_0</ModuleName> <==>     <ModuleName>mig_7series_0</ModuleName> 
MIG: 21:46:17 : IGN:         <InputClkFreq></InputClkFreq> <==>         <InputClkFreq>400</InputClkFreq> 
MIG: 21:46:17 : Running simulation.xit
MIG: 21:46:17 : ################# RUNNING MIG BATCH ###################
MIG: 21:46:17 : Writing IN file for 'mig_7series_0'...compDirPath: /drv_s2/xilinx/Vivado/2014.4/data/ip/xilinx/mig_7series_v2_3... instDirPath: /drv_s2/usb-fpga/ztex/examples/memfifo/fpga-2.18/memfifo.srcs/sources_1/ip/mig_7series_0
MIG: 21:46:17 : synp_flow:  -- synthesis_mode: Other
MIG: 21:46:17 : outputDirectory: /drv_s2/usb-fpga/ztex/examples/memfifo/fpga-2.18/memfifo.srcs/sources_1/ip/mig_7series_0/_tmp/
MIG: 21:46:17 : vivado_mode: xpg_pa
MIG: 21:46:17 :  locked false  
MIG: 21:46:17 : HDL Language: Verilog
MIG: 21:46:17 : compInfo: false
MIG: 21:46:17 : Vivado Options xc7a200t fbg484 -2
MIG: 21:46:17 : 1: xc7a200t 2: fbg484 3: -2
MIG: 21:46:17 : relative mig path: coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/lin/mig
MIG: 21:46:17 : xilinx_path: /drv_s2/xilinx/Vivado/2014.4/ids_lite/ISE
MIG: 21:46:17 : I am in catch area
MIG: 21:46:17 : Running /drv_s2/xilinx/Vivado/2014.4/ids_lite/ISE/coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/lin/mig -cg_exc_inp /drv_s2/usb-fpga/ztex/examples/memfifo/fpga-2.18/memfifo.srcs/sources_1/ip/mig_7series_0/xil_txt.in -cg_exc_out /drv_s2/usb-fpga/ztex/examples/memfifo/fpga-2.18/memfifo.srcs/sources_1/ip/mig_7series_0/xil_txt.out ... 
MIG: 21:46:35 : XML_INPUT_FILE: /drv_s2/usb-fpga/ztex/examples/memfifo/fpga-2.18/memfifo.srcs/sources_1/ip/mig_7series_0/mig_a.prj
MIG: 21:46:35 : Component_Name: mig_7series_0
MIG: 21:46:35 : Moving mig_7series_0_xmdf.tcl ...
MIG: 21:46:35 : Moving mig_7series_0 ...
MIG: 21:46:35 : Moving mig_7series_0.veo ...
MIG: 21:46:35 : Running vlog_sim_rpr.xit .. PRASAD DBG1
MIG: 21:46:35 : IGN:     <ModuleName>mig_7series_0</ModuleName> <==>     <ModuleName>mig_7series_0</ModuleName> 
MIG: 21:46:35 : IGN:         <InputClkFreq></InputClkFreq> <==>         <InputClkFreq>400</InputClkFreq> 
MIG: 21:46:35 : Running implementation.xit
MIG: 21:46:35 : IGN:     <ModuleName>mig_7series_0</ModuleName> <==>     <ModuleName>mig_7series_0</ModuleName> 
MIG: 21:46:35 : IGN:         <InputClkFreq></InputClkFreq> <==>         <InputClkFreq>400</InputClkFreq> 
MIG: 22:08:59 : xml_input_file: mig_a.prj
MIG: 22:08:59 : Absolute path of xml_input_file: /drv_s2/usb-fpga/ztex/examples/memfifo/fpga-2.18/memfifo.srcs/sources_1/ip/mig_7series_0/mig_a.prj
MIG: 22:08:59 : xml_input_file: mig_a.prj
MIG: 22:08:59 : Absolute path of xml_input_file: /drv_s2/usb-fpga/ztex/examples/memfifo/fpga-2.18/memfifo.srcs/sources_1/ip/mig_7series_0/mig_a.prj
MIG: 22:09:01 : xml_input_file: mig_a.prj
MIG: 22:09:01 : Absolute path of xml_input_file: mig_a.prj
MIG: 22:09:01 : xml_input_file: mig_a.prj
MIG: 22:09:01 : Absolute path of xml_input_file: mig_a.prj
MIG: 22:09:01 : xml_input_file: /drv_s2/usb-fpga/ztex/examples/memfifo/fpga-2.18/memfifo.srcs/sources_1/ip/mig_7series_0/mig_a.prj
MIG: 22:09:01 : Absolute path of xml_input_file: /drv_s2/usb-fpga/ztex/examples/memfifo/fpga-2.18/memfifo.srcs/sources_1/ip/mig_7series_0/mig_a.prj
MIG: 22:09:01 : xml_input_file: /drv_s2/usb-fpga/ztex/examples/memfifo/fpga-2.18/memfifo.srcs/sources_1/ip/mig_7series_0/mig_a.prj
MIG: 22:09:01 : Absolute path of xml_input_file: /drv_s2/usb-fpga/ztex/examples/memfifo/fpga-2.18/memfifo.srcs/sources_1/ip/mig_7series_0/mig_a.prj
MIG: 22:09:01 : In updateAllModelParams
MIG: 22:09:01 : IGN:     <ModuleName>mig_7series_0</ModuleName> <==>     <ModuleName>mig_7series_0</ModuleName> 
MIG: 22:09:01 : IGN:         <InputClkFreq></InputClkFreq> <==>         <InputClkFreq>400</InputClkFreq> 
MIG: 22:09:01 : XGUI hdlLanguage: Verilog
MIG: 22:09:01 : xgui vivado_mode: xpg_pa
MIG: 22:09:01 : xgui hdlLanguage: Verilog -- hdlExt: v
MIG: 22:09:01 : Reading /drv_s2/usb-fpga/ztex/examples/memfifo/fpga-2.18/memfifo.srcs/sources_1/ip/mig_7series_0/mig_7series_0/user_design/rtl/mig_7series_0_mig.v ...
MIG: 22:09:02 : 
MIG: 22:09:02 : Inside fn mem: DDR3
MIG: 22:09:02 : QDRII+ Inside fn ui: 100000000
MIG: 22:09:02 : cntrl:  memtype: DDR3
MIG: 22:09:02 : 
MIG: 22:09:02 :  MMCM_VCO single ctrl param_name: MMCM_VCO --  possibleMaxVcoVal: 800 
MIG: 22:09:02 : 
MIG: 22:09:02 : 
MIG: 22:09:02 : 
MIG: 22:09:02 : 
MIG: 22:09:02 :  polarity_value: 1
MIG: 22:09:02 : 
MIG: 22:09:02 : 
MIG: 22:09:02 : cntrl:  memtype: DDR3
MIG: 22:09:02 : 
MIG: 22:09:02 :  Valid Param: DDR3_BANK_WIDTH ==> 3
MIG: 22:09:02 : 
MIG: 22:09:02 :  Valid Param: DDR3_CK_WIDTH ==> 1
MIG: 22:09:02 :  Invalid Param: DDR3_COL_WIDTH ==> 10
MIG: 22:09:02 : 
MIG: 22:09:02 :  Valid Param: DDR3_CS_WIDTH ==> 1
MIG: 22:09:02 : 
MIG: 22:09:02 :  Valid Param: DDR3_nCS_PER_RANK ==> 1
MIG: 22:09:02 : 
MIG: 22:09:02 :  Valid Param: DDR3_CKE_WIDTH ==> 1
MIG: 22:09:02 :  Invalid Param: DDR3_DATA_BUF_ADDR_WIDTH ==> 5
MIG: 22:09:02 :  Invalid Param: DDR3_DQ_CNT_WIDTH ==> 4
MIG: 22:09:02 :  Invalid Param: DDR3_DQ_PER_DM ==> 8
MIG: 22:09:02 : 
MIG: 22:09:02 :  Valid Param: DDR3_DM_WIDTH ==> 2
MIG: 22:09:02 : 
MIG: 22:09:02 :  Valid Param: DDR3_DQ_WIDTH ==> 16
MIG: 22:09:02 : 
MIG: 22:09:02 :  Valid Param: DDR3_DQS_WIDTH ==> 2
MIG: 22:09:02 : 
MIG: 22:09:02 :  Valid Param: DDR3_DQS_CNT_WIDTH ==> 1
MIG: 22:09:02 :  Invalid Param: DDR3_DRAM_WIDTH ==> 8
MIG: 22:09:02 : 
MIG: 22:09:02 :  Valid Param: ECC ==> OFF
MIG: 22:09:02 : 
MIG: 22:09:02 :  Valid Param: DDR3_DATA_WIDTH ==> 16
MIG: 22:09:02 :  Invalid Param: ECC_TEST ==> "OFF"
MIG: 22:09:02 :  Invalid Param: DDR3_PAYLOAD_WIDTH ==> (ECC_TEST == "OFF") ? DATA_WIDTH : DQ_WIDTH
MIG: 22:09:02 :  Invalid Param: DDR3_MEM_ADDR_ORDER ==> "BANK_ROW_COLUMN"
MIG: 22:09:02 :  Invalid Param: DDR3_nBANK_MACHS ==> 4
MIG: 22:09:02 :  Invalid Param: DDR3_RANKS ==> 1
MIG: 22:09:02 : 
MIG: 22:09:02 :  Valid Param: DDR3_ODT_WIDTH ==> 1
MIG: 22:09:02 : 
MIG: 22:09:02 :  Valid Param: DDR3_ROW_WIDTH ==> 14
MIG: 22:09:02 : 
MIG: 22:09:02 :  Valid Param: DDR3_ADDR_WIDTH ==> 28
MIG: 22:09:02 : 
MIG: 22:09:02 :  Valid Param: DDR3_USE_CS_PORT ==> 0
MIG: 22:09:02 : 
MIG: 22:09:02 :  Valid Param: DDR3_USE_DM_PORT ==> 1
MIG: 22:09:02 : 
MIG: 22:09:02 :  Valid Param: DDR3_USE_ODT_PORT ==> 1
MIG: 22:09:02 :  Invalid Param: DDR3_IS_CLK_SHARED ==> "FALSE"
MIG: 22:09:02 :  Invalid Param: DDR3_PHY_CONTROL_MASTER_BANK ==> 0
MIG: 22:09:02 :  Invalid Param: DDR3_MEM_DENSITY ==> "2Gb"
MIG: 22:09:02 :  Invalid Param: DDR3_MEM_SPEEDGRADE ==> "125"
MIG: 22:09:02 :  Invalid Param: DDR3_MEM_DEVICE_WIDTH ==> 16
MIG: 22:09:02 :  Invalid Param: DDR3_AL ==> "0"
MIG: 22:09:02 :  Invalid Param: DDR3_nAL ==> 0
MIG: 22:09:02 :  Invalid Param: DDR3_BURST_MODE ==> "8"
MIG: 22:09:02 :  Invalid Param: DDR3_BURST_TYPE ==> "SEQ"
MIG: 22:09:02 :  Invalid Param: DDR3_CL ==> 6
MIG: 22:09:02 :  Invalid Param: DDR3_CWL ==> 5
MIG: 22:09:02 :  Invalid Param: DDR3_OUTPUT_DRV ==> "HIGH"
MIG: 22:09:02 :  Invalid Param: DDR3_RTT_NOM ==> "40"
MIG: 22:09:02 :  Invalid Param: DDR3_RTT_WR ==> "OFF"
MIG: 22:09:02 :  Invalid Param: DDR3_ADDR_CMD_MODE ==> "1T"
MIG: 22:09:02 : 
MIG: 22:09:02 :  Valid Param: DDR3_REG_CTRL ==> OFF
MIG: 22:09:02 :  Invalid Param: DDR3_CA_MIRROR ==> "OFF"
MIG: 22:09:02 :  Invalid Param: DDR3_VDD_OP_VOLT ==> "150"
MIG: 22:09:02 :  Invalid Param: DDR3_CLKIN_PERIOD ==> 2500
MIG: 22:09:02 :  Invalid Param: DDR3_CLKFBOUT_MULT ==> 2
MIG: 22:09:02 :  Invalid Param: DDR3_DIVCLK_DIVIDE ==> 1
MIG: 22:09:02 :  Invalid Param: DDR3_CLKOUT0_PHASE ==> 337.5
MIG: 22:09:02 :  Invalid Param: DDR3_CLKOUT0_DIVIDE ==> 2
MIG: 22:09:02 :  Invalid Param: DDR3_CLKOUT1_DIVIDE ==> 2
MIG: 22:09:02 :  Invalid Param: DDR3_CLKOUT2_DIVIDE ==> 32
MIG: 22:09:02 :  Invalid Param: DDR3_CLKOUT3_DIVIDE ==> 8
MIG: 22:09:02 :  Invalid Param: DDR3_MMCM_VCO ==> 800
MIG: 22:09:02 :  Invalid Param: DDR3_MMCM_MULT_F ==> 8
MIG: 22:09:02 :  Invalid Param: DDR3_MMCM_DIVCLK_DIVIDE ==> 1
MIG: 22:09:02 :  Invalid Param: DDR3_tCKE ==> 5000
MIG: 22:09:02 :  Invalid Param: DDR3_tFAW ==> 40000
MIG: 22:09:02 :  Invalid Param: DDR3_tPRDI ==> 1_000_000
MIG: 22:09:02 :  Invalid Param: DDR3_tRAS ==> 35000
MIG: 22:09:02 :  Invalid Param: DDR3_tRCD ==> 13750
MIG: 22:09:02 :  Invalid Param: DDR3_tREFI ==> 7800000
MIG: 22:09:02 :  Invalid Param: DDR3_tRFC ==> 160000
MIG: 22:09:02 :  Invalid Param: DDR3_tRP ==> 13750
MIG: 22:09:02 :  Invalid Param: DDR3_tRRD ==> 7500
MIG: 22:09:02 :  Invalid Param: DDR3_tRTP ==> 7500
MIG: 22:09:02 :  Invalid Param: DDR3_tWTR ==> 7500
MIG: 22:09:02 :  Invalid Param: DDR3_tZQI ==> 128_000_000
MIG: 22:09:02 :  Invalid Param: DDR3_tZQCS ==> 64
MIG: 22:09:02 :  Invalid Param: DDR3_SIM_BYPASS_INIT_CAL ==> "OFF"
MIG: 22:09:02 :  Invalid Param: DDR3_SIMULATION ==> "FALSE"
MIG: 22:09:02 :  Invalid Param: DDR3_BYTE_LANES_B0 ==> 4'b1111
MIG: 22:09:02 :  Invalid Param: DDR3_BYTE_LANES_B1 ==> 4'b0000
MIG: 22:09:02 :  Invalid Param: DDR3_BYTE_LANES_B2 ==> 4'b0000
MIG: 22:09:02 :  Invalid Param: DDR3_BYTE_LANES_B3 ==> 4'b0000
MIG: 22:09:02 :  Invalid Param: DDR3_BYTE_LANES_B4 ==> 4'b0000
MIG: 22:09:02 :  Invalid Param: DDR3_DATA_CTL_B0 ==> 4'b0011
MIG: 22:09:02 :  Invalid Param: DDR3_DATA_CTL_B1 ==> 4'b0000
MIG: 22:09:02 :  Invalid Param: DDR3_DATA_CTL_B2 ==> 4'b0000
MIG: 22:09:02 :  Invalid Param: DDR3_DATA_CTL_B3 ==> 4'b0000
MIG: 22:09:02 :  Invalid Param: DDR3_DATA_CTL_B4 ==> 4'b0000
MIG: 22:09:02 :  Invalid Param: DDR3_PHY_0_BITLANES ==> 48'hFFF_FFC_3FE_2FF
MIG: 22:09:02 :  Invalid Param: DDR3_PHY_1_BITLANES ==> 48'h000_000_000_000
MIG: 22:09:02 :  Invalid Param: DDR3_PHY_2_BITLANES ==> 48'h000_000_000_000
MIG: 22:09:02 :  Invalid Param: DDR3_CK_BYTE_MAP ==> 144'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_02
MIG: 22:09:02 :  Invalid Param: DDR3_ADDR_MAP ==> 192'h000_000_027_031_035_032_026_039_025_038_024_037_02B_03B_034_03A
MIG: 22:09:02 :  Invalid Param: DDR3_BANK_MAP ==> 36'h029_033_02A
MIG: 22:09:02 :  Invalid Param: DDR3_CAS_MAP ==> 12'h023
MIG: 22:09:02 :  Invalid Param: DDR3_CKE_ODT_BYTE_MAP ==> 8'h00
MIG: 22:09:02 :  Invalid Param: DDR3_CKE_MAP ==> 96'h000_000_000_000_000_000_000_036
MIG: 22:09:02 :  Invalid Param: DDR3_ODT_MAP ==> 96'h000_000_000_000_000_000_000_030
MIG: 22:09:02 :  Invalid Param: DDR3_CS_MAP ==> 120'h000_000_000_000_000_000_000_000_000_000
MIG: 22:09:02 :  Invalid Param: DDR3_PARITY_MAP ==> 12'h000
MIG: 22:09:02 :  Invalid Param: DDR3_RAS_MAP ==> 12'h022
MIG: 22:09:02 :  Invalid Param: DDR3_WE_MAP ==> 12'h028
MIG: 22:09:02 :  Invalid Param: DDR3_DQS_BYTE_MAP ==> 144'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_01
MIG: 22:09:02 :  Invalid Param: DDR3_DATA0_MAP ==> 96'h019_012_017_013_011_014_018_015
MIG: 22:09:02 :  Invalid Param: DDR3_DATA1_MAP ==> 96'h004_000_007_005_006_001_002_003
MIG: 22:09:02 :  Invalid Param: DDR3_DATA2_MAP ==> 96'h000_000_000_000_000_000_000_000
MIG: 22:09:02 :  Invalid Param: DDR3_DATA3_MAP ==> 96'h000_000_000_000_000_000_000_000
MIG: 22:09:02 :  Invalid Param: DDR3_DATA4_MAP ==> 96'h000_000_000_000_000_000_000_000
MIG: 22:09:02 :  Invalid Param: DDR3_DATA5_MAP ==> 96'h000_000_000_000_000_000_000_000
MIG: 22:09:02 :  Invalid Param: DDR3_DATA6_MAP ==> 96'h000_000_000_000_000_000_000_000
MIG: 22:09:02 :  Invalid Param: DDR3_DATA7_MAP ==> 96'h000_000_000_000_000_000_000_000
MIG: 22:09:02 :  Invalid Param: DDR3_DATA8_MAP ==> 96'h000_000_000_000_000_000_000_000
MIG: 22:09:02 :  Invalid Param: DDR3_DATA9_MAP ==> 96'h000_000_000_000_000_000_000_000
MIG: 22:09:02 :  Invalid Param: DDR3_DATA10_MAP ==> 96'h000_000_000_000_000_000_000_000
MIG: 22:09:02 :  Invalid Param: DDR3_DATA11_MAP ==> 96'h000_000_000_000_000_000_000_000
MIG: 22:09:02 :  Invalid Param: DDR3_DATA12_MAP ==> 96'h000_000_000_000_000_000_000_000
MIG: 22:09:02 :  Invalid Param: DDR3_DATA13_MAP ==> 96'h000_000_000_000_000_000_000_000
MIG: 22:09:02 :  Invalid Param: DDR3_DATA14_MAP ==> 96'h000_000_000_000_000_000_000_000
MIG: 22:09:02 :  Invalid Param: DDR3_DATA15_MAP ==> 96'h000_000_000_000_000_000_000_000
MIG: 22:09:02 :  Invalid Param: DDR3_DATA16_MAP ==> 96'h000_000_000_000_000_000_000_000
MIG: 22:09:02 :  Invalid Param: DDR3_DATA17_MAP ==> 96'h000_000_000_000_000_000_000_000
MIG: 22:09:02 :  Invalid Param: DDR3_MASK0_MAP ==> 108'h000_000_000_000_000_000_000_009_016
MIG: 22:09:02 :  Invalid Param: DDR3_MASK1_MAP ==> 108'h000_000_000_000_000_000_000_000_000
MIG: 22:09:02 :  Invalid Param: DDR3_SLOT_0_CONFIG ==> 8'b0000_0001
MIG: 22:09:02 :  Invalid Param: DDR3_SLOT_1_CONFIG ==> 8'b0000_0000
MIG: 22:09:02 :  Invalid Param: DDR3_IBUF_LPWR_MODE ==> "OFF"
MIG: 22:09:02 :  Invalid Param: DDR3_DATA_IO_IDLE_PWRDWN ==> "ON"
MIG: 22:09:02 :  Invalid Param: DDR3_BANK_TYPE ==> "HR_IO"
MIG: 22:09:02 :  Invalid Param: DDR3_DATA_IO_PRIM_TYPE ==> "HR_LP"
MIG: 22:09:02 :  Invalid Param: DDR3_CKE_ODT_AUX ==> "FALSE"
MIG: 22:09:02 :  Invalid Param: DDR3_USER_REFRESH ==> "OFF"
MIG: 22:09:02 :  Invalid Param: DDR3_WRLVL ==> "ON"
MIG: 22:09:02 :  Invalid Param: DDR3_ORDERING ==> "NORM"
MIG: 22:09:02 :  Invalid Param: DDR3_CALIB_ROW_ADD ==> 16'h0000
MIG: 22:09:02 :  Invalid Param: DDR3_CALIB_COL_ADD ==> 12'h000
MIG: 22:09:02 :  Invalid Param: DDR3_CALIB_BA_ADD ==> 3'h0
MIG: 22:09:02 :  Invalid Param: DDR3_TCQ ==> 100
MIG: 22:09:02 :  Invalid Param: DDR3_IDELAY_ADJ ==> "OFF"
MIG: 22:09:02 :  Invalid Param: DDR3_FINE_PER_BIT ==> "OFF"
MIG: 22:09:02 :  Invalid Param: DDR3_CENTER_COMP_MODE ==> "OFF"
MIG: 22:09:02 :  Invalid Param: DDR3_PI_VAL_ADJ ==> "OFF"
MIG: 22:09:02 :  Invalid Param: DDR3_IODELAY_GRP0 ==> "MIG_7SERIES_0_IODELAY_MIG0"
MIG: 22:09:02 :  Invalid Param: DDR3_IODELAY_GRP1 ==> "MIG_7SERIES_0_IODELAY_MIG1"
MIG: 22:09:02 :  Invalid Param: DDR3_SYSCLK_TYPE ==> "NO_BUFFER"
MIG: 22:09:02 :  Invalid Param: DDR3_REFCLK_TYPE ==> "NO_BUFFER"
MIG: 22:09:02 :  Invalid Param: DDR3_SYS_RST_PORT ==> "FALSE"
MIG: 22:09:02 :  Invalid Param: DDR3_FPGA_SPEED_GRADE ==> 2
MIG: 22:09:02 :  Invalid Param: DDR3_CMD_PIPE_PLUS1 ==> "ON"
MIG: 22:09:02 :  Invalid Param: DDR3_DRAM_TYPE ==> "DDR3"
MIG: 22:09:02 :  Invalid Param: DDR3_CAL_WIDTH ==> "HALF"
MIG: 22:09:02 :  Invalid Param: DDR3_STARVE_LIMIT ==> 2
MIG: 22:09:02 :  Invalid Param: DDR3_REF_CLK_MMCM_IODELAY_CTRL ==> "FALSE"
MIG: 22:09:02 :  Invalid Param: DDR3_REFCLK_FREQ ==> 200.0
MIG: 22:09:02 :  Invalid Param: DDR3_DIFF_TERM_REFCLK ==> "TRUE"
MIG: 22:09:02 :  Invalid Param: DDR3_tCK ==> 2500
MIG: 22:09:02 : 
MIG: 22:09:02 :  Valid Param: DDR3_nCK_PER_CLK ==> 4
MIG: 22:09:02 :  Invalid Param: DDR3_DIFF_TERM_SYSCLK ==> "TRUE"
MIG: 22:09:02 : 
MIG: 22:09:02 :  Valid Param: DDR3_DEBUG_PORT ==> OFF
MIG: 22:09:02 : 
MIG: 22:09:02 :  Invalid Param: DDR3_TEMP_MON_CONTROL ==> "EXTERNAL"
MIG: 22:09:02 :  Invalid Param: DDR3_RST_ACT_LOW ==> 1
MIG: 22:09:02 : 
MIG: 22:09:02 : 
MIG: 22:09:02 : 
MIG: 22:09:02 : Same Interface