Subversion Repositories usb_fpga_2_14

SET_FLAG MODE BATCH
SET_FLAG STANDALONE_MODE TRUE
SET_PREFERENCE ipi_mode no
SET_PREFERENCE is_ip_locked false
SET_PREFERENCE devicefamily artix7
SET_PREFERENCE device xc7a200t
SET_PREFERENCE speedgrade -2
SET_PREFERENCE package fbg484
SET_PREFERENCE verilogsim true
SET_PREFERENCE vhdlsim false
SET_PREFERENCE designentry Verilog
SET_PREFERENCE outputdirectory /drv_s2/usb-fpga/ztex/examples/memfifo/fpga-2.18/memfifo.srcs/sources_1/ip/mig_7series_0/_tmp/
SET_PREFERENCE subworkingdirectory /drv_s2/usb-fpga/ztex/examples/memfifo/fpga-2.18/memfifo.srcs/sources_1/ip/mig_7series_0/_tmp/
SET_PREFERENCE flowvendor Other
SET_PREFERENCE tool vivado
SET_PREFERENCE compnamestatus 0
SET_PARAMETER component_name mig_7series_0
SET_PARAMETER xml_input_file /drv_s2/usb-fpga/ztex/examples/memfifo/fpga-2.18/memfifo.srcs/sources_1/ip/mig_7series_0/mig_a.prj
SET_PARAMETER data_dir_path /drv_s2/xilinx/Vivado/2014.4/data/ip/xilinx/mig_7series_v2_3
SET_CORE_NAME Memory Interface Generator (MIG 7 Series)
SET_CORE_VERSION 2.3
SET_CORE_VLNV xilinx.com:ip:mig_7series:2.3
SET_CORE_PATH /drv_s2/xilinx/Vivado/2014.4/data/ip/xilinx/mig_7series_v2_3
SET_CORE_DATASHEET /drv_s2/xilinx/Vivado/2014.4/data/ip/xilinx/mig_7series_v2_3/data/docs/ds176_7series_MIS.pdf