URL
https://opencores.org/ocsvn/usb_fpga_2_14/usb_fpga_2_14/trunk
Subversion Repositories usb_fpga_2_14
[/] [usb_fpga_2_14/] [trunk/] [examples/] [ucecho/] [fpga-2.16/] [ucecho.xdc] - Rev 2
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# fxclk_increate_clock -name fxclk_in -period 20.833 [get_ports fxclk_in]set_property PACKAGE_PIN Y18 [get_ports fxclk_in]set_property IOSTANDARD LVCMOS33 [get_ports fxclk_in]# reset_inset_property PACKAGE_PIN R18 [get_ports reset_in]set_property IOSTANDARD LVCMOS33 [get_ports reset_in]set_property PULLUP true [get_ports reset_in]# lsi_misoset_property PACKAGE_PIN L20 [get_ports {lsi_miso}] ;# PC0/GPIFADR0set_property IOSTANDARD LVCMOS33 [get_ports lsi_miso]set_property DRIVE 4 [get_ports lsi_miso]# lsi_mosiset_property PACKAGE_PIN L19 [get_ports {lsi_mosi}] ;# PC1/GPIFADR1set_property IOSTANDARD LVCMOS33 [get_ports lsi_mosi]# lsi_clkset_property PACKAGE_PIN L18 [get_ports {lsi_clk}] ;# PC2/GPIFADR2set_property IOSTANDARD LVCMOS33 [get_ports lsi_clk]# lsi_stopset_property PACKAGE_PIN L16 [get_ports {lsi_stop}] ;# PC3/GPIFADR3set_property IOSTANDARD LVCMOS33 [get_ports lsi_stop]# bitstream settingsset_property BITSTREAM.CONFIG.CONFIGRATE 66 [current_design]set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR No [current_design]set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 2 [current_design]set_property BITSTREAM.GENERAL.COMPRESS true [current_design]