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[/] [usb_fpga_2_14/] [trunk/] [fx3/] [ztex-ezusb-io1.c] - Rev 2
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/*% ZTEX Firmware Kit for EZ-USB FX3 Microcontrollers Copyright (C) 2009-2017 ZTEX GmbH. http://www.ztex.de This Source Code Form is subject to the terms of the Mozilla Public License, v. 2.0. If a copy of the MPL was not distributed with this file, You can obtain one at http://mozilla.org/MPL/2.0/. Alternatively, the contents of this file may be used under the terms of the GNU General Public License Version 3, as described below: This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License version 3 as published by the Free Software Foundation. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, see http://www.gnu.org/licenses/. %*/ /* GPIF-II waveform for ezusb_io module for the high speed interface of default firmware. The GPIF-II project can be found in ../default/fpga-fx3/ezusb_iocydsn */ #ifndef _ZTEX_EZUSB_IO1_C_ #define _ZTEX_EZUSB_IO1_C_ #include "cyu3types.h" #include "cyu3gpif.h" //Transition function values used in the state machine. uint16_t ztex_ezusb_io1_gpif_transition[] = { 0x0000, 0xAAAA, 0x5555, 0x1111, 0x8888, 0x7777 }; /* Table containing the transition information for various states. This table has to be stored in the WAVEFORM Registers. This array consists of non-replicated waveform descriptors and acts as a waveform table. */ CyU3PGpifWaveData ztex_ezusb_io1_gpif_wavedata[] = { {{0x1E738301,0x040100C4,0x80000000},{0x00000000,0x00000000,0x00000000}}, {{0x2E738302,0x04000000,0x80000000},{0x00000000,0x00000000,0x00000000}}, {{0x1E738301,0x040100C4,0x80000000},{0x5E702004,0x20000000,0xC0100000}}, {{0x00000000,0x00000000,0x00000000},{0x00000000,0x00000000,0x00000000}}, {{0x00000000,0x00000000,0x00000000},{0x2E738005,0x00000000,0xC0100000}}, {{0x00000000,0x00000000,0x00000000},{0x3E702003,0x20010008,0x80000000}}, {{0x00000000,0x00000000,0x00000000},{0x5E702004,0x20000000,0xC0100000}} }; // Table that maps state indexes to the descriptor table indexes. uint8_t ztex_ezusb_io1_gpif_wavedata_position[] = { 0,1,0,2,0,0,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3, 3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3, 0,4,0,2,0,0,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3, 3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3, 0,5,0,2,0,0,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3, 3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3, 0,6,0,2,0,0 }; // GPIF II configuration register values. uint32_t ztex_ezusb_io1_gpif_reg_value[] = { 0x800083B0, /* CY_U3P_PIB_GPIF_CONFIG */ 0x00001467, /* CY_U3P_PIB_GPIF_BUS_CONFIG */ 0x01000002, /* CY_U3P_PIB_GPIF_BUS_CONFIG2 */ 0x00000044, /* CY_U3P_PIB_GPIF_AD_CONFIG */ 0x00000000, /* CY_U3P_PIB_GPIF_STATUS */ 0x00000000, /* CY_U3P_PIB_GPIF_INTR */ 0x00000000, /* CY_U3P_PIB_GPIF_INTR_MASK */ 0x00000082, /* CY_U3P_PIB_GPIF_SERIAL_IN_CONFIG */ 0x00000782, /* CY_U3P_PIB_GPIF_SERIAL_OUT_CONFIG */ 0x00000500, /* CY_U3P_PIB_GPIF_CTRL_BUS_DIRECTION */ 0x0000FFFF, /* CY_U3P_PIB_GPIF_CTRL_BUS_DEFAULT */ 0x0000003F, /* CY_U3P_PIB_GPIF_CTRL_BUS_POLARITY */ 0x00000000, /* CY_U3P_PIB_GPIF_CTRL_BUS_TOGGLE */ 0x00000000, /* CY_U3P_PIB_GPIF_CTRL_BUS_SELECT */ 0x00000000, /* CY_U3P_PIB_GPIF_CTRL_BUS_SELECT */ 0x00000000, /* CY_U3P_PIB_GPIF_CTRL_BUS_SELECT */ 0x00000000, /* CY_U3P_PIB_GPIF_CTRL_BUS_SELECT */ 0x00000011, /* CY_U3P_PIB_GPIF_CTRL_BUS_SELECT */ 0x00000010, /* CY_U3P_PIB_GPIF_CTRL_BUS_SELECT */ 0x00000000, /* CY_U3P_PIB_GPIF_CTRL_BUS_SELECT */ 0x00000000, /* CY_U3P_PIB_GPIF_CTRL_BUS_SELECT */ 0x00000000, /* CY_U3P_PIB_GPIF_CTRL_BUS_SELECT */ 0x00000000, /* CY_U3P_PIB_GPIF_CTRL_BUS_SELECT */ 0x00000000, /* CY_U3P_PIB_GPIF_CTRL_BUS_SELECT */ 0x00000000, /* CY_U3P_PIB_GPIF_CTRL_BUS_SELECT */ 0x00000000, /* CY_U3P_PIB_GPIF_CTRL_BUS_SELECT */ 0x00000000, /* CY_U3P_PIB_GPIF_CTRL_BUS_SELECT */ 0x00000000, /* CY_U3P_PIB_GPIF_CTRL_BUS_SELECT */ 0x00000000, /* CY_U3P_PIB_GPIF_CTRL_BUS_SELECT */ 0x00000006, /* CY_U3P_PIB_GPIF_CTRL_COUNT_CONFIG */ 0x00000000, /* CY_U3P_PIB_GPIF_CTRL_COUNT_RESET */ 0x0000FFFF, /* CY_U3P_PIB_GPIF_CTRL_COUNT_LIMIT */ 0x0000010A, /* CY_U3P_PIB_GPIF_ADDR_COUNT_CONFIG */ 0x00000000, /* CY_U3P_PIB_GPIF_ADDR_COUNT_RESET */ 0x0000FFFF, /* CY_U3P_PIB_GPIF_ADDR_COUNT_LIMIT */ 0x00000000, /* CY_U3P_PIB_GPIF_STATE_COUNT_CONFIG */ 0x0000FFFF, /* CY_U3P_PIB_GPIF_STATE_COUNT_LIMIT */ 0x0000010A, /* CY_U3P_PIB_GPIF_DATA_COUNT_CONFIG */ 0x00000000, /* CY_U3P_PIB_GPIF_DATA_COUNT_RESET */ 0x0000FFFF, /* CY_U3P_PIB_GPIF_DATA_COUNT_LIMIT */ 0x00000000, /* CY_U3P_PIB_GPIF_CTRL_COMP_VALUE */ 0x00000000, /* CY_U3P_PIB_GPIF_CTRL_COMP_MASK */ 0x00000000, /* CY_U3P_PIB_GPIF_DATA_COMP_VALUE */ 0x00000000, /* CY_U3P_PIB_GPIF_DATA_COMP_MASK */ 0x00000000, /* CY_U3P_PIB_GPIF_ADDR_COMP_VALUE */ 0x00000000, /* CY_U3P_PIB_GPIF_ADDR_COMP_MASK */ 0x00000000, /* CY_U3P_PIB_GPIF_DATA_CTRL */ 0x00000000, /* CY_U3P_PIB_GPIF_INGRESS_DATA */ 0x00000000, /* CY_U3P_PIB_GPIF_INGRESS_DATA */ 0x00000000, /* CY_U3P_PIB_GPIF_INGRESS_DATA */ 0x00000000, /* CY_U3P_PIB_GPIF_INGRESS_DATA */ 0x00000000, /* CY_U3P_PIB_GPIF_EGRESS_DATA */ 0x00000000, /* CY_U3P_PIB_GPIF_EGRESS_DATA */ 0x00000000, /* CY_U3P_PIB_GPIF_EGRESS_DATA */ 0x00000000, /* CY_U3P_PIB_GPIF_EGRESS_DATA */ 0x00000000, /* CY_U3P_PIB_GPIF_INGRESS_ADDRESS */ 0x00000000, /* CY_U3P_PIB_GPIF_INGRESS_ADDRESS */ 0x00000000, /* CY_U3P_PIB_GPIF_INGRESS_ADDRESS */ 0x00000000, /* CY_U3P_PIB_GPIF_INGRESS_ADDRESS */ 0x00000000, /* CY_U3P_PIB_GPIF_EGRESS_ADDRESS */ 0x00000000, /* CY_U3P_PIB_GPIF_EGRESS_ADDRESS */ 0x00000000, /* CY_U3P_PIB_GPIF_EGRESS_ADDRESS */ 0x00000000, /* CY_U3P_PIB_GPIF_EGRESS_ADDRESS */ 0x80010400, /* CY_U3P_PIB_GPIF_THREAD_CONFIG */ 0x80010401, /* CY_U3P_PIB_GPIF_THREAD_CONFIG */ 0x80010402, /* CY_U3P_PIB_GPIF_THREAD_CONFIG */ 0x80010403, /* CY_U3P_PIB_GPIF_THREAD_CONFIG */ 0x00000000, /* CY_U3P_PIB_GPIF_LAMBDA_STAT */ 0x00000000, /* CY_U3P_PIB_GPIF_ALPHA_STAT */ 0x00000000, /* CY_U3P_PIB_GPIF_BETA_STAT */ 0x00000000, /* CY_U3P_PIB_GPIF_WAVEFORM_CTRL_STAT */ 0x00000000, /* CY_U3P_PIB_GPIF_WAVEFORM_SWITCH */ 0x00000000, /* CY_U3P_PIB_GPIF_WAVEFORM_SWITCH_TIMEOUT */ 0x00000000, /* CY_U3P_PIB_GPIF_CRC_CONFIG */ 0x00000000, /* CY_U3P_PIB_GPIF_CRC_DATA */ 0xFFFFFFC1 /* CY_U3P_PIB_GPIF_BETA_DEASSERT */ }; const CyU3PGpifConfig_t ztex_ezusb_io1_gpif_data = { (uint16_t)(sizeof(ztex_ezusb_io1_gpif_wavedata_position)/sizeof(uint8_t)), ztex_ezusb_io1_gpif_wavedata, ztex_ezusb_io1_gpif_wavedata_position, (uint16_t)(sizeof(ztex_ezusb_io1_gpif_transition)/sizeof(uint16_t)), ztex_ezusb_io1_gpif_transition, (uint16_t)(sizeof(ztex_ezusb_io1_gpif_reg_value)/sizeof(uint32_t)), ztex_ezusb_io1_gpif_reg_value }; uint8_t ztex_ezusb_io1_start(CyU3PDmaSocketId_t in_socket, CyU3PDmaSocketId_t out_socket) { // load and start gpif ZTEX_REC_RET( CyU3PGpifLoad ( &ztex_ezusb_io1_gpif_data ) ); // CyU3PDmaChannel* ch = CyU3PDmaChannelGetHandle(out_socket); // ZTEX_LOG("channel size: %d", ch->count*ch->size); // ZTEX_REC( CyU3PGpifSocketConfigure(0, out_socket, ch->count*ch->size-3, CyFalse, 1) ); // thread 0 is output socket: FPGA --> EZUSB, AFULL_FLAG ZTEX_REC( CyU3PGpifSocketConfigure(0, out_socket, 2, CyFalse, 1) ); // thread 0 is output socket: FPGA --> EZUSB, FULL_FLAG ZTEX_REC( CyU3PGpifSocketConfigure(1, in_socket, 2, CyFalse, 1) ); // thread 1 is input socket: EZUSB --> FPGA, EMPTY_FLAG ZTEX_REC_RET( CyU3PGpifSMStart (0, 0) ); return 0; } uint8_t ztex_ezusb_io1_stop() { CyU3PGpifDisable(CyTrue); return 0; } #endif // _ZTEX_EZUSB_IO1_C_